2 * QEMU PowerPC PowerNV CPU Core model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public License
8 * as published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "sysemu/reset.h"
22 #include "qapi/error.h"
24 #include "qemu/module.h"
25 #include "target/ppc/cpu.h"
26 #include "hw/ppc/ppc.h"
27 #include "hw/ppc/pnv.h"
28 #include "hw/ppc/pnv_core.h"
29 #include "hw/ppc/pnv_xscom.h"
30 #include "hw/ppc/xics.h"
31 #include "hw/qdev-properties.h"
33 static const char *pnv_core_cpu_typename(PnvCore
*pc
)
35 const char *core_type
= object_class_get_name(object_get_class(OBJECT(pc
)));
36 int len
= strlen(core_type
) - strlen(PNV_CORE_TYPE_SUFFIX
);
37 char *s
= g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len
, core_type
);
38 const char *cpu_type
= object_class_get_name(object_class_by_name(s
));
43 static void pnv_core_cpu_reset(PowerPCCPU
*cpu
, PnvChip
*chip
)
45 CPUState
*cs
= CPU(cpu
);
46 CPUPPCState
*env
= &cpu
->env
;
47 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
52 * the skiboot firmware elects a primary thread to initialize the
53 * system and it can be any.
55 env
->gpr
[3] = PNV_FDT_ADDR
;
57 env
->msr
|= MSR_HVB
; /* Hypervisor mode */
59 pcc
->intc_reset(chip
, cpu
);
63 * These values are read by the PowerNV HW monitors under Linux
65 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000
66 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001
68 static uint64_t pnv_core_power8_xscom_read(void *opaque
, hwaddr addr
,
71 uint32_t offset
= addr
>> 3;
74 /* The result should be 38 C */
76 case PNV_XSCOM_EX_DTS_RESULT0
:
77 val
= 0x26f024f023f0000ull
;
79 case PNV_XSCOM_EX_DTS_RESULT1
:
80 val
= 0x24f000000000000ull
;
83 qemu_log_mask(LOG_UNIMP
, "Warning: reading reg=0x%" HWADDR_PRIx
"\n",
90 static void pnv_core_power8_xscom_write(void *opaque
, hwaddr addr
, uint64_t val
,
93 qemu_log_mask(LOG_UNIMP
, "Warning: writing to reg=0x%" HWADDR_PRIx
"\n",
97 static const MemoryRegionOps pnv_core_power8_xscom_ops
= {
98 .read
= pnv_core_power8_xscom_read
,
99 .write
= pnv_core_power8_xscom_write
,
100 .valid
.min_access_size
= 8,
101 .valid
.max_access_size
= 8,
102 .impl
.min_access_size
= 8,
103 .impl
.max_access_size
= 8,
104 .endianness
= DEVICE_BIG_ENDIAN
,
109 * POWER9 core controls
111 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
112 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
114 static uint64_t pnv_core_power9_xscom_read(void *opaque
, hwaddr addr
,
117 uint32_t offset
= addr
>> 3;
120 /* The result should be 38 C */
122 case PNV_XSCOM_EX_DTS_RESULT0
:
123 val
= 0x26f024f023f0000ull
;
125 case PNV_XSCOM_EX_DTS_RESULT1
:
126 val
= 0x24f000000000000ull
;
128 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP
:
129 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR
:
133 qemu_log_mask(LOG_UNIMP
, "Warning: reading reg=0x%" HWADDR_PRIx
"\n",
140 static void pnv_core_power9_xscom_write(void *opaque
, hwaddr addr
, uint64_t val
,
143 uint32_t offset
= addr
>> 3;
146 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP
:
147 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR
:
150 qemu_log_mask(LOG_UNIMP
, "Warning: writing to reg=0x%" HWADDR_PRIx
"\n",
155 static const MemoryRegionOps pnv_core_power9_xscom_ops
= {
156 .read
= pnv_core_power9_xscom_read
,
157 .write
= pnv_core_power9_xscom_write
,
158 .valid
.min_access_size
= 8,
159 .valid
.max_access_size
= 8,
160 .impl
.min_access_size
= 8,
161 .impl
.max_access_size
= 8,
162 .endianness
= DEVICE_BIG_ENDIAN
,
165 static void pnv_core_cpu_realize(PowerPCCPU
*cpu
, PnvChip
*chip
, Error
**errp
)
167 CPUPPCState
*env
= &cpu
->env
;
169 int thread_index
= 0; /* TODO: TCG supports only one thread */
170 ppc_spr_t
*pir
= &env
->spr_cb
[SPR_PIR
];
171 Error
*local_err
= NULL
;
172 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
174 object_property_set_bool(OBJECT(cpu
), true, "realized", &local_err
);
176 error_propagate(errp
, local_err
);
180 pcc
->intc_create(chip
, cpu
, &local_err
);
182 error_propagate(errp
, local_err
);
186 core_pir
= object_property_get_uint(OBJECT(cpu
), "core-pir", &error_abort
);
189 * The PIR of a thread is the core PIR + the thread index. We will
190 * need to find a way to get the thread index when TCG supports
191 * more than 1. We could use the object name ?
193 pir
->default_value
= core_pir
+ thread_index
;
195 /* Set time-base frequency to 512 MHz */
196 cpu_ppc_tb_init(env
, PNV_TIMEBASE_FREQ
);
199 static void pnv_core_reset(void *dev
)
201 CPUCore
*cc
= CPU_CORE(dev
);
202 PnvCore
*pc
= PNV_CORE(dev
);
205 for (i
= 0; i
< cc
->nr_threads
; i
++) {
206 pnv_core_cpu_reset(pc
->threads
[i
], pc
->chip
);
210 static void pnv_core_realize(DeviceState
*dev
, Error
**errp
)
212 PnvCore
*pc
= PNV_CORE(OBJECT(dev
));
213 PnvCoreClass
*pcc
= PNV_CORE_GET_CLASS(pc
);
214 CPUCore
*cc
= CPU_CORE(OBJECT(dev
));
215 const char *typename
= pnv_core_cpu_typename(pc
);
216 Error
*local_err
= NULL
;
222 chip
= object_property_get_link(OBJECT(dev
), "chip", &local_err
);
224 error_propagate_prepend(errp
, local_err
,
225 "required link 'chip' not found: ");
228 pc
->chip
= PNV_CHIP(chip
);
230 pc
->threads
= g_new(PowerPCCPU
*, cc
->nr_threads
);
231 for (i
= 0; i
< cc
->nr_threads
; i
++) {
234 obj
= object_new(typename
);
235 cpu
= POWERPC_CPU(obj
);
237 pc
->threads
[i
] = POWERPC_CPU(obj
);
239 snprintf(name
, sizeof(name
), "thread[%d]", i
);
240 object_property_add_child(OBJECT(pc
), name
, obj
, &error_abort
);
241 object_property_add_alias(obj
, "core-pir", OBJECT(pc
),
242 "pir", &error_abort
);
244 cpu
->machine_data
= g_new0(PnvCPUState
, 1);
249 for (j
= 0; j
< cc
->nr_threads
; j
++) {
250 pnv_core_cpu_realize(pc
->threads
[j
], pc
->chip
, &local_err
);
256 snprintf(name
, sizeof(name
), "xscom-core.%d", cc
->core_id
);
257 pnv_xscom_region_init(&pc
->xscom_regs
, OBJECT(dev
), pcc
->xscom_ops
,
258 pc
, name
, PNV_XSCOM_EX_SIZE
);
260 qemu_register_reset(pnv_core_reset
, pc
);
265 obj
= OBJECT(pc
->threads
[i
]);
266 object_unparent(obj
);
269 error_propagate(errp
, local_err
);
272 static void pnv_core_cpu_unrealize(PowerPCCPU
*cpu
, PnvChip
*chip
)
274 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
275 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
277 pcc
->intc_destroy(chip
, cpu
);
278 cpu_remove_sync(CPU(cpu
));
279 cpu
->machine_data
= NULL
;
281 object_unparent(OBJECT(cpu
));
284 static void pnv_core_unrealize(DeviceState
*dev
, Error
**errp
)
286 PnvCore
*pc
= PNV_CORE(dev
);
287 CPUCore
*cc
= CPU_CORE(dev
);
290 qemu_unregister_reset(pnv_core_reset
, pc
);
292 for (i
= 0; i
< cc
->nr_threads
; i
++) {
293 pnv_core_cpu_unrealize(pc
->threads
[i
], pc
->chip
);
298 static Property pnv_core_properties
[] = {
299 DEFINE_PROP_UINT32("pir", PnvCore
, pir
, 0),
300 DEFINE_PROP_END_OF_LIST(),
303 static void pnv_core_power8_class_init(ObjectClass
*oc
, void *data
)
305 PnvCoreClass
*pcc
= PNV_CORE_CLASS(oc
);
307 pcc
->xscom_ops
= &pnv_core_power8_xscom_ops
;
310 static void pnv_core_power9_class_init(ObjectClass
*oc
, void *data
)
312 PnvCoreClass
*pcc
= PNV_CORE_CLASS(oc
);
314 pcc
->xscom_ops
= &pnv_core_power9_xscom_ops
;
317 static void pnv_core_class_init(ObjectClass
*oc
, void *data
)
319 DeviceClass
*dc
= DEVICE_CLASS(oc
);
321 dc
->realize
= pnv_core_realize
;
322 dc
->unrealize
= pnv_core_unrealize
;
323 dc
->props
= pnv_core_properties
;
326 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
328 .parent = TYPE_PNV_CORE, \
329 .name = PNV_CORE_TYPE_NAME(cpu_model), \
330 .class_init = pnv_core_##family##_class_init, \
333 static const TypeInfo pnv_core_infos
[] = {
335 .name
= TYPE_PNV_CORE
,
336 .parent
= TYPE_CPU_CORE
,
337 .instance_size
= sizeof(PnvCore
),
338 .class_size
= sizeof(PnvCoreClass
),
339 .class_init
= pnv_core_class_init
,
342 DEFINE_PNV_CORE_TYPE(power8
, "power8e_v2.1"),
343 DEFINE_PNV_CORE_TYPE(power8
, "power8_v2.0"),
344 DEFINE_PNV_CORE_TYPE(power8
, "power8nvl_v1.0"),
345 DEFINE_PNV_CORE_TYPE(power9
, "power9_v2.0"),
348 DEFINE_TYPES(pnv_core_infos
)
354 #define P9X_EX_NCU_SPEC_BAR 0x11010
356 static uint64_t pnv_quad_xscom_read(void *opaque
, hwaddr addr
,
359 uint32_t offset
= addr
>> 3;
363 case P9X_EX_NCU_SPEC_BAR
:
364 case P9X_EX_NCU_SPEC_BAR
+ 0x400: /* Second EX */
368 qemu_log_mask(LOG_UNIMP
, "%s: writing @0x%08x\n", __func__
,
375 static void pnv_quad_xscom_write(void *opaque
, hwaddr addr
, uint64_t val
,
378 uint32_t offset
= addr
>> 3;
381 case P9X_EX_NCU_SPEC_BAR
:
382 case P9X_EX_NCU_SPEC_BAR
+ 0x400: /* Second EX */
385 qemu_log_mask(LOG_UNIMP
, "%s: writing @0x%08x\n", __func__
,
390 static const MemoryRegionOps pnv_quad_xscom_ops
= {
391 .read
= pnv_quad_xscom_read
,
392 .write
= pnv_quad_xscom_write
,
393 .valid
.min_access_size
= 8,
394 .valid
.max_access_size
= 8,
395 .impl
.min_access_size
= 8,
396 .impl
.max_access_size
= 8,
397 .endianness
= DEVICE_BIG_ENDIAN
,
400 static void pnv_quad_realize(DeviceState
*dev
, Error
**errp
)
402 PnvQuad
*eq
= PNV_QUAD(dev
);
405 snprintf(name
, sizeof(name
), "xscom-quad.%d", eq
->id
);
406 pnv_xscom_region_init(&eq
->xscom_regs
, OBJECT(dev
), &pnv_quad_xscom_ops
,
407 eq
, name
, PNV9_XSCOM_EQ_SIZE
);
410 static Property pnv_quad_properties
[] = {
411 DEFINE_PROP_UINT32("id", PnvQuad
, id
, 0),
412 DEFINE_PROP_END_OF_LIST(),
415 static void pnv_quad_class_init(ObjectClass
*oc
, void *data
)
417 DeviceClass
*dc
= DEVICE_CLASS(oc
);
419 dc
->realize
= pnv_quad_realize
;
420 dc
->props
= pnv_quad_properties
;
423 static const TypeInfo pnv_quad_info
= {
424 .name
= TYPE_PNV_QUAD
,
425 .parent
= TYPE_DEVICE
,
426 .instance_size
= sizeof(PnvQuad
),
427 .class_init
= pnv_quad_class_init
,
430 static void pnv_core_register_types(void)
432 type_register_static(&pnv_quad_info
);
435 type_init(pnv_core_register_types
)