2 * QEMU PowerPC e500-based platforms
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Yu Liu, <yu.liu@freescale.com>
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include "qemu/osdep.h"
18 #include "qemu-common.h"
19 #include "qemu/units.h"
20 #include "qapi/error.h"
22 #include "e500-ccsr.h"
24 #include "qemu/config-file.h"
26 #include "hw/char/serial.h"
27 #include "hw/pci/pci.h"
28 #include "hw/boards.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/kvm.h"
32 #include "sysemu/device_tree.h"
33 #include "hw/ppc/openpic.h"
34 #include "hw/ppc/openpic_kvm.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/loader.h"
38 #include "hw/sysbus.h"
39 #include "exec/address-spaces.h"
40 #include "qemu/host-utils.h"
41 #include "qemu/option.h"
42 #include "hw/pci-host/ppce500.h"
43 #include "qemu/error-report.h"
44 #include "hw/platform-bus.h"
45 #include "hw/net/fsl_etsec/etsec.h"
46 #include "hw/i2c/i2c.h"
48 #define EPAPR_MAGIC (0x45504150)
49 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
50 #define DTC_LOAD_PAD 0x1800000
51 #define DTC_PAD_MASK 0xFFFFF
52 #define DTB_MAX_SIZE (8 * MiB)
53 #define INITRD_LOAD_PAD 0x2000000
54 #define INITRD_PAD_MASK 0xFFFFFF
56 #define RAM_SIZES_ALIGN (64 * MiB)
58 /* TODO: parameterize */
59 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL
60 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
61 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL
62 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
63 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
64 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL
65 #define MPC8544_PCI_REGS_SIZE 0x1000ULL
66 #define MPC8544_UTIL_OFFSET 0xe0000ULL
67 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
68 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL
69 #define MPC8XXX_GPIO_IRQ 47
70 #define MPC8544_I2C_IRQ 43
71 #define RTC_REGS_OFFSET 0x68
80 static uint32_t *pci_map_create(void *fdt
, uint32_t mpic
, int first_slot
,
81 int nr_slots
, int *len
)
87 int last_slot
= first_slot
+ nr_slots
;
90 *len
= nr_slots
* 4 * 7 * sizeof(uint32_t);
91 pci_map
= g_malloc(*len
);
93 for (slot
= first_slot
; slot
< last_slot
; slot
++) {
94 for (pci_irq
= 0; pci_irq
< 4; pci_irq
++) {
95 pci_map
[i
++] = cpu_to_be32(slot
<< 11);
96 pci_map
[i
++] = cpu_to_be32(0x0);
97 pci_map
[i
++] = cpu_to_be32(0x0);
98 pci_map
[i
++] = cpu_to_be32(pci_irq
+ 1);
99 pci_map
[i
++] = cpu_to_be32(mpic
);
100 host_irq
= ppce500_pci_map_irq_slot(slot
, pci_irq
);
101 pci_map
[i
++] = cpu_to_be32(host_irq
+ 1);
102 pci_map
[i
++] = cpu_to_be32(0x1);
106 assert((i
* sizeof(uint32_t)) == *len
);
111 static void dt_serial_create(void *fdt
, unsigned long long offset
,
112 const char *soc
, const char *mpic
,
113 const char *alias
, int idx
, bool defcon
)
117 ser
= g_strdup_printf("%s/serial@%llx", soc
, offset
);
118 qemu_fdt_add_subnode(fdt
, ser
);
119 qemu_fdt_setprop_string(fdt
, ser
, "device_type", "serial");
120 qemu_fdt_setprop_string(fdt
, ser
, "compatible", "ns16550");
121 qemu_fdt_setprop_cells(fdt
, ser
, "reg", offset
, 0x100);
122 qemu_fdt_setprop_cell(fdt
, ser
, "cell-index", idx
);
123 qemu_fdt_setprop_cell(fdt
, ser
, "clock-frequency", 0);
124 qemu_fdt_setprop_cells(fdt
, ser
, "interrupts", 42, 2);
125 qemu_fdt_setprop_phandle(fdt
, ser
, "interrupt-parent", mpic
);
126 qemu_fdt_setprop_string(fdt
, "/aliases", alias
, ser
);
130 * "linux,stdout-path" and "stdout" properties are deprecated by linux
131 * kernel. New platforms should only use the "stdout-path" property. Set
132 * the new property and continue using older property to remain
133 * compatible with the existing firmware.
135 qemu_fdt_setprop_string(fdt
, "/chosen", "linux,stdout-path", ser
);
136 qemu_fdt_setprop_string(fdt
, "/chosen", "stdout-path", ser
);
141 static void create_dt_mpc8xxx_gpio(void *fdt
, const char *soc
, const char *mpic
)
143 hwaddr mmio0
= MPC8XXX_GPIO_OFFSET
;
144 int irq0
= MPC8XXX_GPIO_IRQ
;
145 gchar
*node
= g_strdup_printf("%s/gpio@%"PRIx64
, soc
, mmio0
);
146 gchar
*poweroff
= g_strdup_printf("%s/power-off", soc
);
149 qemu_fdt_add_subnode(fdt
, node
);
150 qemu_fdt_setprop_string(fdt
, node
, "compatible", "fsl,qoriq-gpio");
151 qemu_fdt_setprop_cells(fdt
, node
, "reg", mmio0
, 0x1000);
152 qemu_fdt_setprop_cells(fdt
, node
, "interrupts", irq0
, 0x2);
153 qemu_fdt_setprop_phandle(fdt
, node
, "interrupt-parent", mpic
);
154 qemu_fdt_setprop_cells(fdt
, node
, "#gpio-cells", 2);
155 qemu_fdt_setprop(fdt
, node
, "gpio-controller", NULL
, 0);
156 gpio_ph
= qemu_fdt_alloc_phandle(fdt
);
157 qemu_fdt_setprop_cell(fdt
, node
, "phandle", gpio_ph
);
158 qemu_fdt_setprop_cell(fdt
, node
, "linux,phandle", gpio_ph
);
161 qemu_fdt_add_subnode(fdt
, poweroff
);
162 qemu_fdt_setprop_string(fdt
, poweroff
, "compatible", "gpio-poweroff");
163 qemu_fdt_setprop_cells(fdt
, poweroff
, "gpios", gpio_ph
, 0, 0);
169 static void dt_rtc_create(void *fdt
, const char *i2c
, const char *alias
)
171 int offset
= RTC_REGS_OFFSET
;
173 gchar
*rtc
= g_strdup_printf("%s/rtc@%"PRIx32
, i2c
, offset
);
174 qemu_fdt_add_subnode(fdt
, rtc
);
175 qemu_fdt_setprop_string(fdt
, rtc
, "compatible", "pericom,pt7c4338");
176 qemu_fdt_setprop_cells(fdt
, rtc
, "reg", offset
);
177 qemu_fdt_setprop_string(fdt
, "/aliases", alias
, rtc
);
182 static void dt_i2c_create(void *fdt
, const char *soc
, const char *mpic
,
185 hwaddr mmio0
= MPC8544_I2C_REGS_OFFSET
;
186 int irq0
= MPC8544_I2C_IRQ
;
188 gchar
*i2c
= g_strdup_printf("%s/i2c@%"PRIx64
, soc
, mmio0
);
189 qemu_fdt_add_subnode(fdt
, i2c
);
190 qemu_fdt_setprop_string(fdt
, i2c
, "device_type", "i2c");
191 qemu_fdt_setprop_string(fdt
, i2c
, "compatible", "fsl-i2c");
192 qemu_fdt_setprop_cells(fdt
, i2c
, "reg", mmio0
, 0x14);
193 qemu_fdt_setprop_cells(fdt
, i2c
, "cell-index", 0);
194 qemu_fdt_setprop_cells(fdt
, i2c
, "interrupts", irq0
, 0x2);
195 qemu_fdt_setprop_phandle(fdt
, i2c
, "interrupt-parent", mpic
);
196 qemu_fdt_setprop_string(fdt
, "/aliases", alias
, i2c
);
202 typedef struct PlatformDevtreeData
{
207 PlatformBusDevice
*pbus
;
208 } PlatformDevtreeData
;
210 static int create_devtree_etsec(SysBusDevice
*sbdev
, PlatformDevtreeData
*data
)
212 eTSEC
*etsec
= ETSEC_COMMON(sbdev
);
213 PlatformBusDevice
*pbus
= data
->pbus
;
214 hwaddr mmio0
= platform_bus_get_mmio_addr(pbus
, sbdev
, 0);
215 int irq0
= platform_bus_get_irqn(pbus
, sbdev
, 0);
216 int irq1
= platform_bus_get_irqn(pbus
, sbdev
, 1);
217 int irq2
= platform_bus_get_irqn(pbus
, sbdev
, 2);
218 gchar
*node
= g_strdup_printf("/platform/ethernet@%"PRIx64
, mmio0
);
219 gchar
*group
= g_strdup_printf("%s/queue-group", node
);
220 void *fdt
= data
->fdt
;
222 assert((int64_t)mmio0
>= 0);
227 qemu_fdt_add_subnode(fdt
, node
);
228 qemu_fdt_setprop_string(fdt
, node
, "device_type", "network");
229 qemu_fdt_setprop_string(fdt
, node
, "compatible", "fsl,etsec2");
230 qemu_fdt_setprop_string(fdt
, node
, "model", "eTSEC");
231 qemu_fdt_setprop(fdt
, node
, "local-mac-address", etsec
->conf
.macaddr
.a
, 6);
232 qemu_fdt_setprop_cells(fdt
, node
, "fixed-link", 0, 1, 1000, 0, 0);
234 qemu_fdt_add_subnode(fdt
, group
);
235 qemu_fdt_setprop_cells(fdt
, group
, "reg", mmio0
, 0x1000);
236 qemu_fdt_setprop_cells(fdt
, group
, "interrupts",
237 data
->irq_start
+ irq0
, 0x2,
238 data
->irq_start
+ irq1
, 0x2,
239 data
->irq_start
+ irq2
, 0x2);
247 static void sysbus_device_create_devtree(SysBusDevice
*sbdev
, void *opaque
)
249 PlatformDevtreeData
*data
= opaque
;
250 bool matched
= false;
252 if (object_dynamic_cast(OBJECT(sbdev
), TYPE_ETSEC_COMMON
)) {
253 create_devtree_etsec(sbdev
, data
);
258 error_report("Device %s is not supported by this machine yet.",
259 qdev_fw_name(DEVICE(sbdev
)));
264 static void platform_bus_create_devtree(PPCE500MachineState
*pms
,
265 void *fdt
, const char *mpic
)
267 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
268 gchar
*node
= g_strdup_printf("/platform@%"PRIx64
, pmc
->platform_bus_base
);
269 const char platcomp
[] = "qemu,platform\0simple-bus";
270 uint64_t addr
= pmc
->platform_bus_base
;
271 uint64_t size
= pmc
->platform_bus_size
;
272 int irq_start
= pmc
->platform_bus_first_irq
;
274 /* Create a /platform node that we can put all devices into */
276 qemu_fdt_add_subnode(fdt
, node
);
277 qemu_fdt_setprop(fdt
, node
, "compatible", platcomp
, sizeof(platcomp
));
279 /* Our platform bus region is less than 32bit big, so 1 cell is enough for
281 qemu_fdt_setprop_cells(fdt
, node
, "#size-cells", 1);
282 qemu_fdt_setprop_cells(fdt
, node
, "#address-cells", 1);
283 qemu_fdt_setprop_cells(fdt
, node
, "ranges", 0, addr
>> 32, addr
, size
);
285 qemu_fdt_setprop_phandle(fdt
, node
, "interrupt-parent", mpic
);
287 /* Create dt nodes for dynamic devices */
288 PlatformDevtreeData data
= {
291 .irq_start
= irq_start
,
293 .pbus
= pms
->pbus_dev
,
296 /* Loop through all dynamic sysbus devices and create nodes for them */
297 foreach_dynamic_sysbus_device(sysbus_device_create_devtree
, &data
);
302 static int ppce500_load_device_tree(PPCE500MachineState
*pms
,
310 MachineState
*machine
= MACHINE(pms
);
311 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
312 CPUPPCState
*env
= first_cpu
->env_ptr
;
314 uint64_t mem_reg_property
[] = { 0, cpu_to_be64(machine
->ram_size
) };
317 uint8_t hypercall
[16];
318 uint32_t clock_freq
= 400000000;
319 uint32_t tb_freq
= 400000000;
321 char compatible_sb
[] = "fsl,mpc8544-immr\0simple-bus";
329 uint32_t *pci_map
= NULL
;
331 uint32_t pci_ranges
[14] =
333 0x2000000, 0x0, pmc
->pci_mmio_bus_base
,
334 pmc
->pci_mmio_base
>> 32, pmc
->pci_mmio_base
,
338 pmc
->pci_pio_base
>> 32, pmc
->pci_pio_base
,
341 QemuOpts
*machine_opts
= qemu_get_machine_opts();
342 const char *dtb_file
= qemu_opt_get(machine_opts
, "dtb");
343 const char *toplevel_compat
= qemu_opt_get(machine_opts
, "dt_compatible");
347 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, dtb_file
);
352 fdt
= load_device_tree(filename
, &fdt_size
);
360 fdt
= create_device_tree(&fdt_size
);
365 /* Manipulate device tree in memory. */
366 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 2);
367 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 2);
369 qemu_fdt_add_subnode(fdt
, "/memory");
370 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
371 qemu_fdt_setprop(fdt
, "/memory", "reg", mem_reg_property
,
372 sizeof(mem_reg_property
));
374 qemu_fdt_add_subnode(fdt
, "/chosen");
376 ret
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-start",
379 fprintf(stderr
, "couldn't set /chosen/linux,initrd-start\n");
382 ret
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-end",
383 (initrd_base
+ initrd_size
));
385 fprintf(stderr
, "couldn't set /chosen/linux,initrd-end\n");
390 if (kernel_base
!= -1ULL) {
391 qemu_fdt_setprop_cells(fdt
, "/chosen", "qemu,boot-kernel",
392 kernel_base
>> 32, kernel_base
,
393 kernel_size
>> 32, kernel_size
);
396 ret
= qemu_fdt_setprop_string(fdt
, "/chosen", "bootargs",
397 machine
->kernel_cmdline
);
399 fprintf(stderr
, "couldn't set /chosen/bootargs\n");
402 /* Read out host's frequencies */
403 clock_freq
= kvmppc_get_clockfreq();
404 tb_freq
= kvmppc_get_tbfreq();
406 /* indicate KVM hypercall interface */
407 qemu_fdt_add_subnode(fdt
, "/hypervisor");
408 qemu_fdt_setprop_string(fdt
, "/hypervisor", "compatible",
410 kvmppc_get_hypercall(env
, hypercall
, sizeof(hypercall
));
411 qemu_fdt_setprop(fdt
, "/hypervisor", "hcall-instructions",
412 hypercall
, sizeof(hypercall
));
413 /* if KVM supports the idle hcall, set property indicating this */
414 if (kvmppc_get_hasidle(env
)) {
415 qemu_fdt_setprop(fdt
, "/hypervisor", "has-idle", NULL
, 0);
419 /* Create CPU nodes */
420 qemu_fdt_add_subnode(fdt
, "/cpus");
421 qemu_fdt_setprop_cell(fdt
, "/cpus", "#address-cells", 1);
422 qemu_fdt_setprop_cell(fdt
, "/cpus", "#size-cells", 0);
424 /* We need to generate the cpu nodes in reverse order, so Linux can pick
425 the first node as boot node and be happy */
426 for (i
= smp_cpus
- 1; i
>= 0; i
--) {
429 uint64_t cpu_release_addr
= pmc
->spin_base
+ (i
* 0x20);
431 cpu
= qemu_get_cpu(i
);
437 cpu_name
= g_strdup_printf("/cpus/PowerPC,8544@%x", i
);
438 qemu_fdt_add_subnode(fdt
, cpu_name
);
439 qemu_fdt_setprop_cell(fdt
, cpu_name
, "clock-frequency", clock_freq
);
440 qemu_fdt_setprop_cell(fdt
, cpu_name
, "timebase-frequency", tb_freq
);
441 qemu_fdt_setprop_string(fdt
, cpu_name
, "device_type", "cpu");
442 qemu_fdt_setprop_cell(fdt
, cpu_name
, "reg", i
);
443 qemu_fdt_setprop_cell(fdt
, cpu_name
, "d-cache-line-size",
444 env
->dcache_line_size
);
445 qemu_fdt_setprop_cell(fdt
, cpu_name
, "i-cache-line-size",
446 env
->icache_line_size
);
447 qemu_fdt_setprop_cell(fdt
, cpu_name
, "d-cache-size", 0x8000);
448 qemu_fdt_setprop_cell(fdt
, cpu_name
, "i-cache-size", 0x8000);
449 qemu_fdt_setprop_cell(fdt
, cpu_name
, "bus-frequency", 0);
450 if (cpu
->cpu_index
) {
451 qemu_fdt_setprop_string(fdt
, cpu_name
, "status", "disabled");
452 qemu_fdt_setprop_string(fdt
, cpu_name
, "enable-method",
454 qemu_fdt_setprop_u64(fdt
, cpu_name
, "cpu-release-addr",
457 qemu_fdt_setprop_string(fdt
, cpu_name
, "status", "okay");
462 qemu_fdt_add_subnode(fdt
, "/aliases");
463 /* XXX These should go into their respective devices' code */
464 soc
= g_strdup_printf("/soc@%"PRIx64
, pmc
->ccsrbar_base
);
465 qemu_fdt_add_subnode(fdt
, soc
);
466 qemu_fdt_setprop_string(fdt
, soc
, "device_type", "soc");
467 qemu_fdt_setprop(fdt
, soc
, "compatible", compatible_sb
,
468 sizeof(compatible_sb
));
469 qemu_fdt_setprop_cell(fdt
, soc
, "#address-cells", 1);
470 qemu_fdt_setprop_cell(fdt
, soc
, "#size-cells", 1);
471 qemu_fdt_setprop_cells(fdt
, soc
, "ranges", 0x0,
472 pmc
->ccsrbar_base
>> 32, pmc
->ccsrbar_base
,
473 MPC8544_CCSRBAR_SIZE
);
474 /* XXX should contain a reasonable value */
475 qemu_fdt_setprop_cell(fdt
, soc
, "bus-frequency", 0);
477 mpic
= g_strdup_printf("%s/pic@%llx", soc
, MPC8544_MPIC_REGS_OFFSET
);
478 qemu_fdt_add_subnode(fdt
, mpic
);
479 qemu_fdt_setprop_string(fdt
, mpic
, "device_type", "open-pic");
480 qemu_fdt_setprop_string(fdt
, mpic
, "compatible", "fsl,mpic");
481 qemu_fdt_setprop_cells(fdt
, mpic
, "reg", MPC8544_MPIC_REGS_OFFSET
,
483 qemu_fdt_setprop_cell(fdt
, mpic
, "#address-cells", 0);
484 qemu_fdt_setprop_cell(fdt
, mpic
, "#interrupt-cells", 2);
485 mpic_ph
= qemu_fdt_alloc_phandle(fdt
);
486 qemu_fdt_setprop_cell(fdt
, mpic
, "phandle", mpic_ph
);
487 qemu_fdt_setprop_cell(fdt
, mpic
, "linux,phandle", mpic_ph
);
488 qemu_fdt_setprop(fdt
, mpic
, "interrupt-controller", NULL
, 0);
491 * We have to generate ser1 first, because Linux takes the first
492 * device it finds in the dt as serial output device. And we generate
493 * devices in reverse order to the dt.
496 dt_serial_create(fdt
, MPC8544_SERIAL1_REGS_OFFSET
,
497 soc
, mpic
, "serial1", 1, false);
501 dt_serial_create(fdt
, MPC8544_SERIAL0_REGS_OFFSET
,
502 soc
, mpic
, "serial0", 0, true);
506 dt_i2c_create(fdt
, soc
, mpic
, "i2c");
508 dt_rtc_create(fdt
, "i2c", "rtc");
511 gutil
= g_strdup_printf("%s/global-utilities@%llx", soc
,
512 MPC8544_UTIL_OFFSET
);
513 qemu_fdt_add_subnode(fdt
, gutil
);
514 qemu_fdt_setprop_string(fdt
, gutil
, "compatible", "fsl,mpc8544-guts");
515 qemu_fdt_setprop_cells(fdt
, gutil
, "reg", MPC8544_UTIL_OFFSET
, 0x1000);
516 qemu_fdt_setprop(fdt
, gutil
, "fsl,has-rstcr", NULL
, 0);
519 msi
= g_strdup_printf("/%s/msi@%llx", soc
, MPC8544_MSI_REGS_OFFSET
);
520 qemu_fdt_add_subnode(fdt
, msi
);
521 qemu_fdt_setprop_string(fdt
, msi
, "compatible", "fsl,mpic-msi");
522 qemu_fdt_setprop_cells(fdt
, msi
, "reg", MPC8544_MSI_REGS_OFFSET
, 0x200);
523 msi_ph
= qemu_fdt_alloc_phandle(fdt
);
524 qemu_fdt_setprop_cells(fdt
, msi
, "msi-available-ranges", 0x0, 0x100);
525 qemu_fdt_setprop_phandle(fdt
, msi
, "interrupt-parent", mpic
);
526 qemu_fdt_setprop_cells(fdt
, msi
, "interrupts",
535 qemu_fdt_setprop_cell(fdt
, msi
, "phandle", msi_ph
);
536 qemu_fdt_setprop_cell(fdt
, msi
, "linux,phandle", msi_ph
);
539 pci
= g_strdup_printf("/pci@%llx",
540 pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
);
541 qemu_fdt_add_subnode(fdt
, pci
);
542 qemu_fdt_setprop_cell(fdt
, pci
, "cell-index", 0);
543 qemu_fdt_setprop_string(fdt
, pci
, "compatible", "fsl,mpc8540-pci");
544 qemu_fdt_setprop_string(fdt
, pci
, "device_type", "pci");
545 qemu_fdt_setprop_cells(fdt
, pci
, "interrupt-map-mask", 0xf800, 0x0,
547 pci_map
= pci_map_create(fdt
, qemu_fdt_get_phandle(fdt
, mpic
),
548 pmc
->pci_first_slot
, pmc
->pci_nr_slots
,
550 qemu_fdt_setprop(fdt
, pci
, "interrupt-map", pci_map
, len
);
551 qemu_fdt_setprop_phandle(fdt
, pci
, "interrupt-parent", mpic
);
552 qemu_fdt_setprop_cells(fdt
, pci
, "interrupts", 24, 2);
553 qemu_fdt_setprop_cells(fdt
, pci
, "bus-range", 0, 255);
554 for (i
= 0; i
< 14; i
++) {
555 pci_ranges
[i
] = cpu_to_be32(pci_ranges
[i
]);
557 qemu_fdt_setprop_cell(fdt
, pci
, "fsl,msi", msi_ph
);
558 qemu_fdt_setprop(fdt
, pci
, "ranges", pci_ranges
, sizeof(pci_ranges
));
559 qemu_fdt_setprop_cells(fdt
, pci
, "reg",
560 (pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
) >> 32,
561 (pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
),
563 qemu_fdt_setprop_cell(fdt
, pci
, "clock-frequency", 66666666);
564 qemu_fdt_setprop_cell(fdt
, pci
, "#interrupt-cells", 1);
565 qemu_fdt_setprop_cell(fdt
, pci
, "#size-cells", 2);
566 qemu_fdt_setprop_cell(fdt
, pci
, "#address-cells", 3);
567 qemu_fdt_setprop_string(fdt
, "/aliases", "pci0", pci
);
570 if (pmc
->has_mpc8xxx_gpio
) {
571 create_dt_mpc8xxx_gpio(fdt
, soc
, mpic
);
576 platform_bus_create_devtree(pms
, fdt
, mpic
);
580 pmc
->fixup_devtree(fdt
);
582 if (toplevel_compat
) {
583 qemu_fdt_setprop(fdt
, "/", "compatible", toplevel_compat
,
584 strlen(toplevel_compat
) + 1);
589 qemu_fdt_dumpdtb(fdt
, fdt_size
);
590 cpu_physical_memory_write(addr
, fdt
, fdt_size
);
600 typedef struct DeviceTreeParams
{
601 PPCE500MachineState
*machine
;
610 static void ppce500_reset_device_tree(void *opaque
)
612 DeviceTreeParams
*p
= opaque
;
613 ppce500_load_device_tree(p
->machine
, p
->addr
, p
->initrd_base
,
614 p
->initrd_size
, p
->kernel_base
, p
->kernel_size
,
618 static void ppce500_init_notify(Notifier
*notifier
, void *data
)
620 DeviceTreeParams
*p
= container_of(notifier
, DeviceTreeParams
, notifier
);
621 ppce500_reset_device_tree(p
);
624 static int ppce500_prep_device_tree(PPCE500MachineState
*machine
,
631 DeviceTreeParams
*p
= g_new(DeviceTreeParams
, 1);
632 p
->machine
= machine
;
634 p
->initrd_base
= initrd_base
;
635 p
->initrd_size
= initrd_size
;
636 p
->kernel_base
= kernel_base
;
637 p
->kernel_size
= kernel_size
;
639 qemu_register_reset(ppce500_reset_device_tree
, p
);
640 p
->notifier
.notify
= ppce500_init_notify
;
641 qemu_add_machine_init_done_notifier(&p
->notifier
);
643 /* Issue the device tree loader once, so that we get the size of the blob */
644 return ppce500_load_device_tree(machine
, addr
, initrd_base
, initrd_size
,
645 kernel_base
, kernel_size
, true);
648 /* Create -kernel TLB entries for BookE. */
649 hwaddr
booke206_page_size_to_tlb(uint64_t size
)
651 return 63 - clz64(size
/ KiB
);
654 static int booke206_initial_map_tsize(CPUPPCState
*env
)
656 struct boot_info
*bi
= env
->load_info
;
660 /* Our initial TLB entry needs to cover everything from 0 to
661 the device tree top */
662 dt_end
= bi
->dt_base
+ bi
->dt_size
;
663 ps
= booke206_page_size_to_tlb(dt_end
) + 1;
665 /* e500v2 can only do even TLB size bits */
671 static uint64_t mmubooke_initial_mapsize(CPUPPCState
*env
)
675 tsize
= booke206_initial_map_tsize(env
);
676 return (1ULL << 10 << tsize
);
679 static void mmubooke_create_initial_mapping(CPUPPCState
*env
)
681 ppcmas_tlb_t
*tlb
= booke206_get_tlbm(env
, 1, 0, 0);
685 ps
= booke206_initial_map_tsize(env
);
686 size
= (ps
<< MAS1_TSIZE_SHIFT
);
687 tlb
->mas1
= MAS1_VALID
| size
;
690 tlb
->mas7_3
|= MAS3_UR
| MAS3_UW
| MAS3_UX
| MAS3_SR
| MAS3_SW
| MAS3_SX
;
692 env
->tlb_dirty
= true;
695 static void ppce500_cpu_reset_sec(void *opaque
)
697 PowerPCCPU
*cpu
= opaque
;
698 CPUState
*cs
= CPU(cpu
);
702 /* Secondary CPU starts in halted state for now. Needs to change when
703 implementing non-kernel boot. */
705 cs
->exception_index
= EXCP_HLT
;
708 static void ppce500_cpu_reset(void *opaque
)
710 PowerPCCPU
*cpu
= opaque
;
711 CPUState
*cs
= CPU(cpu
);
712 CPUPPCState
*env
= &cpu
->env
;
713 struct boot_info
*bi
= env
->load_info
;
717 /* Set initial guest state. */
719 env
->gpr
[1] = (16 * MiB
) - 8;
720 env
->gpr
[3] = bi
->dt_base
;
723 env
->gpr
[6] = EPAPR_MAGIC
;
724 env
->gpr
[7] = mmubooke_initial_mapsize(env
);
727 env
->nip
= bi
->entry
;
728 mmubooke_create_initial_mapping(env
);
731 static DeviceState
*ppce500_init_mpic_qemu(PPCE500MachineState
*pms
,
737 MachineState
*machine
= MACHINE(pms
);
738 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
740 dev
= qdev_create(NULL
, TYPE_OPENPIC
);
741 object_property_add_child(OBJECT(machine
), "pic", OBJECT(dev
),
743 qdev_prop_set_uint32(dev
, "model", pmc
->mpic_version
);
744 qdev_prop_set_uint32(dev
, "nb_cpus", smp_cpus
);
746 qdev_init_nofail(dev
);
747 s
= SYS_BUS_DEVICE(dev
);
750 for (i
= 0; i
< smp_cpus
; i
++) {
751 for (j
= 0; j
< OPENPIC_OUTPUT_NB
; j
++) {
752 sysbus_connect_irq(s
, k
++, irqs
[i
].irq
[j
]);
759 static DeviceState
*ppce500_init_mpic_kvm(const PPCE500MachineClass
*pmc
,
760 IrqLines
*irqs
, Error
**errp
)
766 dev
= qdev_create(NULL
, TYPE_KVM_OPENPIC
);
767 qdev_prop_set_uint32(dev
, "model", pmc
->mpic_version
);
769 object_property_set_bool(OBJECT(dev
), true, "realized", &err
);
771 error_propagate(errp
, err
);
772 object_unparent(OBJECT(dev
));
777 if (kvm_openpic_connect_vcpu(dev
, cs
)) {
778 fprintf(stderr
, "%s: failed to connect vcpu to irqchip\n",
787 static DeviceState
*ppce500_init_mpic(PPCE500MachineState
*pms
,
791 MachineState
*machine
= MACHINE(pms
);
792 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
793 DeviceState
*dev
= NULL
;
799 if (machine_kernel_irqchip_allowed(machine
)) {
800 dev
= ppce500_init_mpic_kvm(pmc
, irqs
, &err
);
802 if (machine_kernel_irqchip_required(machine
) && !dev
) {
803 error_reportf_err(err
,
804 "kernel_irqchip requested but unavailable: ");
810 dev
= ppce500_init_mpic_qemu(pms
, irqs
);
813 s
= SYS_BUS_DEVICE(dev
);
814 memory_region_add_subregion(ccsr
, MPC8544_MPIC_REGS_OFFSET
,
820 static void ppce500_power_off(void *opaque
, int line
, int on
)
823 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN
);
827 void ppce500_init(MachineState
*machine
)
829 MemoryRegion
*address_space_mem
= get_system_memory();
830 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
831 PPCE500MachineState
*pms
= PPCE500_MACHINE(machine
);
832 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(machine
);
834 CPUPPCState
*env
= NULL
;
836 hwaddr kernel_base
= -1LL;
839 hwaddr initrd_base
= 0;
843 const char *payload_name
;
844 bool kernel_as_payload
;
845 hwaddr bios_entry
= 0;
846 target_long payload_size
;
847 struct boot_info
*boot_info
;
850 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
852 unsigned int pci_irq_nrs
[PCI_NUM_PINS
] = {1, 2, 3, 4};
854 DeviceState
*dev
, *mpicdev
;
855 CPUPPCState
*firstenv
= NULL
;
856 MemoryRegion
*ccsr_addr_space
;
858 PPCE500CCSRState
*ccsr
;
861 irqs
= g_new0(IrqLines
, smp_cpus
);
862 for (i
= 0; i
< smp_cpus
; i
++) {
867 cpu
= POWERPC_CPU(cpu_create(machine
->cpu_type
));
871 if (env
->mmu_model
!= POWERPC_MMU_BOOKE206
) {
872 error_report("MMU model %i not supported by this machine",
881 input
= (qemu_irq
*)env
->irq_inputs
;
882 irqs
[i
].irq
[OPENPIC_OUTPUT_INT
] = input
[PPCE500_INPUT_INT
];
883 irqs
[i
].irq
[OPENPIC_OUTPUT_CINT
] = input
[PPCE500_INPUT_CINT
];
884 env
->spr_cb
[SPR_BOOKE_PIR
].default_value
= cs
->cpu_index
= i
;
885 env
->mpic_iack
= pmc
->ccsrbar_base
+ MPC8544_MPIC_REGS_OFFSET
+ 0xa0;
887 ppc_booke_timers_init(cpu
, 400000000, PPC_TIMER_E500
);
889 /* Register reset handler */
892 struct boot_info
*boot_info
;
893 boot_info
= g_malloc0(sizeof(struct boot_info
));
894 qemu_register_reset(ppce500_cpu_reset
, cpu
);
895 env
->load_info
= boot_info
;
898 qemu_register_reset(ppce500_cpu_reset_sec
, cpu
);
904 /* Fixup Memory size on a alignment boundary */
905 ram_size
&= ~(RAM_SIZES_ALIGN
- 1);
906 machine
->ram_size
= ram_size
;
908 /* Register Memory */
909 memory_region_allocate_system_memory(ram
, NULL
, "mpc8544ds.ram", ram_size
);
910 memory_region_add_subregion(address_space_mem
, 0, ram
);
912 dev
= qdev_create(NULL
, "e500-ccsr");
913 object_property_add_child(qdev_get_machine(), "e500-ccsr",
915 qdev_init_nofail(dev
);
917 ccsr_addr_space
= &ccsr
->ccsr_space
;
918 memory_region_add_subregion(address_space_mem
, pmc
->ccsrbar_base
,
921 mpicdev
= ppce500_init_mpic(pms
, ccsr_addr_space
, irqs
);
925 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL0_REGS_OFFSET
,
926 0, qdev_get_gpio_in(mpicdev
, 42), 399193,
927 serial_hd(0), DEVICE_BIG_ENDIAN
);
931 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL1_REGS_OFFSET
,
932 0, qdev_get_gpio_in(mpicdev
, 42), 399193,
933 serial_hd(1), DEVICE_BIG_ENDIAN
);
936 dev
= qdev_create(NULL
, "mpc-i2c");
937 s
= SYS_BUS_DEVICE(dev
);
938 qdev_init_nofail(dev
);
939 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(mpicdev
, MPC8544_I2C_IRQ
));
940 memory_region_add_subregion(ccsr_addr_space
, MPC8544_I2C_REGS_OFFSET
,
941 sysbus_mmio_get_region(s
, 0));
942 i2c
= (I2CBus
*)qdev_get_child_bus(dev
, "i2c");
943 i2c_create_slave(i2c
, "ds1338", RTC_REGS_OFFSET
);
946 /* General Utility device */
947 dev
= qdev_create(NULL
, "mpc8544-guts");
948 qdev_init_nofail(dev
);
949 s
= SYS_BUS_DEVICE(dev
);
950 memory_region_add_subregion(ccsr_addr_space
, MPC8544_UTIL_OFFSET
,
951 sysbus_mmio_get_region(s
, 0));
954 dev
= qdev_create(NULL
, "e500-pcihost");
955 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev
),
957 qdev_prop_set_uint32(dev
, "first_slot", pmc
->pci_first_slot
);
958 qdev_prop_set_uint32(dev
, "first_pin_irq", pci_irq_nrs
[0]);
959 qdev_init_nofail(dev
);
960 s
= SYS_BUS_DEVICE(dev
);
961 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
962 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(mpicdev
, pci_irq_nrs
[i
]));
965 memory_region_add_subregion(ccsr_addr_space
, MPC8544_PCI_REGS_OFFSET
,
966 sysbus_mmio_get_region(s
, 0));
968 pci_bus
= (PCIBus
*)qdev_get_child_bus(dev
, "pci.0");
970 printf("couldn't create PCI controller!\n");
973 /* Register network interfaces. */
974 for (i
= 0; i
< nb_nics
; i
++) {
975 pci_nic_init_nofail(&nd_table
[i
], pci_bus
, "virtio-net-pci", NULL
);
979 /* Register spinning region */
980 sysbus_create_simple("e500-spin", pmc
->spin_base
, NULL
);
982 if (pmc
->has_mpc8xxx_gpio
) {
983 qemu_irq poweroff_irq
;
985 dev
= qdev_create(NULL
, "mpc8xxx_gpio");
986 s
= SYS_BUS_DEVICE(dev
);
987 qdev_init_nofail(dev
);
988 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(mpicdev
, MPC8XXX_GPIO_IRQ
));
989 memory_region_add_subregion(ccsr_addr_space
, MPC8XXX_GPIO_OFFSET
,
990 sysbus_mmio_get_region(s
, 0));
992 /* Power Off GPIO at Pin 0 */
993 poweroff_irq
= qemu_allocate_irq(ppce500_power_off
, NULL
, 0);
994 qdev_connect_gpio_out(dev
, 0, poweroff_irq
);
997 /* Platform Bus Device */
998 if (pmc
->has_platform_bus
) {
999 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1000 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1001 qdev_prop_set_uint32(dev
, "num_irqs", pmc
->platform_bus_num_irqs
);
1002 qdev_prop_set_uint32(dev
, "mmio_size", pmc
->platform_bus_size
);
1003 qdev_init_nofail(dev
);
1004 pms
->pbus_dev
= PLATFORM_BUS_DEVICE(dev
);
1006 s
= SYS_BUS_DEVICE(pms
->pbus_dev
);
1007 for (i
= 0; i
< pmc
->platform_bus_num_irqs
; i
++) {
1008 int irqn
= pmc
->platform_bus_first_irq
+ i
;
1009 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(mpicdev
, irqn
));
1012 memory_region_add_subregion(address_space_mem
,
1013 pmc
->platform_bus_base
,
1014 sysbus_mmio_get_region(s
, 0));
1018 * Smart firmware defaults ahead!
1020 * We follow the following table to select which payload we execute.
1022 * -kernel | -bios | payload
1023 * ---------+-------+---------
1029 * This ensures backwards compatibility with how we used to expose
1030 * -kernel to users but allows them to run through u-boot as well.
1032 kernel_as_payload
= false;
1033 if (bios_name
== NULL
) {
1034 if (machine
->kernel_filename
) {
1035 payload_name
= machine
->kernel_filename
;
1036 kernel_as_payload
= true;
1038 payload_name
= "u-boot.e500";
1041 payload_name
= bios_name
;
1044 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, payload_name
);
1046 payload_size
= load_elf(filename
, NULL
, NULL
, NULL
,
1047 &bios_entry
, &loadaddr
, NULL
,
1048 1, PPC_ELF_MACHINE
, 0, 0);
1049 if (payload_size
< 0) {
1051 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
1052 * ePAPR compliant kernel
1054 loadaddr
= LOAD_UIMAGE_LOADADDR_INVALID
;
1055 payload_size
= load_uimage(filename
, &bios_entry
, &loadaddr
, NULL
,
1057 if (payload_size
< 0) {
1058 error_report("could not load firmware '%s'", filename
);
1065 if (kernel_as_payload
) {
1066 kernel_base
= loadaddr
;
1067 kernel_size
= payload_size
;
1070 cur_base
= loadaddr
+ payload_size
;
1071 if (cur_base
< 32 * MiB
) {
1072 /* u-boot occupies memory up to 32MB, so load blobs above */
1073 cur_base
= 32 * MiB
;
1076 /* Load bare kernel only if no bios/u-boot has been provided */
1077 if (machine
->kernel_filename
&& !kernel_as_payload
) {
1078 kernel_base
= cur_base
;
1079 kernel_size
= load_image_targphys(machine
->kernel_filename
,
1081 ram_size
- cur_base
);
1082 if (kernel_size
< 0) {
1083 error_report("could not load kernel '%s'",
1084 machine
->kernel_filename
);
1088 cur_base
+= kernel_size
;
1092 if (machine
->initrd_filename
) {
1093 initrd_base
= (cur_base
+ INITRD_LOAD_PAD
) & ~INITRD_PAD_MASK
;
1094 initrd_size
= load_image_targphys(machine
->initrd_filename
, initrd_base
,
1095 ram_size
- initrd_base
);
1097 if (initrd_size
< 0) {
1098 error_report("could not load initial ram disk '%s'",
1099 machine
->initrd_filename
);
1103 cur_base
= initrd_base
+ initrd_size
;
1107 * Reserve space for dtb behind the kernel image because Linux has a bug
1108 * where it can only handle the dtb if it's within the first 64MB of where
1109 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD
1110 * ensures enough space between kernel and initrd.
1112 dt_base
= (loadaddr
+ payload_size
+ DTC_LOAD_PAD
) & ~DTC_PAD_MASK
;
1113 if (dt_base
+ DTB_MAX_SIZE
> ram_size
) {
1114 error_report("not enough memory for device tree");
1118 dt_size
= ppce500_prep_device_tree(pms
, dt_base
,
1119 initrd_base
, initrd_size
,
1120 kernel_base
, kernel_size
);
1122 error_report("couldn't load device tree");
1125 assert(dt_size
< DTB_MAX_SIZE
);
1127 boot_info
= env
->load_info
;
1128 boot_info
->entry
= bios_entry
;
1129 boot_info
->dt_base
= dt_base
;
1130 boot_info
->dt_size
= dt_size
;
1133 static void e500_ccsr_initfn(Object
*obj
)
1135 PPCE500CCSRState
*ccsr
= CCSR(obj
);
1136 memory_region_init(&ccsr
->ccsr_space
, obj
, "e500-ccsr",
1137 MPC8544_CCSRBAR_SIZE
);
1140 static const TypeInfo e500_ccsr_info
= {
1142 .parent
= TYPE_SYS_BUS_DEVICE
,
1143 .instance_size
= sizeof(PPCE500CCSRState
),
1144 .instance_init
= e500_ccsr_initfn
,
1147 static const TypeInfo ppce500_info
= {
1148 .name
= TYPE_PPCE500_MACHINE
,
1149 .parent
= TYPE_MACHINE
,
1151 .instance_size
= sizeof(PPCE500MachineState
),
1152 .class_size
= sizeof(PPCE500MachineClass
),
1155 static void e500_register_types(void)
1157 type_register_static(&e500_ccsr_info
);
1158 type_register_static(&ppce500_info
);
1161 type_init(e500_register_types
)