2 * PPC4xx I2C controller emulation
4 * Copyright (c) 2007 Jocelyn Mayer
5 * Copyright (c) 2012 François Revol
6 * Copyright (c) 2016-2018 BALATON Zoltan
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
29 #include "qemu/module.h"
31 #include "hw/i2c/ppc4xx_i2c.h"
34 #define PPC4xx_I2C_MEM_SIZE 18
55 #define IIC_CNTL_PT (1 << 0)
56 #define IIC_CNTL_READ (1 << 1)
57 #define IIC_CNTL_CHT (1 << 2)
58 #define IIC_CNTL_RPST (1 << 3)
59 #define IIC_CNTL_AMD (1 << 6)
60 #define IIC_CNTL_HMT (1 << 7)
62 #define IIC_MDCNTL_EINT (1 << 2)
63 #define IIC_MDCNTL_ESM (1 << 3)
64 #define IIC_MDCNTL_FMDB (1 << 6)
66 #define IIC_STS_PT (1 << 0)
67 #define IIC_STS_IRQA (1 << 1)
68 #define IIC_STS_ERR (1 << 2)
69 #define IIC_STS_MDBF (1 << 4)
70 #define IIC_STS_MDBS (1 << 5)
72 #define IIC_EXTSTS_XFRA (1 << 0)
73 #define IIC_EXTSTS_BCS_FREE (4 << 4)
74 #define IIC_EXTSTS_BCS_BUSY (5 << 4)
76 #define IIC_INTRMSK_EIMTC (1 << 0)
77 #define IIC_INTRMSK_EITA (1 << 1)
78 #define IIC_INTRMSK_EIIC (1 << 2)
79 #define IIC_INTRMSK_EIHE (1 << 3)
81 #define IIC_XTCNTLSS_SRST (1 << 0)
83 #define IIC_DIRECTCNTL_SDAC (1 << 3)
84 #define IIC_DIRECTCNTL_SCLC (1 << 2)
85 #define IIC_DIRECTCNTL_MSDA (1 << 1)
86 #define IIC_DIRECTCNTL_MSCL (1 << 0)
88 static void ppc4xx_i2c_reset(DeviceState
*s
)
90 PPC4xxI2CState
*i2c
= PPC4xx_I2C(s
);
93 memset(i2c
->mdata
, 0, ARRAY_SIZE(i2c
->mdata
));
94 /* [hl][ms]addr are not affected by reset */
98 i2c
->extsts
= IIC_EXTSTS_BCS_FREE
;
103 i2c
->directcntl
= 0xf; /* all non-reserved bits set */
106 static uint64_t ppc4xx_i2c_readb(void *opaque
, hwaddr addr
, unsigned int size
)
108 PPC4xxI2CState
*i2c
= PPC4xx_I2C(opaque
);
114 if (i2c
->mdidx
< 0) {
119 if (i2c
->mdidx
== 3) {
120 i2c
->sts
&= ~IIC_STS_MDBF
;
121 } else if (i2c
->mdidx
== 0) {
122 i2c
->sts
&= ~IIC_STS_MDBS
;
124 for (i
= 0; i
< i2c
->mdidx
; i
++) {
125 i2c
->mdata
[i
] = i2c
->mdata
[i
+ 1];
127 if (i2c
->mdidx
>= 0) {
147 ret
= i2c_bus_busy(i2c
->bus
) ?
148 IIC_EXTSTS_BCS_BUSY
: IIC_EXTSTS_BCS_FREE
;
169 ret
= i2c
->directcntl
;
172 if (addr
< PPC4xx_I2C_MEM_SIZE
) {
173 qemu_log_mask(LOG_UNIMP
, "%s: Unimplemented register 0x%"
174 HWADDR_PRIx
"\n", __func__
, addr
);
176 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address 0x%"
177 HWADDR_PRIx
"\n", __func__
, addr
);
185 static void ppc4xx_i2c_writeb(void *opaque
, hwaddr addr
, uint64_t value
,
188 PPC4xxI2CState
*i2c
= opaque
;
192 if (i2c
->mdidx
>= 3) {
195 i2c
->mdata
[++i2c
->mdidx
] = value
;
196 if (i2c
->mdidx
== 3) {
197 i2c
->sts
|= IIC_STS_MDBF
;
198 } else if (i2c
->mdidx
== 0) {
199 i2c
->sts
|= IIC_STS_MDBS
;
209 i2c
->cntl
= value
& ~IIC_CNTL_PT
;
210 if (value
& IIC_CNTL_AMD
) {
211 qemu_log_mask(LOG_UNIMP
, "%s: only 7 bit addresses supported\n",
214 if (value
& IIC_CNTL_HMT
&& i2c_bus_busy(i2c
->bus
)) {
215 i2c_end_transfer(i2c
->bus
);
216 if (i2c
->mdcntl
& IIC_MDCNTL_EINT
&&
217 i2c
->intrmsk
& IIC_INTRMSK_EIHE
) {
218 i2c
->sts
|= IIC_STS_IRQA
;
219 qemu_irq_raise(i2c
->irq
);
221 } else if (value
& IIC_CNTL_PT
) {
222 int recv
= (value
& IIC_CNTL_READ
) >> 1;
223 int tct
= value
>> 4 & 3;
226 if (recv
&& (i2c
->lmadr
>> 1) >= 0x50 && (i2c
->lmadr
>> 1) < 0x58) {
227 /* smbus emulation does not like multi byte reads w/o restart */
228 value
|= IIC_CNTL_RPST
;
231 for (i
= 0; i
<= tct
; i
++) {
232 if (!i2c_bus_busy(i2c
->bus
)) {
233 i2c
->extsts
= IIC_EXTSTS_BCS_FREE
;
234 if (i2c_start_transfer(i2c
->bus
, i2c
->lmadr
>> 1, recv
)) {
235 i2c
->sts
|= IIC_STS_ERR
;
236 i2c
->extsts
|= IIC_EXTSTS_XFRA
;
239 i2c
->sts
&= ~IIC_STS_ERR
;
242 if (!(i2c
->sts
& IIC_STS_ERR
) &&
243 i2c_send_recv(i2c
->bus
, &i2c
->mdata
[i
], !recv
)) {
244 i2c
->sts
|= IIC_STS_ERR
;
245 i2c
->extsts
|= IIC_EXTSTS_XFRA
;
248 if (value
& IIC_CNTL_RPST
|| !(value
& IIC_CNTL_CHT
)) {
249 i2c_end_transfer(i2c
->bus
);
254 if (recv
&& i2c
->mdidx
>= 0) {
255 i2c
->sts
|= IIC_STS_MDBS
;
257 if (recv
&& i2c
->mdidx
== 3) {
258 i2c
->sts
|= IIC_STS_MDBF
;
260 if (i
&& i2c
->mdcntl
& IIC_MDCNTL_EINT
&&
261 i2c
->intrmsk
& IIC_INTRMSK_EIMTC
) {
262 i2c
->sts
|= IIC_STS_IRQA
;
263 qemu_irq_raise(i2c
->irq
);
268 i2c
->mdcntl
= value
& 0x3d;
269 if (value
& IIC_MDCNTL_ESM
) {
270 qemu_log_mask(LOG_UNIMP
, "%s: slave mode not implemented\n",
273 if (value
& IIC_MDCNTL_FMDB
) {
275 memset(i2c
->mdata
, 0, ARRAY_SIZE(i2c
->mdata
));
276 i2c
->sts
&= ~(IIC_STS_MDBF
| IIC_STS_MDBS
);
280 i2c
->sts
&= ~(value
& 0x0a);
281 if (value
& IIC_STS_IRQA
&& i2c
->mdcntl
& IIC_MDCNTL_EINT
) {
282 qemu_irq_lower(i2c
->irq
);
286 i2c
->extsts
&= ~(value
& 0x8f);
298 i2c
->intrmsk
= value
;
301 i2c
->xfrcnt
= value
& 0x77;
304 i2c
->xtcntlss
&= ~(value
& 0xf0);
305 if (value
& IIC_XTCNTLSS_SRST
) {
306 /* Is it actually a full reset? U-Boot sets some regs before */
307 ppc4xx_i2c_reset(DEVICE(i2c
));
312 i2c
->directcntl
= value
& (IIC_DIRECTCNTL_SDAC
& IIC_DIRECTCNTL_SCLC
);
313 i2c
->directcntl
|= (value
& IIC_DIRECTCNTL_SCLC
? 1 : 0);
314 bitbang_i2c_set(&i2c
->bitbang
, BITBANG_I2C_SCL
,
315 i2c
->directcntl
& IIC_DIRECTCNTL_MSCL
);
316 i2c
->directcntl
|= bitbang_i2c_set(&i2c
->bitbang
, BITBANG_I2C_SDA
,
317 (value
& IIC_DIRECTCNTL_SDAC
) != 0) << 1;
320 if (addr
< PPC4xx_I2C_MEM_SIZE
) {
321 qemu_log_mask(LOG_UNIMP
, "%s: Unimplemented register 0x%"
322 HWADDR_PRIx
"\n", __func__
, addr
);
324 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address 0x%"
325 HWADDR_PRIx
"\n", __func__
, addr
);
331 static const MemoryRegionOps ppc4xx_i2c_ops
= {
332 .read
= ppc4xx_i2c_readb
,
333 .write
= ppc4xx_i2c_writeb
,
334 .valid
.min_access_size
= 1,
335 .valid
.max_access_size
= 4,
336 .impl
.min_access_size
= 1,
337 .impl
.max_access_size
= 1,
338 .endianness
= DEVICE_NATIVE_ENDIAN
,
341 static void ppc4xx_i2c_init(Object
*o
)
343 PPC4xxI2CState
*s
= PPC4xx_I2C(o
);
345 memory_region_init_io(&s
->iomem
, OBJECT(s
), &ppc4xx_i2c_ops
, s
,
346 TYPE_PPC4xx_I2C
, PPC4xx_I2C_MEM_SIZE
);
347 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->iomem
);
348 sysbus_init_irq(SYS_BUS_DEVICE(s
), &s
->irq
);
349 s
->bus
= i2c_init_bus(DEVICE(s
), "i2c");
350 bitbang_i2c_init(&s
->bitbang
, s
->bus
);
353 static void ppc4xx_i2c_class_init(ObjectClass
*klass
, void *data
)
355 DeviceClass
*dc
= DEVICE_CLASS(klass
);
357 dc
->reset
= ppc4xx_i2c_reset
;
360 static const TypeInfo ppc4xx_i2c_type_info
= {
361 .name
= TYPE_PPC4xx_I2C
,
362 .parent
= TYPE_SYS_BUS_DEVICE
,
363 .instance_size
= sizeof(PPC4xxI2CState
),
364 .instance_init
= ppc4xx_i2c_init
,
365 .class_init
= ppc4xx_i2c_class_init
,
368 static void ppc4xx_i2c_register_types(void)
370 type_register_static(&ppc4xx_i2c_type_info
);
373 type_init(ppc4xx_i2c_register_types
)