2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/char/parallel.h"
30 #include "hw/i386/apic.h"
31 #include "hw/i386/topology.h"
32 #include "sysemu/cpus.h"
33 #include "hw/block/fdc.h"
35 #include "hw/pci/pci.h"
36 #include "hw/pci/pci_bus.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/timer/hpet.h"
39 #include "hw/smbios/smbios.h"
40 #include "hw/loader.h"
42 #include "multiboot.h"
43 #include "hw/timer/mc146818rtc.h"
44 #include "hw/timer/i8254.h"
45 #include "hw/audio/pcspk.h"
46 #include "hw/pci/msi.h"
47 #include "hw/sysbus.h"
48 #include "sysemu/sysemu.h"
49 #include "sysemu/numa.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/qtest.h"
53 #include "hw/xen/xen.h"
54 #include "ui/qemu-spice.h"
55 #include "exec/memory.h"
56 #include "exec/address-spaces.h"
57 #include "sysemu/arch_init.h"
58 #include "qemu/bitmap.h"
59 #include "qemu/config-file.h"
60 #include "qemu/error-report.h"
61 #include "qemu/option.h"
62 #include "hw/acpi/acpi.h"
63 #include "hw/acpi/cpu_hotplug.h"
64 #include "hw/boards.h"
65 #include "hw/pci/pci_host.h"
66 #include "acpi-build.h"
67 #include "hw/mem/pc-dimm.h"
68 #include "qapi/error.h"
69 #include "qapi/qapi-visit-common.h"
70 #include "qapi/visitor.h"
73 #include "hw/i386/intel_iommu.h"
74 #include "hw/net/ne2000-isa.h"
76 /* debug PC/ISA interrupts */
80 #define DPRINTF(fmt, ...) \
81 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
83 #define DPRINTF(fmt, ...)
86 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
87 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
88 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
89 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
90 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
92 #define E820_NR_ENTRIES 16
98 } QEMU_PACKED
__attribute((__aligned__(4)));
102 struct e820_entry entry
[E820_NR_ENTRIES
];
103 } QEMU_PACKED
__attribute((__aligned__(4)));
105 static struct e820_table e820_reserve
;
106 static struct e820_entry
*e820_table
;
107 static unsigned e820_entries
;
108 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
110 void gsi_handler(void *opaque
, int n
, int level
)
112 GSIState
*s
= opaque
;
114 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
115 if (n
< ISA_NUM_IRQS
) {
116 qemu_set_irq(s
->i8259_irq
[n
], level
);
118 qemu_set_irq(s
->ioapic_irq
[n
], level
);
121 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
126 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
128 return 0xffffffffffffffffULL
;
131 /* MSDOS compatibility mode FPU exception support */
132 static qemu_irq ferr_irq
;
134 void pc_register_ferr_irq(qemu_irq irq
)
139 /* XXX: add IGNNE support */
140 void cpu_set_ferr(CPUX86State
*s
)
142 qemu_irq_raise(ferr_irq
);
145 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
148 qemu_irq_lower(ferr_irq
);
151 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
153 return 0xffffffffffffffffULL
;
157 uint64_t cpu_get_tsc(CPUX86State
*env
)
159 return cpu_get_ticks();
163 int cpu_get_pic_interrupt(CPUX86State
*env
)
165 X86CPU
*cpu
= x86_env_get_cpu(env
);
168 if (!kvm_irqchip_in_kernel()) {
169 intno
= apic_get_interrupt(cpu
->apic_state
);
173 /* read the irq from the PIC */
174 if (!apic_accept_pic_intr(cpu
->apic_state
)) {
179 intno
= pic_read_irq(isa_pic
);
183 static void pic_irq_request(void *opaque
, int irq
, int level
)
185 CPUState
*cs
= first_cpu
;
186 X86CPU
*cpu
= X86_CPU(cs
);
188 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
189 if (cpu
->apic_state
&& !kvm_irqchip_in_kernel()) {
192 if (apic_accept_pic_intr(cpu
->apic_state
)) {
193 apic_deliver_pic_intr(cpu
->apic_state
, level
);
198 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
200 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
205 /* PC cmos mappings */
207 #define REG_EQUIPMENT_BYTE 0x14
209 int cmos_get_fd_drive_type(FloppyDriveType fd0
)
214 case FLOPPY_DRIVE_TYPE_144
:
215 /* 1.44 Mb 3"5 drive */
218 case FLOPPY_DRIVE_TYPE_288
:
219 /* 2.88 Mb 3"5 drive */
222 case FLOPPY_DRIVE_TYPE_120
:
223 /* 1.2 Mb 5"5 drive */
226 case FLOPPY_DRIVE_TYPE_NONE
:
234 static void cmos_init_hd(ISADevice
*s
, int type_ofs
, int info_ofs
,
235 int16_t cylinders
, int8_t heads
, int8_t sectors
)
237 rtc_set_memory(s
, type_ofs
, 47);
238 rtc_set_memory(s
, info_ofs
, cylinders
);
239 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
240 rtc_set_memory(s
, info_ofs
+ 2, heads
);
241 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
242 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
243 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
244 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
245 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
246 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
249 /* convert boot_device letter to something recognizable by the bios */
250 static int boot_device2nibble(char boot_device
)
252 switch(boot_device
) {
255 return 0x01; /* floppy boot */
257 return 0x02; /* hard drive boot */
259 return 0x03; /* CD-ROM boot */
261 return 0x04; /* Network boot */
266 static void set_boot_dev(ISADevice
*s
, const char *boot_device
, Error
**errp
)
268 #define PC_MAX_BOOT_DEVICES 3
269 int nbds
, bds
[3] = { 0, };
272 nbds
= strlen(boot_device
);
273 if (nbds
> PC_MAX_BOOT_DEVICES
) {
274 error_setg(errp
, "Too many boot devices for PC");
277 for (i
= 0; i
< nbds
; i
++) {
278 bds
[i
] = boot_device2nibble(boot_device
[i
]);
280 error_setg(errp
, "Invalid boot device for PC: '%c'",
285 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
286 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
289 static void pc_boot_set(void *opaque
, const char *boot_device
, Error
**errp
)
291 set_boot_dev(opaque
, boot_device
, errp
);
294 static void pc_cmos_init_floppy(ISADevice
*rtc_state
, ISADevice
*floppy
)
297 FloppyDriveType fd_type
[2] = { FLOPPY_DRIVE_TYPE_NONE
,
298 FLOPPY_DRIVE_TYPE_NONE
};
302 for (i
= 0; i
< 2; i
++) {
303 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
306 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
307 cmos_get_fd_drive_type(fd_type
[1]);
308 rtc_set_memory(rtc_state
, 0x10, val
);
310 val
= rtc_get_memory(rtc_state
, REG_EQUIPMENT_BYTE
);
312 if (fd_type
[0] != FLOPPY_DRIVE_TYPE_NONE
) {
315 if (fd_type
[1] != FLOPPY_DRIVE_TYPE_NONE
) {
322 val
|= 0x01; /* 1 drive, ready for boot */
325 val
|= 0x41; /* 2 drives, ready for boot */
328 rtc_set_memory(rtc_state
, REG_EQUIPMENT_BYTE
, val
);
331 typedef struct pc_cmos_init_late_arg
{
332 ISADevice
*rtc_state
;
334 } pc_cmos_init_late_arg
;
336 typedef struct check_fdc_state
{
341 static int check_fdc(Object
*obj
, void *opaque
)
343 CheckFdcState
*state
= opaque
;
346 Error
*local_err
= NULL
;
348 fdc
= object_dynamic_cast(obj
, TYPE_ISA_FDC
);
353 iobase
= object_property_get_uint(obj
, "iobase", &local_err
);
354 if (local_err
|| iobase
!= 0x3f0) {
355 error_free(local_err
);
360 state
->multiple
= true;
362 state
->floppy
= ISA_DEVICE(obj
);
367 static const char * const fdc_container_path
[] = {
368 "/unattached", "/peripheral", "/peripheral-anon"
372 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
375 ISADevice
*pc_find_fdc0(void)
379 CheckFdcState state
= { 0 };
381 for (i
= 0; i
< ARRAY_SIZE(fdc_container_path
); i
++) {
382 container
= container_get(qdev_get_machine(), fdc_container_path
[i
]);
383 object_child_foreach(container
, check_fdc
, &state
);
386 if (state
.multiple
) {
387 warn_report("multiple floppy disk controllers with "
388 "iobase=0x3f0 have been found");
389 error_printf("the one being picked for CMOS setup might not reflect "
396 static void pc_cmos_init_late(void *opaque
)
398 pc_cmos_init_late_arg
*arg
= opaque
;
399 ISADevice
*s
= arg
->rtc_state
;
401 int8_t heads
, sectors
;
406 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 0,
407 &cylinders
, &heads
, §ors
) >= 0) {
408 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
411 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 1,
412 &cylinders
, &heads
, §ors
) >= 0) {
413 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
416 rtc_set_memory(s
, 0x12, val
);
419 for (i
= 0; i
< 4; i
++) {
420 /* NOTE: ide_get_geometry() returns the physical
421 geometry. It is always such that: 1 <= sects <= 63, 1
422 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
423 geometry can be different if a translation is done. */
424 if (arg
->idebus
[i
/ 2] &&
425 ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
426 &cylinders
, &heads
, §ors
) >= 0) {
427 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
428 assert((trans
& ~3) == 0);
429 val
|= trans
<< (i
* 2);
432 rtc_set_memory(s
, 0x39, val
);
434 pc_cmos_init_floppy(s
, pc_find_fdc0());
436 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
439 void pc_cmos_init(PCMachineState
*pcms
,
440 BusState
*idebus0
, BusState
*idebus1
,
444 static pc_cmos_init_late_arg arg
;
446 /* various important CMOS locations needed by PC/Bochs bios */
449 /* base memory (first MiB) */
450 val
= MIN(pcms
->below_4g_mem_size
/ 1024, 640);
451 rtc_set_memory(s
, 0x15, val
);
452 rtc_set_memory(s
, 0x16, val
>> 8);
453 /* extended memory (next 64MiB) */
454 if (pcms
->below_4g_mem_size
> 1024 * 1024) {
455 val
= (pcms
->below_4g_mem_size
- 1024 * 1024) / 1024;
461 rtc_set_memory(s
, 0x17, val
);
462 rtc_set_memory(s
, 0x18, val
>> 8);
463 rtc_set_memory(s
, 0x30, val
);
464 rtc_set_memory(s
, 0x31, val
>> 8);
465 /* memory between 16MiB and 4GiB */
466 if (pcms
->below_4g_mem_size
> 16 * 1024 * 1024) {
467 val
= (pcms
->below_4g_mem_size
- 16 * 1024 * 1024) / 65536;
473 rtc_set_memory(s
, 0x34, val
);
474 rtc_set_memory(s
, 0x35, val
>> 8);
475 /* memory above 4GiB */
476 val
= pcms
->above_4g_mem_size
/ 65536;
477 rtc_set_memory(s
, 0x5b, val
);
478 rtc_set_memory(s
, 0x5c, val
>> 8);
479 rtc_set_memory(s
, 0x5d, val
>> 16);
481 object_property_add_link(OBJECT(pcms
), "rtc_state",
483 (Object
**)&pcms
->rtc
,
484 object_property_allow_set_link
,
485 OBJ_PROP_LINK_UNREF_ON_RELEASE
, &error_abort
);
486 object_property_set_link(OBJECT(pcms
), OBJECT(s
),
487 "rtc_state", &error_abort
);
489 set_boot_dev(s
, MACHINE(pcms
)->boot_order
, &error_fatal
);
492 val
|= 0x02; /* FPU is there */
493 val
|= 0x04; /* PS/2 mouse installed */
494 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
496 /* hard drives and FDC */
498 arg
.idebus
[0] = idebus0
;
499 arg
.idebus
[1] = idebus1
;
500 qemu_register_reset(pc_cmos_init_late
, &arg
);
503 #define TYPE_PORT92 "port92"
504 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
506 /* port 92 stuff: could be split off */
507 typedef struct Port92State
{
508 ISADevice parent_obj
;
515 static void port92_write(void *opaque
, hwaddr addr
, uint64_t val
,
518 Port92State
*s
= opaque
;
519 int oldval
= s
->outport
;
521 DPRINTF("port92: write 0x%02" PRIx64
"\n", val
);
523 qemu_set_irq(s
->a20_out
, (val
>> 1) & 1);
524 if ((val
& 1) && !(oldval
& 1)) {
525 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
529 static uint64_t port92_read(void *opaque
, hwaddr addr
,
532 Port92State
*s
= opaque
;
536 DPRINTF("port92: read 0x%02x\n", ret
);
540 static void port92_init(ISADevice
*dev
, qemu_irq a20_out
)
542 qdev_connect_gpio_out_named(DEVICE(dev
), PORT92_A20_LINE
, 0, a20_out
);
545 static const VMStateDescription vmstate_port92_isa
= {
548 .minimum_version_id
= 1,
549 .fields
= (VMStateField
[]) {
550 VMSTATE_UINT8(outport
, Port92State
),
551 VMSTATE_END_OF_LIST()
555 static void port92_reset(DeviceState
*d
)
557 Port92State
*s
= PORT92(d
);
562 static const MemoryRegionOps port92_ops
= {
564 .write
= port92_write
,
566 .min_access_size
= 1,
567 .max_access_size
= 1,
569 .endianness
= DEVICE_LITTLE_ENDIAN
,
572 static void port92_initfn(Object
*obj
)
574 Port92State
*s
= PORT92(obj
);
576 memory_region_init_io(&s
->io
, OBJECT(s
), &port92_ops
, s
, "port92", 1);
580 qdev_init_gpio_out_named(DEVICE(obj
), &s
->a20_out
, PORT92_A20_LINE
, 1);
583 static void port92_realizefn(DeviceState
*dev
, Error
**errp
)
585 ISADevice
*isadev
= ISA_DEVICE(dev
);
586 Port92State
*s
= PORT92(dev
);
588 isa_register_ioport(isadev
, &s
->io
, 0x92);
591 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
593 DeviceClass
*dc
= DEVICE_CLASS(klass
);
595 dc
->realize
= port92_realizefn
;
596 dc
->reset
= port92_reset
;
597 dc
->vmsd
= &vmstate_port92_isa
;
599 * Reason: unlike ordinary ISA devices, this one needs additional
600 * wiring: its A20 output line needs to be wired up by
603 dc
->user_creatable
= false;
606 static const TypeInfo port92_info
= {
608 .parent
= TYPE_ISA_DEVICE
,
609 .instance_size
= sizeof(Port92State
),
610 .instance_init
= port92_initfn
,
611 .class_init
= port92_class_initfn
,
614 static void port92_register_types(void)
616 type_register_static(&port92_info
);
619 type_init(port92_register_types
)
621 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
623 X86CPU
*cpu
= opaque
;
625 /* XXX: send to all CPUs ? */
626 /* XXX: add logic to handle multiple A20 line sources */
627 x86_cpu_set_a20(cpu
, level
);
630 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
632 int index
= le32_to_cpu(e820_reserve
.count
);
633 struct e820_entry
*entry
;
635 if (type
!= E820_RAM
) {
636 /* old FW_CFG_E820_TABLE entry -- reservations only */
637 if (index
>= E820_NR_ENTRIES
) {
640 entry
= &e820_reserve
.entry
[index
++];
642 entry
->address
= cpu_to_le64(address
);
643 entry
->length
= cpu_to_le64(length
);
644 entry
->type
= cpu_to_le32(type
);
646 e820_reserve
.count
= cpu_to_le32(index
);
649 /* new "etc/e820" file -- include ram too */
650 e820_table
= g_renew(struct e820_entry
, e820_table
, e820_entries
+ 1);
651 e820_table
[e820_entries
].address
= cpu_to_le64(address
);
652 e820_table
[e820_entries
].length
= cpu_to_le64(length
);
653 e820_table
[e820_entries
].type
= cpu_to_le32(type
);
659 int e820_get_num_entries(void)
664 bool e820_get_entry(int idx
, uint32_t type
, uint64_t *address
, uint64_t *length
)
666 if (idx
< e820_entries
&& e820_table
[idx
].type
== cpu_to_le32(type
)) {
667 *address
= le64_to_cpu(e820_table
[idx
].address
);
668 *length
= le64_to_cpu(e820_table
[idx
].length
);
674 /* Enables contiguous-apic-ID mode, for compatibility */
675 static bool compat_apic_id_mode
;
677 void enable_compat_apic_id_mode(void)
679 compat_apic_id_mode
= true;
682 /* Calculates initial APIC ID for a specific CPU index
684 * Currently we need to be able to calculate the APIC ID from the CPU index
685 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
686 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
687 * all CPUs up to max_cpus.
689 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index
)
694 correct_id
= x86_apicid_from_cpu_idx(smp_cores
, smp_threads
, cpu_index
);
695 if (compat_apic_id_mode
) {
696 if (cpu_index
!= correct_id
&& !warned
&& !qtest_enabled()) {
697 error_report("APIC IDs set in compatibility mode, "
698 "CPU topology won't match the configuration");
707 static void pc_build_smbios(PCMachineState
*pcms
)
709 uint8_t *smbios_tables
, *smbios_anchor
;
710 size_t smbios_tables_len
, smbios_anchor_len
;
711 struct smbios_phys_mem_area
*mem_array
;
712 unsigned i
, array_count
;
713 MachineState
*ms
= MACHINE(pcms
);
714 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
716 /* tell smbios about cpuid version and features */
717 smbios_set_cpuid(cpu
->env
.cpuid_version
, cpu
->env
.features
[FEAT_1_EDX
]);
719 smbios_tables
= smbios_get_table_legacy(&smbios_tables_len
);
721 fw_cfg_add_bytes(pcms
->fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
722 smbios_tables
, smbios_tables_len
);
725 /* build the array of physical mem area from e820 table */
726 mem_array
= g_malloc0(sizeof(*mem_array
) * e820_get_num_entries());
727 for (i
= 0, array_count
= 0; i
< e820_get_num_entries(); i
++) {
730 if (e820_get_entry(i
, E820_RAM
, &addr
, &len
)) {
731 mem_array
[array_count
].address
= addr
;
732 mem_array
[array_count
].length
= len
;
736 smbios_get_tables(mem_array
, array_count
,
737 &smbios_tables
, &smbios_tables_len
,
738 &smbios_anchor
, &smbios_anchor_len
);
742 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-tables",
743 smbios_tables
, smbios_tables_len
);
744 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-anchor",
745 smbios_anchor
, smbios_anchor_len
);
749 static FWCfgState
*bochs_bios_init(AddressSpace
*as
, PCMachineState
*pcms
)
752 uint64_t *numa_fw_cfg
;
754 const CPUArchIdList
*cpus
;
755 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
757 fw_cfg
= fw_cfg_init_io_dma(FW_CFG_IO_BASE
, FW_CFG_IO_BASE
+ 4, as
);
758 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
760 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
762 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
763 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
764 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
765 * for CPU hotplug also uses APIC ID and not "CPU index".
766 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
767 * but the "limit to the APIC ID values SeaBIOS may see".
769 * So for compatibility reasons with old BIOSes we are stuck with
770 * "etc/max-cpus" actually being apic_id_limit
772 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)pcms
->apic_id_limit
);
773 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
774 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
,
775 acpi_tables
, acpi_tables_len
);
776 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
778 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
,
779 &e820_reserve
, sizeof(e820_reserve
));
780 fw_cfg_add_file(fw_cfg
, "etc/e820", e820_table
,
781 sizeof(struct e820_entry
) * e820_entries
);
783 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, &hpet_cfg
, sizeof(hpet_cfg
));
784 /* allocate memory for the NUMA channel: one (64bit) word for the number
785 * of nodes, one word for each VCPU->node and one word for each node to
786 * hold the amount of memory.
788 numa_fw_cfg
= g_new0(uint64_t, 1 + pcms
->apic_id_limit
+ nb_numa_nodes
);
789 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
790 cpus
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
791 for (i
= 0; i
< cpus
->len
; i
++) {
792 unsigned int apic_id
= cpus
->cpus
[i
].arch_id
;
793 assert(apic_id
< pcms
->apic_id_limit
);
794 numa_fw_cfg
[apic_id
+ 1] = cpu_to_le64(cpus
->cpus
[i
].props
.node_id
);
796 for (i
= 0; i
< nb_numa_nodes
; i
++) {
797 numa_fw_cfg
[pcms
->apic_id_limit
+ 1 + i
] =
798 cpu_to_le64(numa_info
[i
].node_mem
);
800 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, numa_fw_cfg
,
801 (1 + pcms
->apic_id_limit
+ nb_numa_nodes
) *
802 sizeof(*numa_fw_cfg
));
807 static long get_file_size(FILE *f
)
811 /* XXX: on Unix systems, using fstat() probably makes more sense */
814 fseek(f
, 0, SEEK_END
);
816 fseek(f
, where
, SEEK_SET
);
821 /* setup_data types */
823 #define SETUP_E820_EXT 1
833 } __attribute__((packed
));
835 static void load_linux(PCMachineState
*pcms
,
839 int setup_size
, kernel_size
, initrd_size
= 0, cmdline_size
;
840 int dtb_size
, setup_data_offset
;
842 uint8_t header
[8192], *setup
, *kernel
, *initrd_data
;
843 hwaddr real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
846 MachineState
*machine
= MACHINE(pcms
);
847 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
848 struct setup_data
*setup_data
;
849 const char *kernel_filename
= machine
->kernel_filename
;
850 const char *initrd_filename
= machine
->initrd_filename
;
851 const char *dtb_filename
= machine
->dtb
;
852 const char *kernel_cmdline
= machine
->kernel_cmdline
;
854 /* Align to 16 bytes as a paranoia measure */
855 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
857 /* load the kernel header */
858 f
= fopen(kernel_filename
, "rb");
859 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
860 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
861 MIN(ARRAY_SIZE(header
), kernel_size
)) {
862 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
863 kernel_filename
, strerror(errno
));
867 /* kernel protocol version */
869 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
871 if (ldl_p(header
+0x202) == 0x53726448) {
872 protocol
= lduw_p(header
+0x206);
874 /* This looks like a multiboot kernel. If it is, let's stop
875 treating it like a Linux kernel. */
876 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
877 kernel_cmdline
, kernel_size
, header
)) {
883 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
886 cmdline_addr
= 0x9a000 - cmdline_size
;
888 } else if (protocol
< 0x202) {
889 /* High but ancient kernel */
891 cmdline_addr
= 0x9a000 - cmdline_size
;
892 prot_addr
= 0x100000;
894 /* High and recent kernel */
896 cmdline_addr
= 0x20000;
897 prot_addr
= 0x100000;
902 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
903 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
904 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
910 /* highest address for loading the initrd */
911 if (protocol
>= 0x203) {
912 initrd_max
= ldl_p(header
+0x22c);
914 initrd_max
= 0x37ffffff;
917 if (initrd_max
>= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
) {
918 initrd_max
= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
- 1;
921 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
922 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
923 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
925 if (protocol
>= 0x202) {
926 stl_p(header
+0x228, cmdline_addr
);
928 stw_p(header
+0x20, 0xA33F);
929 stw_p(header
+0x22, cmdline_addr
-real_addr
);
932 /* handle vga= parameter */
933 vmode
= strstr(kernel_cmdline
, "vga=");
935 unsigned int video_mode
;
938 if (!strncmp(vmode
, "normal", 6)) {
940 } else if (!strncmp(vmode
, "ext", 3)) {
942 } else if (!strncmp(vmode
, "ask", 3)) {
945 video_mode
= strtol(vmode
, NULL
, 0);
947 stw_p(header
+0x1fa, video_mode
);
951 /* High nybble = B reserved for QEMU; low nybble is revision number.
952 If this code is substantially changed, you may want to consider
953 incrementing the revision. */
954 if (protocol
>= 0x200) {
955 header
[0x210] = 0xB0;
958 if (protocol
>= 0x201) {
959 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
960 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
964 if (initrd_filename
) {
965 if (protocol
< 0x200) {
966 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
970 initrd_size
= get_image_size(initrd_filename
);
971 if (initrd_size
< 0) {
972 fprintf(stderr
, "qemu: error reading initrd %s: %s\n",
973 initrd_filename
, strerror(errno
));
977 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
979 initrd_data
= g_malloc(initrd_size
);
980 load_image(initrd_filename
, initrd_data
);
982 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
983 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
984 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
986 stl_p(header
+0x218, initrd_addr
);
987 stl_p(header
+0x21c, initrd_size
);
990 /* load kernel and setup */
991 setup_size
= header
[0x1f1];
992 if (setup_size
== 0) {
995 setup_size
= (setup_size
+1)*512;
996 if (setup_size
> kernel_size
) {
997 fprintf(stderr
, "qemu: invalid kernel header\n");
1000 kernel_size
-= setup_size
;
1002 setup
= g_malloc(setup_size
);
1003 kernel
= g_malloc(kernel_size
);
1004 fseek(f
, 0, SEEK_SET
);
1005 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
1006 fprintf(stderr
, "fread() failed\n");
1009 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
1010 fprintf(stderr
, "fread() failed\n");
1015 /* append dtb to kernel */
1017 if (protocol
< 0x209) {
1018 fprintf(stderr
, "qemu: Linux kernel too old to load a dtb\n");
1022 dtb_size
= get_image_size(dtb_filename
);
1023 if (dtb_size
<= 0) {
1024 fprintf(stderr
, "qemu: error reading dtb %s: %s\n",
1025 dtb_filename
, strerror(errno
));
1029 setup_data_offset
= QEMU_ALIGN_UP(kernel_size
, 16);
1030 kernel_size
= setup_data_offset
+ sizeof(struct setup_data
) + dtb_size
;
1031 kernel
= g_realloc(kernel
, kernel_size
);
1033 stq_p(header
+0x250, prot_addr
+ setup_data_offset
);
1035 setup_data
= (struct setup_data
*)(kernel
+ setup_data_offset
);
1036 setup_data
->next
= 0;
1037 setup_data
->type
= cpu_to_le32(SETUP_DTB
);
1038 setup_data
->len
= cpu_to_le32(dtb_size
);
1040 load_image_size(dtb_filename
, setup_data
->data
, dtb_size
);
1043 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
1045 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
1046 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1047 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
1049 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
1050 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
1051 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
1053 option_rom
[nb_option_roms
].bootindex
= 0;
1054 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
1055 if (pcmc
->linuxboot_dma_enabled
&& fw_cfg_dma_enabled(fw_cfg
)) {
1056 option_rom
[nb_option_roms
].name
= "linuxboot_dma.bin";
1061 #define NE2000_NB_MAX 6
1063 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
1065 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
1067 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
1069 static int nb_ne2k
= 0;
1071 if (nb_ne2k
== NE2000_NB_MAX
)
1073 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
1074 ne2000_irq
[nb_ne2k
], nd
);
1078 DeviceState
*cpu_get_current_apic(void)
1081 X86CPU
*cpu
= X86_CPU(current_cpu
);
1082 return cpu
->apic_state
;
1088 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
1090 X86CPU
*cpu
= opaque
;
1093 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
1097 static void pc_new_cpu(const char *typename
, int64_t apic_id
, Error
**errp
)
1100 Error
*local_err
= NULL
;
1102 cpu
= object_new(typename
);
1104 object_property_set_uint(cpu
, apic_id
, "apic-id", &local_err
);
1105 object_property_set_bool(cpu
, true, "realized", &local_err
);
1108 error_propagate(errp
, local_err
);
1111 void pc_hot_add_cpu(const int64_t id
, Error
**errp
)
1113 MachineState
*ms
= MACHINE(qdev_get_machine());
1114 int64_t apic_id
= x86_cpu_apic_id_from_index(id
);
1115 Error
*local_err
= NULL
;
1118 error_setg(errp
, "Invalid CPU id: %" PRIi64
, id
);
1122 if (apic_id
>= ACPI_CPU_HOTPLUG_ID_LIMIT
) {
1123 error_setg(errp
, "Unable to add CPU: %" PRIi64
1124 ", resulting APIC ID (%" PRIi64
") is too large",
1129 pc_new_cpu(ms
->cpu_type
, apic_id
, &local_err
);
1131 error_propagate(errp
, local_err
);
1136 void pc_cpus_init(PCMachineState
*pcms
)
1139 const CPUArchIdList
*possible_cpus
;
1140 MachineState
*ms
= MACHINE(pcms
);
1141 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
1143 /* Calculates the limit to CPU APIC ID values
1145 * Limit for the APIC ID value, so that all
1146 * CPU APIC IDs are < pcms->apic_id_limit.
1148 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1150 pcms
->apic_id_limit
= x86_cpu_apic_id_from_index(max_cpus
- 1) + 1;
1151 possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
1152 for (i
= 0; i
< smp_cpus
; i
++) {
1153 pc_new_cpu(possible_cpus
->cpus
[i
].type
, possible_cpus
->cpus
[i
].arch_id
,
1158 static void pc_build_feature_control_file(PCMachineState
*pcms
)
1160 MachineState
*ms
= MACHINE(pcms
);
1161 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
1162 CPUX86State
*env
= &cpu
->env
;
1163 uint32_t unused
, ecx
, edx
;
1164 uint64_t feature_control_bits
= 0;
1167 cpu_x86_cpuid(env
, 1, 0, &unused
, &unused
, &ecx
, &edx
);
1168 if (ecx
& CPUID_EXT_VMX
) {
1169 feature_control_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
1172 if ((edx
& (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
)) ==
1173 (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
) &&
1174 (env
->mcg_cap
& MCG_LMCE_P
)) {
1175 feature_control_bits
|= FEATURE_CONTROL_LMCE
;
1178 if (!feature_control_bits
) {
1182 val
= g_malloc(sizeof(*val
));
1183 *val
= cpu_to_le64(feature_control_bits
| FEATURE_CONTROL_LOCKED
);
1184 fw_cfg_add_file(pcms
->fw_cfg
, "etc/msr_feature_control", val
, sizeof(*val
));
1187 static void rtc_set_cpus_count(ISADevice
*rtc
, uint16_t cpus_count
)
1189 if (cpus_count
> 0xff) {
1190 /* If the number of CPUs can't be represented in 8 bits, the
1191 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1192 * to make old BIOSes fail more predictably.
1194 rtc_set_memory(rtc
, 0x5f, 0);
1196 rtc_set_memory(rtc
, 0x5f, cpus_count
- 1);
1201 void pc_machine_done(Notifier
*notifier
, void *data
)
1203 PCMachineState
*pcms
= container_of(notifier
,
1204 PCMachineState
, machine_done
);
1205 PCIBus
*bus
= pcms
->bus
;
1207 /* set the number of CPUs */
1208 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1211 int extra_hosts
= 0;
1213 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1214 /* look for expander root buses */
1215 if (pci_bus_is_root(bus
)) {
1219 if (extra_hosts
&& pcms
->fw_cfg
) {
1220 uint64_t *val
= g_malloc(sizeof(*val
));
1221 *val
= cpu_to_le64(extra_hosts
);
1222 fw_cfg_add_file(pcms
->fw_cfg
,
1223 "etc/extra-pci-roots", val
, sizeof(*val
));
1229 pc_build_smbios(pcms
);
1230 pc_build_feature_control_file(pcms
);
1231 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1232 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1235 if (pcms
->apic_id_limit
> 255 && !xen_enabled()) {
1236 IntelIOMMUState
*iommu
= INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1238 if (!iommu
|| !iommu
->x86_iommu
.intr_supported
||
1239 iommu
->intr_eim
!= ON_OFF_AUTO_ON
) {
1240 error_report("current -smp configuration requires "
1241 "Extended Interrupt Mode enabled. "
1242 "You can add an IOMMU using: "
1243 "-device intel-iommu,intremap=on,eim=on");
1249 void pc_guest_info_init(PCMachineState
*pcms
)
1253 pcms
->apic_xrupt_override
= kvm_allows_irq0_override();
1254 pcms
->numa_nodes
= nb_numa_nodes
;
1255 pcms
->node_mem
= g_malloc0(pcms
->numa_nodes
*
1256 sizeof *pcms
->node_mem
);
1257 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1258 pcms
->node_mem
[i
] = numa_info
[i
].node_mem
;
1261 pcms
->machine_done
.notify
= pc_machine_done
;
1262 qemu_add_machine_init_done_notifier(&pcms
->machine_done
);
1265 /* setup pci memory address space mapping into system address space */
1266 void pc_pci_as_mapping_init(Object
*owner
, MemoryRegion
*system_memory
,
1267 MemoryRegion
*pci_address_space
)
1269 /* Set to lower priority than RAM */
1270 memory_region_add_subregion_overlap(system_memory
, 0x0,
1271 pci_address_space
, -1);
1274 void pc_acpi_init(const char *default_dsdt
)
1278 if (acpi_tables
!= NULL
) {
1279 /* manually set via -acpitable, leave it alone */
1283 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, default_dsdt
);
1284 if (filename
== NULL
) {
1285 warn_report("failed to find %s", default_dsdt
);
1287 QemuOpts
*opts
= qemu_opts_create(qemu_find_opts("acpi"), NULL
, 0,
1291 qemu_opt_set(opts
, "file", filename
, &error_abort
);
1293 acpi_table_add_builtin(opts
, &err
);
1295 warn_reportf_err(err
, "failed to load %s: ", filename
);
1301 void xen_load_linux(PCMachineState
*pcms
)
1306 assert(MACHINE(pcms
)->kernel_filename
!= NULL
);
1308 fw_cfg
= fw_cfg_init_io(FW_CFG_IO_BASE
);
1309 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1312 load_linux(pcms
, fw_cfg
);
1313 for (i
= 0; i
< nb_option_roms
; i
++) {
1314 assert(!strcmp(option_rom
[i
].name
, "linuxboot.bin") ||
1315 !strcmp(option_rom
[i
].name
, "linuxboot_dma.bin") ||
1316 !strcmp(option_rom
[i
].name
, "multiboot.bin"));
1317 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1319 pcms
->fw_cfg
= fw_cfg
;
1322 void pc_memory_init(PCMachineState
*pcms
,
1323 MemoryRegion
*system_memory
,
1324 MemoryRegion
*rom_memory
,
1325 MemoryRegion
**ram_memory
)
1328 MemoryRegion
*ram
, *option_rom_mr
;
1329 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
1331 MachineState
*machine
= MACHINE(pcms
);
1332 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1334 assert(machine
->ram_size
== pcms
->below_4g_mem_size
+
1335 pcms
->above_4g_mem_size
);
1337 linux_boot
= (machine
->kernel_filename
!= NULL
);
1339 /* Allocate RAM. We allocate it as a single memory region and use
1340 * aliases to address portions of it, mostly for backwards compatibility
1341 * with older qemus that used qemu_ram_alloc().
1343 ram
= g_malloc(sizeof(*ram
));
1344 memory_region_allocate_system_memory(ram
, NULL
, "pc.ram",
1347 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
1348 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", ram
,
1349 0, pcms
->below_4g_mem_size
);
1350 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
1351 e820_add_entry(0, pcms
->below_4g_mem_size
, E820_RAM
);
1352 if (pcms
->above_4g_mem_size
> 0) {
1353 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
1354 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g", ram
,
1355 pcms
->below_4g_mem_size
,
1356 pcms
->above_4g_mem_size
);
1357 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
1359 e820_add_entry(0x100000000ULL
, pcms
->above_4g_mem_size
, E820_RAM
);
1362 if (!pcmc
->has_reserved_memory
&&
1363 (machine
->ram_slots
||
1364 (machine
->maxram_size
> machine
->ram_size
))) {
1365 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1367 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1372 /* initialize hotplug memory address space */
1373 if (pcmc
->has_reserved_memory
&&
1374 (machine
->ram_size
< machine
->maxram_size
)) {
1375 ram_addr_t hotplug_mem_size
=
1376 machine
->maxram_size
- machine
->ram_size
;
1378 if (machine
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1379 error_report("unsupported amount of memory slots: %"PRIu64
,
1380 machine
->ram_slots
);
1384 if (QEMU_ALIGN_UP(machine
->maxram_size
,
1385 TARGET_PAGE_SIZE
) != machine
->maxram_size
) {
1386 error_report("maximum memory size must by aligned to multiple of "
1387 "%d bytes", TARGET_PAGE_SIZE
);
1391 pcms
->hotplug_memory
.base
=
1392 ROUND_UP(0x100000000ULL
+ pcms
->above_4g_mem_size
, 1ULL << 30);
1394 if (pcmc
->enforce_aligned_dimm
) {
1395 /* size hotplug region assuming 1G page max alignment per slot */
1396 hotplug_mem_size
+= (1ULL << 30) * machine
->ram_slots
;
1399 if ((pcms
->hotplug_memory
.base
+ hotplug_mem_size
) <
1401 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT
,
1402 machine
->maxram_size
);
1406 memory_region_init(&pcms
->hotplug_memory
.mr
, OBJECT(pcms
),
1407 "hotplug-memory", hotplug_mem_size
);
1408 memory_region_add_subregion(system_memory
, pcms
->hotplug_memory
.base
,
1409 &pcms
->hotplug_memory
.mr
);
1412 /* Initialize PC system firmware */
1413 pc_system_firmware_init(rom_memory
, !pcmc
->pci_enabled
);
1415 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1416 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
,
1418 if (pcmc
->pci_enabled
) {
1419 memory_region_set_readonly(option_rom_mr
, true);
1421 memory_region_add_subregion_overlap(rom_memory
,
1426 fw_cfg
= bochs_bios_init(&address_space_memory
, pcms
);
1430 if (pcmc
->has_reserved_memory
&& pcms
->hotplug_memory
.base
) {
1431 uint64_t *val
= g_malloc(sizeof(*val
));
1432 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1433 uint64_t res_mem_end
= pcms
->hotplug_memory
.base
;
1435 if (!pcmc
->broken_reserved_end
) {
1436 res_mem_end
+= memory_region_size(&pcms
->hotplug_memory
.mr
);
1438 *val
= cpu_to_le64(ROUND_UP(res_mem_end
, 0x1ULL
<< 30));
1439 fw_cfg_add_file(fw_cfg
, "etc/reserved-memory-end", val
, sizeof(*val
));
1443 load_linux(pcms
, fw_cfg
);
1446 for (i
= 0; i
< nb_option_roms
; i
++) {
1447 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1449 pcms
->fw_cfg
= fw_cfg
;
1451 /* Init default IOAPIC address space */
1452 pcms
->ioapic_as
= &address_space_memory
;
1456 * The 64bit pci hole starts after "above 4G RAM" and
1457 * potentially the space reserved for memory hotplug.
1459 uint64_t pc_pci_hole64_start(void)
1461 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
1462 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1463 uint64_t hole64_start
= 0;
1465 if (pcmc
->has_reserved_memory
&& pcms
->hotplug_memory
.base
) {
1466 hole64_start
= pcms
->hotplug_memory
.base
;
1467 if (!pcmc
->broken_reserved_end
) {
1468 hole64_start
+= memory_region_size(&pcms
->hotplug_memory
.mr
);
1471 hole64_start
= 0x100000000ULL
+ pcms
->above_4g_mem_size
;
1474 return ROUND_UP(hole64_start
, 1ULL << 30);
1477 qemu_irq
pc_allocate_cpu_irq(void)
1479 return qemu_allocate_irq(pic_irq_request
, NULL
, 0);
1482 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1484 DeviceState
*dev
= NULL
;
1486 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA
);
1488 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
1489 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1490 } else if (isa_bus
) {
1491 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1492 dev
= isadev
? DEVICE(isadev
) : NULL
;
1494 rom_reset_order_override();
1498 static const MemoryRegionOps ioport80_io_ops
= {
1499 .write
= ioport80_write
,
1500 .read
= ioport80_read
,
1501 .endianness
= DEVICE_NATIVE_ENDIAN
,
1503 .min_access_size
= 1,
1504 .max_access_size
= 1,
1508 static const MemoryRegionOps ioportF0_io_ops
= {
1509 .write
= ioportF0_write
,
1510 .read
= ioportF0_read
,
1511 .endianness
= DEVICE_NATIVE_ENDIAN
,
1513 .min_access_size
= 1,
1514 .max_access_size
= 1,
1518 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
1519 ISADevice
**rtc_state
,
1526 DriveInfo
*fd
[MAX_FD
];
1527 DeviceState
*hpet
= NULL
;
1528 int pit_isa_irq
= 0;
1529 qemu_irq pit_alt_irq
= NULL
;
1530 qemu_irq rtc_irq
= NULL
;
1532 ISADevice
*i8042
, *port92
, *vmmouse
, *pit
= NULL
;
1533 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
1534 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
1536 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
1537 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
1539 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
1540 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
1543 * Check if an HPET shall be created.
1545 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1546 * when the HPET wants to take over. Thus we have to disable the latter.
1548 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1549 /* In order to set property, here not using sysbus_try_create_simple */
1550 hpet
= qdev_try_create(NULL
, TYPE_HPET
);
1552 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1553 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1556 uint8_t compat
= object_property_get_uint(OBJECT(hpet
),
1559 qdev_prop_set_uint32(hpet
, HPET_INTCAP
, hpet_irqs
);
1561 qdev_init_nofail(hpet
);
1562 sysbus_mmio_map(SYS_BUS_DEVICE(hpet
), 0, HPET_BASE
);
1564 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
1565 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
1568 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
1569 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
1572 *rtc_state
= mc146818_rtc_init(isa_bus
, 2000, rtc_irq
);
1574 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
1576 if (!xen_enabled() && has_pit
) {
1577 if (kvm_pit_in_kernel()) {
1578 pit
= kvm_pit_init(isa_bus
, 0x40);
1580 pit
= i8254_pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
1583 /* connect PIT to output control line of the HPET */
1584 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
1586 pcspk_init(isa_bus
, pit
);
1589 serial_hds_isa_init(isa_bus
, 0, MAX_SERIAL_PORTS
);
1590 parallel_hds_isa_init(isa_bus
, MAX_PARALLEL_PORTS
);
1592 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1593 i8042
= isa_create_simple(isa_bus
, "i8042");
1594 i8042_setup_a20_line(i8042
, a20_line
[0]);
1596 vmport_init(isa_bus
);
1597 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
1602 DeviceState
*dev
= DEVICE(vmmouse
);
1603 qdev_prop_set_ptr(dev
, "ps2_mouse", i8042
);
1604 qdev_init_nofail(dev
);
1606 port92
= isa_create_simple(isa_bus
, "port92");
1607 port92_init(port92
, a20_line
[1]);
1610 DMA_init(isa_bus
, 0);
1612 for(i
= 0; i
< MAX_FD
; i
++) {
1613 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1614 create_fdctrl
|= !!fd
[i
];
1616 if (create_fdctrl
) {
1617 fdctrl_init_isa(isa_bus
, fd
);
1621 void pc_nic_init(PCMachineClass
*pcmc
, ISABus
*isa_bus
, PCIBus
*pci_bus
)
1625 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC
);
1626 for (i
= 0; i
< nb_nics
; i
++) {
1627 NICInfo
*nd
= &nd_table
[i
];
1628 const char *model
= nd
->model
? nd
->model
: pcmc
->default_nic_model
;
1630 if (g_str_equal(model
, "ne2k_isa")) {
1631 pc_init_ne2k_isa(isa_bus
, nd
);
1633 pci_nic_init_nofail(nd
, pci_bus
, model
, NULL
);
1636 rom_reset_order_override();
1639 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
)
1645 if (kvm_ioapic_in_kernel()) {
1646 dev
= qdev_create(NULL
, "kvm-ioapic");
1648 dev
= qdev_create(NULL
, "ioapic");
1651 object_property_add_child(object_resolve_path(parent_name
, NULL
),
1652 "ioapic", OBJECT(dev
), NULL
);
1654 qdev_init_nofail(dev
);
1655 d
= SYS_BUS_DEVICE(dev
);
1656 sysbus_mmio_map(d
, 0, IO_APIC_DEFAULT_ADDRESS
);
1658 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1659 gsi_state
->ioapic_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1663 static void pc_dimm_plug(HotplugHandler
*hotplug_dev
,
1664 DeviceState
*dev
, Error
**errp
)
1666 HotplugHandlerClass
*hhc
;
1667 Error
*local_err
= NULL
;
1668 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1669 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1670 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
1671 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
1673 uint64_t align
= TARGET_PAGE_SIZE
;
1674 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
1676 mr
= ddc
->get_memory_region(dimm
, &local_err
);
1681 if (memory_region_get_alignment(mr
) && pcmc
->enforce_aligned_dimm
) {
1682 align
= memory_region_get_alignment(mr
);
1686 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1687 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1688 * addition to cover this case.
1690 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
1691 error_setg(&local_err
,
1692 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1696 if (is_nvdimm
&& !pcms
->acpi_nvdimm_state
.is_enabled
) {
1697 error_setg(&local_err
,
1698 "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1702 pc_dimm_memory_plug(dev
, &pcms
->hotplug_memory
, mr
, align
, &local_err
);
1708 nvdimm_plug(&pcms
->acpi_nvdimm_state
);
1711 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1712 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &error_abort
);
1714 error_propagate(errp
, local_err
);
1717 static void pc_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
1718 DeviceState
*dev
, Error
**errp
)
1720 HotplugHandlerClass
*hhc
;
1721 Error
*local_err
= NULL
;
1722 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1725 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1726 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1727 * addition to cover this case.
1729 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
1730 error_setg(&local_err
,
1731 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1735 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
1736 error_setg(&local_err
,
1737 "nvdimm device hot unplug is not supported yet.");
1741 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1742 hhc
->unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1745 error_propagate(errp
, local_err
);
1748 static void pc_dimm_unplug(HotplugHandler
*hotplug_dev
,
1749 DeviceState
*dev
, Error
**errp
)
1751 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1752 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
1753 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
1755 HotplugHandlerClass
*hhc
;
1756 Error
*local_err
= NULL
;
1758 mr
= ddc
->get_memory_region(dimm
, &local_err
);
1763 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1764 hhc
->unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1770 pc_dimm_memory_unplug(dev
, &pcms
->hotplug_memory
, mr
);
1771 object_unparent(OBJECT(dev
));
1774 error_propagate(errp
, local_err
);
1777 static int pc_apic_cmp(const void *a
, const void *b
)
1779 CPUArchId
*apic_a
= (CPUArchId
*)a
;
1780 CPUArchId
*apic_b
= (CPUArchId
*)b
;
1782 return apic_a
->arch_id
- apic_b
->arch_id
;
1785 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1786 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1787 * entry corresponding to CPU's apic_id returns NULL.
1789 static CPUArchId
*pc_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
1791 CPUArchId apic_id
, *found_cpu
;
1793 apic_id
.arch_id
= id
;
1794 found_cpu
= bsearch(&apic_id
, ms
->possible_cpus
->cpus
,
1795 ms
->possible_cpus
->len
, sizeof(*ms
->possible_cpus
->cpus
),
1797 if (found_cpu
&& idx
) {
1798 *idx
= found_cpu
- ms
->possible_cpus
->cpus
;
1803 static void pc_cpu_plug(HotplugHandler
*hotplug_dev
,
1804 DeviceState
*dev
, Error
**errp
)
1806 CPUArchId
*found_cpu
;
1807 HotplugHandlerClass
*hhc
;
1808 Error
*local_err
= NULL
;
1809 X86CPU
*cpu
= X86_CPU(dev
);
1810 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1812 if (pcms
->acpi_dev
) {
1813 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1814 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1820 /* increment the number of CPUs */
1823 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1826 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1829 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
1830 found_cpu
->cpu
= OBJECT(dev
);
1832 error_propagate(errp
, local_err
);
1834 static void pc_cpu_unplug_request_cb(HotplugHandler
*hotplug_dev
,
1835 DeviceState
*dev
, Error
**errp
)
1838 HotplugHandlerClass
*hhc
;
1839 Error
*local_err
= NULL
;
1840 X86CPU
*cpu
= X86_CPU(dev
);
1841 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1843 if (!pcms
->acpi_dev
) {
1844 error_setg(&local_err
, "CPU hot unplug not supported without ACPI");
1848 pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
1851 error_setg(&local_err
, "Boot CPU is unpluggable");
1855 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1856 hhc
->unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1863 error_propagate(errp
, local_err
);
1867 static void pc_cpu_unplug_cb(HotplugHandler
*hotplug_dev
,
1868 DeviceState
*dev
, Error
**errp
)
1870 CPUArchId
*found_cpu
;
1871 HotplugHandlerClass
*hhc
;
1872 Error
*local_err
= NULL
;
1873 X86CPU
*cpu
= X86_CPU(dev
);
1874 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1876 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1877 hhc
->unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1883 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
1884 found_cpu
->cpu
= NULL
;
1885 object_unparent(OBJECT(dev
));
1887 /* decrement the number of CPUs */
1889 /* Update the number of CPUs in CMOS */
1890 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1891 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1893 error_propagate(errp
, local_err
);
1896 static void pc_cpu_pre_plug(HotplugHandler
*hotplug_dev
,
1897 DeviceState
*dev
, Error
**errp
)
1901 CPUArchId
*cpu_slot
;
1902 X86CPUTopoInfo topo
;
1903 X86CPU
*cpu
= X86_CPU(dev
);
1904 MachineState
*ms
= MACHINE(hotplug_dev
);
1905 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1907 if(!object_dynamic_cast(OBJECT(cpu
), ms
->cpu_type
)) {
1908 error_setg(errp
, "Invalid CPU type, expected cpu type: '%s'",
1913 /* if APIC ID is not set, set it based on socket/core/thread properties */
1914 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
1915 int max_socket
= (max_cpus
- 1) / smp_threads
/ smp_cores
;
1917 if (cpu
->socket_id
< 0) {
1918 error_setg(errp
, "CPU socket-id is not set");
1920 } else if (cpu
->socket_id
> max_socket
) {
1921 error_setg(errp
, "Invalid CPU socket-id: %u must be in range 0:%u",
1922 cpu
->socket_id
, max_socket
);
1925 if (cpu
->core_id
< 0) {
1926 error_setg(errp
, "CPU core-id is not set");
1928 } else if (cpu
->core_id
> (smp_cores
- 1)) {
1929 error_setg(errp
, "Invalid CPU core-id: %u must be in range 0:%u",
1930 cpu
->core_id
, smp_cores
- 1);
1933 if (cpu
->thread_id
< 0) {
1934 error_setg(errp
, "CPU thread-id is not set");
1936 } else if (cpu
->thread_id
> (smp_threads
- 1)) {
1937 error_setg(errp
, "Invalid CPU thread-id: %u must be in range 0:%u",
1938 cpu
->thread_id
, smp_threads
- 1);
1942 topo
.pkg_id
= cpu
->socket_id
;
1943 topo
.core_id
= cpu
->core_id
;
1944 topo
.smt_id
= cpu
->thread_id
;
1945 cpu
->apic_id
= apicid_from_topo_ids(smp_cores
, smp_threads
, &topo
);
1948 cpu_slot
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
1950 MachineState
*ms
= MACHINE(pcms
);
1952 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
1953 error_setg(errp
, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
1954 " APIC ID %" PRIu32
", valid index range 0:%d",
1955 topo
.pkg_id
, topo
.core_id
, topo
.smt_id
, cpu
->apic_id
,
1956 ms
->possible_cpus
->len
- 1);
1960 if (cpu_slot
->cpu
) {
1961 error_setg(errp
, "CPU[%d] with APIC ID %" PRIu32
" exists",
1966 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1967 * so that machine_query_hotpluggable_cpus would show correct values
1969 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1970 * once -smp refactoring is complete and there will be CPU private
1971 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1972 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
1973 if (cpu
->socket_id
!= -1 && cpu
->socket_id
!= topo
.pkg_id
) {
1974 error_setg(errp
, "property socket-id: %u doesn't match set apic-id:"
1975 " 0x%x (socket-id: %u)", cpu
->socket_id
, cpu
->apic_id
, topo
.pkg_id
);
1978 cpu
->socket_id
= topo
.pkg_id
;
1980 if (cpu
->core_id
!= -1 && cpu
->core_id
!= topo
.core_id
) {
1981 error_setg(errp
, "property core-id: %u doesn't match set apic-id:"
1982 " 0x%x (core-id: %u)", cpu
->core_id
, cpu
->apic_id
, topo
.core_id
);
1985 cpu
->core_id
= topo
.core_id
;
1987 if (cpu
->thread_id
!= -1 && cpu
->thread_id
!= topo
.smt_id
) {
1988 error_setg(errp
, "property thread-id: %u doesn't match set apic-id:"
1989 " 0x%x (thread-id: %u)", cpu
->thread_id
, cpu
->apic_id
, topo
.smt_id
);
1992 cpu
->thread_id
= topo
.smt_id
;
1995 cs
->cpu_index
= idx
;
1997 numa_cpu_pre_plug(cpu_slot
, dev
, errp
);
2000 static void pc_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2001 DeviceState
*dev
, Error
**errp
)
2003 if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2004 pc_cpu_pre_plug(hotplug_dev
, dev
, errp
);
2008 static void pc_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2009 DeviceState
*dev
, Error
**errp
)
2011 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2012 pc_dimm_plug(hotplug_dev
, dev
, errp
);
2013 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2014 pc_cpu_plug(hotplug_dev
, dev
, errp
);
2018 static void pc_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2019 DeviceState
*dev
, Error
**errp
)
2021 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2022 pc_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2023 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2024 pc_cpu_unplug_request_cb(hotplug_dev
, dev
, errp
);
2026 error_setg(errp
, "acpi: device unplug request for not supported device"
2027 " type: %s", object_get_typename(OBJECT(dev
)));
2031 static void pc_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2032 DeviceState
*dev
, Error
**errp
)
2034 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2035 pc_dimm_unplug(hotplug_dev
, dev
, errp
);
2036 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2037 pc_cpu_unplug_cb(hotplug_dev
, dev
, errp
);
2039 error_setg(errp
, "acpi: device unplug for not supported device"
2040 " type: %s", object_get_typename(OBJECT(dev
)));
2044 static HotplugHandler
*pc_get_hotpug_handler(MachineState
*machine
,
2047 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(machine
);
2049 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2050 object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2051 return HOTPLUG_HANDLER(machine
);
2054 return pcmc
->get_hotplug_handler
?
2055 pcmc
->get_hotplug_handler(machine
, dev
) : NULL
;
2059 pc_machine_get_hotplug_memory_region_size(Object
*obj
, Visitor
*v
,
2060 const char *name
, void *opaque
,
2063 PCMachineState
*pcms
= PC_MACHINE(obj
);
2064 int64_t value
= memory_region_size(&pcms
->hotplug_memory
.mr
);
2066 visit_type_int(v
, name
, &value
, errp
);
2069 static void pc_machine_get_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2070 const char *name
, void *opaque
,
2073 PCMachineState
*pcms
= PC_MACHINE(obj
);
2074 uint64_t value
= pcms
->max_ram_below_4g
;
2076 visit_type_size(v
, name
, &value
, errp
);
2079 static void pc_machine_set_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2080 const char *name
, void *opaque
,
2083 PCMachineState
*pcms
= PC_MACHINE(obj
);
2084 Error
*error
= NULL
;
2087 visit_type_size(v
, name
, &value
, &error
);
2089 error_propagate(errp
, error
);
2092 if (value
> (1ULL << 32)) {
2094 "Machine option 'max-ram-below-4g=%"PRIu64
2095 "' expects size less than or equal to 4G", value
);
2096 error_propagate(errp
, error
);
2100 if (value
< (1ULL << 20)) {
2101 warn_report("Only %" PRIu64
" bytes of RAM below the 4GiB boundary,"
2102 "BIOS may not work with less than 1MiB", value
);
2105 pcms
->max_ram_below_4g
= value
;
2108 static void pc_machine_get_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2109 void *opaque
, Error
**errp
)
2111 PCMachineState
*pcms
= PC_MACHINE(obj
);
2112 OnOffAuto vmport
= pcms
->vmport
;
2114 visit_type_OnOffAuto(v
, name
, &vmport
, errp
);
2117 static void pc_machine_set_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2118 void *opaque
, Error
**errp
)
2120 PCMachineState
*pcms
= PC_MACHINE(obj
);
2122 visit_type_OnOffAuto(v
, name
, &pcms
->vmport
, errp
);
2125 bool pc_machine_is_smm_enabled(PCMachineState
*pcms
)
2127 bool smm_available
= false;
2129 if (pcms
->smm
== ON_OFF_AUTO_OFF
) {
2133 if (tcg_enabled() || qtest_enabled()) {
2134 smm_available
= true;
2135 } else if (kvm_enabled()) {
2136 smm_available
= kvm_has_smm();
2139 if (smm_available
) {
2143 if (pcms
->smm
== ON_OFF_AUTO_ON
) {
2144 error_report("System Management Mode not supported by this hypervisor.");
2150 static void pc_machine_get_smm(Object
*obj
, Visitor
*v
, const char *name
,
2151 void *opaque
, Error
**errp
)
2153 PCMachineState
*pcms
= PC_MACHINE(obj
);
2154 OnOffAuto smm
= pcms
->smm
;
2156 visit_type_OnOffAuto(v
, name
, &smm
, errp
);
2159 static void pc_machine_set_smm(Object
*obj
, Visitor
*v
, const char *name
,
2160 void *opaque
, Error
**errp
)
2162 PCMachineState
*pcms
= PC_MACHINE(obj
);
2164 visit_type_OnOffAuto(v
, name
, &pcms
->smm
, errp
);
2167 static bool pc_machine_get_nvdimm(Object
*obj
, Error
**errp
)
2169 PCMachineState
*pcms
= PC_MACHINE(obj
);
2171 return pcms
->acpi_nvdimm_state
.is_enabled
;
2174 static void pc_machine_set_nvdimm(Object
*obj
, bool value
, Error
**errp
)
2176 PCMachineState
*pcms
= PC_MACHINE(obj
);
2178 pcms
->acpi_nvdimm_state
.is_enabled
= value
;
2181 static bool pc_machine_get_smbus(Object
*obj
, Error
**errp
)
2183 PCMachineState
*pcms
= PC_MACHINE(obj
);
2188 static void pc_machine_set_smbus(Object
*obj
, bool value
, Error
**errp
)
2190 PCMachineState
*pcms
= PC_MACHINE(obj
);
2192 pcms
->smbus
= value
;
2195 static bool pc_machine_get_sata(Object
*obj
, Error
**errp
)
2197 PCMachineState
*pcms
= PC_MACHINE(obj
);
2202 static void pc_machine_set_sata(Object
*obj
, bool value
, Error
**errp
)
2204 PCMachineState
*pcms
= PC_MACHINE(obj
);
2209 static bool pc_machine_get_pit(Object
*obj
, Error
**errp
)
2211 PCMachineState
*pcms
= PC_MACHINE(obj
);
2216 static void pc_machine_set_pit(Object
*obj
, bool value
, Error
**errp
)
2218 PCMachineState
*pcms
= PC_MACHINE(obj
);
2223 static void pc_machine_initfn(Object
*obj
)
2225 PCMachineState
*pcms
= PC_MACHINE(obj
);
2227 pcms
->max_ram_below_4g
= 0; /* use default */
2228 pcms
->smm
= ON_OFF_AUTO_AUTO
;
2229 pcms
->vmport
= ON_OFF_AUTO_AUTO
;
2230 /* nvdimm is disabled on default. */
2231 pcms
->acpi_nvdimm_state
.is_enabled
= false;
2232 /* acpi build is enabled by default if machine supports it */
2233 pcms
->acpi_build_enabled
= PC_MACHINE_GET_CLASS(pcms
)->has_acpi_build
;
2239 static void pc_machine_reset(void)
2244 qemu_devices_reset();
2246 /* Reset APIC after devices have been reset to cancel
2247 * any changes that qemu_devices_reset() might have done.
2252 if (cpu
->apic_state
) {
2253 device_reset(cpu
->apic_state
);
2258 static CpuInstanceProperties
2259 pc_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2261 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2262 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2264 assert(cpu_index
< possible_cpus
->len
);
2265 return possible_cpus
->cpus
[cpu_index
].props
;
2268 static int64_t pc_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2270 X86CPUTopoInfo topo
;
2272 assert(idx
< ms
->possible_cpus
->len
);
2273 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[idx
].arch_id
,
2274 smp_cores
, smp_threads
, &topo
);
2275 return topo
.pkg_id
% nb_numa_nodes
;
2278 static const CPUArchIdList
*pc_possible_cpu_arch_ids(MachineState
*ms
)
2282 if (ms
->possible_cpus
) {
2284 * make sure that max_cpus hasn't changed since the first use, i.e.
2285 * -smp hasn't been parsed after it
2287 assert(ms
->possible_cpus
->len
== max_cpus
);
2288 return ms
->possible_cpus
;
2291 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2292 sizeof(CPUArchId
) * max_cpus
);
2293 ms
->possible_cpus
->len
= max_cpus
;
2294 for (i
= 0; i
< ms
->possible_cpus
->len
; i
++) {
2295 X86CPUTopoInfo topo
;
2297 ms
->possible_cpus
->cpus
[i
].type
= ms
->cpu_type
;
2298 ms
->possible_cpus
->cpus
[i
].vcpus_count
= 1;
2299 ms
->possible_cpus
->cpus
[i
].arch_id
= x86_cpu_apic_id_from_index(i
);
2300 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[i
].arch_id
,
2301 smp_cores
, smp_threads
, &topo
);
2302 ms
->possible_cpus
->cpus
[i
].props
.has_socket_id
= true;
2303 ms
->possible_cpus
->cpus
[i
].props
.socket_id
= topo
.pkg_id
;
2304 ms
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
2305 ms
->possible_cpus
->cpus
[i
].props
.core_id
= topo
.core_id
;
2306 ms
->possible_cpus
->cpus
[i
].props
.has_thread_id
= true;
2307 ms
->possible_cpus
->cpus
[i
].props
.thread_id
= topo
.smt_id
;
2309 return ms
->possible_cpus
;
2312 static void x86_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
2314 /* cpu index isn't used */
2318 X86CPU
*cpu
= X86_CPU(cs
);
2320 if (!cpu
->apic_state
) {
2321 cpu_interrupt(cs
, CPU_INTERRUPT_NMI
);
2323 apic_deliver_nmi(cpu
->apic_state
);
2328 static void pc_machine_class_init(ObjectClass
*oc
, void *data
)
2330 MachineClass
*mc
= MACHINE_CLASS(oc
);
2331 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(oc
);
2332 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2333 NMIClass
*nc
= NMI_CLASS(oc
);
2335 pcmc
->get_hotplug_handler
= mc
->get_hotplug_handler
;
2336 pcmc
->pci_enabled
= true;
2337 pcmc
->has_acpi_build
= true;
2338 pcmc
->rsdp_in_ram
= true;
2339 pcmc
->smbios_defaults
= true;
2340 pcmc
->smbios_uuid_encoded
= true;
2341 pcmc
->gigabyte_align
= true;
2342 pcmc
->has_reserved_memory
= true;
2343 pcmc
->kvmclock_enabled
= true;
2344 pcmc
->enforce_aligned_dimm
= true;
2345 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2346 * to be used at the moment, 32K should be enough for a while. */
2347 pcmc
->acpi_data_size
= 0x20000 + 0x8000;
2348 pcmc
->save_tsc_khz
= true;
2349 pcmc
->linuxboot_dma_enabled
= true;
2350 mc
->get_hotplug_handler
= pc_get_hotpug_handler
;
2351 mc
->cpu_index_to_instance_props
= pc_cpu_index_to_props
;
2352 mc
->get_default_cpu_node_id
= pc_get_default_cpu_node_id
;
2353 mc
->possible_cpu_arch_ids
= pc_possible_cpu_arch_ids
;
2354 mc
->auto_enable_numa_with_memhp
= true;
2355 mc
->has_hotpluggable_cpus
= true;
2356 mc
->default_boot_order
= "cad";
2357 mc
->hot_add_cpu
= pc_hot_add_cpu
;
2358 mc
->block_default_type
= IF_IDE
;
2360 mc
->reset
= pc_machine_reset
;
2361 hc
->pre_plug
= pc_machine_device_pre_plug_cb
;
2362 hc
->plug
= pc_machine_device_plug_cb
;
2363 hc
->unplug_request
= pc_machine_device_unplug_request_cb
;
2364 hc
->unplug
= pc_machine_device_unplug_cb
;
2365 nc
->nmi_monitor_handler
= x86_nmi
;
2366 mc
->default_cpu_type
= TARGET_DEFAULT_CPU_TYPE
;
2368 object_class_property_add(oc
, PC_MACHINE_MEMHP_REGION_SIZE
, "int",
2369 pc_machine_get_hotplug_memory_region_size
, NULL
,
2370 NULL
, NULL
, &error_abort
);
2372 object_class_property_add(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
, "size",
2373 pc_machine_get_max_ram_below_4g
, pc_machine_set_max_ram_below_4g
,
2374 NULL
, NULL
, &error_abort
);
2376 object_class_property_set_description(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
,
2377 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort
);
2379 object_class_property_add(oc
, PC_MACHINE_SMM
, "OnOffAuto",
2380 pc_machine_get_smm
, pc_machine_set_smm
,
2381 NULL
, NULL
, &error_abort
);
2382 object_class_property_set_description(oc
, PC_MACHINE_SMM
,
2383 "Enable SMM (pc & q35)", &error_abort
);
2385 object_class_property_add(oc
, PC_MACHINE_VMPORT
, "OnOffAuto",
2386 pc_machine_get_vmport
, pc_machine_set_vmport
,
2387 NULL
, NULL
, &error_abort
);
2388 object_class_property_set_description(oc
, PC_MACHINE_VMPORT
,
2389 "Enable vmport (pc & q35)", &error_abort
);
2391 object_class_property_add_bool(oc
, PC_MACHINE_NVDIMM
,
2392 pc_machine_get_nvdimm
, pc_machine_set_nvdimm
, &error_abort
);
2394 object_class_property_add_bool(oc
, PC_MACHINE_SMBUS
,
2395 pc_machine_get_smbus
, pc_machine_set_smbus
, &error_abort
);
2397 object_class_property_add_bool(oc
, PC_MACHINE_SATA
,
2398 pc_machine_get_sata
, pc_machine_set_sata
, &error_abort
);
2400 object_class_property_add_bool(oc
, PC_MACHINE_PIT
,
2401 pc_machine_get_pit
, pc_machine_set_pit
, &error_abort
);
2404 static const TypeInfo pc_machine_info
= {
2405 .name
= TYPE_PC_MACHINE
,
2406 .parent
= TYPE_MACHINE
,
2408 .instance_size
= sizeof(PCMachineState
),
2409 .instance_init
= pc_machine_initfn
,
2410 .class_size
= sizeof(PCMachineClass
),
2411 .class_init
= pc_machine_class_init
,
2412 .interfaces
= (InterfaceInfo
[]) {
2413 { TYPE_HOTPLUG_HANDLER
},
2419 static void pc_machine_register_types(void)
2421 type_register_static(&pc_machine_info
);
2424 type_init(pc_machine_register_types
)