2 * QEMU ESP/NCR53C9x emulation
4 * Copyright (c) 2005-2006 Fabrice Bellard
5 * Copyright (c) 2012 Herve Poussineau
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "hw/sysbus.h"
28 #include "migration/vmstate.h"
30 #include "hw/scsi/esp.h"
33 #include "qemu/module.h"
36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
37 * also produced as NCR89C100. See
38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
42 * On Macintosh Quadra it is a NCR53C96.
45 static void esp_raise_irq(ESPState
*s
)
47 if (!(s
->rregs
[ESP_RSTAT
] & STAT_INT
)) {
48 s
->rregs
[ESP_RSTAT
] |= STAT_INT
;
49 qemu_irq_raise(s
->irq
);
50 trace_esp_raise_irq();
54 static void esp_lower_irq(ESPState
*s
)
56 if (s
->rregs
[ESP_RSTAT
] & STAT_INT
) {
57 s
->rregs
[ESP_RSTAT
] &= ~STAT_INT
;
58 qemu_irq_lower(s
->irq
);
59 trace_esp_lower_irq();
63 static void esp_raise_drq(ESPState
*s
)
65 qemu_irq_raise(s
->irq_data
);
68 static void esp_lower_drq(ESPState
*s
)
70 qemu_irq_lower(s
->irq_data
);
73 void esp_dma_enable(ESPState
*s
, int irq
, int level
)
77 trace_esp_dma_enable();
83 trace_esp_dma_disable();
88 void esp_request_cancelled(SCSIRequest
*req
)
90 ESPState
*s
= req
->hba_private
;
92 if (req
== s
->current_req
) {
93 scsi_req_unref(s
->current_req
);
94 s
->current_req
= NULL
;
95 s
->current_dev
= NULL
;
99 static void set_pdma(ESPState
*s
, enum pdma_origin_id origin
,
100 uint32_t index
, uint32_t len
)
102 s
->pdma_origin
= origin
;
103 s
->pdma_start
= index
;
108 static uint8_t *get_pdma_buf(ESPState
*s
)
110 switch (s
->pdma_origin
) {
123 static int get_cmd_cb(ESPState
*s
)
127 target
= s
->wregs
[ESP_WBUSID
] & BUSID_DID
;
133 if (s
->current_req
) {
134 /* Started a new command before the old one finished. Cancel it. */
135 scsi_req_cancel(s
->current_req
);
139 s
->current_dev
= scsi_device_find(&s
->bus
, 0, target
, 0);
140 if (!s
->current_dev
) {
142 s
->rregs
[ESP_RSTAT
] = 0;
143 s
->rregs
[ESP_RINTR
] = INTR_DC
;
144 s
->rregs
[ESP_RSEQ
] = SEQ_0
;
151 static uint32_t get_cmd(ESPState
*s
, uint8_t *buf
, uint8_t buflen
)
156 target
= s
->wregs
[ESP_WBUSID
] & BUSID_DID
;
158 dmalen
= s
->rregs
[ESP_TCLO
];
159 dmalen
|= s
->rregs
[ESP_TCMID
] << 8;
160 dmalen
|= s
->rregs
[ESP_TCHI
] << 16;
161 if (dmalen
> buflen
) {
164 if (s
->dma_memory_read
) {
165 s
->dma_memory_read(s
->dma_opaque
, buf
, dmalen
);
167 memcpy(s
->pdma_buf
, buf
, dmalen
);
168 set_pdma(s
, PDMA
, 0, dmalen
);
174 if (dmalen
> TI_BUFSZ
) {
177 memcpy(buf
, s
->ti_buf
, dmalen
);
178 buf
[0] = buf
[2] >> 5;
180 trace_esp_get_cmd(dmalen
, target
);
182 if (get_cmd_cb(s
) < 0) {
188 static void do_busid_cmd(ESPState
*s
, uint8_t *buf
, uint8_t busid
)
192 SCSIDevice
*current_lun
;
194 trace_esp_do_busid_cmd(busid
);
196 current_lun
= scsi_device_find(&s
->bus
, 0, s
->current_dev
->id
, lun
);
197 s
->current_req
= scsi_req_new(current_lun
, 0, lun
, buf
, s
);
198 datalen
= scsi_req_enqueue(s
->current_req
);
199 s
->ti_size
= datalen
;
201 s
->rregs
[ESP_RSTAT
] = STAT_TC
;
205 s
->rregs
[ESP_RSTAT
] |= STAT_DI
;
207 s
->rregs
[ESP_RSTAT
] |= STAT_DO
;
209 scsi_req_continue(s
->current_req
);
211 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
212 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
216 static void do_cmd(ESPState
*s
, uint8_t *buf
)
218 uint8_t busid
= buf
[0];
220 do_busid_cmd(s
, &buf
[1], busid
);
223 static void satn_pdma_cb(ESPState
*s
)
225 if (get_cmd_cb(s
) < 0) {
228 if (s
->pdma_cur
!= s
->pdma_start
) {
229 do_cmd(s
, get_pdma_buf(s
) + s
->pdma_start
);
233 static void handle_satn(ESPState
*s
)
238 if (s
->dma
&& !s
->dma_enabled
) {
239 s
->dma_cb
= handle_satn
;
242 s
->pdma_cb
= satn_pdma_cb
;
243 len
= get_cmd(s
, buf
, sizeof(buf
));
249 static void s_without_satn_pdma_cb(ESPState
*s
)
251 if (get_cmd_cb(s
) < 0) {
254 if (s
->pdma_cur
!= s
->pdma_start
) {
255 do_busid_cmd(s
, get_pdma_buf(s
) + s
->pdma_start
, 0);
259 static void handle_s_without_atn(ESPState
*s
)
264 if (s
->dma
&& !s
->dma_enabled
) {
265 s
->dma_cb
= handle_s_without_atn
;
268 s
->pdma_cb
= s_without_satn_pdma_cb
;
269 len
= get_cmd(s
, buf
, sizeof(buf
));
271 do_busid_cmd(s
, buf
, 0);
275 static void satn_stop_pdma_cb(ESPState
*s
)
277 if (get_cmd_cb(s
) < 0) {
280 s
->cmdlen
= s
->pdma_cur
- s
->pdma_start
;
282 trace_esp_handle_satn_stop(s
->cmdlen
);
284 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_CD
;
285 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
286 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
291 static void handle_satn_stop(ESPState
*s
)
293 if (s
->dma
&& !s
->dma_enabled
) {
294 s
->dma_cb
= handle_satn_stop
;
297 s
->pdma_cb
= satn_stop_pdma_cb
;
298 s
->cmdlen
= get_cmd(s
, s
->cmdbuf
, sizeof(s
->cmdbuf
));
300 trace_esp_handle_satn_stop(s
->cmdlen
);
302 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_CD
;
303 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
304 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
309 static void write_response_pdma_cb(ESPState
*s
)
311 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_ST
;
312 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
313 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
317 static void write_response(ESPState
*s
)
319 trace_esp_write_response(s
->status
);
320 s
->ti_buf
[0] = s
->status
;
323 if (s
->dma_memory_write
) {
324 s
->dma_memory_write(s
->dma_opaque
, s
->ti_buf
, 2);
325 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_ST
;
326 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
327 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
329 set_pdma(s
, TI
, 0, 2);
330 s
->pdma_cb
= write_response_pdma_cb
;
338 s
->rregs
[ESP_RFLAGS
] = 2;
343 static void esp_dma_done(ESPState
*s
)
345 s
->rregs
[ESP_RSTAT
] |= STAT_TC
;
346 s
->rregs
[ESP_RINTR
] = INTR_BS
;
347 s
->rregs
[ESP_RSEQ
] = 0;
348 s
->rregs
[ESP_RFLAGS
] = 0;
349 s
->rregs
[ESP_TCLO
] = 0;
350 s
->rregs
[ESP_TCMID
] = 0;
351 s
->rregs
[ESP_TCHI
] = 0;
355 static void do_dma_pdma_cb(ESPState
*s
)
357 int to_device
= (s
->ti_size
< 0);
358 int len
= s
->pdma_cur
- s
->pdma_start
;
363 do_cmd(s
, s
->cmdbuf
);
374 if (s
->async_len
== 0) {
375 scsi_req_continue(s
->current_req
);
377 * If there is still data to be read from the device then
378 * complete the DMA operation immediately. Otherwise defer
379 * until the scsi layer has completed.
381 if (to_device
|| s
->dma_left
!= 0 || s
->ti_size
== 0) {
386 /* Partially filled a scsi buffer. Complete immediately. */
390 static void esp_do_dma(ESPState
*s
)
398 * handle_ti_cmd() case: esp_do_dma() is called only from
399 * handle_ti_cmd() with do_cmd != NULL (see the assert())
401 trace_esp_do_dma(s
->cmdlen
, len
);
402 assert(s
->cmdlen
<= sizeof(s
->cmdbuf
) &&
403 len
<= sizeof(s
->cmdbuf
) - s
->cmdlen
);
404 if (s
->dma_memory_read
) {
405 s
->dma_memory_read(s
->dma_opaque
, &s
->cmdbuf
[s
->cmdlen
], len
);
407 set_pdma(s
, CMD
, s
->cmdlen
, len
);
408 s
->pdma_cb
= do_dma_pdma_cb
;
412 trace_esp_handle_ti_cmd(s
->cmdlen
);
416 do_cmd(s
, s
->cmdbuf
);
419 if (s
->async_len
== 0) {
420 /* Defer until data is available. */
423 if (len
> s
->async_len
) {
426 to_device
= (s
->ti_size
< 0);
428 if (s
->dma_memory_read
) {
429 s
->dma_memory_read(s
->dma_opaque
, s
->async_buf
, len
);
431 set_pdma(s
, ASYNC
, 0, len
);
432 s
->pdma_cb
= do_dma_pdma_cb
;
437 if (s
->dma_memory_write
) {
438 s
->dma_memory_write(s
->dma_opaque
, s
->async_buf
, len
);
440 set_pdma(s
, ASYNC
, 0, len
);
441 s
->pdma_cb
= do_dma_pdma_cb
;
454 if (s
->async_len
== 0) {
455 scsi_req_continue(s
->current_req
);
457 * If there is still data to be read from the device then
458 * complete the DMA operation immediately. Otherwise defer
459 * until the scsi layer has completed.
461 if (to_device
|| s
->dma_left
!= 0 || s
->ti_size
== 0) {
466 /* Partially filled a scsi buffer. Complete immediately. */
470 static void esp_report_command_complete(ESPState
*s
, uint32_t status
)
472 trace_esp_command_complete();
473 if (s
->ti_size
!= 0) {
474 trace_esp_command_complete_unexpected();
480 trace_esp_command_complete_fail();
483 s
->rregs
[ESP_RSTAT
] = STAT_ST
;
485 if (s
->current_req
) {
486 scsi_req_unref(s
->current_req
);
487 s
->current_req
= NULL
;
488 s
->current_dev
= NULL
;
492 void esp_command_complete(SCSIRequest
*req
, size_t resid
)
494 ESPState
*s
= req
->hba_private
;
496 if (s
->rregs
[ESP_RSTAT
] & STAT_INT
) {
498 * Defer handling command complete until the previous
499 * interrupt has been handled.
501 trace_esp_command_complete_deferred();
502 s
->deferred_status
= req
->status
;
503 s
->deferred_complete
= true;
506 esp_report_command_complete(s
, req
->status
);
509 void esp_transfer_data(SCSIRequest
*req
, uint32_t len
)
511 ESPState
*s
= req
->hba_private
;
514 trace_esp_transfer_data(s
->dma_left
, s
->ti_size
);
516 s
->async_buf
= scsi_req_get_buf(req
);
519 } else if (s
->dma_counter
!= 0 && s
->ti_size
<= 0) {
521 * If this was the last part of a DMA transfer then the
522 * completion interrupt is deferred to here.
528 static void handle_ti(ESPState
*s
)
530 uint32_t dmalen
, minlen
;
532 if (s
->dma
&& !s
->dma_enabled
) {
533 s
->dma_cb
= handle_ti
;
537 dmalen
= s
->rregs
[ESP_TCLO
];
538 dmalen
|= s
->rregs
[ESP_TCMID
] << 8;
539 dmalen
|= s
->rregs
[ESP_TCHI
] << 16;
543 s
->dma_counter
= dmalen
;
546 minlen
= (dmalen
< ESP_CMDBUF_SZ
) ? dmalen
: ESP_CMDBUF_SZ
;
547 } else if (s
->ti_size
< 0) {
548 minlen
= (dmalen
< -s
->ti_size
) ? dmalen
: -s
->ti_size
;
550 minlen
= (dmalen
< s
->ti_size
) ? dmalen
: s
->ti_size
;
552 trace_esp_handle_ti(minlen
);
554 s
->dma_left
= minlen
;
555 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
557 } else if (s
->do_cmd
) {
558 trace_esp_handle_ti_cmd(s
->cmdlen
);
562 do_cmd(s
, s
->cmdbuf
);
566 void esp_hard_reset(ESPState
*s
)
568 memset(s
->rregs
, 0, ESP_REGS
);
569 memset(s
->wregs
, 0, ESP_REGS
);
578 s
->rregs
[ESP_CFG1
] = 7;
581 static void esp_soft_reset(ESPState
*s
)
583 qemu_irq_lower(s
->irq
);
584 qemu_irq_lower(s
->irq_data
);
588 static void parent_esp_reset(ESPState
*s
, int irq
, int level
)
595 uint64_t esp_reg_read(ESPState
*s
, uint32_t saddr
)
601 if ((s
->rregs
[ESP_RSTAT
] & STAT_PIO_MASK
) == 0) {
603 qemu_log_mask(LOG_UNIMP
, "esp: PIO data read not implemented\n");
604 s
->rregs
[ESP_FIFO
] = 0;
605 } else if (s
->ti_rptr
< s
->ti_wptr
) {
607 s
->rregs
[ESP_FIFO
] = s
->ti_buf
[s
->ti_rptr
++];
609 if (s
->ti_rptr
== s
->ti_wptr
) {
613 val
= s
->rregs
[ESP_FIFO
];
617 * Clear sequence step, interrupt register and all status bits
620 val
= s
->rregs
[ESP_RINTR
];
621 s
->rregs
[ESP_RINTR
] = 0;
622 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
623 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
625 if (s
->deferred_complete
) {
626 esp_report_command_complete(s
, s
->deferred_status
);
627 s
->deferred_complete
= false;
631 /* Return the unique id if the value has never been written */
632 if (!s
->tchi_written
) {
635 val
= s
->rregs
[saddr
];
639 val
= s
->rregs
[saddr
];
643 trace_esp_mem_readb(saddr
, val
);
647 void esp_reg_write(ESPState
*s
, uint32_t saddr
, uint64_t val
)
649 trace_esp_mem_writeb(saddr
, s
->wregs
[saddr
], val
);
652 s
->tchi_written
= true;
656 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
660 if (s
->cmdlen
< ESP_CMDBUF_SZ
) {
661 s
->cmdbuf
[s
->cmdlen
++] = val
& 0xff;
663 trace_esp_error_fifo_overrun();
665 } else if (s
->ti_wptr
== TI_BUFSZ
- 1) {
666 trace_esp_error_fifo_overrun();
669 s
->ti_buf
[s
->ti_wptr
++] = val
& 0xff;
673 s
->rregs
[saddr
] = val
;
676 /* Reload DMA counter. */
677 s
->rregs
[ESP_TCLO
] = s
->wregs
[ESP_TCLO
];
678 s
->rregs
[ESP_TCMID
] = s
->wregs
[ESP_TCMID
];
679 s
->rregs
[ESP_TCHI
] = s
->wregs
[ESP_TCHI
];
683 switch (val
& CMD_CMD
) {
685 trace_esp_mem_writeb_cmd_nop(val
);
688 trace_esp_mem_writeb_cmd_flush(val
);
690 s
->rregs
[ESP_RINTR
] = INTR_FC
;
691 s
->rregs
[ESP_RSEQ
] = 0;
692 s
->rregs
[ESP_RFLAGS
] = 0;
695 trace_esp_mem_writeb_cmd_reset(val
);
699 trace_esp_mem_writeb_cmd_bus_reset(val
);
700 s
->rregs
[ESP_RINTR
] = INTR_RST
;
701 if (!(s
->wregs
[ESP_CFG1
] & CFG1_RESREPT
)) {
706 trace_esp_mem_writeb_cmd_ti(val
);
710 trace_esp_mem_writeb_cmd_iccs(val
);
712 s
->rregs
[ESP_RINTR
] = INTR_FC
;
713 s
->rregs
[ESP_RSTAT
] |= STAT_MI
;
716 trace_esp_mem_writeb_cmd_msgacc(val
);
717 s
->rregs
[ESP_RINTR
] = INTR_DC
;
718 s
->rregs
[ESP_RSEQ
] = 0;
719 s
->rregs
[ESP_RFLAGS
] = 0;
723 trace_esp_mem_writeb_cmd_pad(val
);
724 s
->rregs
[ESP_RSTAT
] = STAT_TC
;
725 s
->rregs
[ESP_RINTR
] = INTR_FC
;
726 s
->rregs
[ESP_RSEQ
] = 0;
729 trace_esp_mem_writeb_cmd_satn(val
);
732 trace_esp_mem_writeb_cmd_rstatn(val
);
735 trace_esp_mem_writeb_cmd_sel(val
);
736 handle_s_without_atn(s
);
739 trace_esp_mem_writeb_cmd_selatn(val
);
743 trace_esp_mem_writeb_cmd_selatns(val
);
747 trace_esp_mem_writeb_cmd_ensel(val
);
748 s
->rregs
[ESP_RINTR
] = 0;
751 trace_esp_mem_writeb_cmd_dissel(val
);
752 s
->rregs
[ESP_RINTR
] = 0;
756 trace_esp_error_unhandled_command(val
);
760 case ESP_WBUSID
... ESP_WSYNO
:
763 case ESP_CFG2
: case ESP_CFG3
:
764 case ESP_RES3
: case ESP_RES4
:
765 s
->rregs
[saddr
] = val
;
767 case ESP_WCCF
... ESP_WTEST
:
770 trace_esp_error_invalid_write(val
, saddr
);
773 s
->wregs
[saddr
] = val
;
776 static bool esp_mem_accepts(void *opaque
, hwaddr addr
,
777 unsigned size
, bool is_write
,
780 return (size
== 1) || (is_write
&& size
== 4);
783 static bool esp_pdma_needed(void *opaque
)
785 ESPState
*s
= opaque
;
786 return s
->dma_memory_read
== NULL
&& s
->dma_memory_write
== NULL
&&
790 static const VMStateDescription vmstate_esp_pdma
= {
793 .minimum_version_id
= 1,
794 .needed
= esp_pdma_needed
,
795 .fields
= (VMStateField
[]) {
796 VMSTATE_BUFFER(pdma_buf
, ESPState
),
797 VMSTATE_INT32(pdma_origin
, ESPState
),
798 VMSTATE_UINT32(pdma_len
, ESPState
),
799 VMSTATE_UINT32(pdma_start
, ESPState
),
800 VMSTATE_UINT32(pdma_cur
, ESPState
),
801 VMSTATE_END_OF_LIST()
805 static int esp_pre_save(void *opaque
)
807 ESPState
*s
= ESP(opaque
);
809 s
->mig_version_id
= vmstate_esp
.version_id
;
813 static int esp_post_load(void *opaque
, int version_id
)
815 ESPState
*s
= ESP(opaque
);
817 s
->mig_version_id
= vmstate_esp
.version_id
;
821 const VMStateDescription vmstate_esp
= {
824 .minimum_version_id
= 3,
825 .pre_save
= esp_pre_save
,
826 .post_load
= esp_post_load
,
827 .fields
= (VMStateField
[]) {
828 VMSTATE_BUFFER(rregs
, ESPState
),
829 VMSTATE_BUFFER(wregs
, ESPState
),
830 VMSTATE_INT32(ti_size
, ESPState
),
831 VMSTATE_UINT32(ti_rptr
, ESPState
),
832 VMSTATE_UINT32(ti_wptr
, ESPState
),
833 VMSTATE_BUFFER(ti_buf
, ESPState
),
834 VMSTATE_UINT32(status
, ESPState
),
835 VMSTATE_UINT32(deferred_status
, ESPState
),
836 VMSTATE_BOOL(deferred_complete
, ESPState
),
837 VMSTATE_UINT32(dma
, ESPState
),
838 VMSTATE_PARTIAL_BUFFER(cmdbuf
, ESPState
, 16),
839 VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf
, ESPState
, 16, 4),
840 VMSTATE_UINT32(cmdlen
, ESPState
),
841 VMSTATE_UINT32(do_cmd
, ESPState
),
842 VMSTATE_UINT32(dma_left
, ESPState
),
843 VMSTATE_END_OF_LIST()
845 .subsections
= (const VMStateDescription
* []) {
851 static void sysbus_esp_mem_write(void *opaque
, hwaddr addr
,
852 uint64_t val
, unsigned int size
)
854 SysBusESPState
*sysbus
= opaque
;
855 ESPState
*s
= ESP(&sysbus
->esp
);
858 saddr
= addr
>> sysbus
->it_shift
;
859 esp_reg_write(s
, saddr
, val
);
862 static uint64_t sysbus_esp_mem_read(void *opaque
, hwaddr addr
,
865 SysBusESPState
*sysbus
= opaque
;
866 ESPState
*s
= ESP(&sysbus
->esp
);
869 saddr
= addr
>> sysbus
->it_shift
;
870 return esp_reg_read(s
, saddr
);
873 static const MemoryRegionOps sysbus_esp_mem_ops
= {
874 .read
= sysbus_esp_mem_read
,
875 .write
= sysbus_esp_mem_write
,
876 .endianness
= DEVICE_NATIVE_ENDIAN
,
877 .valid
.accepts
= esp_mem_accepts
,
880 static void sysbus_esp_pdma_write(void *opaque
, hwaddr addr
,
881 uint64_t val
, unsigned int size
)
883 SysBusESPState
*sysbus
= opaque
;
884 ESPState
*s
= ESP(&sysbus
->esp
);
886 uint8_t *buf
= get_pdma_buf(s
);
888 dmalen
= s
->rregs
[ESP_TCLO
];
889 dmalen
|= s
->rregs
[ESP_TCMID
] << 8;
890 dmalen
|= s
->rregs
[ESP_TCHI
] << 16;
891 if (dmalen
== 0 || s
->pdma_len
== 0) {
896 buf
[s
->pdma_cur
++] = val
;
901 buf
[s
->pdma_cur
++] = val
>> 8;
902 buf
[s
->pdma_cur
++] = val
;
907 s
->rregs
[ESP_TCLO
] = dmalen
& 0xff;
908 s
->rregs
[ESP_TCMID
] = dmalen
>> 8;
909 s
->rregs
[ESP_TCHI
] = dmalen
>> 16;
910 if (s
->pdma_len
== 0 && s
->pdma_cb
) {
917 static uint64_t sysbus_esp_pdma_read(void *opaque
, hwaddr addr
,
920 SysBusESPState
*sysbus
= opaque
;
921 ESPState
*s
= ESP(&sysbus
->esp
);
922 uint8_t *buf
= get_pdma_buf(s
);
925 if (s
->pdma_len
== 0) {
930 val
= buf
[s
->pdma_cur
++];
934 val
= buf
[s
->pdma_cur
++];
935 val
= (val
<< 8) | buf
[s
->pdma_cur
++];
940 if (s
->pdma_len
== 0 && s
->pdma_cb
) {
948 static const MemoryRegionOps sysbus_esp_pdma_ops
= {
949 .read
= sysbus_esp_pdma_read
,
950 .write
= sysbus_esp_pdma_write
,
951 .endianness
= DEVICE_NATIVE_ENDIAN
,
952 .valid
.min_access_size
= 1,
953 .valid
.max_access_size
= 2,
956 static const struct SCSIBusInfo esp_scsi_info
= {
958 .max_target
= ESP_MAX_DEVS
,
961 .transfer_data
= esp_transfer_data
,
962 .complete
= esp_command_complete
,
963 .cancel
= esp_request_cancelled
966 static void sysbus_esp_gpio_demux(void *opaque
, int irq
, int level
)
968 SysBusESPState
*sysbus
= SYSBUS_ESP(opaque
);
969 ESPState
*s
= ESP(&sysbus
->esp
);
973 parent_esp_reset(s
, irq
, level
);
976 esp_dma_enable(opaque
, irq
, level
);
981 static void sysbus_esp_realize(DeviceState
*dev
, Error
**errp
)
983 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
984 SysBusESPState
*sysbus
= SYSBUS_ESP(dev
);
985 ESPState
*s
= ESP(&sysbus
->esp
);
987 if (!qdev_realize(DEVICE(s
), NULL
, errp
)) {
991 sysbus_init_irq(sbd
, &s
->irq
);
992 sysbus_init_irq(sbd
, &s
->irq_data
);
993 assert(sysbus
->it_shift
!= -1);
995 s
->chip_id
= TCHI_FAS100A
;
996 memory_region_init_io(&sysbus
->iomem
, OBJECT(sysbus
), &sysbus_esp_mem_ops
,
997 sysbus
, "esp-regs", ESP_REGS
<< sysbus
->it_shift
);
998 sysbus_init_mmio(sbd
, &sysbus
->iomem
);
999 memory_region_init_io(&sysbus
->pdma
, OBJECT(sysbus
), &sysbus_esp_pdma_ops
,
1000 sysbus
, "esp-pdma", 2);
1001 sysbus_init_mmio(sbd
, &sysbus
->pdma
);
1003 qdev_init_gpio_in(dev
, sysbus_esp_gpio_demux
, 2);
1005 scsi_bus_new(&s
->bus
, sizeof(s
->bus
), dev
, &esp_scsi_info
, NULL
);
1008 static void sysbus_esp_hard_reset(DeviceState
*dev
)
1010 SysBusESPState
*sysbus
= SYSBUS_ESP(dev
);
1011 ESPState
*s
= ESP(&sysbus
->esp
);
1016 static void sysbus_esp_init(Object
*obj
)
1018 SysBusESPState
*sysbus
= SYSBUS_ESP(obj
);
1020 object_initialize_child(obj
, "esp", &sysbus
->esp
, TYPE_ESP
);
1023 static const VMStateDescription vmstate_sysbus_esp_scsi
= {
1024 .name
= "sysbusespscsi",
1026 .minimum_version_id
= 1,
1027 .fields
= (VMStateField
[]) {
1028 VMSTATE_UINT8_V(esp
.mig_version_id
, SysBusESPState
, 2),
1029 VMSTATE_STRUCT(esp
, SysBusESPState
, 0, vmstate_esp
, ESPState
),
1030 VMSTATE_END_OF_LIST()
1034 static void sysbus_esp_class_init(ObjectClass
*klass
, void *data
)
1036 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1038 dc
->realize
= sysbus_esp_realize
;
1039 dc
->reset
= sysbus_esp_hard_reset
;
1040 dc
->vmsd
= &vmstate_sysbus_esp_scsi
;
1041 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1044 static const TypeInfo sysbus_esp_info
= {
1045 .name
= TYPE_SYSBUS_ESP
,
1046 .parent
= TYPE_SYS_BUS_DEVICE
,
1047 .instance_init
= sysbus_esp_init
,
1048 .instance_size
= sizeof(SysBusESPState
),
1049 .class_init
= sysbus_esp_class_init
,
1052 static void esp_class_init(ObjectClass
*klass
, void *data
)
1054 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1056 /* internal device for sysbusesp/pciespscsi, not user-creatable */
1057 dc
->user_creatable
= false;
1058 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1061 static const TypeInfo esp_info
= {
1063 .parent
= TYPE_DEVICE
,
1064 .instance_size
= sizeof(ESPState
),
1065 .class_init
= esp_class_init
,
1068 static void esp_register_types(void)
1070 type_register_static(&sysbus_esp_info
);
1071 type_register_static(&esp_info
);
1074 type_init(esp_register_types
)