Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210330' into...
[qemu/ar7.git] / util / cacheinfo.c
blobb182f0b6936c2324c901b28c8d66e33c189d55a8
1 /*
2 * cacheinfo.c - helpers to query the host about its caches
4 * Copyright (C) 2017, Emilio G. Cota <cota@braap.org>
5 * License: GNU GPL, version 2 or later.
6 * See the COPYING file in the top-level directory.
7 */
9 #include "qemu/osdep.h"
10 #include "qemu/host-utils.h"
11 #include "qemu/atomic.h"
13 int qemu_icache_linesize = 0;
14 int qemu_icache_linesize_log;
15 int qemu_dcache_linesize = 0;
16 int qemu_dcache_linesize_log;
19 * Operating system specific detection mechanisms.
22 #if defined(_WIN32)
24 static void sys_cache_info(int *isize, int *dsize)
26 SYSTEM_LOGICAL_PROCESSOR_INFORMATION *buf;
27 DWORD size = 0;
28 BOOL success;
29 size_t i, n;
31 /* Check for the required buffer size first. Note that if the zero
32 size we use for the probe results in success, then there is no
33 data available; fail in that case. */
34 success = GetLogicalProcessorInformation(0, &size);
35 if (success || GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
36 return;
39 n = size / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
40 size = n * sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
41 buf = g_new0(SYSTEM_LOGICAL_PROCESSOR_INFORMATION, n);
42 if (!GetLogicalProcessorInformation(buf, &size)) {
43 goto fail;
46 for (i = 0; i < n; i++) {
47 if (buf[i].Relationship == RelationCache
48 && buf[i].Cache.Level == 1) {
49 switch (buf[i].Cache.Type) {
50 case CacheUnified:
51 *isize = *dsize = buf[i].Cache.LineSize;
52 break;
53 case CacheInstruction:
54 *isize = buf[i].Cache.LineSize;
55 break;
56 case CacheData:
57 *dsize = buf[i].Cache.LineSize;
58 break;
59 default:
60 break;
64 fail:
65 g_free(buf);
68 #elif defined(__APPLE__)
69 # include <sys/sysctl.h>
70 static void sys_cache_info(int *isize, int *dsize)
72 /* There's only a single sysctl for both I/D cache line sizes. */
73 long size;
74 size_t len = sizeof(size);
75 if (!sysctlbyname("hw.cachelinesize", &size, &len, NULL, 0)) {
76 *isize = *dsize = size;
79 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
80 # include <sys/sysctl.h>
81 static void sys_cache_info(int *isize, int *dsize)
83 /* There's only a single sysctl for both I/D cache line sizes. */
84 int size;
85 size_t len = sizeof(size);
86 if (!sysctlbyname("machdep.cacheline_size", &size, &len, NULL, 0)) {
87 *isize = *dsize = size;
90 #else
91 /* POSIX */
93 static void sys_cache_info(int *isize, int *dsize)
95 # ifdef _SC_LEVEL1_ICACHE_LINESIZE
96 int tmp_isize = (int) sysconf(_SC_LEVEL1_ICACHE_LINESIZE);
97 if (tmp_isize > 0) {
98 *isize = tmp_isize;
100 # endif
101 # ifdef _SC_LEVEL1_DCACHE_LINESIZE
102 int tmp_dsize = (int) sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
103 if (tmp_dsize > 0) {
104 *dsize = tmp_dsize;
106 # endif
108 #endif /* sys_cache_info */
111 * Architecture (+ OS) specific detection mechanisms.
114 #if defined(__aarch64__)
116 static void arch_cache_info(int *isize, int *dsize)
118 if (*isize == 0 || *dsize == 0) {
119 uint64_t ctr;
121 /* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,
122 but (at least under Linux) these are marked protected by the
123 kernel. However, CTR_EL0 contains the minimum linesize in the
124 entire hierarchy, and is used by userspace cache flushing. */
125 asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
126 if (*isize == 0) {
127 *isize = 4 << (ctr & 0xf);
129 if (*dsize == 0) {
130 *dsize = 4 << ((ctr >> 16) & 0xf);
135 #elif defined(_ARCH_PPC) && defined(__linux__)
136 # include "elf.h"
138 static void arch_cache_info(int *isize, int *dsize)
140 if (*isize == 0) {
141 *isize = qemu_getauxval(AT_ICACHEBSIZE);
143 if (*dsize == 0) {
144 *dsize = qemu_getauxval(AT_DCACHEBSIZE);
148 #else
149 static void arch_cache_info(int *isize, int *dsize) { }
150 #endif /* arch_cache_info */
153 * ... and if all else fails ...
156 static void fallback_cache_info(int *isize, int *dsize)
158 /* If we can only find one of the two, assume they're the same. */
159 if (*isize) {
160 if (*dsize) {
161 /* Success! */
162 } else {
163 *dsize = *isize;
165 } else if (*dsize) {
166 *isize = *dsize;
167 } else {
168 #if defined(_ARCH_PPC)
170 * For PPC, we're going to use the cache sizes computed for
171 * flush_idcache_range. Which means that we must use the
172 * architecture minimum.
174 *isize = *dsize = 16;
175 #else
176 /* Otherwise, 64 bytes is not uncommon. */
177 *isize = *dsize = 64;
178 #endif
182 static void __attribute__((constructor)) init_cache_info(void)
184 int isize = 0, dsize = 0;
186 sys_cache_info(&isize, &dsize);
187 arch_cache_info(&isize, &dsize);
188 fallback_cache_info(&isize, &dsize);
190 assert((isize & (isize - 1)) == 0);
191 assert((dsize & (dsize - 1)) == 0);
193 qemu_icache_linesize = isize;
194 qemu_icache_linesize_log = ctz32(isize);
195 qemu_dcache_linesize = dsize;
196 qemu_dcache_linesize_log = ctz32(dsize);
198 qatomic64_init();