4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "exec-memory.h"
31 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
33 #define RAVEN_PCI_HOST_BRIDGE(obj) \
34 OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
36 typedef struct PRePPCIState
{
37 PCIHostState host_state
;
43 typedef struct RavenPCIState
{
47 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr
)
51 for (i
= 0; i
< 11; i
++) {
52 if ((addr
& (1 << (11 + i
))) != 0) {
56 return (addr
& 0x7ff) | (i
<< 11);
59 static void ppc_pci_io_write(void *opaque
, target_phys_addr_t addr
,
60 uint64_t val
, unsigned int size
)
62 PREPPCIState
*s
= opaque
;
63 pci_data_write(s
->host_state
.bus
, PPC_PCIIO_config(addr
), val
, size
);
66 static uint64_t ppc_pci_io_read(void *opaque
, target_phys_addr_t addr
,
69 PREPPCIState
*s
= opaque
;
70 return pci_data_read(s
->host_state
.bus
, PPC_PCIIO_config(addr
), size
);
73 static const MemoryRegionOps PPC_PCIIO_ops
= {
74 .read
= ppc_pci_io_read
,
75 .write
= ppc_pci_io_write
,
76 .endianness
= DEVICE_LITTLE_ENDIAN
,
79 static uint64_t ppc_intack_read(void *opaque
, target_phys_addr_t addr
,
82 return pic_read_irq(isa_pic
);
85 static const MemoryRegionOps PPC_intack_ops
= {
86 .read
= ppc_intack_read
,
92 static int prep_map_irq(PCIDevice
*pci_dev
, int irq_num
)
94 return (irq_num
+ (pci_dev
->devfn
>> 3)) & 1;
97 static void prep_set_irq(void *opaque
, int irq_num
, int level
)
99 qemu_irq
*pic
= opaque
;
101 qemu_set_irq(pic
[irq_num
] , level
);
104 static int raven_pcihost_init(SysBusDevice
*dev
)
106 PCIHostState
*h
= FROM_SYSBUS(PCIHostState
, dev
);
107 PREPPCIState
*s
= RAVEN_PCI_HOST_BRIDGE(dev
);
108 MemoryRegion
*address_space_mem
= get_system_memory();
109 MemoryRegion
*address_space_io
= get_system_io();
113 for (i
= 0; i
< 4; i
++) {
114 sysbus_init_irq(dev
, &s
->irq
[i
]);
117 bus
= pci_register_bus(DEVICE(dev
), NULL
,
118 prep_set_irq
, prep_map_irq
, s
->irq
,
119 address_space_mem
, address_space_io
, 0, 4);
122 memory_region_init_io(&h
->conf_mem
, &pci_host_conf_be_ops
, s
,
124 sysbus_add_io(dev
, 0xcf8, &h
->conf_mem
);
125 sysbus_init_ioports(&h
->busdev
, 0xcf8, 1);
127 memory_region_init_io(&h
->data_mem
, &pci_host_data_be_ops
, s
,
129 sysbus_add_io(dev
, 0xcfc, &h
->data_mem
);
130 sysbus_init_ioports(&h
->busdev
, 0xcfc, 1);
132 memory_region_init_io(&h
->mmcfg
, &PPC_PCIIO_ops
, s
, "pciio", 0x00400000);
133 memory_region_add_subregion(address_space_mem
, 0x80800000, &h
->mmcfg
);
135 memory_region_init_io(&s
->intack
, &PPC_intack_ops
, s
, "pci-intack", 1);
136 memory_region_add_subregion(address_space_mem
, 0xbffffff0, &s
->intack
);
137 pci_create_simple(bus
, 0, "raven");
142 static int raven_init(PCIDevice
*d
)
144 d
->config
[0x0C] = 0x08; // cache_line_size
145 d
->config
[0x0D] = 0x10; // latency_timer
146 d
->config
[0x34] = 0x00; // capabilities_pointer
151 static const VMStateDescription vmstate_raven
= {
154 .minimum_version_id
= 0,
155 .fields
= (VMStateField
[]) {
156 VMSTATE_PCI_DEVICE(dev
, RavenPCIState
),
157 VMSTATE_END_OF_LIST()
161 static void raven_class_init(ObjectClass
*klass
, void *data
)
163 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
164 DeviceClass
*dc
= DEVICE_CLASS(klass
);
166 k
->init
= raven_init
;
167 k
->vendor_id
= PCI_VENDOR_ID_MOTOROLA
;
168 k
->device_id
= PCI_DEVICE_ID_MOTOROLA_RAVEN
;
170 k
->class_id
= PCI_CLASS_BRIDGE_HOST
;
171 dc
->desc
= "PReP Host Bridge - Motorola Raven";
172 dc
->vmsd
= &vmstate_raven
;
176 static const TypeInfo raven_info
= {
178 .parent
= TYPE_PCI_DEVICE
,
179 .instance_size
= sizeof(RavenPCIState
),
180 .class_init
= raven_class_init
,
183 static void raven_pcihost_class_init(ObjectClass
*klass
, void *data
)
185 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
186 DeviceClass
*dc
= DEVICE_CLASS(klass
);
188 k
->init
= raven_pcihost_init
;
193 static const TypeInfo raven_pcihost_info
= {
194 .name
= TYPE_RAVEN_PCI_HOST_BRIDGE
,
195 .parent
= TYPE_SYS_BUS_DEVICE
,
196 .instance_size
= sizeof(PREPPCIState
),
197 .class_init
= raven_pcihost_class_init
,
200 static void raven_register_types(void)
202 type_register_static(&raven_pcihost_info
);
203 type_register_static(&raven_info
);
206 type_init(raven_register_types
)