?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
hw/audio/ac97: Coding style fixes to avoid checkpatch errors
[qemu/ar7.git] / hw / audio / ac97.c
blob6b1c12bece0c895230d7a84f26dde72c60991c8a
1 /*
2 * Copyright (C) 2006 InnoTek Systemberatung GmbH
3 *
4 * This file is part of VirtualBox Open Source Edition (OSE), as
5 * available from http://www.virtualbox.org. This file is free software;
6 * you can redistribute it and/or modify it under the terms of the GNU
7 * General Public License as published by the Free Software Foundation,
8 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
9 * distribution. VirtualBox OSE is distributed in the hope that it will
10 * be useful, but WITHOUT ANY WARRANTY of any kind.
11 *
12 * If you received this file as part of a commercial VirtualBox
13 * distribution, then only the terms of your commercial VirtualBox
14 * license agreement apply instead of the previous paragraph.
15 *
16 * Contributions after 2012-01-13 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/audio/soundhw.h"
22 #include "audio/audio.h"
23 #include "hw/pci/pci.h"
24 #include "hw/qdev-properties.h"
25 #include "migration/vmstate.h"
26 #include "qemu/module.h"
27 #include "sysemu/dma.h"
28 #include "qom/object.h"
29
30 enum {
31 AC97_Reset = 0x00,
32 AC97_Master_Volume_Mute = 0x02,
33 AC97_Headphone_Volume_Mute = 0x04,
34 AC97_Master_Volume_Mono_Mute = 0x06,
35 AC97_Master_Tone_RL = 0x08,
36 AC97_PC_BEEP_Volume_Mute = 0x0A,
37 AC97_Phone_Volume_Mute = 0x0C,
38 AC97_Mic_Volume_Mute = 0x0E,
39 AC97_Line_In_Volume_Mute = 0x10,
40 AC97_CD_Volume_Mute = 0x12,
41 AC97_Video_Volume_Mute = 0x14,
42 AC97_Aux_Volume_Mute = 0x16,
43 AC97_PCM_Out_Volume_Mute = 0x18,
44 AC97_Record_Select = 0x1A,
45 AC97_Record_Gain_Mute = 0x1C,
46 AC97_Record_Gain_Mic_Mute = 0x1E,
47 AC97_General_Purpose = 0x20,
48 AC97_3D_Control = 0x22,
49 AC97_AC_97_RESERVED = 0x24,
50 AC97_Powerdown_Ctrl_Stat = 0x26,
51 AC97_Extended_Audio_ID = 0x28,
52 AC97_Extended_Audio_Ctrl_Stat = 0x2A,
53 AC97_PCM_Front_DAC_Rate = 0x2C,
54 AC97_PCM_Surround_DAC_Rate = 0x2E,
55 AC97_PCM_LFE_DAC_Rate = 0x30,
56 AC97_PCM_LR_ADC_Rate = 0x32,
57 AC97_MIC_ADC_Rate = 0x34,
58 AC97_6Ch_Vol_C_LFE_Mute = 0x36,
59 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
60 AC97_Vendor_Reserved = 0x58,
61 AC97_Sigmatel_Analog = 0x6c, /* We emulate a Sigmatel codec */
62 AC97_Sigmatel_Dac2Invert = 0x6e, /* We emulate a Sigmatel codec */
63 AC97_Vendor_ID1 = 0x7c,
64 AC97_Vendor_ID2 = 0x7e
65 };
66
67 #define SOFT_VOLUME
68 #define SR_FIFOE 16 /* rwc */
69 #define SR_BCIS 8 /* rwc */
70 #define SR_LVBCI 4 /* rwc */
71 #define SR_CELV 2 /* ro */
72 #define SR_DCH 1 /* ro */
73 #define SR_VALID_MASK ((1 << 5) - 1)
74 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
75 #define SR_RO_MASK (SR_DCH | SR_CELV)
76 #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
77
78 #define CR_IOCE 16 /* rw */
79 #define CR_FEIE 8 /* rw */
80 #define CR_LVBIE 4 /* rw */
81 #define CR_RR 2 /* rw */
82 #define CR_RPBM 1 /* rw */
83 #define CR_VALID_MASK ((1 << 5) - 1)
84 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
85
86 #define GC_WR 4 /* rw */
87 #define GC_CR 2 /* rw */
88 #define GC_VALID_MASK ((1 << 6) - 1)
89
90 #define GS_MD3 (1 << 17) /* rw */
91 #define GS_AD3 (1 << 16) /* rw */
92 #define GS_RCS (1 << 15) /* rwc */
93 #define GS_B3S12 (1 << 14) /* ro */
94 #define GS_B2S12 (1 << 13) /* ro */
95 #define GS_B1S12 (1 << 12) /* ro */
96 #define GS_S1R1 (1 << 11) /* rwc */
97 #define GS_S0R1 (1 << 10) /* rwc */
98 #define GS_S1CR (1 << 9) /* ro */
99 #define GS_S0CR (1 << 8) /* ro */
100 #define GS_MINT (1 << 7) /* ro */
101 #define GS_POINT (1 << 6) /* ro */
102 #define GS_PIINT (1 << 5) /* ro */
103 #define GS_RSRVD ((1 << 4) | (1 << 3))
104 #define GS_MOINT (1 << 2) /* ro */
105 #define GS_MIINT (1 << 1) /* ro */
106 #define GS_GSCI 1 /* rwc */
107 #define GS_RO_MASK (GS_B3S12 | \
108 GS_B2S12 | \
109 GS_B1S12 | \
110 GS_S1CR | \
111 GS_S0CR | \
112 GS_MINT | \
113 GS_POINT | \
114 GS_PIINT | \
115 GS_RSRVD | \
116 GS_MOINT | \
117 GS_MIINT)
118 #define GS_VALID_MASK ((1 << 18) - 1)
119 #define GS_WCLEAR_MASK (GS_RCS | GS_S1R1 | GS_S0R1 | GS_GSCI)
120
121 #define BD_IOC (1 << 31)
122 #define BD_BUP (1 << 30)
123
124 #define EACS_VRA 1
125 #define EACS_VRM 8
126
127 #define MUTE_SHIFT 15
128
129 #define TYPE_AC97 "AC97"
130 OBJECT_DECLARE_SIMPLE_TYPE(AC97LinkState, AC97)
131
132 #define REC_MASK 7
133 enum {
134 REC_MIC = 0,
135 REC_CD,
136 REC_VIDEO,
137 REC_AUX,
138 REC_LINE_IN,
139 REC_STEREO_MIX,
140 REC_MONO_MIX,
141 REC_PHONE
142 };
143
144 typedef struct BD {
145 uint32_t addr;
146 uint32_t ctl_len;
147 } BD;
148
149 typedef struct AC97BusMasterRegs {
150 uint32_t bdbar; /* rw 0 */
151 uint8_t civ; /* ro 0 */
152 uint8_t lvi; /* rw 0 */
153 uint16_t sr; /* rw 1 */
154 uint16_t picb; /* ro 0 */
155 uint8_t piv; /* ro 0 */
156 uint8_t cr; /* rw 0 */
157 unsigned int bd_valid;
158 BD bd;
159 } AC97BusMasterRegs;
160
161 struct AC97LinkState {
162 PCIDevice dev;
163 QEMUSoundCard card;
164 uint32_t glob_cnt;
165 uint32_t glob_sta;
166 uint32_t cas;
167 uint32_t last_samp;
168 AC97BusMasterRegs bm_regs[3];
169 uint8_t mixer_data[256];
170 SWVoiceIn *voice_pi;
171 SWVoiceOut *voice_po;
172 SWVoiceIn *voice_mc;
173 int invalid_freq[3];
174 uint8_t silence[128];
175 int bup_flag;
176 MemoryRegion io_nam;
177 MemoryRegion io_nabm;
178 };
179
180 enum {
181 BUP_SET = 1,
182 BUP_LAST = 2
183 };
184
185 #ifdef DEBUG_AC97
186 #define dolog(...) AUD_log("ac97", __VA_ARGS__)
187 #else
188 #define dolog(...)
189 #endif
190
191 #define MKREGS(prefix, start) \
192 enum { \
193 prefix ## _BDBAR = start, \
194 prefix ## _CIV = start + 4, \
195 prefix ## _LVI = start + 5, \
196 prefix ## _SR = start + 6, \
197 prefix ## _PICB = start + 8, \
198 prefix ## _PIV = start + 10, \
199 prefix ## _CR = start + 11 \
200 }
201
202 enum {
203 PI_INDEX = 0,
204 PO_INDEX,
205 MC_INDEX,
206 LAST_INDEX
207 };
208
209 MKREGS(PI, PI_INDEX * 16);
210 MKREGS(PO, PO_INDEX * 16);
211 MKREGS(MC, MC_INDEX * 16);
212
213 enum {
214 GLOB_CNT = 0x2c,
215 GLOB_STA = 0x30,
216 CAS = 0x34
217 };
218
219 #define GET_BM(index) (((index) >> 4) & 3)
220
221 static void po_callback(void *opaque, int free);
222 static void pi_callback(void *opaque, int avail);
223 static void mc_callback(void *opaque, int avail);
224
225 static void warm_reset(AC97LinkState *s)
226 {
227 (void)s;
228 }
229
230 static void cold_reset(AC97LinkState *s)
231 {
232 (void)s;
233 }
234
235 static void fetch_bd(AC97LinkState *s, AC97BusMasterRegs *r)
236 {
237 uint8_t b[8];
238
239 pci_dma_read(&s->dev, r->bdbar + r->civ * 8, b, 8);
240 r->bd_valid = 1;
241 r->bd.addr = le32_to_cpu(*(uint32_t *) &b[0]) & ~3;
242 r->bd.ctl_len = le32_to_cpu(*(uint32_t *) &b[4]);
243 r->picb = r->bd.ctl_len & 0xffff;
244 dolog("bd %2d addr=0x%x ctl=0x%06x len=0x%x(%d bytes)\n",
245 r->civ, r->bd.addr, r->bd.ctl_len >> 16,
246 r->bd.ctl_len & 0xffff, (r->bd.ctl_len & 0xffff) << 1);
247 }
248
249 static void update_sr(AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)
250 {
251 int event = 0;
252 int level = 0;
253 uint32_t new_mask = new_sr & SR_INT_MASK;
254 uint32_t old_mask = r->sr & SR_INT_MASK;
255 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT};
256
257 if (new_mask ^ old_mask) {
258 /** @todo is IRQ deasserted when only one of status bits is cleared? */
259 if (!new_mask) {
260 event = 1;
261 level = 0;
262 } else {
263 if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) {
264 event = 1;
265 level = 1;
266 }
267 if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) {
268 event = 1;
269 level = 1;
270 }
271 }
272 }
273
274 r->sr = new_sr;
275
276 dolog("IOC%d LVB%d sr=0x%x event=%d level=%d\n",
277 r->sr & SR_BCIS, r->sr & SR_LVBCI, r->sr, event, level);
278
279 if (!event) {
280 return;
281 }
282
283 if (level) {
284 s->glob_sta |= masks[r - s->bm_regs];
285 dolog("set irq level=1\n");
286 pci_irq_assert(&s->dev);
287 } else {
288 s->glob_sta &= ~masks[r - s->bm_regs];
289 dolog("set irq level=0\n");
290 pci_irq_deassert(&s->dev);
291 }
292 }
293
294 static void voice_set_active(AC97LinkState *s, int bm_index, int on)
295 {
296 switch (bm_index) {
297 case PI_INDEX:
298 AUD_set_active_in(s->voice_pi, on);
299 break;
300
301 case PO_INDEX:
302 AUD_set_active_out(s->voice_po, on);
303 break;
304
305 case MC_INDEX:
306 AUD_set_active_in(s->voice_mc, on);
307 break;
308
309 default:
310 AUD_log("ac97", "invalid bm_index(%d) in voice_set_active", bm_index);
311 break;
312 }
313 }
314
315 static void reset_bm_regs(AC97LinkState *s, AC97BusMasterRegs *r)
316 {
317 dolog("reset_bm_regs\n");
318 r->bdbar = 0;
319 r->civ = 0;
320 r->lvi = 0;
321 /** todo do we need to do that? */
322 update_sr(s, r, SR_DCH);
323 r->picb = 0;
324 r->piv = 0;
325 r->cr = r->cr & CR_DONT_CLEAR_MASK;
326 r->bd_valid = 0;
327
328 voice_set_active(s, r - s->bm_regs, 0);
329 memset(s->silence, 0, sizeof(s->silence));
330 }
331
332 static void mixer_store(AC97LinkState *s, uint32_t i, uint16_t v)
333 {
334 if (i + 2 > sizeof(s->mixer_data)) {
335 dolog("mixer_store: index %d out of bounds %zd\n",
336 i, sizeof(s->mixer_data));
337 return;
338 }
339
340 s->mixer_data[i + 0] = v & 0xff;
341 s->mixer_data[i + 1] = v >> 8;
342 }
343
344 static uint16_t mixer_load(AC97LinkState *s, uint32_t i)
345 {
346 uint16_t val = 0xffff;
347
348 if (i + 2 > sizeof(s->mixer_data)) {
349 dolog("mixer_load: index %d out of bounds %zd\n",
350 i, sizeof(s->mixer_data));
351 } else {
352 val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8);
353 }
354
355 return val;
356 }
357
358 static void open_voice(AC97LinkState *s, int index, int freq)
359 {
360 struct audsettings as;
361
362 as.freq = freq;
363 as.nchannels = 2;
364 as.fmt = AUDIO_FORMAT_S16;
365 as.endianness = 0;
366
367 if (freq > 0) {
368 s->invalid_freq[index] = 0;
369 switch (index) {
370 case PI_INDEX:
371 s->voice_pi = AUD_open_in(
372 &s->card,
373 s->voice_pi,
374 "ac97.pi",
375 s,
376 pi_callback,
377 &as
378 );
379 break;
380
381 case PO_INDEX:
382 s->voice_po = AUD_open_out(
383 &s->card,
384 s->voice_po,
385 "ac97.po",
386 s,
387 po_callback,
388 &as
389 );
390 break;
391
392 case MC_INDEX:
393 s->voice_mc = AUD_open_in(
394 &s->card,
395 s->voice_mc,
396 "ac97.mc",
397 s,
398 mc_callback,
399 &as
400 );
401 break;
402 }
403 } else {
404 s->invalid_freq[index] = freq;
405 switch (index) {
406 case PI_INDEX:
407 AUD_close_in(&s->card, s->voice_pi);
408 s->voice_pi = NULL;
409 break;
410
411 case PO_INDEX:
412 AUD_close_out(&s->card, s->voice_po);
413 s->voice_po = NULL;
414 break;
415
416 case MC_INDEX:
417 AUD_close_in(&s->card, s->voice_mc);
418 s->voice_mc = NULL;
419 break;
420 }
421 }
422 }
423
424 static void reset_voices(AC97LinkState *s, uint8_t active[LAST_INDEX])
425 {
426 uint16_t freq;
427
428 freq = mixer_load(s, AC97_PCM_LR_ADC_Rate);
429 open_voice(s, PI_INDEX, freq);
430 AUD_set_active_in(s->voice_pi, active[PI_INDEX]);
431
432 freq = mixer_load(s, AC97_PCM_Front_DAC_Rate);
433 open_voice(s, PO_INDEX, freq);
434 AUD_set_active_out(s->voice_po, active[PO_INDEX]);
435
436 freq = mixer_load(s, AC97_MIC_ADC_Rate);
437 open_voice(s, MC_INDEX, freq);
438 AUD_set_active_in(s->voice_mc, active[MC_INDEX]);
439 }
440
441 static void get_volume(uint16_t vol, uint16_t mask, int inverse,
442 int *mute, uint8_t *lvol, uint8_t *rvol)
443 {
444 *mute = (vol >> MUTE_SHIFT) & 1;
445 *rvol = (255 * (vol & mask)) / mask;
446 *lvol = (255 * ((vol >> 8) & mask)) / mask;
447
448 if (inverse) {
449 *rvol = 255 - *rvol;
450 *lvol = 255 - *lvol;
451 }
452 }
453
454 static void update_combined_volume_out(AC97LinkState *s)
455 {
456 uint8_t lvol, rvol, plvol, prvol;
457 int mute, pmute;
458
459 get_volume(mixer_load(s, AC97_Master_Volume_Mute), 0x3f, 1,
460 &mute, &lvol, &rvol);
461 get_volume(mixer_load(s, AC97_PCM_Out_Volume_Mute), 0x1f, 1,
462 &pmute, &plvol, &prvol);
463
464 mute = mute | pmute;
465 lvol = (lvol * plvol) / 255;
466 rvol = (rvol * prvol) / 255;
467
468 AUD_set_volume_out(s->voice_po, mute, lvol, rvol);
469 }
470
471 static void update_volume_in(AC97LinkState *s)
472 {
473 uint8_t lvol, rvol;
474 int mute;
475
476 get_volume(mixer_load(s, AC97_Record_Gain_Mute), 0x0f, 0,
477 &mute, &lvol, &rvol);
478
479 AUD_set_volume_in(s->voice_pi, mute, lvol, rvol);
480 }
481
482 static void set_volume(AC97LinkState *s, int index, uint32_t val)
483 {
484 switch (index) {
485 case AC97_Master_Volume_Mute:
486 val &= 0xbf3f;
487 mixer_store(s, index, val);
488 update_combined_volume_out(s);
489 break;
490 case AC97_PCM_Out_Volume_Mute:
491 val &= 0x9f1f;
492 mixer_store(s, index, val);
493 update_combined_volume_out(s);
494 break;
495 case AC97_Record_Gain_Mute:
496 val &= 0x8f0f;
497 mixer_store(s, index, val);
498 update_volume_in(s);
499 break;
500 }
501 }
502
503 static void record_select(AC97LinkState *s, uint32_t val)
504 {
505 uint8_t rs = val & REC_MASK;
506 uint8_t ls = (val >> 8) & REC_MASK;
507 mixer_store(s, AC97_Record_Select, rs | (ls << 8));
508 }
509
510 static void mixer_reset(AC97LinkState *s)
511 {
512 uint8_t active[LAST_INDEX];
513
514 dolog("mixer_reset\n");
515 memset(s->mixer_data, 0, sizeof(s->mixer_data));
516 memset(active, 0, sizeof(active));
517 mixer_store(s, AC97_Reset, 0x0000); /* 6940 */
518 mixer_store(s, AC97_Headphone_Volume_Mute, 0x0000);
519 mixer_store(s, AC97_Master_Volume_Mono_Mute, 0x0000);
520 mixer_store(s, AC97_Master_Tone_RL, 0x0000);
521 mixer_store(s, AC97_PC_BEEP_Volume_Mute, 0x0000);
522 mixer_store(s, AC97_Phone_Volume_Mute, 0x0000);
523 mixer_store(s, AC97_Mic_Volume_Mute, 0x0000);
524 mixer_store(s, AC97_Line_In_Volume_Mute, 0x0000);
525 mixer_store(s, AC97_CD_Volume_Mute, 0x0000);
526 mixer_store(s, AC97_Video_Volume_Mute, 0x0000);
527 mixer_store(s, AC97_Aux_Volume_Mute, 0x0000);
528 mixer_store(s, AC97_Record_Gain_Mic_Mute, 0x0000);
529 mixer_store(s, AC97_General_Purpose, 0x0000);
530 mixer_store(s, AC97_3D_Control, 0x0000);
531 mixer_store(s, AC97_Powerdown_Ctrl_Stat, 0x000f);
532
533 /*
534 * Sigmatel 9700 (STAC9700)
535 */
536 mixer_store(s, AC97_Vendor_ID1, 0x8384);
537 mixer_store(s, AC97_Vendor_ID2, 0x7600); /* 7608 */
538
539 mixer_store(s, AC97_Extended_Audio_ID, 0x0809);
540 mixer_store(s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
541 mixer_store(s, AC97_PCM_Front_DAC_Rate, 0xbb80);
542 mixer_store(s, AC97_PCM_Surround_DAC_Rate, 0xbb80);
543 mixer_store(s, AC97_PCM_LFE_DAC_Rate, 0xbb80);
544 mixer_store(s, AC97_PCM_LR_ADC_Rate, 0xbb80);
545 mixer_store(s, AC97_MIC_ADC_Rate, 0xbb80);
546
547 record_select(s, 0);
548 set_volume(s, AC97_Master_Volume_Mute, 0x8000);
549 set_volume(s, AC97_PCM_Out_Volume_Mute, 0x8808);
550 set_volume(s, AC97_Record_Gain_Mute, 0x8808);
551
552 reset_voices(s, active);
553 }
554
555 /**
556 * Native audio mixer
557 * I/O Reads
558 */
559 static uint32_t nam_readb(void *opaque, uint32_t addr)
560 {
561 AC97LinkState *s = opaque;
562 dolog("U nam readb 0x%x\n", addr);
563 s->cas = 0;
564 return ~0U;
565 }
566
567 static uint32_t nam_readw(void *opaque, uint32_t addr)
568 {
569 AC97LinkState *s = opaque;
570 uint32_t index = addr;
571 s->cas = 0;
572 return mixer_load(s, index);
573 }
574
575 static uint32_t nam_readl(void *opaque, uint32_t addr)
576 {
577 AC97LinkState *s = opaque;
578 dolog("U nam readl 0x%x\n", addr);
579 s->cas = 0;
580 return ~0U;
581 }
582
583 /**
584 * Native audio mixer
585 * I/O Writes
586 */
587 static void nam_writeb(void *opaque, uint32_t addr, uint32_t val)
588 {
589 AC97LinkState *s = opaque;
590 dolog("U nam writeb 0x%x <- 0x%x\n", addr, val);
591 s->cas = 0;
592 }
593
594 static void nam_writew(void *opaque, uint32_t addr, uint32_t val)
595 {
596 AC97LinkState *s = opaque;
597 uint32_t index = addr;
598 s->cas = 0;
599 switch (index) {
600 case AC97_Reset:
601 mixer_reset(s);
602 break;
603 case AC97_Powerdown_Ctrl_Stat:
604 val &= ~0x800f;
605 val |= mixer_load(s, index) & 0xf;
606 mixer_store(s, index, val);
607 break;
608 case AC97_PCM_Out_Volume_Mute:
609 case AC97_Master_Volume_Mute:
610 case AC97_Record_Gain_Mute:
611 set_volume(s, index, val);
612 break;
613 case AC97_Record_Select:
614 record_select(s, val);
615 break;
616 case AC97_Vendor_ID1:
617 case AC97_Vendor_ID2:
618 dolog("Attempt to write vendor ID to 0x%x\n", val);
619 break;
620 case AC97_Extended_Audio_ID:
621 dolog("Attempt to write extended audio ID to 0x%x\n", val);
622 break;
623 case AC97_Extended_Audio_Ctrl_Stat:
624 if (!(val & EACS_VRA)) {
625 mixer_store(s, AC97_PCM_Front_DAC_Rate, 0xbb80);
626 mixer_store(s, AC97_PCM_LR_ADC_Rate, 0xbb80);
627 open_voice(s, PI_INDEX, 48000);
628 open_voice(s, PO_INDEX, 48000);
629 }
630 if (!(val & EACS_VRM)) {
631 mixer_store(s, AC97_MIC_ADC_Rate, 0xbb80);
632 open_voice(s, MC_INDEX, 48000);
633 }
634 dolog("Setting extended audio control to 0x%x\n", val);
635 mixer_store(s, AC97_Extended_Audio_Ctrl_Stat, val);
636 break;
637 case AC97_PCM_Front_DAC_Rate:
638 if (mixer_load(s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
639 mixer_store(s, index, val);
640 dolog("Set front DAC rate to %d\n", val);
641 open_voice(s, PO_INDEX, val);
642 } else {
643 dolog("Attempt to set front DAC rate to %d, but VRA is not set\n",
644 val);
645 }
646 break;
647 case AC97_MIC_ADC_Rate:
648 if (mixer_load(s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) {
649 mixer_store(s, index, val);
650 dolog("Set MIC ADC rate to %d\n", val);
651 open_voice(s, MC_INDEX, val);
652 } else {
653 dolog("Attempt to set MIC ADC rate to %d, but VRM is not set\n",
654 val);
655 }
656 break;
657 case AC97_PCM_LR_ADC_Rate:
658 if (mixer_load(s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
659 mixer_store(s, index, val);
660 dolog("Set front LR ADC rate to %d\n", val);
661 open_voice(s, PI_INDEX, val);
662 } else {
663 dolog("Attempt to set LR ADC rate to %d, but VRA is not set\n",
664 val);
665 }
666 break;
667 case AC97_Headphone_Volume_Mute:
668 case AC97_Master_Volume_Mono_Mute:
669 case AC97_Master_Tone_RL:
670 case AC97_PC_BEEP_Volume_Mute:
671 case AC97_Phone_Volume_Mute:
672 case AC97_Mic_Volume_Mute:
673 case AC97_Line_In_Volume_Mute:
674 case AC97_CD_Volume_Mute:
675 case AC97_Video_Volume_Mute:
676 case AC97_Aux_Volume_Mute:
677 case AC97_Record_Gain_Mic_Mute:
678 case AC97_General_Purpose:
679 case AC97_3D_Control:
680 case AC97_Sigmatel_Analog:
681 case AC97_Sigmatel_Dac2Invert:
682 /* None of the features in these regs are emulated, so they are RO */
683 break;
684 default:
685 dolog("U nam writew 0x%x <- 0x%x\n", addr, val);
686 mixer_store(s, index, val);
687 break;
688 }
689 }
690
691 static void nam_writel(void *opaque, uint32_t addr, uint32_t val)
692 {
693 AC97LinkState *s = opaque;
694 dolog("U nam writel 0x%x <- 0x%x\n", addr, val);
695 s->cas = 0;
696 }
697
698 /**
699 * Native audio bus master
700 * I/O Reads
701 */
702 static uint32_t nabm_readb(void *opaque, uint32_t addr)
703 {
704 AC97LinkState *s = opaque;
705 AC97BusMasterRegs *r = NULL;
706 uint32_t index = addr;
707 uint32_t val = ~0U;
708
709 switch (index) {
710 case CAS:
711 dolog("CAS %d\n", s->cas);
712 val = s->cas;
713 s->cas = 1;
714 break;
715 case PI_CIV:
716 case PO_CIV:
717 case MC_CIV:
718 r = &s->bm_regs[GET_BM(index)];
719 val = r->civ;
720 dolog("CIV[%d] -> 0x%x\n", GET_BM(index), val);
721 break;
722 case PI_LVI:
723 case PO_LVI:
724 case MC_LVI:
725 r = &s->bm_regs[GET_BM(index)];
726 val = r->lvi;
727 dolog("LVI[%d] -> 0x%x\n", GET_BM(index), val);
728 break;
729 case PI_PIV:
730 case PO_PIV:
731 case MC_PIV:
732 r = &s->bm_regs[GET_BM(index)];
733 val = r->piv;
734 dolog("PIV[%d] -> 0x%x\n", GET_BM(index), val);
735 break;
736 case PI_CR:
737 case PO_CR:
738 case MC_CR:
739 r = &s->bm_regs[GET_BM(index)];
740 val = r->cr;
741 dolog("CR[%d] -> 0x%x\n", GET_BM(index), val);
742 break;
743 case PI_SR:
744 case PO_SR:
745 case MC_SR:
746 r = &s->bm_regs[GET_BM(index)];
747 val = r->sr & 0xff;
748 dolog("SRb[%d] -> 0x%x\n", GET_BM(index), val);
749 break;
750 default:
751 dolog("U nabm readb 0x%x -> 0x%x\n", addr, val);
752 break;
753 }
754 return val;
755 }
756
757 static uint32_t nabm_readw(void *opaque, uint32_t addr)
758 {
759 AC97LinkState *s = opaque;
760 AC97BusMasterRegs *r = NULL;
761 uint32_t index = addr;
762 uint32_t val = ~0U;
763
764 switch (index) {
765 case PI_SR:
766 case PO_SR:
767 case MC_SR:
768 r = &s->bm_regs[GET_BM(index)];
769 val = r->sr;
770 dolog("SR[%d] -> 0x%x\n", GET_BM(index), val);
771 break;
772 case PI_PICB:
773 case PO_PICB:
774 case MC_PICB:
775 r = &s->bm_regs[GET_BM(index)];
776 val = r->picb;
777 dolog("PICB[%d] -> 0x%x\n", GET_BM(index), val);
778 break;
779 default:
780 dolog("U nabm readw 0x%x -> 0x%x\n", addr, val);
781 break;
782 }
783 return val;
784 }
785
786 static uint32_t nabm_readl(void *opaque, uint32_t addr)
787 {
788 AC97LinkState *s = opaque;
789 AC97BusMasterRegs *r = NULL;
790 uint32_t index = addr;
791 uint32_t val = ~0U;
792
793 switch (index) {
794 case PI_BDBAR:
795 case PO_BDBAR:
796 case MC_BDBAR:
797 r = &s->bm_regs[GET_BM(index)];
798 val = r->bdbar;
799 dolog("BMADDR[%d] -> 0x%x\n", GET_BM(index), val);
800 break;
801 case PI_CIV:
802 case PO_CIV:
803 case MC_CIV:
804 r = &s->bm_regs[GET_BM(index)];
805 val = r->civ | (r->lvi << 8) | (r->sr << 16);
806 dolog("CIV LVI SR[%d] -> 0x%x, 0x%x, 0x%x\n", GET_BM(index),
807 r->civ, r->lvi, r->sr);
808 break;
809 case PI_PICB:
810 case PO_PICB:
811 case MC_PICB:
812 r = &s->bm_regs[GET_BM(index)];
813 val = r->picb | (r->piv << 16) | (r->cr << 24);
814 dolog("PICB PIV CR[%d] -> 0x%x 0x%x 0x%x 0x%x\n", GET_BM(index),
815 val, r->picb, r->piv, r->cr);
816 break;
817 case GLOB_CNT:
818 val = s->glob_cnt;
819 dolog("glob_cnt -> 0x%x\n", val);
820 break;
821 case GLOB_STA:
822 val = s->glob_sta | GS_S0CR;
823 dolog("glob_sta -> 0x%x\n", val);
824 break;
825 default:
826 dolog("U nabm readl 0x%x -> 0x%x\n", addr, val);
827 break;
828 }
829 return val;
830 }
831
832 /**
833 * Native audio bus master
834 * I/O Writes
835 */
836 static void nabm_writeb(void *opaque, uint32_t addr, uint32_t val)
837 {
838 AC97LinkState *s = opaque;
839 AC97BusMasterRegs *r = NULL;
840 uint32_t index = addr;
841 switch (index) {
842 case PI_LVI:
843 case PO_LVI:
844 case MC_LVI:
845 r = &s->bm_regs[GET_BM(index)];
846 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) {
847 r->sr &= ~(SR_DCH | SR_CELV);
848 r->civ = r->piv;
849 r->piv = (r->piv + 1) % 32;
850 fetch_bd(s, r);
851 }
852 r->lvi = val % 32;
853 dolog("LVI[%d] <- 0x%x\n", GET_BM(index), val);
854 break;
855 case PI_CR:
856 case PO_CR:
857 case MC_CR:
858 r = &s->bm_regs[GET_BM(index)];
859 if (val & CR_RR) {
860 reset_bm_regs(s, r);
861 } else {
862 r->cr = val & CR_VALID_MASK;
863 if (!(r->cr & CR_RPBM)) {
864 voice_set_active(s, r - s->bm_regs, 0);
865 r->sr |= SR_DCH;
866 } else {
867 r->civ = r->piv;
868 r->piv = (r->piv + 1) % 32;
869 fetch_bd(s, r);
870 r->sr &= ~SR_DCH;
871 voice_set_active(s, r - s->bm_regs, 1);
872 }
873 }
874 dolog("CR[%d] <- 0x%x (cr 0x%x)\n", GET_BM(index), val, r->cr);
875 break;
876 case PI_SR:
877 case PO_SR:
878 case MC_SR:
879 r = &s->bm_regs[GET_BM(index)];
880 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
881 update_sr(s, r, r->sr & ~(val & SR_WCLEAR_MASK));
882 dolog("SR[%d] <- 0x%x (sr 0x%x)\n", GET_BM(index), val, r->sr);
883 break;
884 default:
885 dolog("U nabm writeb 0x%x <- 0x%x\n", addr, val);
886 break;
887 }
888 }
889
890 static void nabm_writew(void *opaque, uint32_t addr, uint32_t val)
891 {
892 AC97LinkState *s = opaque;
893 AC97BusMasterRegs *r = NULL;
894 uint32_t index = addr;
895 switch (index) {
896 case PI_SR:
897 case PO_SR:
898 case MC_SR:
899 r = &s->bm_regs[GET_BM(index)];
900 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
901 update_sr(s, r, r->sr & ~(val & SR_WCLEAR_MASK));
902 dolog("SR[%d] <- 0x%x (sr 0x%x)\n", GET_BM(index), val, r->sr);
903 break;
904 default:
905 dolog("U nabm writew 0x%x <- 0x%x\n", addr, val);
906 break;
907 }
908 }
909
910 static void nabm_writel(void *opaque, uint32_t addr, uint32_t val)
911 {
912 AC97LinkState *s = opaque;
913 AC97BusMasterRegs *r = NULL;
914 uint32_t index = addr;
915 switch (index) {
916 case PI_BDBAR:
917 case PO_BDBAR:
918 case MC_BDBAR:
919 r = &s->bm_regs[GET_BM(index)];
920 r->bdbar = val & ~3;
921 dolog("BDBAR[%d] <- 0x%x (bdbar 0x%x)\n", GET_BM(index), val, r->bdbar);
922 break;
923 case GLOB_CNT:
924 if (val & GC_WR) {
925 warm_reset(s);
926 }
927 if (val & GC_CR) {
928 cold_reset(s);
929 }
930 if (!(val & (GC_WR | GC_CR))) {
931 s->glob_cnt = val & GC_VALID_MASK;
932 }
933 dolog("glob_cnt <- 0x%x (glob_cnt 0x%x)\n", val, s->glob_cnt);
934 break;
935 case GLOB_STA:
936 s->glob_sta &= ~(val & GS_WCLEAR_MASK);
937 s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;
938 dolog("glob_sta <- 0x%x (glob_sta 0x%x)\n", val, s->glob_sta);
939 break;
940 default:
941 dolog("U nabm writel 0x%x <- 0x%x\n", addr, val);
942 break;
943 }
944 }
945
946 static int write_audio(AC97LinkState *s, AC97BusMasterRegs *r,
947 int max, int *stop)
948 {
949 uint8_t tmpbuf[4096];
950 uint32_t addr = r->bd.addr;
951 uint32_t temp = r->picb << 1;
952 uint32_t written = 0;
953 int to_copy = 0;
954 temp = MIN(temp, max);
955
956 if (!temp) {
957 *stop = 1;
958 return 0;
959 }
960
961 while (temp) {
962 int copied;
963 to_copy = MIN(temp, sizeof(tmpbuf));
964 pci_dma_read(&s->dev, addr, tmpbuf, to_copy);
965 copied = AUD_write(s->voice_po, tmpbuf, to_copy);
966 dolog("write_audio max=%x to_copy=%x copied=%x\n",
967 max, to_copy, copied);
968 if (!copied) {
969 *stop = 1;
970 break;
971 }
972 temp -= copied;
973 addr += copied;
974 written += copied;
975 }
976
977 if (!temp) {
978 if (to_copy < 4) {
979 dolog("whoops\n");
980 s->last_samp = 0;
981 } else {
982 s->last_samp = *(uint32_t *)&tmpbuf[to_copy - 4];
983 }
984 }
985
986 r->bd.addr = addr;
987 return written;
988 }
989
990 static void write_bup(AC97LinkState *s, int elapsed)
991 {
992 dolog("write_bup\n");
993 if (!(s->bup_flag & BUP_SET)) {
994 if (s->bup_flag & BUP_LAST) {
995 int i;
996 uint8_t *p = s->silence;
997 for (i = 0; i < sizeof(s->silence) / 4; i++, p += 4) {
998 *(uint32_t *) p = s->last_samp;
999 }
1000 } else {
1001 memset(s->silence, 0, sizeof(s->silence));
1002 }
1003 s->bup_flag |= BUP_SET;
1004 }
1005
1006 while (elapsed) {
1007 int temp = MIN(elapsed, sizeof(s->silence));
1008 while (temp) {
1009 int copied = AUD_write(s->voice_po, s->silence, temp);
1010 if (!copied) {
1011 return;
1012 }
1013 temp -= copied;
1014 elapsed -= copied;
1015 }
1016 }
1017 }
1018
1019 static int read_audio(AC97LinkState *s, AC97BusMasterRegs *r,
1020 int max, int *stop)
1021 {
1022 uint8_t tmpbuf[4096];
1023 uint32_t addr = r->bd.addr;
1024 uint32_t temp = r->picb << 1;
1025 uint32_t nread = 0;
1026 int to_copy = 0;
1027 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi;
1028
1029 temp = MIN(temp, max);
1030
1031 if (!temp) {
1032 *stop = 1;
1033 return 0;
1034 }
1035
1036 while (temp) {
1037 int acquired;
1038 to_copy = MIN(temp, sizeof(tmpbuf));
1039 acquired = AUD_read(voice, tmpbuf, to_copy);
1040 if (!acquired) {
1041 *stop = 1;
1042 break;
1043 }
1044 pci_dma_write(&s->dev, addr, tmpbuf, acquired);
1045 temp -= acquired;
1046 addr += acquired;
1047 nread += acquired;
1048 }
1049
1050 r->bd.addr = addr;
1051 return nread;
1052 }
1053
1054 static void transfer_audio(AC97LinkState *s, int index, int elapsed)
1055 {
1056 AC97BusMasterRegs *r = &s->bm_regs[index];
1057 int stop = 0;
1058
1059 if (s->invalid_freq[index]) {
1060 AUD_log("ac97", "attempt to use voice %d with invalid frequency %d\n",
1061 index, s->invalid_freq[index]);
1062 return;
1063 }
1064
1065 if (r->sr & SR_DCH) {
1066 if (r->cr & CR_RPBM) {
1067 switch (index) {
1068 case PO_INDEX:
1069 write_bup(s, elapsed);
1070 break;
1071 }
1072 }
1073 return;
1074 }
1075
1076 while ((elapsed >> 1) && !stop) {
1077 int temp;
1078
1079 if (!r->bd_valid) {
1080 dolog("invalid bd\n");
1081 fetch_bd(s, r);
1082 }
1083
1084 if (!r->picb) {
1085 dolog("fresh bd %d is empty 0x%x 0x%x\n",
1086 r->civ, r->bd.addr, r->bd.ctl_len);
1087 if (r->civ == r->lvi) {
1088 r->sr |= SR_DCH; /* CELV? */
1089 s->bup_flag = 0;
1090 break;
1091 }
1092 r->sr &= ~SR_CELV;
1093 r->civ = r->piv;
1094 r->piv = (r->piv + 1) % 32;
1095 fetch_bd(s, r);
1096 return;
1097 }
1098
1099 switch (index) {
1100 case PO_INDEX:
1101 temp = write_audio(s, r, elapsed, &stop);
1102 elapsed -= temp;
1103 r->picb -= (temp >> 1);
1104 break;
1105
1106 case PI_INDEX:
1107 case MC_INDEX:
1108 temp = read_audio(s, r, elapsed, &stop);
1109 elapsed -= temp;
1110 r->picb -= (temp >> 1);
1111 break;
1112 }
1113
1114 if (!r->picb) {
1115 uint32_t new_sr = r->sr & ~SR_CELV;
1116
1117 if (r->bd.ctl_len & BD_IOC) {
1118 new_sr |= SR_BCIS;
1119 }
1120
1121 if (r->civ == r->lvi) {
1122 dolog("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi);
1123
1124 new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
1125 stop = 1;
1126 s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
1127 } else {
1128 r->civ = r->piv;
1129 r->piv = (r->piv + 1) % 32;
1130 fetch_bd(s, r);
1131 }
1132
1133 update_sr(s, r, new_sr);
1134 }
1135 }
1136 }
1137
1138 static void pi_callback(void *opaque, int avail)
1139 {
1140 transfer_audio(opaque, PI_INDEX, avail);
1141 }
1142
1143 static void mc_callback(void *opaque, int avail)
1144 {
1145 transfer_audio(opaque, MC_INDEX, avail);
1146 }
1147
1148 static void po_callback(void *opaque, int free)
1149 {
1150 transfer_audio(opaque, PO_INDEX, free);
1151 }
1152
1153 static const VMStateDescription vmstate_ac97_bm_regs = {
1154 .name = "ac97_bm_regs",
1155 .version_id = 1,
1156 .minimum_version_id = 1,
1157 .fields = (VMStateField[]) {
1158 VMSTATE_UINT32(bdbar, AC97BusMasterRegs),
1159 VMSTATE_UINT8(civ, AC97BusMasterRegs),
1160 VMSTATE_UINT8(lvi, AC97BusMasterRegs),
1161 VMSTATE_UINT16(sr, AC97BusMasterRegs),
1162 VMSTATE_UINT16(picb, AC97BusMasterRegs),
1163 VMSTATE_UINT8(piv, AC97BusMasterRegs),
1164 VMSTATE_UINT8(cr, AC97BusMasterRegs),
1165 VMSTATE_UINT32(bd_valid, AC97BusMasterRegs),
1166 VMSTATE_UINT32(bd.addr, AC97BusMasterRegs),
1167 VMSTATE_UINT32(bd.ctl_len, AC97BusMasterRegs),
1168 VMSTATE_END_OF_LIST()
1169 }
1170 };
1171
1172 static int ac97_post_load(void *opaque, int version_id)
1173 {
1174 uint8_t active[LAST_INDEX];
1175 AC97LinkState *s = opaque;
1176
1177 record_select(s, mixer_load(s, AC97_Record_Select));
1178 set_volume(s, AC97_Master_Volume_Mute,
1179 mixer_load(s, AC97_Master_Volume_Mute));
1180 set_volume(s, AC97_PCM_Out_Volume_Mute,
1181 mixer_load(s, AC97_PCM_Out_Volume_Mute));
1182 set_volume(s, AC97_Record_Gain_Mute,
1183 mixer_load(s, AC97_Record_Gain_Mute));
1184
1185 active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM);
1186 active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM);
1187 active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM);
1188 reset_voices(s, active);
1189
1190 s->bup_flag = 0;
1191 s->last_samp = 0;
1192 return 0;
1193 }
1194
1195 static bool is_version_2(void *opaque, int version_id)
1196 {
1197 return version_id == 2;
1198 }
1199
1200 static const VMStateDescription vmstate_ac97 = {
1201 .name = "ac97",
1202 .version_id = 3,
1203 .minimum_version_id = 2,
1204 .post_load = ac97_post_load,
1205 .fields = (VMStateField[]) {
1206 VMSTATE_PCI_DEVICE(dev, AC97LinkState),
1207 VMSTATE_UINT32(glob_cnt, AC97LinkState),
1208 VMSTATE_UINT32(glob_sta, AC97LinkState),
1209 VMSTATE_UINT32(cas, AC97LinkState),
1210 VMSTATE_STRUCT_ARRAY(bm_regs, AC97LinkState, 3, 1,
1211 vmstate_ac97_bm_regs, AC97BusMasterRegs),
1212 VMSTATE_BUFFER(mixer_data, AC97LinkState),
1213 VMSTATE_UNUSED_TEST(is_version_2, 3),
1214 VMSTATE_END_OF_LIST()
1215 }
1216 };
1217
1218 static uint64_t nam_read(void *opaque, hwaddr addr, unsigned size)
1219 {
1220 if ((addr / size) > 256) {
1221 return -1;
1222 }
1223
1224 switch (size) {
1225 case 1:
1226 return nam_readb(opaque, addr);
1227 case 2:
1228 return nam_readw(opaque, addr);
1229 case 4:
1230 return nam_readl(opaque, addr);
1231 default:
1232 return -1;
1233 }
1234 }
1235
1236 static void nam_write(void *opaque, hwaddr addr, uint64_t val,
1237 unsigned size)
1238 {
1239 if ((addr / size) > 256) {
1240 return;
1241 }
1242
1243 switch (size) {
1244 case 1:
1245 nam_writeb(opaque, addr, val);
1246 break;
1247 case 2:
1248 nam_writew(opaque, addr, val);
1249 break;
1250 case 4:
1251 nam_writel(opaque, addr, val);
1252 break;
1253 }
1254 }
1255
1256 static const MemoryRegionOps ac97_io_nam_ops = {
1257 .read = nam_read,
1258 .write = nam_write,
1259 .impl = {
1260 .min_access_size = 1,
1261 .max_access_size = 4,
1262 },
1263 .endianness = DEVICE_LITTLE_ENDIAN,
1264 };
1265
1266 static uint64_t nabm_read(void *opaque, hwaddr addr, unsigned size)
1267 {
1268 if ((addr / size) > 64) {
1269 return -1;
1270 }
1271
1272 switch (size) {
1273 case 1:
1274 return nabm_readb(opaque, addr);
1275 case 2:
1276 return nabm_readw(opaque, addr);
1277 case 4:
1278 return nabm_readl(opaque, addr);
1279 default:
1280 return -1;
1281 }
1282 }
1283
1284 static void nabm_write(void *opaque, hwaddr addr, uint64_t val,
1285 unsigned size)
1286 {
1287 if ((addr / size) > 64) {
1288 return;
1289 }
1290
1291 switch (size) {
1292 case 1:
1293 nabm_writeb(opaque, addr, val);
1294 break;
1295 case 2:
1296 nabm_writew(opaque, addr, val);
1297 break;
1298 case 4:
1299 nabm_writel(opaque, addr, val);
1300 break;
1301 }
1302 }
1303
1304
1305 static const MemoryRegionOps ac97_io_nabm_ops = {
1306 .read = nabm_read,
1307 .write = nabm_write,
1308 .impl = {
1309 .min_access_size = 1,
1310 .max_access_size = 4,
1311 },
1312 .endianness = DEVICE_LITTLE_ENDIAN,
1313 };
1314
1315 static void ac97_on_reset(DeviceState *dev)
1316 {
1317 AC97LinkState *s = container_of(dev, AC97LinkState, dev.qdev);
1318
1319 reset_bm_regs(s, &s->bm_regs[0]);
1320 reset_bm_regs(s, &s->bm_regs[1]);
1321 reset_bm_regs(s, &s->bm_regs[2]);
1322
1323 /*
1324 * Reset the mixer too. The Windows XP driver seems to rely on
1325 * this. At least it wants to read the vendor id before it resets
1326 * the codec manually.
1327 */
1328 mixer_reset(s);
1329 }
1330
1331 static void ac97_realize(PCIDevice *dev, Error **errp)
1332 {
1333 AC97LinkState *s = AC97(dev);
1334 uint8_t *c = s->dev.config;
1335
1336 /* TODO: no need to override */
1337 c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */
1338 c[PCI_COMMAND + 1] = 0x00;
1339
1340 /* TODO: */
1341 c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
1342 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
1343
1344 c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
1345
1346 /* TODO set when bar is registered. no need to override. */
1347 /* nabmar native audio mixer base address rw */
1348 c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
1349 c[PCI_BASE_ADDRESS_0 + 1] = 0x00;
1350 c[PCI_BASE_ADDRESS_0 + 2] = 0x00;
1351 c[PCI_BASE_ADDRESS_0 + 3] = 0x00;
1352
1353 /* TODO set when bar is registered. no need to override. */
1354 /* nabmbar native audio bus mastering base address rw */
1355 c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO;
1356 c[PCI_BASE_ADDRESS_0 + 5] = 0x00;
1357 c[PCI_BASE_ADDRESS_0 + 6] = 0x00;
1358 c[PCI_BASE_ADDRESS_0 + 7] = 0x00;
1359
1360 c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */
1361 c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
1362
1363 memory_region_init_io(&s->io_nam, OBJECT(s), &ac97_io_nam_ops, s,
1364 "ac97-nam", 1024);
1365 memory_region_init_io(&s->io_nabm, OBJECT(s), &ac97_io_nabm_ops, s,
1366 "ac97-nabm", 256);
1367 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
1368 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
1369 AUD_register_card("ac97", &s->card);
1370 ac97_on_reset(DEVICE(s));
1371 }
1372
1373 static void ac97_exit(PCIDevice *dev)
1374 {
1375 AC97LinkState *s = AC97(dev);
1376
1377 AUD_close_in(&s->card, s->voice_pi);
1378 AUD_close_out(&s->card, s->voice_po);
1379 AUD_close_in(&s->card, s->voice_mc);
1380 AUD_remove_card(&s->card);
1381 }
1382
1383 static Property ac97_properties[] = {
1384 DEFINE_AUDIO_PROPERTIES(AC97LinkState, card),
1385 DEFINE_PROP_END_OF_LIST(),
1386 };
1387
1388 static void ac97_class_init(ObjectClass *klass, void *data)
1389 {
1390 DeviceClass *dc = DEVICE_CLASS(klass);
1391 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1392
1393 k->realize = ac97_realize;
1394 k->exit = ac97_exit;
1395 k->vendor_id = PCI_VENDOR_ID_INTEL;
1396 k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5;
1397 k->revision = 0x01;
1398 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
1399 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1400 dc->desc = "Intel 82801AA AC97 Audio";
1401 dc->vmsd = &vmstate_ac97;
1402 device_class_set_props(dc, ac97_properties);
1403 dc->reset = ac97_on_reset;
1404 }
1405
1406 static const TypeInfo ac97_info = {
1407 .name = TYPE_AC97,
1408 .parent = TYPE_PCI_DEVICE,
1409 .instance_size = sizeof(AC97LinkState),
1410 .class_init = ac97_class_init,
1411 .interfaces = (InterfaceInfo[]) {
1412 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1413 { },
1414 },
1415 };
1416
1417 static void ac97_register_types(void)
1418 {
1419 type_register_static(&ac97_info);
1420 deprecated_register_soundhw("ac97", "Intel 82801AA AC97 Audio",
1421 0, TYPE_AC97);
1422 }
1423
1424 type_init(ac97_register_types)
AR7 emulation for QEMU