4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
25 #include "exec/exec-all.h"
26 #include "qapi/error.h"
27 #include "qemu/error-report.h"
28 #include "hw/qdev-properties.h"
29 #include "migration/vmstate.h"
30 #include "fpu/softfloat-helpers.h"
32 /* RISC-V CPU definitions */
34 static const char riscv_exts
[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
36 const char * const riscv_int_regnames
[] = {
37 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
38 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
39 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
40 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
41 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
44 const char * const riscv_fpr_regnames
[] = {
45 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
46 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
47 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
48 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
49 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
50 "f30/ft10", "f31/ft11"
53 const char * const riscv_excp_names
[] = {
56 "illegal_instruction",
74 "guest_exec_page_fault",
75 "guest_load_page_fault",
77 "guest_store_page_fault",
80 const char * const riscv_intr_names
[] = {
99 static void set_misa(CPURISCVState
*env
, target_ulong misa
)
101 env
->misa_mask
= env
->misa
= misa
;
104 static void set_priv_version(CPURISCVState
*env
, int priv_ver
)
106 env
->priv_ver
= priv_ver
;
109 static void set_feature(CPURISCVState
*env
, int feature
)
111 env
->features
|= (1ULL << feature
);
114 static void set_resetvec(CPURISCVState
*env
, int resetvec
)
116 #ifndef CONFIG_USER_ONLY
117 env
->resetvec
= resetvec
;
121 static void riscv_any_cpu_init(Object
*obj
)
123 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
124 set_misa(env
, RVXLEN
| RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVU
);
125 set_priv_version(env
, PRIV_VERSION_1_11_0
);
126 set_resetvec(env
, DEFAULT_RSTVEC
);
129 #if defined(TARGET_RISCV32)
131 static void riscv_base32_cpu_init(Object
*obj
)
133 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
134 /* We set this in the realise function */
138 static void rv32gcsu_priv1_09_1_cpu_init(Object
*obj
)
140 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
141 set_misa(env
, RV32
| RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
142 set_priv_version(env
, PRIV_VERSION_1_09_1
);
143 set_resetvec(env
, DEFAULT_RSTVEC
);
144 set_feature(env
, RISCV_FEATURE_MMU
);
145 set_feature(env
, RISCV_FEATURE_PMP
);
148 static void rv32gcsu_priv1_10_0_cpu_init(Object
*obj
)
150 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
151 set_misa(env
, RV32
| RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
152 set_priv_version(env
, PRIV_VERSION_1_10_0
);
153 set_resetvec(env
, DEFAULT_RSTVEC
);
154 set_feature(env
, RISCV_FEATURE_MMU
);
155 set_feature(env
, RISCV_FEATURE_PMP
);
158 static void rv32imacu_nommu_cpu_init(Object
*obj
)
160 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
161 set_misa(env
, RV32
| RVI
| RVM
| RVA
| RVC
| RVU
);
162 set_priv_version(env
, PRIV_VERSION_1_10_0
);
163 set_resetvec(env
, DEFAULT_RSTVEC
);
164 set_feature(env
, RISCV_FEATURE_PMP
);
167 static void rv32imafcu_nommu_cpu_init(Object
*obj
)
169 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
170 set_misa(env
, RV32
| RVI
| RVM
| RVA
| RVF
| RVC
| RVU
);
171 set_priv_version(env
, PRIV_VERSION_1_10_0
);
172 set_resetvec(env
, DEFAULT_RSTVEC
);
173 set_feature(env
, RISCV_FEATURE_PMP
);
176 #elif defined(TARGET_RISCV64)
178 static void riscv_base64_cpu_init(Object
*obj
)
180 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
181 /* We set this in the realise function */
185 static void rv64gcsu_priv1_09_1_cpu_init(Object
*obj
)
187 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
188 set_misa(env
, RV64
| RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
189 set_priv_version(env
, PRIV_VERSION_1_09_1
);
190 set_resetvec(env
, DEFAULT_RSTVEC
);
191 set_feature(env
, RISCV_FEATURE_MMU
);
192 set_feature(env
, RISCV_FEATURE_PMP
);
195 static void rv64gcsu_priv1_10_0_cpu_init(Object
*obj
)
197 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
198 set_misa(env
, RV64
| RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
199 set_priv_version(env
, PRIV_VERSION_1_10_0
);
200 set_resetvec(env
, DEFAULT_RSTVEC
);
201 set_feature(env
, RISCV_FEATURE_MMU
);
202 set_feature(env
, RISCV_FEATURE_PMP
);
205 static void rv64imacu_nommu_cpu_init(Object
*obj
)
207 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
208 set_misa(env
, RV64
| RVI
| RVM
| RVA
| RVC
| RVU
);
209 set_priv_version(env
, PRIV_VERSION_1_10_0
);
210 set_resetvec(env
, DEFAULT_RSTVEC
);
211 set_feature(env
, RISCV_FEATURE_PMP
);
216 static ObjectClass
*riscv_cpu_class_by_name(const char *cpu_model
)
222 cpuname
= g_strsplit(cpu_model
, ",", 1);
223 typename
= g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname
[0]);
224 oc
= object_class_by_name(typename
);
227 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_RISCV_CPU
) ||
228 object_class_is_abstract(oc
)) {
234 static void riscv_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
236 RISCVCPU
*cpu
= RISCV_CPU(cs
);
237 CPURISCVState
*env
= &cpu
->env
;
240 #if !defined(CONFIG_USER_ONLY)
241 if (riscv_has_ext(env
, RVH
)) {
242 qemu_fprintf(f
, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env
));
245 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "pc ", env
->pc
);
246 #ifndef CONFIG_USER_ONLY
247 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mhartid ", env
->mhartid
);
248 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mstatus ", env
->mstatus
);
249 #ifdef TARGET_RISCV32
250 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mstatush ", env
->mstatush
);
252 if (riscv_has_ext(env
, RVH
)) {
253 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "hstatus ", env
->hstatus
);
254 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "vsstatus ", env
->vsstatus
);
256 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mip ", env
->mip
);
257 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mie ", env
->mie
);
258 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mideleg ", env
->mideleg
);
259 if (riscv_has_ext(env
, RVH
)) {
260 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "hideleg ", env
->hideleg
);
262 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "medeleg ", env
->medeleg
);
263 if (riscv_has_ext(env
, RVH
)) {
264 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "hedeleg ", env
->hedeleg
);
266 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mtvec ", env
->mtvec
);
267 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "stvec ", env
->stvec
);
268 if (riscv_has_ext(env
, RVH
)) {
269 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "vstvec ", env
->vstvec
);
271 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mepc ", env
->mepc
);
272 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "sepc ", env
->sepc
);
273 if (riscv_has_ext(env
, RVH
)) {
274 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "vsepc ", env
->vsepc
);
276 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mcause ", env
->mcause
);
277 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "scause ", env
->scause
);
278 if (riscv_has_ext(env
, RVH
)) {
279 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "vscause ", env
->vscause
);
281 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mtval ", env
->mtval
);
282 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "stval ", env
->sbadaddr
);
283 if (riscv_has_ext(env
, RVH
)) {
284 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "htval ", env
->htval
);
285 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mtval2 ", env
->mtval2
);
289 for (i
= 0; i
< 32; i
++) {
290 qemu_fprintf(f
, " %s " TARGET_FMT_lx
,
291 riscv_int_regnames
[i
], env
->gpr
[i
]);
293 qemu_fprintf(f
, "\n");
296 if (flags
& CPU_DUMP_FPU
) {
297 for (i
= 0; i
< 32; i
++) {
298 qemu_fprintf(f
, " %s %016" PRIx64
,
299 riscv_fpr_regnames
[i
], env
->fpr
[i
]);
301 qemu_fprintf(f
, "\n");
307 static void riscv_cpu_set_pc(CPUState
*cs
, vaddr value
)
309 RISCVCPU
*cpu
= RISCV_CPU(cs
);
310 CPURISCVState
*env
= &cpu
->env
;
314 static void riscv_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
316 RISCVCPU
*cpu
= RISCV_CPU(cs
);
317 CPURISCVState
*env
= &cpu
->env
;
321 static bool riscv_cpu_has_work(CPUState
*cs
)
323 #ifndef CONFIG_USER_ONLY
324 RISCVCPU
*cpu
= RISCV_CPU(cs
);
325 CPURISCVState
*env
= &cpu
->env
;
327 * Definition of the WFI instruction requires it to ignore the privilege
328 * mode and delegation registers, but respect individual enables
330 return (env
->mip
& env
->mie
) != 0;
336 void restore_state_to_opc(CPURISCVState
*env
, TranslationBlock
*tb
,
342 static void riscv_cpu_reset(DeviceState
*dev
)
344 CPUState
*cs
= CPU(dev
);
345 RISCVCPU
*cpu
= RISCV_CPU(cs
);
346 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(cpu
);
347 CPURISCVState
*env
= &cpu
->env
;
349 mcc
->parent_reset(dev
);
350 #ifndef CONFIG_USER_ONLY
352 env
->mstatus
&= ~(MSTATUS_MIE
| MSTATUS_MPRV
);
354 env
->pc
= env
->resetvec
;
356 cs
->exception_index
= EXCP_NONE
;
358 set_default_nan_mode(1, &env
->fp_status
);
361 static void riscv_cpu_disas_set_info(CPUState
*s
, disassemble_info
*info
)
363 #if defined(TARGET_RISCV32)
364 info
->print_insn
= print_insn_riscv32
;
365 #elif defined(TARGET_RISCV64)
366 info
->print_insn
= print_insn_riscv64
;
370 static void riscv_cpu_realize(DeviceState
*dev
, Error
**errp
)
372 CPUState
*cs
= CPU(dev
);
373 RISCVCPU
*cpu
= RISCV_CPU(dev
);
374 CPURISCVState
*env
= &cpu
->env
;
375 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(dev
);
376 int priv_version
= PRIV_VERSION_1_11_0
;
377 target_ulong target_misa
= 0;
378 Error
*local_err
= NULL
;
380 cpu_exec_realizefn(cs
, &local_err
);
381 if (local_err
!= NULL
) {
382 error_propagate(errp
, local_err
);
386 if (cpu
->cfg
.priv_spec
) {
387 if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.11.0")) {
388 priv_version
= PRIV_VERSION_1_11_0
;
389 } else if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.10.0")) {
390 priv_version
= PRIV_VERSION_1_10_0
;
391 } else if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.9.1")) {
392 priv_version
= PRIV_VERSION_1_09_1
;
395 "Unsupported privilege spec version '%s'",
401 set_priv_version(env
, priv_version
);
402 set_resetvec(env
, DEFAULT_RSTVEC
);
405 set_feature(env
, RISCV_FEATURE_MMU
);
409 set_feature(env
, RISCV_FEATURE_PMP
);
412 /* If misa isn't set (rv32 and rv64 machines) set it here */
414 /* Do some ISA extension error checking */
415 if (cpu
->cfg
.ext_i
&& cpu
->cfg
.ext_e
) {
417 "I and E extensions are incompatible");
421 if (!cpu
->cfg
.ext_i
&& !cpu
->cfg
.ext_e
) {
423 "Either I or E extension must be set");
427 if (cpu
->cfg
.ext_g
&& !(cpu
->cfg
.ext_i
& cpu
->cfg
.ext_m
&
428 cpu
->cfg
.ext_a
& cpu
->cfg
.ext_f
&
430 warn_report("Setting G will also set IMAFD");
431 cpu
->cfg
.ext_i
= true;
432 cpu
->cfg
.ext_m
= true;
433 cpu
->cfg
.ext_a
= true;
434 cpu
->cfg
.ext_f
= true;
435 cpu
->cfg
.ext_d
= true;
438 /* Set the ISA extensions, checks should have happened above */
439 if (cpu
->cfg
.ext_i
) {
442 if (cpu
->cfg
.ext_e
) {
445 if (cpu
->cfg
.ext_m
) {
448 if (cpu
->cfg
.ext_a
) {
451 if (cpu
->cfg
.ext_f
) {
454 if (cpu
->cfg
.ext_d
) {
457 if (cpu
->cfg
.ext_c
) {
460 if (cpu
->cfg
.ext_s
) {
463 if (cpu
->cfg
.ext_u
) {
466 if (cpu
->cfg
.ext_h
) {
470 set_misa(env
, RVXLEN
| target_misa
);
473 riscv_cpu_register_gdb_regs_for_features(cs
);
478 mcc
->parent_realize(dev
, errp
);
481 static void riscv_cpu_init(Object
*obj
)
483 RISCVCPU
*cpu
= RISCV_CPU(obj
);
485 cpu_set_cpustate_pointers(cpu
);
488 static const VMStateDescription vmstate_riscv_cpu
= {
493 static Property riscv_cpu_properties
[] = {
494 DEFINE_PROP_BOOL("i", RISCVCPU
, cfg
.ext_i
, true),
495 DEFINE_PROP_BOOL("e", RISCVCPU
, cfg
.ext_e
, false),
496 DEFINE_PROP_BOOL("g", RISCVCPU
, cfg
.ext_g
, true),
497 DEFINE_PROP_BOOL("m", RISCVCPU
, cfg
.ext_m
, true),
498 DEFINE_PROP_BOOL("a", RISCVCPU
, cfg
.ext_a
, true),
499 DEFINE_PROP_BOOL("f", RISCVCPU
, cfg
.ext_f
, true),
500 DEFINE_PROP_BOOL("d", RISCVCPU
, cfg
.ext_d
, true),
501 DEFINE_PROP_BOOL("c", RISCVCPU
, cfg
.ext_c
, true),
502 DEFINE_PROP_BOOL("s", RISCVCPU
, cfg
.ext_s
, true),
503 DEFINE_PROP_BOOL("u", RISCVCPU
, cfg
.ext_u
, true),
504 /* This is experimental so mark with 'x-' */
505 DEFINE_PROP_BOOL("x-h", RISCVCPU
, cfg
.ext_h
, false),
506 DEFINE_PROP_BOOL("Counters", RISCVCPU
, cfg
.ext_counters
, true),
507 DEFINE_PROP_BOOL("Zifencei", RISCVCPU
, cfg
.ext_ifencei
, true),
508 DEFINE_PROP_BOOL("Zicsr", RISCVCPU
, cfg
.ext_icsr
, true),
509 DEFINE_PROP_STRING("priv_spec", RISCVCPU
, cfg
.priv_spec
),
510 DEFINE_PROP_BOOL("mmu", RISCVCPU
, cfg
.mmu
, true),
511 DEFINE_PROP_BOOL("pmp", RISCVCPU
, cfg
.pmp
, true),
512 DEFINE_PROP_END_OF_LIST(),
515 static void riscv_cpu_class_init(ObjectClass
*c
, void *data
)
517 RISCVCPUClass
*mcc
= RISCV_CPU_CLASS(c
);
518 CPUClass
*cc
= CPU_CLASS(c
);
519 DeviceClass
*dc
= DEVICE_CLASS(c
);
521 device_class_set_parent_realize(dc
, riscv_cpu_realize
,
522 &mcc
->parent_realize
);
524 device_class_set_parent_reset(dc
, riscv_cpu_reset
, &mcc
->parent_reset
);
526 cc
->class_by_name
= riscv_cpu_class_by_name
;
527 cc
->has_work
= riscv_cpu_has_work
;
528 cc
->do_interrupt
= riscv_cpu_do_interrupt
;
529 cc
->cpu_exec_interrupt
= riscv_cpu_exec_interrupt
;
530 cc
->dump_state
= riscv_cpu_dump_state
;
531 cc
->set_pc
= riscv_cpu_set_pc
;
532 cc
->synchronize_from_tb
= riscv_cpu_synchronize_from_tb
;
533 cc
->gdb_read_register
= riscv_cpu_gdb_read_register
;
534 cc
->gdb_write_register
= riscv_cpu_gdb_write_register
;
535 cc
->gdb_num_core_regs
= 33;
536 #if defined(TARGET_RISCV32)
537 cc
->gdb_core_xml_file
= "riscv-32bit-cpu.xml";
538 #elif defined(TARGET_RISCV64)
539 cc
->gdb_core_xml_file
= "riscv-64bit-cpu.xml";
541 cc
->gdb_stop_before_watchpoint
= true;
542 cc
->disas_set_info
= riscv_cpu_disas_set_info
;
543 #ifndef CONFIG_USER_ONLY
544 cc
->do_transaction_failed
= riscv_cpu_do_transaction_failed
;
545 cc
->do_unaligned_access
= riscv_cpu_do_unaligned_access
;
546 cc
->get_phys_page_debug
= riscv_cpu_get_phys_page_debug
;
549 cc
->tcg_initialize
= riscv_translate_init
;
550 cc
->tlb_fill
= riscv_cpu_tlb_fill
;
552 /* For now, mark unmigratable: */
553 cc
->vmsd
= &vmstate_riscv_cpu
;
554 device_class_set_props(dc
, riscv_cpu_properties
);
557 char *riscv_isa_string(RISCVCPU
*cpu
)
560 const size_t maxlen
= sizeof("rv128") + sizeof(riscv_exts
) + 1;
561 char *isa_str
= g_new(char, maxlen
);
562 char *p
= isa_str
+ snprintf(isa_str
, maxlen
, "rv%d", TARGET_LONG_BITS
);
563 for (i
= 0; i
< sizeof(riscv_exts
); i
++) {
564 if (cpu
->env
.misa
& RV(riscv_exts
[i
])) {
565 *p
++ = qemu_tolower(riscv_exts
[i
]);
572 static gint
riscv_cpu_list_compare(gconstpointer a
, gconstpointer b
)
574 ObjectClass
*class_a
= (ObjectClass
*)a
;
575 ObjectClass
*class_b
= (ObjectClass
*)b
;
576 const char *name_a
, *name_b
;
578 name_a
= object_class_get_name(class_a
);
579 name_b
= object_class_get_name(class_b
);
580 return strcmp(name_a
, name_b
);
583 static void riscv_cpu_list_entry(gpointer data
, gpointer user_data
)
585 const char *typename
= object_class_get_name(OBJECT_CLASS(data
));
586 int len
= strlen(typename
) - strlen(RISCV_CPU_TYPE_SUFFIX
);
588 qemu_printf("%.*s\n", len
, typename
);
591 void riscv_cpu_list(void)
595 list
= object_class_get_list(TYPE_RISCV_CPU
, false);
596 list
= g_slist_sort(list
, riscv_cpu_list_compare
);
597 g_slist_foreach(list
, riscv_cpu_list_entry
, NULL
);
601 #define DEFINE_CPU(type_name, initfn) \
604 .parent = TYPE_RISCV_CPU, \
605 .instance_init = initfn \
608 static const TypeInfo riscv_cpu_type_infos
[] = {
610 .name
= TYPE_RISCV_CPU
,
612 .instance_size
= sizeof(RISCVCPU
),
613 .instance_init
= riscv_cpu_init
,
615 .class_size
= sizeof(RISCVCPUClass
),
616 .class_init
= riscv_cpu_class_init
,
618 DEFINE_CPU(TYPE_RISCV_CPU_ANY
, riscv_any_cpu_init
),
619 #if defined(TARGET_RISCV32)
620 DEFINE_CPU(TYPE_RISCV_CPU_BASE32
, riscv_base32_cpu_init
),
621 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31
, rv32imacu_nommu_cpu_init
),
622 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34
, rv32imafcu_nommu_cpu_init
),
623 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34
, rv32gcsu_priv1_10_0_cpu_init
),
625 DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU
, rv32imacu_nommu_cpu_init
),
626 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1
, rv32gcsu_priv1_09_1_cpu_init
),
627 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0
, rv32gcsu_priv1_10_0_cpu_init
)
628 #elif defined(TARGET_RISCV64)
629 DEFINE_CPU(TYPE_RISCV_CPU_BASE64
, riscv_base64_cpu_init
),
630 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51
, rv64imacu_nommu_cpu_init
),
631 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54
, rv64gcsu_priv1_10_0_cpu_init
),
633 DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU
, rv64imacu_nommu_cpu_init
),
634 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1
, rv64gcsu_priv1_09_1_cpu_init
),
635 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0
, rv64gcsu_priv1_10_0_cpu_init
)
639 DEFINE_TYPES(riscv_cpu_type_infos
)