2 * ColdFire UART emulation.
4 * Copyright (c) 2007 CodeSourcery.
6 * This code is licensed under the GPL
9 #include "qemu/osdep.h"
11 #include "hw/sysbus.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "hw/m68k/mcf.h"
15 #include "hw/qdev-properties.h"
16 #include "chardev/char-fe.h"
17 #include "qom/object.h"
19 struct mcf_uart_state
{
20 SysBusDevice parent_obj
;
39 #define TYPE_MCF_UART "mcf-uart"
40 OBJECT_DECLARE_SIMPLE_TYPE(mcf_uart_state
, MCF_UART
)
42 /* UART Status Register bits. */
43 #define MCF_UART_RxRDY 0x01
44 #define MCF_UART_FFULL 0x02
45 #define MCF_UART_TxRDY 0x04
46 #define MCF_UART_TxEMP 0x08
47 #define MCF_UART_OE 0x10
48 #define MCF_UART_PE 0x20
49 #define MCF_UART_FE 0x40
50 #define MCF_UART_RB 0x80
52 /* Interrupt flags. */
53 #define MCF_UART_TxINT 0x01
54 #define MCF_UART_RxINT 0x02
55 #define MCF_UART_DBINT 0x04
56 #define MCF_UART_COSINT 0x80
59 #define MCF_UART_BC0 0x01
60 #define MCF_UART_BC1 0x02
61 #define MCF_UART_PT 0x04
62 #define MCF_UART_PM0 0x08
63 #define MCF_UART_PM1 0x10
64 #define MCF_UART_ERR 0x20
65 #define MCF_UART_RxIRQ 0x40
66 #define MCF_UART_RxRTS 0x80
68 static void mcf_uart_update(mcf_uart_state
*s
)
70 s
->isr
&= ~(MCF_UART_TxINT
| MCF_UART_RxINT
);
71 if (s
->sr
& MCF_UART_TxRDY
)
72 s
->isr
|= MCF_UART_TxINT
;
73 if ((s
->sr
& ((s
->mr
[0] & MCF_UART_RxIRQ
)
74 ? MCF_UART_FFULL
: MCF_UART_RxRDY
)) != 0)
75 s
->isr
|= MCF_UART_RxINT
;
77 qemu_set_irq(s
->irq
, (s
->isr
& s
->imr
) != 0);
80 uint64_t mcf_uart_read(void *opaque
, hwaddr addr
,
83 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
84 switch (addr
& 0x3f) {
86 return s
->mr
[s
->current_mr
];
99 for (i
= 0; i
< s
->fifo_len
; i
++)
100 s
->fifo
[i
] = s
->fifo
[i
+ 1];
101 s
->sr
&= ~MCF_UART_FFULL
;
102 if (s
->fifo_len
== 0)
103 s
->sr
&= ~MCF_UART_RxRDY
;
105 qemu_chr_fe_accept_input(&s
->chr
);
109 /* TODO: Implement IPCR. */
122 /* Update TxRDY flag and set data if present and enabled. */
123 static void mcf_uart_do_tx(mcf_uart_state
*s
)
125 if (s
->tx_enabled
&& (s
->sr
& MCF_UART_TxEMP
) == 0) {
126 /* XXX this blocks entire thread. Rewrite to use
127 * qemu_chr_fe_write and background I/O callbacks */
128 qemu_chr_fe_write_all(&s
->chr
, (unsigned char *)&s
->tb
, 1);
129 s
->sr
|= MCF_UART_TxEMP
;
132 s
->sr
|= MCF_UART_TxRDY
;
134 s
->sr
&= ~MCF_UART_TxRDY
;
138 static void mcf_do_command(mcf_uart_state
*s
, uint8_t cmd
)
141 switch ((cmd
>> 4) & 7) {
144 case 1: /* Reset mode register pointer. */
147 case 2: /* Reset receiver. */
150 s
->sr
&= ~(MCF_UART_RxRDY
| MCF_UART_FFULL
);
152 case 3: /* Reset transmitter. */
154 s
->sr
|= MCF_UART_TxEMP
;
155 s
->sr
&= ~MCF_UART_TxRDY
;
157 case 4: /* Reset error status. */
159 case 5: /* Reset break-change interrupt. */
160 s
->isr
&= ~MCF_UART_DBINT
;
162 case 6: /* Start break. */
163 case 7: /* Stop break. */
167 /* Transmitter command. */
168 switch ((cmd
>> 2) & 3) {
171 case 1: /* Enable. */
175 case 2: /* Disable. */
179 case 3: /* Reserved. */
180 fprintf(stderr
, "mcf_uart: Bad TX command\n");
184 /* Receiver command. */
188 case 1: /* Enable. */
194 case 3: /* Reserved. */
195 fprintf(stderr
, "mcf_uart: Bad RX command\n");
200 void mcf_uart_write(void *opaque
, hwaddr addr
,
201 uint64_t val
, unsigned size
)
203 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
204 switch (addr
& 0x3f) {
206 s
->mr
[s
->current_mr
] = val
;
210 /* CSR is ignored. */
212 case 0x08: /* Command Register. */
213 mcf_do_command(s
, val
);
215 case 0x0c: /* Transmit Buffer. */
216 s
->sr
&= ~MCF_UART_TxEMP
;
221 /* ACR is ignored. */
232 static void mcf_uart_reset(DeviceState
*dev
)
234 mcf_uart_state
*s
= MCF_UART(dev
);
239 s
->sr
= MCF_UART_TxEMP
;
246 static void mcf_uart_push_byte(mcf_uart_state
*s
, uint8_t data
)
248 /* Break events overwrite the last byte if the fifo is full. */
249 if (s
->fifo_len
== 4)
252 s
->fifo
[s
->fifo_len
] = data
;
254 s
->sr
|= MCF_UART_RxRDY
;
255 if (s
->fifo_len
== 4)
256 s
->sr
|= MCF_UART_FFULL
;
261 static void mcf_uart_event(void *opaque
, QEMUChrEvent event
)
263 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
266 case CHR_EVENT_BREAK
:
267 s
->isr
|= MCF_UART_DBINT
;
268 mcf_uart_push_byte(s
, 0);
275 static int mcf_uart_can_receive(void *opaque
)
277 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
279 return s
->rx_enabled
&& (s
->sr
& MCF_UART_FFULL
) == 0;
282 static void mcf_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
284 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
286 mcf_uart_push_byte(s
, buf
[0]);
289 static const MemoryRegionOps mcf_uart_ops
= {
290 .read
= mcf_uart_read
,
291 .write
= mcf_uart_write
,
292 .endianness
= DEVICE_NATIVE_ENDIAN
,
295 static void mcf_uart_instance_init(Object
*obj
)
297 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
298 mcf_uart_state
*s
= MCF_UART(dev
);
300 memory_region_init_io(&s
->iomem
, obj
, &mcf_uart_ops
, s
, "uart", 0x40);
301 sysbus_init_mmio(dev
, &s
->iomem
);
303 sysbus_init_irq(dev
, &s
->irq
);
306 static void mcf_uart_realize(DeviceState
*dev
, Error
**errp
)
308 mcf_uart_state
*s
= MCF_UART(dev
);
310 qemu_chr_fe_set_handlers(&s
->chr
, mcf_uart_can_receive
, mcf_uart_receive
,
311 mcf_uart_event
, NULL
, s
, NULL
, true);
314 static Property mcf_uart_properties
[] = {
315 DEFINE_PROP_CHR("chardev", mcf_uart_state
, chr
),
316 DEFINE_PROP_END_OF_LIST(),
319 static void mcf_uart_class_init(ObjectClass
*oc
, void *data
)
321 DeviceClass
*dc
= DEVICE_CLASS(oc
);
323 dc
->realize
= mcf_uart_realize
;
324 dc
->reset
= mcf_uart_reset
;
325 device_class_set_props(dc
, mcf_uart_properties
);
326 set_bit(DEVICE_CATEGORY_INPUT
, dc
->categories
);
329 static const TypeInfo mcf_uart_info
= {
330 .name
= TYPE_MCF_UART
,
331 .parent
= TYPE_SYS_BUS_DEVICE
,
332 .instance_size
= sizeof(mcf_uart_state
),
333 .instance_init
= mcf_uart_instance_init
,
334 .class_init
= mcf_uart_class_init
,
337 static void mcf_uart_register(void)
339 type_register_static(&mcf_uart_info
);
342 type_init(mcf_uart_register
)
344 void *mcf_uart_init(qemu_irq irq
, Chardev
*chrdrv
)
348 dev
= qdev_new(TYPE_MCF_UART
);
350 qdev_prop_set_chr(dev
, "chardev", chrdrv
);
352 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
354 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, irq
);
359 void mcf_uart_mm_init(hwaddr base
, qemu_irq irq
, Chardev
*chrdrv
)
363 dev
= mcf_uart_init(irq
, chrdrv
);
364 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);