2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "tcg-pool.inc.c"
28 #if defined _CALL_DARWIN || defined __APPLE__
29 #define TCG_TARGET_CALL_DARWIN
32 # define TCG_TARGET_CALL_ALIGN_ARGS 1
35 /* For some memory operations, we need a scratch that isn't R0. For the AIX
36 calling convention, we can re-use the TOC register since we'll be reloading
37 it at every call. Otherwise R12 will do nicely as neither a call-saved
38 register nor a parameter register. */
40 # define TCG_REG_TMP1 TCG_REG_R2
42 # define TCG_REG_TMP1 TCG_REG_R12
45 #define TCG_REG_TB TCG_REG_R31
46 #define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
48 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */
49 #define SZP ((int)sizeof(void *))
51 /* Shorthand for size of a register. */
52 #define SZR (TCG_TARGET_REG_BITS / 8)
54 #define TCG_CT_CONST_S16 0x100
55 #define TCG_CT_CONST_U16 0x200
56 #define TCG_CT_CONST_S32 0x400
57 #define TCG_CT_CONST_U32 0x800
58 #define TCG_CT_CONST_ZERO 0x1000
59 #define TCG_CT_CONST_MONE 0x2000
60 #define TCG_CT_CONST_WSZ 0x4000
62 static tcg_insn_unit
*tb_ret_addr
;
67 #define HAVE_ISA_2_06 have_isa_2_06
68 #define HAVE_ISEL have_isa_2_06
70 #ifndef CONFIG_SOFTMMU
71 #define TCG_GUEST_BASE_REG 30
74 #ifdef CONFIG_DEBUG_TCG
75 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
111 static const int tcg_target_reg_alloc_order
[] = {
112 TCG_REG_R14
, /* call saved registers */
130 TCG_REG_R12
, /* call clobbered, non-arguments */
134 TCG_REG_R10
, /* call clobbered, arguments */
144 static const int tcg_target_call_iarg_regs
[] = {
155 static const int tcg_target_call_oarg_regs
[] = {
160 static const int tcg_target_callee_save_regs
[] = {
161 #ifdef TCG_TARGET_CALL_DARWIN
177 TCG_REG_R27
, /* currently used for the global env */
184 static inline bool in_range_b(tcg_target_long target
)
186 return target
== sextract64(target
, 0, 26);
189 static uint32_t reloc_pc24_val(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
191 ptrdiff_t disp
= tcg_ptr_byte_diff(target
, pc
);
192 tcg_debug_assert(in_range_b(disp
));
193 return disp
& 0x3fffffc;
196 static bool reloc_pc24(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
198 ptrdiff_t disp
= tcg_ptr_byte_diff(target
, pc
);
199 if (in_range_b(disp
)) {
200 *pc
= (*pc
& ~0x3fffffc) | (disp
& 0x3fffffc);
206 static uint16_t reloc_pc14_val(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
208 ptrdiff_t disp
= tcg_ptr_byte_diff(target
, pc
);
209 tcg_debug_assert(disp
== (int16_t) disp
);
210 return disp
& 0xfffc;
213 static bool reloc_pc14(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
215 ptrdiff_t disp
= tcg_ptr_byte_diff(target
, pc
);
216 if (disp
== (int16_t) disp
) {
217 *pc
= (*pc
& ~0xfffc) | (disp
& 0xfffc);
223 /* parse target specific constraints */
224 static const char *target_parse_constraint(TCGArgConstraint
*ct
,
225 const char *ct_str
, TCGType type
)
228 case 'A': case 'B': case 'C': case 'D':
229 ct
->ct
|= TCG_CT_REG
;
230 tcg_regset_set_reg(ct
->u
.regs
, 3 + ct_str
[0] - 'A');
233 ct
->ct
|= TCG_CT_REG
;
234 ct
->u
.regs
= 0xffffffff;
236 case 'L': /* qemu_ld constraint */
237 ct
->ct
|= TCG_CT_REG
;
238 ct
->u
.regs
= 0xffffffff;
239 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
240 #ifdef CONFIG_SOFTMMU
241 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
242 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
245 case 'S': /* qemu_st constraint */
246 ct
->ct
|= TCG_CT_REG
;
247 ct
->u
.regs
= 0xffffffff;
248 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
249 #ifdef CONFIG_SOFTMMU
250 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
251 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
252 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R6
);
256 ct
->ct
|= TCG_CT_CONST_S16
;
259 ct
->ct
|= TCG_CT_CONST_U16
;
262 ct
->ct
|= TCG_CT_CONST_MONE
;
265 ct
->ct
|= TCG_CT_CONST_S32
;
268 ct
->ct
|= TCG_CT_CONST_U32
;
271 ct
->ct
|= TCG_CT_CONST_WSZ
;
274 ct
->ct
|= TCG_CT_CONST_ZERO
;
282 /* test if a constant matches the constraint */
283 static int tcg_target_const_match(tcg_target_long val
, TCGType type
,
284 const TCGArgConstraint
*arg_ct
)
287 if (ct
& TCG_CT_CONST
) {
291 /* The only 32-bit constraint we use aside from
292 TCG_CT_CONST is TCG_CT_CONST_S16. */
293 if (type
== TCG_TYPE_I32
) {
297 if ((ct
& TCG_CT_CONST_S16
) && val
== (int16_t)val
) {
299 } else if ((ct
& TCG_CT_CONST_U16
) && val
== (uint16_t)val
) {
301 } else if ((ct
& TCG_CT_CONST_S32
) && val
== (int32_t)val
) {
303 } else if ((ct
& TCG_CT_CONST_U32
) && val
== (uint32_t)val
) {
305 } else if ((ct
& TCG_CT_CONST_ZERO
) && val
== 0) {
307 } else if ((ct
& TCG_CT_CONST_MONE
) && val
== -1) {
309 } else if ((ct
& TCG_CT_CONST_WSZ
)
310 && val
== (type
== TCG_TYPE_I32
? 32 : 64)) {
316 #define OPCD(opc) ((opc)<<26)
317 #define XO19(opc) (OPCD(19)|((opc)<<1))
318 #define MD30(opc) (OPCD(30)|((opc)<<2))
319 #define MDS30(opc) (OPCD(30)|((opc)<<1))
320 #define XO31(opc) (OPCD(31)|((opc)<<1))
321 #define XO58(opc) (OPCD(58)|(opc))
322 #define XO62(opc) (OPCD(62)|(opc))
326 #define LBZ OPCD( 34)
327 #define LHZ OPCD( 40)
328 #define LHA OPCD( 42)
329 #define LWZ OPCD( 32)
330 #define STB OPCD( 38)
331 #define STH OPCD( 44)
332 #define STW OPCD( 36)
335 #define STDU XO62( 1)
336 #define STDX XO31(149)
339 #define LDX XO31( 21)
342 #define LWAX XO31(341)
344 #define ADDIC OPCD( 12)
345 #define ADDI OPCD( 14)
346 #define ADDIS OPCD( 15)
347 #define ORI OPCD( 24)
348 #define ORIS OPCD( 25)
349 #define XORI OPCD( 26)
350 #define XORIS OPCD( 27)
351 #define ANDI OPCD( 28)
352 #define ANDIS OPCD( 29)
353 #define MULLI OPCD( 7)
354 #define CMPLI OPCD( 10)
355 #define CMPI OPCD( 11)
356 #define SUBFIC OPCD( 8)
358 #define LWZU OPCD( 33)
359 #define STWU OPCD( 37)
361 #define RLWIMI OPCD( 20)
362 #define RLWINM OPCD( 21)
363 #define RLWNM OPCD( 23)
365 #define RLDICL MD30( 0)
366 #define RLDICR MD30( 1)
367 #define RLDIMI MD30( 3)
368 #define RLDCL MDS30( 8)
370 #define BCLR XO19( 16)
371 #define BCCTR XO19(528)
372 #define CRAND XO19(257)
373 #define CRANDC XO19(129)
374 #define CRNAND XO19(225)
375 #define CROR XO19(449)
376 #define CRNOR XO19( 33)
378 #define EXTSB XO31(954)
379 #define EXTSH XO31(922)
380 #define EXTSW XO31(986)
381 #define ADD XO31(266)
382 #define ADDE XO31(138)
383 #define ADDME XO31(234)
384 #define ADDZE XO31(202)
385 #define ADDC XO31( 10)
386 #define AND XO31( 28)
387 #define SUBF XO31( 40)
388 #define SUBFC XO31( 8)
389 #define SUBFE XO31(136)
390 #define SUBFME XO31(232)
391 #define SUBFZE XO31(200)
393 #define XOR XO31(316)
394 #define MULLW XO31(235)
395 #define MULHW XO31( 75)
396 #define MULHWU XO31( 11)
397 #define DIVW XO31(491)
398 #define DIVWU XO31(459)
400 #define CMPL XO31( 32)
401 #define LHBRX XO31(790)
402 #define LWBRX XO31(534)
403 #define LDBRX XO31(532)
404 #define STHBRX XO31(918)
405 #define STWBRX XO31(662)
406 #define STDBRX XO31(660)
407 #define MFSPR XO31(339)
408 #define MTSPR XO31(467)
409 #define SRAWI XO31(824)
410 #define NEG XO31(104)
411 #define MFCR XO31( 19)
412 #define MFOCRF (MFCR | (1u << 20))
413 #define NOR XO31(124)
414 #define CNTLZW XO31( 26)
415 #define CNTLZD XO31( 58)
416 #define CNTTZW XO31(538)
417 #define CNTTZD XO31(570)
418 #define CNTPOPW XO31(378)
419 #define CNTPOPD XO31(506)
420 #define ANDC XO31( 60)
421 #define ORC XO31(412)
422 #define EQV XO31(284)
423 #define NAND XO31(476)
424 #define ISEL XO31( 15)
426 #define MULLD XO31(233)
427 #define MULHD XO31( 73)
428 #define MULHDU XO31( 9)
429 #define DIVD XO31(489)
430 #define DIVDU XO31(457)
432 #define LBZX XO31( 87)
433 #define LHZX XO31(279)
434 #define LHAX XO31(343)
435 #define LWZX XO31( 23)
436 #define STBX XO31(215)
437 #define STHX XO31(407)
438 #define STWX XO31(151)
440 #define EIEIO XO31(854)
441 #define HWSYNC XO31(598)
442 #define LWSYNC (HWSYNC | (1u << 21))
444 #define SPR(a, b) ((((a)<<5)|(b))<<11)
446 #define CTR SPR(9, 0)
448 #define SLW XO31( 24)
449 #define SRW XO31(536)
450 #define SRAW XO31(792)
452 #define SLD XO31( 27)
453 #define SRD XO31(539)
454 #define SRAD XO31(794)
455 #define SRADI XO31(413<<1)
458 #define TRAP (TW | TO(31))
460 #define NOP ORI /* ori 0,0,0 */
462 #define RT(r) ((r)<<21)
463 #define RS(r) ((r)<<21)
464 #define RA(r) ((r)<<16)
465 #define RB(r) ((r)<<11)
466 #define TO(t) ((t)<<21)
467 #define SH(s) ((s)<<11)
468 #define MB(b) ((b)<<6)
469 #define ME(e) ((e)<<1)
470 #define BO(o) ((o)<<21)
471 #define MB64(b) ((b)<<5)
472 #define FXM(b) (1 << (19 - (b)))
476 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
477 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
478 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
479 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
481 #define BF(n) ((n)<<23)
482 #define BI(n, c) (((c)+((n)*4))<<16)
483 #define BT(n, c) (((c)+((n)*4))<<21)
484 #define BA(n, c) (((c)+((n)*4))<<16)
485 #define BB(n, c) (((c)+((n)*4))<<11)
486 #define BC_(n, c) (((c)+((n)*4))<<6)
488 #define BO_COND_TRUE BO(12)
489 #define BO_COND_FALSE BO( 4)
490 #define BO_ALWAYS BO(20)
499 static const uint32_t tcg_to_bc
[] = {
500 [TCG_COND_EQ
] = BC
| BI(7, CR_EQ
) | BO_COND_TRUE
,
501 [TCG_COND_NE
] = BC
| BI(7, CR_EQ
) | BO_COND_FALSE
,
502 [TCG_COND_LT
] = BC
| BI(7, CR_LT
) | BO_COND_TRUE
,
503 [TCG_COND_GE
] = BC
| BI(7, CR_LT
) | BO_COND_FALSE
,
504 [TCG_COND_LE
] = BC
| BI(7, CR_GT
) | BO_COND_FALSE
,
505 [TCG_COND_GT
] = BC
| BI(7, CR_GT
) | BO_COND_TRUE
,
506 [TCG_COND_LTU
] = BC
| BI(7, CR_LT
) | BO_COND_TRUE
,
507 [TCG_COND_GEU
] = BC
| BI(7, CR_LT
) | BO_COND_FALSE
,
508 [TCG_COND_LEU
] = BC
| BI(7, CR_GT
) | BO_COND_FALSE
,
509 [TCG_COND_GTU
] = BC
| BI(7, CR_GT
) | BO_COND_TRUE
,
512 /* The low bit here is set if the RA and RB fields must be inverted. */
513 static const uint32_t tcg_to_isel
[] = {
514 [TCG_COND_EQ
] = ISEL
| BC_(7, CR_EQ
),
515 [TCG_COND_NE
] = ISEL
| BC_(7, CR_EQ
) | 1,
516 [TCG_COND_LT
] = ISEL
| BC_(7, CR_LT
),
517 [TCG_COND_GE
] = ISEL
| BC_(7, CR_LT
) | 1,
518 [TCG_COND_LE
] = ISEL
| BC_(7, CR_GT
) | 1,
519 [TCG_COND_GT
] = ISEL
| BC_(7, CR_GT
),
520 [TCG_COND_LTU
] = ISEL
| BC_(7, CR_LT
),
521 [TCG_COND_GEU
] = ISEL
| BC_(7, CR_LT
) | 1,
522 [TCG_COND_LEU
] = ISEL
| BC_(7, CR_GT
) | 1,
523 [TCG_COND_GTU
] = ISEL
| BC_(7, CR_GT
),
526 static bool patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
527 intptr_t value
, intptr_t addend
)
529 tcg_insn_unit
*target
;
533 target
= (tcg_insn_unit
*)value
;
537 return reloc_pc14(code_ptr
, target
);
539 return reloc_pc24(code_ptr
, target
);
541 /* We are abusing this relocation type. This points to a pair
542 of insns, addis + load. If the displacement is small, we
543 can nop out the addis. */
544 if (value
== (int16_t)value
) {
546 old
= deposit32(code_ptr
[1], 0, 16, value
);
547 code_ptr
[1] = deposit32(old
, 16, 5, TCG_REG_TB
);
551 if (hi
+ lo
!= value
) {
554 code_ptr
[0] = deposit32(code_ptr
[0], 0, 16, hi
>> 16);
555 code_ptr
[1] = deposit32(code_ptr
[1], 0, 16, lo
);
559 g_assert_not_reached();
564 static void tcg_out_mem_long(TCGContext
*s
, int opi
, int opx
, TCGReg rt
,
565 TCGReg base
, tcg_target_long offset
);
567 static void tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
)
569 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
571 tcg_out32(s
, OR
| SAB(arg
, ret
, arg
));
575 static inline void tcg_out_rld(TCGContext
*s
, int op
, TCGReg ra
, TCGReg rs
,
578 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64);
579 sh
= SH(sh
& 0x1f) | (((sh
>> 5) & 1) << 1);
580 mb
= MB64((mb
>> 5) | ((mb
<< 1) & 0x3f));
581 tcg_out32(s
, op
| RA(ra
) | RS(rs
) | sh
| mb
);
584 static inline void tcg_out_rlw(TCGContext
*s
, int op
, TCGReg ra
, TCGReg rs
,
585 int sh
, int mb
, int me
)
587 tcg_out32(s
, op
| RA(ra
) | RS(rs
) | SH(sh
) | MB(mb
) | ME(me
));
590 static inline void tcg_out_ext32u(TCGContext
*s
, TCGReg dst
, TCGReg src
)
592 tcg_out_rld(s
, RLDICL
, dst
, src
, 0, 32);
595 static inline void tcg_out_shli32(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
597 tcg_out_rlw(s
, RLWINM
, dst
, src
, c
, 0, 31 - c
);
600 static inline void tcg_out_shli64(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
602 tcg_out_rld(s
, RLDICR
, dst
, src
, c
, 63 - c
);
605 static inline void tcg_out_shri32(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
607 tcg_out_rlw(s
, RLWINM
, dst
, src
, 32 - c
, c
, 31);
610 static inline void tcg_out_shri64(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
612 tcg_out_rld(s
, RLDICL
, dst
, src
, 64 - c
, c
);
615 /* Emit a move into ret of arg, if it can be done in one insn. */
616 static bool tcg_out_movi_one(TCGContext
*s
, TCGReg ret
, tcg_target_long arg
)
618 if (arg
== (int16_t)arg
) {
619 tcg_out32(s
, ADDI
| TAI(ret
, 0, arg
));
622 if (arg
== (int32_t)arg
&& (arg
& 0xffff) == 0) {
623 tcg_out32(s
, ADDIS
| TAI(ret
, 0, arg
>> 16));
629 static void tcg_out_movi_int(TCGContext
*s
, TCGType type
, TCGReg ret
,
630 tcg_target_long arg
, bool in_prologue
)
636 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
638 if (TCG_TARGET_REG_BITS
== 64 && type
== TCG_TYPE_I32
) {
642 /* Load 16-bit immediates with one insn. */
643 if (tcg_out_movi_one(s
, ret
, arg
)) {
647 /* Load addresses within the TB with one insn. */
648 tb_diff
= arg
- (intptr_t)s
->code_gen_ptr
;
649 if (!in_prologue
&& USE_REG_TB
&& tb_diff
== (int16_t)tb_diff
) {
650 tcg_out32(s
, ADDI
| TAI(ret
, TCG_REG_TB
, tb_diff
));
654 /* Load 32-bit immediates with two insns. Note that we've already
655 eliminated bare ADDIS, so we know both insns are required. */
656 if (TCG_TARGET_REG_BITS
== 32 || arg
== (int32_t)arg
) {
657 tcg_out32(s
, ADDIS
| TAI(ret
, 0, arg
>> 16));
658 tcg_out32(s
, ORI
| SAI(ret
, ret
, arg
));
661 if (arg
== (uint32_t)arg
&& !(arg
& 0x8000)) {
662 tcg_out32(s
, ADDI
| TAI(ret
, 0, arg
));
663 tcg_out32(s
, ORIS
| SAI(ret
, ret
, arg
>> 16));
667 /* Load masked 16-bit value. */
668 if (arg
> 0 && (arg
& 0x8000)) {
670 if ((tmp
& (tmp
+ 1)) == 0) {
671 int mb
= clz64(tmp
+ 1) + 1;
672 tcg_out32(s
, ADDI
| TAI(ret
, 0, arg
));
673 tcg_out_rld(s
, RLDICL
, ret
, ret
, 0, mb
);
678 /* Load common masks with 2 insns. */
681 if (tmp
== (int16_t)tmp
) {
682 tcg_out32(s
, ADDI
| TAI(ret
, 0, tmp
));
683 tcg_out_shli64(s
, ret
, ret
, shift
);
687 if (tcg_out_movi_one(s
, ret
, arg
<< shift
)) {
688 tcg_out_shri64(s
, ret
, ret
, shift
);
692 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */
693 if (!in_prologue
&& USE_REG_TB
&& tb_diff
== (int32_t)tb_diff
) {
694 tcg_out_mem_long(s
, ADDI
, ADD
, ret
, TCG_REG_TB
, tb_diff
);
698 /* Use the constant pool, if possible. */
699 if (!in_prologue
&& USE_REG_TB
) {
700 new_pool_label(s
, arg
, R_PPC_ADDR16
, s
->code_ptr
,
701 -(intptr_t)s
->code_gen_ptr
);
702 tcg_out32(s
, ADDIS
| TAI(ret
, TCG_REG_TB
, 0));
703 tcg_out32(s
, LD
| TAI(ret
, ret
, 0));
707 tmp
= arg
>> 31 >> 1;
708 tcg_out_movi(s
, TCG_TYPE_I32
, ret
, tmp
);
710 tcg_out_shli64(s
, ret
, ret
, 32);
712 if (arg
& 0xffff0000) {
713 tcg_out32(s
, ORIS
| SAI(ret
, ret
, arg
>> 16));
716 tcg_out32(s
, ORI
| SAI(ret
, ret
, arg
));
720 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
, TCGReg ret
,
723 tcg_out_movi_int(s
, type
, ret
, arg
, false);
726 static bool mask_operand(uint32_t c
, int *mb
, int *me
)
730 /* Accept a bit pattern like:
734 Keep track of the transitions. */
735 if (c
== 0 || c
== -1) {
741 if (test
& (test
- 1)) {
746 *mb
= test
? clz32(test
& -test
) + 1 : 0;
750 static bool mask64_operand(uint64_t c
, int *mb
, int *me
)
759 /* Accept 1..10..0. */
765 /* Accept 0..01..1. */
766 if (lsb
== 1 && (c
& (c
+ 1)) == 0) {
767 *mb
= clz64(c
+ 1) + 1;
774 static void tcg_out_andi32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
)
778 if (mask_operand(c
, &mb
, &me
)) {
779 tcg_out_rlw(s
, RLWINM
, dst
, src
, 0, mb
, me
);
780 } else if ((c
& 0xffff) == c
) {
781 tcg_out32(s
, ANDI
| SAI(src
, dst
, c
));
783 } else if ((c
& 0xffff0000) == c
) {
784 tcg_out32(s
, ANDIS
| SAI(src
, dst
, c
>> 16));
787 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_R0
, c
);
788 tcg_out32(s
, AND
| SAB(src
, dst
, TCG_REG_R0
));
792 static void tcg_out_andi64(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint64_t c
)
796 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64);
797 if (mask64_operand(c
, &mb
, &me
)) {
799 tcg_out_rld(s
, RLDICR
, dst
, src
, 0, me
);
801 tcg_out_rld(s
, RLDICL
, dst
, src
, 0, mb
);
803 } else if ((c
& 0xffff) == c
) {
804 tcg_out32(s
, ANDI
| SAI(src
, dst
, c
));
806 } else if ((c
& 0xffff0000) == c
) {
807 tcg_out32(s
, ANDIS
| SAI(src
, dst
, c
>> 16));
810 tcg_out_movi(s
, TCG_TYPE_I64
, TCG_REG_R0
, c
);
811 tcg_out32(s
, AND
| SAB(src
, dst
, TCG_REG_R0
));
815 static void tcg_out_zori32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
,
816 int op_lo
, int op_hi
)
819 tcg_out32(s
, op_hi
| SAI(src
, dst
, c
>> 16));
823 tcg_out32(s
, op_lo
| SAI(src
, dst
, c
));
828 static void tcg_out_ori32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
)
830 tcg_out_zori32(s
, dst
, src
, c
, ORI
, ORIS
);
833 static void tcg_out_xori32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
)
835 tcg_out_zori32(s
, dst
, src
, c
, XORI
, XORIS
);
838 static void tcg_out_b(TCGContext
*s
, int mask
, tcg_insn_unit
*target
)
840 ptrdiff_t disp
= tcg_pcrel_diff(s
, target
);
841 if (in_range_b(disp
)) {
842 tcg_out32(s
, B
| (disp
& 0x3fffffc) | mask
);
844 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R0
, (uintptr_t)target
);
845 tcg_out32(s
, MTSPR
| RS(TCG_REG_R0
) | CTR
);
846 tcg_out32(s
, BCCTR
| BO_ALWAYS
| mask
);
850 static void tcg_out_mem_long(TCGContext
*s
, int opi
, int opx
, TCGReg rt
,
851 TCGReg base
, tcg_target_long offset
)
853 tcg_target_long orig
= offset
, l0
, l1
, extra
= 0, align
= 0;
854 bool is_store
= false;
855 TCGReg rs
= TCG_REG_TMP1
;
862 if (rt
!= TCG_REG_R0
) {
870 case STB
: case STH
: case STW
:
875 /* For unaligned, or very large offsets, use the indexed form. */
876 if (offset
& align
|| offset
!= (int32_t)offset
) {
880 tcg_debug_assert(!is_store
|| rs
!= rt
);
881 tcg_out_movi(s
, TCG_TYPE_PTR
, rs
, orig
);
882 tcg_out32(s
, opx
| TAB(rt
, base
, rs
));
886 l0
= (int16_t)offset
;
887 offset
= (offset
- l0
) >> 16;
888 l1
= (int16_t)offset
;
890 if (l1
< 0 && orig
>= 0) {
892 l1
= (int16_t)(offset
- 0x4000);
895 tcg_out32(s
, ADDIS
| TAI(rs
, base
, l1
));
899 tcg_out32(s
, ADDIS
| TAI(rs
, base
, extra
));
902 if (opi
!= ADDI
|| base
!= rt
|| l0
!= 0) {
903 tcg_out32(s
, opi
| TAI(rt
, base
, l0
));
907 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
,
908 TCGReg arg1
, intptr_t arg2
)
912 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
913 if (type
== TCG_TYPE_I32
) {
914 opi
= LWZ
, opx
= LWZX
;
918 tcg_out_mem_long(s
, opi
, opx
, ret
, arg1
, arg2
);
921 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
,
922 TCGReg arg1
, intptr_t arg2
)
926 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
927 if (type
== TCG_TYPE_I32
) {
928 opi
= STW
, opx
= STWX
;
930 opi
= STD
, opx
= STDX
;
932 tcg_out_mem_long(s
, opi
, opx
, arg
, arg1
, arg2
);
935 static inline bool tcg_out_sti(TCGContext
*s
, TCGType type
, TCGArg val
,
936 TCGReg base
, intptr_t ofs
)
941 static void tcg_out_cmp(TCGContext
*s
, int cond
, TCGArg arg1
, TCGArg arg2
,
942 int const_arg2
, int cr
, TCGType type
)
947 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
949 /* Simplify the comparisons below wrt CMPI. */
950 if (type
== TCG_TYPE_I32
) {
951 arg2
= (int32_t)arg2
;
958 if ((int16_t) arg2
== arg2
) {
962 } else if ((uint16_t) arg2
== arg2
) {
977 if ((int16_t) arg2
== arg2
) {
992 if ((uint16_t) arg2
== arg2
) {
1005 op
|= BF(cr
) | ((type
== TCG_TYPE_I64
) << 21);
1008 tcg_out32(s
, op
| RA(arg1
) | (arg2
& 0xffff));
1011 tcg_out_movi(s
, type
, TCG_REG_R0
, arg2
);
1014 tcg_out32(s
, op
| RA(arg1
) | RB(arg2
));
1018 static void tcg_out_setcond_eq0(TCGContext
*s
, TCGType type
,
1019 TCGReg dst
, TCGReg src
)
1021 if (type
== TCG_TYPE_I32
) {
1022 tcg_out32(s
, CNTLZW
| RS(src
) | RA(dst
));
1023 tcg_out_shri32(s
, dst
, dst
, 5);
1025 tcg_out32(s
, CNTLZD
| RS(src
) | RA(dst
));
1026 tcg_out_shri64(s
, dst
, dst
, 6);
1030 static void tcg_out_setcond_ne0(TCGContext
*s
, TCGReg dst
, TCGReg src
)
1032 /* X != 0 implies X + -1 generates a carry. Extra addition
1033 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1035 tcg_out32(s
, ADDIC
| TAI(dst
, src
, -1));
1036 tcg_out32(s
, SUBFE
| TAB(dst
, dst
, src
));
1038 tcg_out32(s
, ADDIC
| TAI(TCG_REG_R0
, src
, -1));
1039 tcg_out32(s
, SUBFE
| TAB(dst
, TCG_REG_R0
, src
));
1043 static TCGReg
tcg_gen_setcond_xor(TCGContext
*s
, TCGReg arg1
, TCGArg arg2
,
1047 if ((uint32_t)arg2
== arg2
) {
1048 tcg_out_xori32(s
, TCG_REG_R0
, arg1
, arg2
);
1050 tcg_out_movi(s
, TCG_TYPE_I64
, TCG_REG_R0
, arg2
);
1051 tcg_out32(s
, XOR
| SAB(arg1
, TCG_REG_R0
, TCG_REG_R0
));
1054 tcg_out32(s
, XOR
| SAB(arg1
, TCG_REG_R0
, arg2
));
1059 static void tcg_out_setcond(TCGContext
*s
, TCGType type
, TCGCond cond
,
1060 TCGArg arg0
, TCGArg arg1
, TCGArg arg2
,
1065 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
1067 /* Ignore high bits of a potential constant arg2. */
1068 if (type
== TCG_TYPE_I32
) {
1069 arg2
= (uint32_t)arg2
;
1072 /* Handle common and trivial cases before handling anything else. */
1076 tcg_out_setcond_eq0(s
, type
, arg0
, arg1
);
1079 if (TCG_TARGET_REG_BITS
== 64 && type
== TCG_TYPE_I32
) {
1080 tcg_out_ext32u(s
, TCG_REG_R0
, arg1
);
1083 tcg_out_setcond_ne0(s
, arg0
, arg1
);
1086 tcg_out32(s
, NOR
| SAB(arg1
, arg0
, arg1
));
1090 /* Extract the sign bit. */
1091 if (type
== TCG_TYPE_I32
) {
1092 tcg_out_shri32(s
, arg0
, arg1
, 31);
1094 tcg_out_shri64(s
, arg0
, arg1
, 63);
1102 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1103 All other cases below are also at least 3 insns, so speed up the
1104 code generator by not considering them and always using ISEL. */
1108 tcg_out_cmp(s
, cond
, arg1
, arg2
, const_arg2
, 7, type
);
1110 isel
= tcg_to_isel
[cond
];
1112 tcg_out_movi(s
, type
, arg0
, 1);
1114 /* arg0 = (bc ? 0 : 1) */
1115 tab
= TAB(arg0
, 0, arg0
);
1118 /* arg0 = (bc ? 1 : 0) */
1119 tcg_out_movi(s
, type
, TCG_REG_R0
, 0);
1120 tab
= TAB(arg0
, arg0
, TCG_REG_R0
);
1122 tcg_out32(s
, isel
| tab
);
1128 arg1
= tcg_gen_setcond_xor(s
, arg1
, arg2
, const_arg2
);
1129 tcg_out_setcond_eq0(s
, type
, arg0
, arg1
);
1133 arg1
= tcg_gen_setcond_xor(s
, arg1
, arg2
, const_arg2
);
1134 /* Discard the high bits only once, rather than both inputs. */
1135 if (TCG_TARGET_REG_BITS
== 64 && type
== TCG_TYPE_I32
) {
1136 tcg_out_ext32u(s
, TCG_REG_R0
, arg1
);
1139 tcg_out_setcond_ne0(s
, arg0
, arg1
);
1157 crop
= CRNOR
| BT(7, CR_EQ
) | BA(7, CR_LT
) | BB(7, CR_LT
);
1163 crop
= CRNOR
| BT(7, CR_EQ
) | BA(7, CR_GT
) | BB(7, CR_GT
);
1165 tcg_out_cmp(s
, cond
, arg1
, arg2
, const_arg2
, 7, type
);
1169 tcg_out32(s
, MFOCRF
| RT(TCG_REG_R0
) | FXM(7));
1170 tcg_out_rlw(s
, RLWINM
, arg0
, TCG_REG_R0
, sh
, 31, 31);
1178 static void tcg_out_bc(TCGContext
*s
, int bc
, TCGLabel
*l
)
1181 bc
|= reloc_pc14_val(s
->code_ptr
, l
->u
.value_ptr
);
1183 tcg_out_reloc(s
, s
->code_ptr
, R_PPC_REL14
, l
, 0);
1188 static void tcg_out_brcond(TCGContext
*s
, TCGCond cond
,
1189 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
1190 TCGLabel
*l
, TCGType type
)
1192 tcg_out_cmp(s
, cond
, arg1
, arg2
, const_arg2
, 7, type
);
1193 tcg_out_bc(s
, tcg_to_bc
[cond
], l
);
1196 static void tcg_out_movcond(TCGContext
*s
, TCGType type
, TCGCond cond
,
1197 TCGArg dest
, TCGArg c1
, TCGArg c2
, TCGArg v1
,
1198 TCGArg v2
, bool const_c2
)
1200 /* If for some reason both inputs are zero, don't produce bad code. */
1201 if (v1
== 0 && v2
== 0) {
1202 tcg_out_movi(s
, type
, dest
, 0);
1206 tcg_out_cmp(s
, cond
, c1
, c2
, const_c2
, 7, type
);
1209 int isel
= tcg_to_isel
[cond
];
1211 /* Swap the V operands if the operation indicates inversion. */
1218 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1220 tcg_out_movi(s
, type
, TCG_REG_R0
, 0);
1222 tcg_out32(s
, isel
| TAB(dest
, v1
, v2
));
1225 cond
= tcg_invert_cond(cond
);
1227 } else if (dest
!= v1
) {
1229 tcg_out_movi(s
, type
, dest
, 0);
1231 tcg_out_mov(s
, type
, dest
, v1
);
1234 /* Branch forward over one insn */
1235 tcg_out32(s
, tcg_to_bc
[cond
] | 8);
1237 tcg_out_movi(s
, type
, dest
, 0);
1239 tcg_out_mov(s
, type
, dest
, v2
);
1244 static void tcg_out_cntxz(TCGContext
*s
, TCGType type
, uint32_t opc
,
1245 TCGArg a0
, TCGArg a1
, TCGArg a2
, bool const_a2
)
1247 if (const_a2
&& a2
== (type
== TCG_TYPE_I32
? 32 : 64)) {
1248 tcg_out32(s
, opc
| RA(a0
) | RS(a1
));
1250 tcg_out_cmp(s
, TCG_COND_EQ
, a1
, 0, 1, 7, type
);
1251 /* Note that the only other valid constant for a2 is 0. */
1253 tcg_out32(s
, opc
| RA(TCG_REG_R0
) | RS(a1
));
1254 tcg_out32(s
, tcg_to_isel
[TCG_COND_EQ
] | TAB(a0
, a2
, TCG_REG_R0
));
1255 } else if (!const_a2
&& a0
== a2
) {
1256 tcg_out32(s
, tcg_to_bc
[TCG_COND_EQ
] | 8);
1257 tcg_out32(s
, opc
| RA(a0
) | RS(a1
));
1259 tcg_out32(s
, opc
| RA(a0
) | RS(a1
));
1260 tcg_out32(s
, tcg_to_bc
[TCG_COND_NE
] | 8);
1262 tcg_out_movi(s
, type
, a0
, 0);
1264 tcg_out_mov(s
, type
, a0
, a2
);
1270 static void tcg_out_cmp2(TCGContext
*s
, const TCGArg
*args
,
1271 const int *const_args
)
1273 static const struct { uint8_t bit1
, bit2
; } bits
[] = {
1274 [TCG_COND_LT
] = { CR_LT
, CR_LT
},
1275 [TCG_COND_LE
] = { CR_LT
, CR_GT
},
1276 [TCG_COND_GT
] = { CR_GT
, CR_GT
},
1277 [TCG_COND_GE
] = { CR_GT
, CR_LT
},
1278 [TCG_COND_LTU
] = { CR_LT
, CR_LT
},
1279 [TCG_COND_LEU
] = { CR_LT
, CR_GT
},
1280 [TCG_COND_GTU
] = { CR_GT
, CR_GT
},
1281 [TCG_COND_GEU
] = { CR_GT
, CR_LT
},
1284 TCGCond cond
= args
[4], cond2
;
1285 TCGArg al
, ah
, bl
, bh
;
1286 int blconst
, bhconst
;
1293 blconst
= const_args
[2];
1294 bhconst
= const_args
[3];
1303 tcg_out_cmp(s
, cond
, al
, bl
, blconst
, 6, TCG_TYPE_I32
);
1304 tcg_out_cmp(s
, cond
, ah
, bh
, bhconst
, 7, TCG_TYPE_I32
);
1305 tcg_out32(s
, op
| BT(7, CR_EQ
) | BA(6, CR_EQ
) | BB(7, CR_EQ
));
1316 bit1
= bits
[cond
].bit1
;
1317 bit2
= bits
[cond
].bit2
;
1318 op
= (bit1
!= bit2
? CRANDC
: CRAND
);
1319 cond2
= tcg_unsigned_cond(cond
);
1321 tcg_out_cmp(s
, cond
, ah
, bh
, bhconst
, 6, TCG_TYPE_I32
);
1322 tcg_out_cmp(s
, cond2
, al
, bl
, blconst
, 7, TCG_TYPE_I32
);
1323 tcg_out32(s
, op
| BT(7, CR_EQ
) | BA(6, CR_EQ
) | BB(7, bit2
));
1324 tcg_out32(s
, CROR
| BT(7, CR_EQ
) | BA(6, bit1
) | BB(7, CR_EQ
));
1332 static void tcg_out_setcond2(TCGContext
*s
, const TCGArg
*args
,
1333 const int *const_args
)
1335 tcg_out_cmp2(s
, args
+ 1, const_args
+ 1);
1336 tcg_out32(s
, MFOCRF
| RT(TCG_REG_R0
) | FXM(7));
1337 tcg_out_rlw(s
, RLWINM
, args
[0], TCG_REG_R0
, 31, 31, 31);
1340 static void tcg_out_brcond2 (TCGContext
*s
, const TCGArg
*args
,
1341 const int *const_args
)
1343 tcg_out_cmp2(s
, args
, const_args
);
1344 tcg_out_bc(s
, BC
| BI(7, CR_EQ
) | BO_COND_TRUE
, arg_label(args
[5]));
1347 static void tcg_out_mb(TCGContext
*s
, TCGArg a0
)
1349 uint32_t insn
= HWSYNC
;
1351 if (a0
== TCG_MO_LD_LD
) {
1353 } else if (a0
== TCG_MO_ST_ST
) {
1359 void tb_target_set_jmp_target(uintptr_t tc_ptr
, uintptr_t jmp_addr
,
1362 if (TCG_TARGET_REG_BITS
== 64) {
1363 tcg_insn_unit i1
, i2
;
1364 intptr_t tb_diff
= addr
- tc_ptr
;
1365 intptr_t br_diff
= addr
- (jmp_addr
+ 4);
1368 /* This does not exercise the range of the branch, but we do
1369 still need to be able to load the new value of TCG_REG_TB.
1370 But this does still happen quite often. */
1371 if (tb_diff
== (int16_t)tb_diff
) {
1372 i1
= ADDI
| TAI(TCG_REG_TB
, TCG_REG_TB
, tb_diff
);
1373 i2
= B
| (br_diff
& 0x3fffffc);
1375 intptr_t lo
= (int16_t)tb_diff
;
1376 intptr_t hi
= (int32_t)(tb_diff
- lo
);
1377 assert(tb_diff
== hi
+ lo
);
1378 i1
= ADDIS
| TAI(TCG_REG_TB
, TCG_REG_TB
, hi
>> 16);
1379 i2
= ADDI
| TAI(TCG_REG_TB
, TCG_REG_TB
, lo
);
1381 #ifdef HOST_WORDS_BIGENDIAN
1382 pair
= (uint64_t)i1
<< 32 | i2
;
1384 pair
= (uint64_t)i2
<< 32 | i1
;
1387 /* As per the enclosing if, this is ppc64. Avoid the _Static_assert
1388 within atomic_set that would fail to build a ppc32 host. */
1389 atomic_set__nocheck((uint64_t *)jmp_addr
, pair
);
1390 flush_icache_range(jmp_addr
, jmp_addr
+ 8);
1392 intptr_t diff
= addr
- jmp_addr
;
1393 tcg_debug_assert(in_range_b(diff
));
1394 atomic_set((uint32_t *)jmp_addr
, B
| (diff
& 0x3fffffc));
1395 flush_icache_range(jmp_addr
, jmp_addr
+ 4);
1399 static void tcg_out_call(TCGContext
*s
, tcg_insn_unit
*target
)
1402 /* Look through the descriptor. If the branch is in range, and we
1403 don't have to spend too much effort on building the toc. */
1404 void *tgt
= ((void **)target
)[0];
1405 uintptr_t toc
= ((uintptr_t *)target
)[1];
1406 intptr_t diff
= tcg_pcrel_diff(s
, tgt
);
1408 if (in_range_b(diff
) && toc
== (uint32_t)toc
) {
1409 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_TMP1
, toc
);
1410 tcg_out_b(s
, LK
, tgt
);
1412 /* Fold the low bits of the constant into the addresses below. */
1413 intptr_t arg
= (intptr_t)target
;
1414 int ofs
= (int16_t)arg
;
1416 if (ofs
+ 8 < 0x8000) {
1421 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_TMP1
, arg
);
1422 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R0
, TCG_REG_TMP1
, ofs
);
1423 tcg_out32(s
, MTSPR
| RA(TCG_REG_R0
) | CTR
);
1424 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R2
, TCG_REG_TMP1
, ofs
+ SZP
);
1425 tcg_out32(s
, BCCTR
| BO_ALWAYS
| LK
);
1427 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1430 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1431 address, which the callee uses to compute its TOC address. */
1432 /* FIXME: when the branch is in range, we could avoid r12 load if we
1433 knew that the destination uses the same TOC, and what its local
1434 entry point offset is. */
1435 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R12
, (intptr_t)target
);
1437 diff
= tcg_pcrel_diff(s
, target
);
1438 if (in_range_b(diff
)) {
1439 tcg_out_b(s
, LK
, target
);
1441 tcg_out32(s
, MTSPR
| RS(TCG_REG_R12
) | CTR
);
1442 tcg_out32(s
, BCCTR
| BO_ALWAYS
| LK
);
1445 tcg_out_b(s
, LK
, target
);
1449 static const uint32_t qemu_ldx_opc
[16] = {
1456 [MO_BSWAP
| MO_UB
] = LBZX
,
1457 [MO_BSWAP
| MO_UW
] = LHBRX
,
1458 [MO_BSWAP
| MO_UL
] = LWBRX
,
1459 [MO_BSWAP
| MO_Q
] = LDBRX
,
1462 static const uint32_t qemu_stx_opc
[16] = {
1467 [MO_BSWAP
| MO_UB
] = STBX
,
1468 [MO_BSWAP
| MO_UW
] = STHBRX
,
1469 [MO_BSWAP
| MO_UL
] = STWBRX
,
1470 [MO_BSWAP
| MO_Q
] = STDBRX
,
1473 static const uint32_t qemu_exts_opc
[4] = {
1474 EXTSB
, EXTSH
, EXTSW
, 0
1477 #if defined (CONFIG_SOFTMMU)
1478 #include "tcg-ldst.inc.c"
1480 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1481 * int mmu_idx, uintptr_t ra)
1483 static void * const qemu_ld_helpers
[16] = {
1484 [MO_UB
] = helper_ret_ldub_mmu
,
1485 [MO_LEUW
] = helper_le_lduw_mmu
,
1486 [MO_LEUL
] = helper_le_ldul_mmu
,
1487 [MO_LEQ
] = helper_le_ldq_mmu
,
1488 [MO_BEUW
] = helper_be_lduw_mmu
,
1489 [MO_BEUL
] = helper_be_ldul_mmu
,
1490 [MO_BEQ
] = helper_be_ldq_mmu
,
1493 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1494 * uintxx_t val, int mmu_idx, uintptr_t ra)
1496 static void * const qemu_st_helpers
[16] = {
1497 [MO_UB
] = helper_ret_stb_mmu
,
1498 [MO_LEUW
] = helper_le_stw_mmu
,
1499 [MO_LEUL
] = helper_le_stl_mmu
,
1500 [MO_LEQ
] = helper_le_stq_mmu
,
1501 [MO_BEUW
] = helper_be_stw_mmu
,
1502 [MO_BEUL
] = helper_be_stl_mmu
,
1503 [MO_BEQ
] = helper_be_stq_mmu
,
1506 /* Perform the TLB load and compare. Places the result of the comparison
1507 in CR7, loads the addend of the TLB into R3, and returns the register
1508 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1510 static TCGReg
tcg_out_tlb_read(TCGContext
*s
, TCGMemOp opc
,
1511 TCGReg addrlo
, TCGReg addrhi
,
1512 int mem_index
, bool is_read
)
1516 ? offsetof(CPUArchState
, tlb_table
[mem_index
][0].addr_read
)
1517 : offsetof(CPUArchState
, tlb_table
[mem_index
][0].addr_write
));
1518 int add_off
= offsetof(CPUArchState
, tlb_table
[mem_index
][0].addend
);
1519 TCGReg base
= TCG_AREG0
;
1520 unsigned s_bits
= opc
& MO_SIZE
;
1521 unsigned a_bits
= get_alignment_bits(opc
);
1523 /* Extract the page index, shifted into place for tlb index. */
1524 if (TCG_TARGET_REG_BITS
== 64) {
1525 if (TARGET_LONG_BITS
== 32) {
1526 /* Zero-extend the address into a place helpful for further use. */
1527 tcg_out_ext32u(s
, TCG_REG_R4
, addrlo
);
1528 addrlo
= TCG_REG_R4
;
1530 tcg_out_rld(s
, RLDICL
, TCG_REG_R3
, addrlo
,
1531 64 - TARGET_PAGE_BITS
, 64 - CPU_TLB_BITS
);
1535 /* Compensate for very large offsets. */
1536 if (add_off
>= 0x8000) {
1537 int low
= (int16_t)cmp_off
;
1538 int high
= cmp_off
- low
;
1539 assert((high
& 0xffff) == 0);
1540 assert(cmp_off
- high
== (int16_t)(cmp_off
- high
));
1541 assert(add_off
- high
== (int16_t)(add_off
- high
));
1542 tcg_out32(s
, ADDIS
| TAI(TCG_REG_TMP1
, base
, high
>> 16));
1543 base
= TCG_REG_TMP1
;
1548 /* Extraction and shifting, part 2. */
1549 if (TCG_TARGET_REG_BITS
== 32 || TARGET_LONG_BITS
== 32) {
1550 tcg_out_rlw(s
, RLWINM
, TCG_REG_R3
, addrlo
,
1551 32 - (TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
),
1552 32 - (CPU_TLB_BITS
+ CPU_TLB_ENTRY_BITS
),
1553 31 - CPU_TLB_ENTRY_BITS
);
1555 tcg_out_shli64(s
, TCG_REG_R3
, TCG_REG_R3
, CPU_TLB_ENTRY_BITS
);
1558 tcg_out32(s
, ADD
| TAB(TCG_REG_R3
, TCG_REG_R3
, base
));
1560 /* Load the tlb comparator. */
1561 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1562 tcg_out_ld(s
, TCG_TYPE_I32
, TCG_REG_R4
, TCG_REG_R3
, cmp_off
);
1563 tcg_out_ld(s
, TCG_TYPE_I32
, TCG_REG_TMP1
, TCG_REG_R3
, cmp_off
+ 4);
1565 tcg_out_ld(s
, TCG_TYPE_TL
, TCG_REG_TMP1
, TCG_REG_R3
, cmp_off
);
1568 /* Load the TLB addend for use on the fast path. Do this asap
1569 to minimize any load use delay. */
1570 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R3
, TCG_REG_R3
, add_off
);
1572 /* Clear the non-page, non-alignment bits from the address */
1573 if (TCG_TARGET_REG_BITS
== 32) {
1574 /* We don't support unaligned accesses on 32-bits.
1575 * Preserve the bottom bits and thus trigger a comparison
1576 * failure on unaligned accesses.
1578 if (a_bits
< s_bits
) {
1581 tcg_out_rlw(s
, RLWINM
, TCG_REG_R0
, addrlo
, 0,
1582 (32 - a_bits
) & 31, 31 - TARGET_PAGE_BITS
);
1586 /* If the access is unaligned, we need to make sure we fail if we
1587 * cross a page boundary. The trick is to add the access size-1
1588 * to the address before masking the low bits. That will make the
1589 * address overflow to the next page if we cross a page boundary,
1590 * which will then force a mismatch of the TLB compare.
1592 if (a_bits
< s_bits
) {
1593 unsigned a_mask
= (1 << a_bits
) - 1;
1594 unsigned s_mask
= (1 << s_bits
) - 1;
1595 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, t
, s_mask
- a_mask
));
1599 /* Mask the address for the requested alignment. */
1600 if (TARGET_LONG_BITS
== 32) {
1601 tcg_out_rlw(s
, RLWINM
, TCG_REG_R0
, t
, 0,
1602 (32 - a_bits
) & 31, 31 - TARGET_PAGE_BITS
);
1603 } else if (a_bits
== 0) {
1604 tcg_out_rld(s
, RLDICR
, TCG_REG_R0
, t
, 0, 63 - TARGET_PAGE_BITS
);
1606 tcg_out_rld(s
, RLDICL
, TCG_REG_R0
, t
,
1607 64 - TARGET_PAGE_BITS
, TARGET_PAGE_BITS
- a_bits
);
1608 tcg_out_rld(s
, RLDICL
, TCG_REG_R0
, TCG_REG_R0
, TARGET_PAGE_BITS
, 0);
1612 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1613 tcg_out_cmp(s
, TCG_COND_EQ
, TCG_REG_R0
, TCG_REG_TMP1
,
1614 0, 7, TCG_TYPE_I32
);
1615 tcg_out_cmp(s
, TCG_COND_EQ
, addrhi
, TCG_REG_R4
, 0, 6, TCG_TYPE_I32
);
1616 tcg_out32(s
, CRAND
| BT(7, CR_EQ
) | BA(6, CR_EQ
) | BB(7, CR_EQ
));
1618 tcg_out_cmp(s
, TCG_COND_EQ
, TCG_REG_R0
, TCG_REG_TMP1
,
1625 /* Record the context of a call to the out of line helper code for the slow
1626 path for a load or store, so that we can later generate the correct
1628 static void add_qemu_ldst_label(TCGContext
*s
, bool is_ld
, TCGMemOpIdx oi
,
1629 TCGReg datalo_reg
, TCGReg datahi_reg
,
1630 TCGReg addrlo_reg
, TCGReg addrhi_reg
,
1631 tcg_insn_unit
*raddr
, tcg_insn_unit
*lptr
)
1633 TCGLabelQemuLdst
*label
= new_ldst_label(s
);
1635 label
->is_ld
= is_ld
;
1637 label
->datalo_reg
= datalo_reg
;
1638 label
->datahi_reg
= datahi_reg
;
1639 label
->addrlo_reg
= addrlo_reg
;
1640 label
->addrhi_reg
= addrhi_reg
;
1641 label
->raddr
= raddr
;
1642 label
->label_ptr
[0] = lptr
;
1645 static void tcg_out_qemu_ld_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*lb
)
1647 TCGMemOpIdx oi
= lb
->oi
;
1648 TCGMemOp opc
= get_memop(oi
);
1649 TCGReg hi
, lo
, arg
= TCG_REG_R3
;
1651 **lb
->label_ptr
|= reloc_pc14_val(*lb
->label_ptr
, s
->code_ptr
);
1653 tcg_out_mov(s
, TCG_TYPE_PTR
, arg
++, TCG_AREG0
);
1655 lo
= lb
->addrlo_reg
;
1656 hi
= lb
->addrhi_reg
;
1657 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1658 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1661 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, hi
);
1662 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, lo
);
1664 /* If the address needed to be zero-extended, we'll have already
1665 placed it in R4. The only remaining case is 64-bit guest. */
1666 tcg_out_mov(s
, TCG_TYPE_TL
, arg
++, lo
);
1669 tcg_out_movi(s
, TCG_TYPE_I32
, arg
++, oi
);
1670 tcg_out32(s
, MFSPR
| RT(arg
) | LR
);
1672 tcg_out_call(s
, qemu_ld_helpers
[opc
& (MO_BSWAP
| MO_SIZE
)]);
1674 lo
= lb
->datalo_reg
;
1675 hi
= lb
->datahi_reg
;
1676 if (TCG_TARGET_REG_BITS
== 32 && (opc
& MO_SIZE
) == MO_64
) {
1677 tcg_out_mov(s
, TCG_TYPE_I32
, lo
, TCG_REG_R4
);
1678 tcg_out_mov(s
, TCG_TYPE_I32
, hi
, TCG_REG_R3
);
1679 } else if (opc
& MO_SIGN
) {
1680 uint32_t insn
= qemu_exts_opc
[opc
& MO_SIZE
];
1681 tcg_out32(s
, insn
| RA(lo
) | RS(TCG_REG_R3
));
1683 tcg_out_mov(s
, TCG_TYPE_REG
, lo
, TCG_REG_R3
);
1686 tcg_out_b(s
, 0, lb
->raddr
);
1689 static void tcg_out_qemu_st_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*lb
)
1691 TCGMemOpIdx oi
= lb
->oi
;
1692 TCGMemOp opc
= get_memop(oi
);
1693 TCGMemOp s_bits
= opc
& MO_SIZE
;
1694 TCGReg hi
, lo
, arg
= TCG_REG_R3
;
1696 **lb
->label_ptr
|= reloc_pc14_val(*lb
->label_ptr
, s
->code_ptr
);
1698 tcg_out_mov(s
, TCG_TYPE_PTR
, arg
++, TCG_AREG0
);
1700 lo
= lb
->addrlo_reg
;
1701 hi
= lb
->addrhi_reg
;
1702 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1703 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1706 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, hi
);
1707 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, lo
);
1709 /* If the address needed to be zero-extended, we'll have already
1710 placed it in R4. The only remaining case is 64-bit guest. */
1711 tcg_out_mov(s
, TCG_TYPE_TL
, arg
++, lo
);
1714 lo
= lb
->datalo_reg
;
1715 hi
= lb
->datahi_reg
;
1716 if (TCG_TARGET_REG_BITS
== 32) {
1719 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1722 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, hi
);
1725 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, lo
);
1728 tcg_out_rlw(s
, RLWINM
, arg
++, lo
, 0, 32 - (8 << s_bits
), 31);
1732 if (s_bits
== MO_64
) {
1733 tcg_out_mov(s
, TCG_TYPE_I64
, arg
++, lo
);
1735 tcg_out_rld(s
, RLDICL
, arg
++, lo
, 0, 64 - (8 << s_bits
));
1739 tcg_out_movi(s
, TCG_TYPE_I32
, arg
++, oi
);
1740 tcg_out32(s
, MFSPR
| RT(arg
) | LR
);
1742 tcg_out_call(s
, qemu_st_helpers
[opc
& (MO_BSWAP
| MO_SIZE
)]);
1744 tcg_out_b(s
, 0, lb
->raddr
);
1746 #endif /* SOFTMMU */
1748 static void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, bool is_64
)
1750 TCGReg datalo
, datahi
, addrlo
, rbase
;
1751 TCGReg addrhi
__attribute__((unused
));
1753 TCGMemOp opc
, s_bits
;
1754 #ifdef CONFIG_SOFTMMU
1756 tcg_insn_unit
*label_ptr
;
1760 datahi
= (TCG_TARGET_REG_BITS
== 32 && is_64
? *args
++ : 0);
1762 addrhi
= (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
? *args
++ : 0);
1764 opc
= get_memop(oi
);
1765 s_bits
= opc
& MO_SIZE
;
1767 #ifdef CONFIG_SOFTMMU
1768 mem_index
= get_mmuidx(oi
);
1769 addrlo
= tcg_out_tlb_read(s
, opc
, addrlo
, addrhi
, mem_index
, true);
1771 /* Load a pointer into the current opcode w/conditional branch-link. */
1772 label_ptr
= s
->code_ptr
;
1773 tcg_out32(s
, BC
| BI(7, CR_EQ
) | BO_COND_FALSE
| LK
);
1776 #else /* !CONFIG_SOFTMMU */
1777 rbase
= guest_base
? TCG_GUEST_BASE_REG
: 0;
1778 if (TCG_TARGET_REG_BITS
> TARGET_LONG_BITS
) {
1779 tcg_out_ext32u(s
, TCG_REG_TMP1
, addrlo
);
1780 addrlo
= TCG_REG_TMP1
;
1784 if (TCG_TARGET_REG_BITS
== 32 && s_bits
== MO_64
) {
1785 if (opc
& MO_BSWAP
) {
1786 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1787 tcg_out32(s
, LWBRX
| TAB(datalo
, rbase
, addrlo
));
1788 tcg_out32(s
, LWBRX
| TAB(datahi
, rbase
, TCG_REG_R0
));
1789 } else if (rbase
!= 0) {
1790 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1791 tcg_out32(s
, LWZX
| TAB(datahi
, rbase
, addrlo
));
1792 tcg_out32(s
, LWZX
| TAB(datalo
, rbase
, TCG_REG_R0
));
1793 } else if (addrlo
== datahi
) {
1794 tcg_out32(s
, LWZ
| TAI(datalo
, addrlo
, 4));
1795 tcg_out32(s
, LWZ
| TAI(datahi
, addrlo
, 0));
1797 tcg_out32(s
, LWZ
| TAI(datahi
, addrlo
, 0));
1798 tcg_out32(s
, LWZ
| TAI(datalo
, addrlo
, 4));
1801 uint32_t insn
= qemu_ldx_opc
[opc
& (MO_BSWAP
| MO_SSIZE
)];
1802 if (!HAVE_ISA_2_06
&& insn
== LDBRX
) {
1803 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1804 tcg_out32(s
, LWBRX
| TAB(datalo
, rbase
, addrlo
));
1805 tcg_out32(s
, LWBRX
| TAB(TCG_REG_R0
, rbase
, TCG_REG_R0
));
1806 tcg_out_rld(s
, RLDIMI
, datalo
, TCG_REG_R0
, 32, 0);
1808 tcg_out32(s
, insn
| TAB(datalo
, rbase
, addrlo
));
1810 insn
= qemu_ldx_opc
[opc
& (MO_SIZE
| MO_BSWAP
)];
1811 tcg_out32(s
, insn
| TAB(datalo
, rbase
, addrlo
));
1812 insn
= qemu_exts_opc
[s_bits
];
1813 tcg_out32(s
, insn
| RA(datalo
) | RS(datalo
));
1817 #ifdef CONFIG_SOFTMMU
1818 add_qemu_ldst_label(s
, true, oi
, datalo
, datahi
, addrlo
, addrhi
,
1819 s
->code_ptr
, label_ptr
);
1823 static void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, bool is_64
)
1825 TCGReg datalo
, datahi
, addrlo
, rbase
;
1826 TCGReg addrhi
__attribute__((unused
));
1828 TCGMemOp opc
, s_bits
;
1829 #ifdef CONFIG_SOFTMMU
1831 tcg_insn_unit
*label_ptr
;
1835 datahi
= (TCG_TARGET_REG_BITS
== 32 && is_64
? *args
++ : 0);
1837 addrhi
= (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
? *args
++ : 0);
1839 opc
= get_memop(oi
);
1840 s_bits
= opc
& MO_SIZE
;
1842 #ifdef CONFIG_SOFTMMU
1843 mem_index
= get_mmuidx(oi
);
1844 addrlo
= tcg_out_tlb_read(s
, opc
, addrlo
, addrhi
, mem_index
, false);
1846 /* Load a pointer into the current opcode w/conditional branch-link. */
1847 label_ptr
= s
->code_ptr
;
1848 tcg_out32(s
, BC
| BI(7, CR_EQ
) | BO_COND_FALSE
| LK
);
1851 #else /* !CONFIG_SOFTMMU */
1852 rbase
= guest_base
? TCG_GUEST_BASE_REG
: 0;
1853 if (TCG_TARGET_REG_BITS
> TARGET_LONG_BITS
) {
1854 tcg_out_ext32u(s
, TCG_REG_TMP1
, addrlo
);
1855 addrlo
= TCG_REG_TMP1
;
1859 if (TCG_TARGET_REG_BITS
== 32 && s_bits
== MO_64
) {
1860 if (opc
& MO_BSWAP
) {
1861 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1862 tcg_out32(s
, STWBRX
| SAB(datalo
, rbase
, addrlo
));
1863 tcg_out32(s
, STWBRX
| SAB(datahi
, rbase
, TCG_REG_R0
));
1864 } else if (rbase
!= 0) {
1865 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1866 tcg_out32(s
, STWX
| SAB(datahi
, rbase
, addrlo
));
1867 tcg_out32(s
, STWX
| SAB(datalo
, rbase
, TCG_REG_R0
));
1869 tcg_out32(s
, STW
| TAI(datahi
, addrlo
, 0));
1870 tcg_out32(s
, STW
| TAI(datalo
, addrlo
, 4));
1873 uint32_t insn
= qemu_stx_opc
[opc
& (MO_BSWAP
| MO_SIZE
)];
1874 if (!HAVE_ISA_2_06
&& insn
== STDBRX
) {
1875 tcg_out32(s
, STWBRX
| SAB(datalo
, rbase
, addrlo
));
1876 tcg_out32(s
, ADDI
| TAI(TCG_REG_TMP1
, addrlo
, 4));
1877 tcg_out_shri64(s
, TCG_REG_R0
, datalo
, 32);
1878 tcg_out32(s
, STWBRX
| SAB(TCG_REG_R0
, rbase
, TCG_REG_TMP1
));
1880 tcg_out32(s
, insn
| SAB(datalo
, rbase
, addrlo
));
1884 #ifdef CONFIG_SOFTMMU
1885 add_qemu_ldst_label(s
, false, oi
, datalo
, datahi
, addrlo
, addrhi
,
1886 s
->code_ptr
, label_ptr
);
1890 static void tcg_out_nop_fill(tcg_insn_unit
*p
, int count
)
1893 for (i
= 0; i
< count
; ++i
) {
1898 /* Parameters for function call generation, used in tcg.c. */
1899 #define TCG_TARGET_STACK_ALIGN 16
1900 #define TCG_TARGET_EXTEND_ARGS 1
1903 # define LINK_AREA_SIZE (6 * SZR)
1904 # define LR_OFFSET (1 * SZR)
1905 # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1906 #elif defined(TCG_TARGET_CALL_DARWIN)
1907 # define LINK_AREA_SIZE (6 * SZR)
1908 # define LR_OFFSET (2 * SZR)
1909 #elif TCG_TARGET_REG_BITS == 64
1910 # if defined(_CALL_ELF) && _CALL_ELF == 2
1911 # define LINK_AREA_SIZE (4 * SZR)
1912 # define LR_OFFSET (1 * SZR)
1914 #else /* TCG_TARGET_REG_BITS == 32 */
1915 # if defined(_CALL_SYSV)
1916 # define LINK_AREA_SIZE (2 * SZR)
1917 # define LR_OFFSET (1 * SZR)
1921 # error "Unhandled abi"
1923 #ifndef TCG_TARGET_CALL_STACK_OFFSET
1924 # define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
1927 #define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1928 #define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
1930 #define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1931 + TCG_STATIC_CALL_ARGS_SIZE \
1932 + CPU_TEMP_BUF_SIZE \
1934 + TCG_TARGET_STACK_ALIGN - 1) \
1935 & -TCG_TARGET_STACK_ALIGN)
1937 #define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
1939 static void tcg_target_qemu_prologue(TCGContext
*s
)
1944 void **desc
= (void **)s
->code_ptr
;
1945 desc
[0] = desc
+ 2; /* entry point */
1946 desc
[1] = 0; /* environment pointer */
1947 s
->code_ptr
= (void *)(desc
+ 2); /* skip over descriptor */
1950 tcg_set_frame(s
, TCG_REG_CALL_STACK
, REG_SAVE_BOT
- CPU_TEMP_BUF_SIZE
,
1954 tcg_out32(s
, MFSPR
| RT(TCG_REG_R0
) | LR
);
1955 tcg_out32(s
, (SZR
== 8 ? STDU
: STWU
)
1956 | SAI(TCG_REG_R1
, TCG_REG_R1
, -FRAME_SIZE
));
1958 for (i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); ++i
) {
1959 tcg_out_st(s
, TCG_TYPE_REG
, tcg_target_callee_save_regs
[i
],
1960 TCG_REG_R1
, REG_SAVE_BOT
+ i
* SZR
);
1962 tcg_out_st(s
, TCG_TYPE_PTR
, TCG_REG_R0
, TCG_REG_R1
, FRAME_SIZE
+LR_OFFSET
);
1964 #ifndef CONFIG_SOFTMMU
1966 tcg_out_movi_int(s
, TCG_TYPE_PTR
, TCG_GUEST_BASE_REG
, guest_base
, true);
1967 tcg_regset_set_reg(s
->reserved_regs
, TCG_GUEST_BASE_REG
);
1971 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_AREG0
, tcg_target_call_iarg_regs
[0]);
1972 tcg_out32(s
, MTSPR
| RS(tcg_target_call_iarg_regs
[1]) | CTR
);
1974 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_REG_TB
, tcg_target_call_iarg_regs
[1]);
1976 tcg_out32(s
, BCCTR
| BO_ALWAYS
);
1979 s
->code_gen_epilogue
= tb_ret_addr
= s
->code_ptr
;
1981 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R0
, TCG_REG_R1
, FRAME_SIZE
+LR_OFFSET
);
1982 for (i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); ++i
) {
1983 tcg_out_ld(s
, TCG_TYPE_REG
, tcg_target_callee_save_regs
[i
],
1984 TCG_REG_R1
, REG_SAVE_BOT
+ i
* SZR
);
1986 tcg_out32(s
, MTSPR
| RS(TCG_REG_R0
) | LR
);
1987 tcg_out32(s
, ADDI
| TAI(TCG_REG_R1
, TCG_REG_R1
, FRAME_SIZE
));
1988 tcg_out32(s
, BCLR
| BO_ALWAYS
);
1991 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
1992 const int *const_args
)
1998 case INDEX_op_exit_tb
:
1999 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R3
, args
[0]);
2000 tcg_out_b(s
, 0, tb_ret_addr
);
2002 case INDEX_op_goto_tb
:
2003 if (s
->tb_jmp_insn_offset
) {
2005 if (TCG_TARGET_REG_BITS
== 64) {
2006 /* Ensure the next insns are 8-byte aligned. */
2007 if ((uintptr_t)s
->code_ptr
& 7) {
2010 s
->tb_jmp_insn_offset
[args
[0]] = tcg_current_code_size(s
);
2011 tcg_out32(s
, ADDIS
| TAI(TCG_REG_TB
, TCG_REG_TB
, 0));
2012 tcg_out32(s
, ADDI
| TAI(TCG_REG_TB
, TCG_REG_TB
, 0));
2014 s
->tb_jmp_insn_offset
[args
[0]] = tcg_current_code_size(s
);
2016 s
->tb_jmp_reset_offset
[args
[0]] = tcg_current_code_size(s
);
2020 /* Indirect jump. */
2021 tcg_debug_assert(s
->tb_jmp_insn_offset
== NULL
);
2022 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_TB
, 0,
2023 (intptr_t)(s
->tb_jmp_insn_offset
+ args
[0]));
2025 tcg_out32(s
, MTSPR
| RS(TCG_REG_TB
) | CTR
);
2026 tcg_out32(s
, BCCTR
| BO_ALWAYS
);
2027 set_jmp_reset_offset(s
, args
[0]);
2029 /* For the unlinked case, need to reset TCG_REG_TB. */
2030 c
= -tcg_current_code_size(s
);
2031 assert(c
== (int16_t)c
);
2032 tcg_out32(s
, ADDI
| TAI(TCG_REG_TB
, TCG_REG_TB
, c
));
2035 case INDEX_op_goto_ptr
:
2036 tcg_out32(s
, MTSPR
| RS(args
[0]) | CTR
);
2038 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_REG_TB
, args
[0]);
2040 tcg_out32(s
, ADDI
| TAI(TCG_REG_R3
, 0, 0));
2041 tcg_out32(s
, BCCTR
| BO_ALWAYS
);
2045 TCGLabel
*l
= arg_label(args
[0]);
2049 insn
|= reloc_pc24_val(s
->code_ptr
, l
->u
.value_ptr
);
2051 tcg_out_reloc(s
, s
->code_ptr
, R_PPC_REL24
, l
, 0);
2056 case INDEX_op_ld8u_i32
:
2057 case INDEX_op_ld8u_i64
:
2058 tcg_out_mem_long(s
, LBZ
, LBZX
, args
[0], args
[1], args
[2]);
2060 case INDEX_op_ld8s_i32
:
2061 case INDEX_op_ld8s_i64
:
2062 tcg_out_mem_long(s
, LBZ
, LBZX
, args
[0], args
[1], args
[2]);
2063 tcg_out32(s
, EXTSB
| RS(args
[0]) | RA(args
[0]));
2065 case INDEX_op_ld16u_i32
:
2066 case INDEX_op_ld16u_i64
:
2067 tcg_out_mem_long(s
, LHZ
, LHZX
, args
[0], args
[1], args
[2]);
2069 case INDEX_op_ld16s_i32
:
2070 case INDEX_op_ld16s_i64
:
2071 tcg_out_mem_long(s
, LHA
, LHAX
, args
[0], args
[1], args
[2]);
2073 case INDEX_op_ld_i32
:
2074 case INDEX_op_ld32u_i64
:
2075 tcg_out_mem_long(s
, LWZ
, LWZX
, args
[0], args
[1], args
[2]);
2077 case INDEX_op_ld32s_i64
:
2078 tcg_out_mem_long(s
, LWA
, LWAX
, args
[0], args
[1], args
[2]);
2080 case INDEX_op_ld_i64
:
2081 tcg_out_mem_long(s
, LD
, LDX
, args
[0], args
[1], args
[2]);
2083 case INDEX_op_st8_i32
:
2084 case INDEX_op_st8_i64
:
2085 tcg_out_mem_long(s
, STB
, STBX
, args
[0], args
[1], args
[2]);
2087 case INDEX_op_st16_i32
:
2088 case INDEX_op_st16_i64
:
2089 tcg_out_mem_long(s
, STH
, STHX
, args
[0], args
[1], args
[2]);
2091 case INDEX_op_st_i32
:
2092 case INDEX_op_st32_i64
:
2093 tcg_out_mem_long(s
, STW
, STWX
, args
[0], args
[1], args
[2]);
2095 case INDEX_op_st_i64
:
2096 tcg_out_mem_long(s
, STD
, STDX
, args
[0], args
[1], args
[2]);
2099 case INDEX_op_add_i32
:
2100 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2101 if (const_args
[2]) {
2103 tcg_out_mem_long(s
, ADDI
, ADD
, a0
, a1
, (int32_t)a2
);
2105 tcg_out32(s
, ADD
| TAB(a0
, a1
, a2
));
2108 case INDEX_op_sub_i32
:
2109 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2110 if (const_args
[1]) {
2111 if (const_args
[2]) {
2112 tcg_out_movi(s
, TCG_TYPE_I32
, a0
, a1
- a2
);
2114 tcg_out32(s
, SUBFIC
| TAI(a0
, a2
, a1
));
2116 } else if (const_args
[2]) {
2120 tcg_out32(s
, SUBF
| TAB(a0
, a2
, a1
));
2124 case INDEX_op_and_i32
:
2125 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2126 if (const_args
[2]) {
2127 tcg_out_andi32(s
, a0
, a1
, a2
);
2129 tcg_out32(s
, AND
| SAB(a1
, a0
, a2
));
2132 case INDEX_op_and_i64
:
2133 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2134 if (const_args
[2]) {
2135 tcg_out_andi64(s
, a0
, a1
, a2
);
2137 tcg_out32(s
, AND
| SAB(a1
, a0
, a2
));
2140 case INDEX_op_or_i64
:
2141 case INDEX_op_or_i32
:
2142 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2143 if (const_args
[2]) {
2144 tcg_out_ori32(s
, a0
, a1
, a2
);
2146 tcg_out32(s
, OR
| SAB(a1
, a0
, a2
));
2149 case INDEX_op_xor_i64
:
2150 case INDEX_op_xor_i32
:
2151 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2152 if (const_args
[2]) {
2153 tcg_out_xori32(s
, a0
, a1
, a2
);
2155 tcg_out32(s
, XOR
| SAB(a1
, a0
, a2
));
2158 case INDEX_op_andc_i32
:
2159 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2160 if (const_args
[2]) {
2161 tcg_out_andi32(s
, a0
, a1
, ~a2
);
2163 tcg_out32(s
, ANDC
| SAB(a1
, a0
, a2
));
2166 case INDEX_op_andc_i64
:
2167 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2168 if (const_args
[2]) {
2169 tcg_out_andi64(s
, a0
, a1
, ~a2
);
2171 tcg_out32(s
, ANDC
| SAB(a1
, a0
, a2
));
2174 case INDEX_op_orc_i32
:
2175 if (const_args
[2]) {
2176 tcg_out_ori32(s
, args
[0], args
[1], ~args
[2]);
2180 case INDEX_op_orc_i64
:
2181 tcg_out32(s
, ORC
| SAB(args
[1], args
[0], args
[2]));
2183 case INDEX_op_eqv_i32
:
2184 if (const_args
[2]) {
2185 tcg_out_xori32(s
, args
[0], args
[1], ~args
[2]);
2189 case INDEX_op_eqv_i64
:
2190 tcg_out32(s
, EQV
| SAB(args
[1], args
[0], args
[2]));
2192 case INDEX_op_nand_i32
:
2193 case INDEX_op_nand_i64
:
2194 tcg_out32(s
, NAND
| SAB(args
[1], args
[0], args
[2]));
2196 case INDEX_op_nor_i32
:
2197 case INDEX_op_nor_i64
:
2198 tcg_out32(s
, NOR
| SAB(args
[1], args
[0], args
[2]));
2201 case INDEX_op_clz_i32
:
2202 tcg_out_cntxz(s
, TCG_TYPE_I32
, CNTLZW
, args
[0], args
[1],
2203 args
[2], const_args
[2]);
2205 case INDEX_op_ctz_i32
:
2206 tcg_out_cntxz(s
, TCG_TYPE_I32
, CNTTZW
, args
[0], args
[1],
2207 args
[2], const_args
[2]);
2209 case INDEX_op_ctpop_i32
:
2210 tcg_out32(s
, CNTPOPW
| SAB(args
[1], args
[0], 0));
2213 case INDEX_op_clz_i64
:
2214 tcg_out_cntxz(s
, TCG_TYPE_I64
, CNTLZD
, args
[0], args
[1],
2215 args
[2], const_args
[2]);
2217 case INDEX_op_ctz_i64
:
2218 tcg_out_cntxz(s
, TCG_TYPE_I64
, CNTTZD
, args
[0], args
[1],
2219 args
[2], const_args
[2]);
2221 case INDEX_op_ctpop_i64
:
2222 tcg_out32(s
, CNTPOPD
| SAB(args
[1], args
[0], 0));
2225 case INDEX_op_mul_i32
:
2226 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2227 if (const_args
[2]) {
2228 tcg_out32(s
, MULLI
| TAI(a0
, a1
, a2
));
2230 tcg_out32(s
, MULLW
| TAB(a0
, a1
, a2
));
2234 case INDEX_op_div_i32
:
2235 tcg_out32(s
, DIVW
| TAB(args
[0], args
[1], args
[2]));
2238 case INDEX_op_divu_i32
:
2239 tcg_out32(s
, DIVWU
| TAB(args
[0], args
[1], args
[2]));
2242 case INDEX_op_shl_i32
:
2243 if (const_args
[2]) {
2244 tcg_out_shli32(s
, args
[0], args
[1], args
[2]);
2246 tcg_out32(s
, SLW
| SAB(args
[1], args
[0], args
[2]));
2249 case INDEX_op_shr_i32
:
2250 if (const_args
[2]) {
2251 tcg_out_shri32(s
, args
[0], args
[1], args
[2]);
2253 tcg_out32(s
, SRW
| SAB(args
[1], args
[0], args
[2]));
2256 case INDEX_op_sar_i32
:
2257 if (const_args
[2]) {
2258 tcg_out32(s
, SRAWI
| RS(args
[1]) | RA(args
[0]) | SH(args
[2]));
2260 tcg_out32(s
, SRAW
| SAB(args
[1], args
[0], args
[2]));
2263 case INDEX_op_rotl_i32
:
2264 if (const_args
[2]) {
2265 tcg_out_rlw(s
, RLWINM
, args
[0], args
[1], args
[2], 0, 31);
2267 tcg_out32(s
, RLWNM
| SAB(args
[1], args
[0], args
[2])
2271 case INDEX_op_rotr_i32
:
2272 if (const_args
[2]) {
2273 tcg_out_rlw(s
, RLWINM
, args
[0], args
[1], 32 - args
[2], 0, 31);
2275 tcg_out32(s
, SUBFIC
| TAI(TCG_REG_R0
, args
[2], 32));
2276 tcg_out32(s
, RLWNM
| SAB(args
[1], args
[0], TCG_REG_R0
)
2281 case INDEX_op_brcond_i32
:
2282 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
2283 arg_label(args
[3]), TCG_TYPE_I32
);
2285 case INDEX_op_brcond_i64
:
2286 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
2287 arg_label(args
[3]), TCG_TYPE_I64
);
2289 case INDEX_op_brcond2_i32
:
2290 tcg_out_brcond2(s
, args
, const_args
);
2293 case INDEX_op_neg_i32
:
2294 case INDEX_op_neg_i64
:
2295 tcg_out32(s
, NEG
| RT(args
[0]) | RA(args
[1]));
2298 case INDEX_op_not_i32
:
2299 case INDEX_op_not_i64
:
2300 tcg_out32(s
, NOR
| SAB(args
[1], args
[0], args
[1]));
2303 case INDEX_op_add_i64
:
2304 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2305 if (const_args
[2]) {
2307 tcg_out_mem_long(s
, ADDI
, ADD
, a0
, a1
, a2
);
2309 tcg_out32(s
, ADD
| TAB(a0
, a1
, a2
));
2312 case INDEX_op_sub_i64
:
2313 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2314 if (const_args
[1]) {
2315 if (const_args
[2]) {
2316 tcg_out_movi(s
, TCG_TYPE_I64
, a0
, a1
- a2
);
2318 tcg_out32(s
, SUBFIC
| TAI(a0
, a2
, a1
));
2320 } else if (const_args
[2]) {
2324 tcg_out32(s
, SUBF
| TAB(a0
, a2
, a1
));
2328 case INDEX_op_shl_i64
:
2329 if (const_args
[2]) {
2330 tcg_out_shli64(s
, args
[0], args
[1], args
[2]);
2332 tcg_out32(s
, SLD
| SAB(args
[1], args
[0], args
[2]));
2335 case INDEX_op_shr_i64
:
2336 if (const_args
[2]) {
2337 tcg_out_shri64(s
, args
[0], args
[1], args
[2]);
2339 tcg_out32(s
, SRD
| SAB(args
[1], args
[0], args
[2]));
2342 case INDEX_op_sar_i64
:
2343 if (const_args
[2]) {
2344 int sh
= SH(args
[2] & 0x1f) | (((args
[2] >> 5) & 1) << 1);
2345 tcg_out32(s
, SRADI
| RA(args
[0]) | RS(args
[1]) | sh
);
2347 tcg_out32(s
, SRAD
| SAB(args
[1], args
[0], args
[2]));
2350 case INDEX_op_rotl_i64
:
2351 if (const_args
[2]) {
2352 tcg_out_rld(s
, RLDICL
, args
[0], args
[1], args
[2], 0);
2354 tcg_out32(s
, RLDCL
| SAB(args
[1], args
[0], args
[2]) | MB64(0));
2357 case INDEX_op_rotr_i64
:
2358 if (const_args
[2]) {
2359 tcg_out_rld(s
, RLDICL
, args
[0], args
[1], 64 - args
[2], 0);
2361 tcg_out32(s
, SUBFIC
| TAI(TCG_REG_R0
, args
[2], 64));
2362 tcg_out32(s
, RLDCL
| SAB(args
[1], args
[0], TCG_REG_R0
) | MB64(0));
2366 case INDEX_op_mul_i64
:
2367 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2368 if (const_args
[2]) {
2369 tcg_out32(s
, MULLI
| TAI(a0
, a1
, a2
));
2371 tcg_out32(s
, MULLD
| TAB(a0
, a1
, a2
));
2374 case INDEX_op_div_i64
:
2375 tcg_out32(s
, DIVD
| TAB(args
[0], args
[1], args
[2]));
2377 case INDEX_op_divu_i64
:
2378 tcg_out32(s
, DIVDU
| TAB(args
[0], args
[1], args
[2]));
2381 case INDEX_op_qemu_ld_i32
:
2382 tcg_out_qemu_ld(s
, args
, false);
2384 case INDEX_op_qemu_ld_i64
:
2385 tcg_out_qemu_ld(s
, args
, true);
2387 case INDEX_op_qemu_st_i32
:
2388 tcg_out_qemu_st(s
, args
, false);
2390 case INDEX_op_qemu_st_i64
:
2391 tcg_out_qemu_st(s
, args
, true);
2394 case INDEX_op_ext8s_i32
:
2395 case INDEX_op_ext8s_i64
:
2398 case INDEX_op_ext16s_i32
:
2399 case INDEX_op_ext16s_i64
:
2402 case INDEX_op_ext_i32_i64
:
2403 case INDEX_op_ext32s_i64
:
2407 tcg_out32(s
, c
| RS(args
[1]) | RA(args
[0]));
2409 case INDEX_op_extu_i32_i64
:
2410 tcg_out_ext32u(s
, args
[0], args
[1]);
2413 case INDEX_op_setcond_i32
:
2414 tcg_out_setcond(s
, TCG_TYPE_I32
, args
[3], args
[0], args
[1], args
[2],
2417 case INDEX_op_setcond_i64
:
2418 tcg_out_setcond(s
, TCG_TYPE_I64
, args
[3], args
[0], args
[1], args
[2],
2421 case INDEX_op_setcond2_i32
:
2422 tcg_out_setcond2(s
, args
, const_args
);
2425 case INDEX_op_bswap16_i32
:
2426 case INDEX_op_bswap16_i64
:
2427 a0
= args
[0], a1
= args
[1];
2430 /* a0 = (a1 r<< 24) & 0xff # 000c */
2431 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 24, 24, 31);
2432 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2433 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 8, 16, 23);
2435 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2436 tcg_out_rlw(s
, RLWINM
, TCG_REG_R0
, a1
, 8, 16, 23);
2437 /* a0 = (a1 r<< 24) & 0xff # 000c */
2438 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 24, 24, 31);
2439 /* a0 = a0 | r0 # 00dc */
2440 tcg_out32(s
, OR
| SAB(TCG_REG_R0
, a0
, a0
));
2444 case INDEX_op_bswap32_i32
:
2445 case INDEX_op_bswap32_i64
:
2446 /* Stolen from gcc's builtin_bswap32 */
2448 a0
= args
[0] == a1
? TCG_REG_R0
: args
[0];
2450 /* a1 = args[1] # abcd */
2451 /* a0 = rotate_left (a1, 8) # bcda */
2452 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 8, 0, 31);
2453 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2454 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 0, 7);
2455 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2456 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 16, 23);
2458 if (a0
== TCG_REG_R0
) {
2459 tcg_out_mov(s
, TCG_TYPE_REG
, args
[0], a0
);
2463 case INDEX_op_bswap64_i64
:
2464 a0
= args
[0], a1
= args
[1], a2
= TCG_REG_R0
;
2470 /* a1 = # abcd efgh */
2471 /* a0 = rl32(a1, 8) # 0000 fghe */
2472 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 8, 0, 31);
2473 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2474 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 0, 7);
2475 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2476 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 16, 23);
2478 /* a0 = rl64(a0, 32) # hgfe 0000 */
2479 /* a2 = rl64(a1, 32) # efgh abcd */
2480 tcg_out_rld(s
, RLDICL
, a0
, a0
, 32, 0);
2481 tcg_out_rld(s
, RLDICL
, a2
, a1
, 32, 0);
2483 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2484 tcg_out_rlw(s
, RLWIMI
, a0
, a2
, 8, 0, 31);
2485 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2486 tcg_out_rlw(s
, RLWIMI
, a0
, a2
, 24, 0, 7);
2487 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2488 tcg_out_rlw(s
, RLWIMI
, a0
, a2
, 24, 16, 23);
2491 tcg_out_mov(s
, TCG_TYPE_REG
, args
[0], a0
);
2495 case INDEX_op_deposit_i32
:
2496 if (const_args
[2]) {
2497 uint32_t mask
= ((2u << (args
[4] - 1)) - 1) << args
[3];
2498 tcg_out_andi32(s
, args
[0], args
[0], ~mask
);
2500 tcg_out_rlw(s
, RLWIMI
, args
[0], args
[2], args
[3],
2501 32 - args
[3] - args
[4], 31 - args
[3]);
2504 case INDEX_op_deposit_i64
:
2505 if (const_args
[2]) {
2506 uint64_t mask
= ((2ull << (args
[4] - 1)) - 1) << args
[3];
2507 tcg_out_andi64(s
, args
[0], args
[0], ~mask
);
2509 tcg_out_rld(s
, RLDIMI
, args
[0], args
[2], args
[3],
2510 64 - args
[3] - args
[4]);
2514 case INDEX_op_extract_i32
:
2515 tcg_out_rlw(s
, RLWINM
, args
[0], args
[1],
2516 32 - args
[2], 32 - args
[3], 31);
2518 case INDEX_op_extract_i64
:
2519 tcg_out_rld(s
, RLDICL
, args
[0], args
[1], 64 - args
[2], 64 - args
[3]);
2522 case INDEX_op_movcond_i32
:
2523 tcg_out_movcond(s
, TCG_TYPE_I32
, args
[5], args
[0], args
[1], args
[2],
2524 args
[3], args
[4], const_args
[2]);
2526 case INDEX_op_movcond_i64
:
2527 tcg_out_movcond(s
, TCG_TYPE_I64
, args
[5], args
[0], args
[1], args
[2],
2528 args
[3], args
[4], const_args
[2]);
2531 #if TCG_TARGET_REG_BITS == 64
2532 case INDEX_op_add2_i64
:
2534 case INDEX_op_add2_i32
:
2536 /* Note that the CA bit is defined based on the word size of the
2537 environment. So in 64-bit mode it's always carry-out of bit 63.
2538 The fallback code using deposit works just as well for 32-bit. */
2539 a0
= args
[0], a1
= args
[1];
2540 if (a0
== args
[3] || (!const_args
[5] && a0
== args
[5])) {
2543 if (const_args
[4]) {
2544 tcg_out32(s
, ADDIC
| TAI(a0
, args
[2], args
[4]));
2546 tcg_out32(s
, ADDC
| TAB(a0
, args
[2], args
[4]));
2548 if (const_args
[5]) {
2549 tcg_out32(s
, (args
[5] ? ADDME
: ADDZE
) | RT(a1
) | RA(args
[3]));
2551 tcg_out32(s
, ADDE
| TAB(a1
, args
[3], args
[5]));
2553 if (a0
!= args
[0]) {
2554 tcg_out_mov(s
, TCG_TYPE_REG
, args
[0], a0
);
2558 #if TCG_TARGET_REG_BITS == 64
2559 case INDEX_op_sub2_i64
:
2561 case INDEX_op_sub2_i32
:
2563 a0
= args
[0], a1
= args
[1];
2564 if (a0
== args
[5] || (!const_args
[3] && a0
== args
[3])) {
2567 if (const_args
[2]) {
2568 tcg_out32(s
, SUBFIC
| TAI(a0
, args
[4], args
[2]));
2570 tcg_out32(s
, SUBFC
| TAB(a0
, args
[4], args
[2]));
2572 if (const_args
[3]) {
2573 tcg_out32(s
, (args
[3] ? SUBFME
: SUBFZE
) | RT(a1
) | RA(args
[5]));
2575 tcg_out32(s
, SUBFE
| TAB(a1
, args
[5], args
[3]));
2577 if (a0
!= args
[0]) {
2578 tcg_out_mov(s
, TCG_TYPE_REG
, args
[0], a0
);
2582 case INDEX_op_muluh_i32
:
2583 tcg_out32(s
, MULHWU
| TAB(args
[0], args
[1], args
[2]));
2585 case INDEX_op_mulsh_i32
:
2586 tcg_out32(s
, MULHW
| TAB(args
[0], args
[1], args
[2]));
2588 case INDEX_op_muluh_i64
:
2589 tcg_out32(s
, MULHDU
| TAB(args
[0], args
[1], args
[2]));
2591 case INDEX_op_mulsh_i64
:
2592 tcg_out32(s
, MULHD
| TAB(args
[0], args
[1], args
[2]));
2596 tcg_out_mb(s
, args
[0]);
2599 case INDEX_op_mov_i32
: /* Always emitted via tcg_out_mov. */
2600 case INDEX_op_mov_i64
:
2601 case INDEX_op_movi_i32
: /* Always emitted via tcg_out_movi. */
2602 case INDEX_op_movi_i64
:
2603 case INDEX_op_call
: /* Always emitted via tcg_out_call. */
2609 static const TCGTargetOpDef
*tcg_target_op_def(TCGOpcode op
)
2611 static const TCGTargetOpDef r
= { .args_ct_str
= { "r" } };
2612 static const TCGTargetOpDef r_r
= { .args_ct_str
= { "r", "r" } };
2613 static const TCGTargetOpDef r_L
= { .args_ct_str
= { "r", "L" } };
2614 static const TCGTargetOpDef S_S
= { .args_ct_str
= { "S", "S" } };
2615 static const TCGTargetOpDef r_ri
= { .args_ct_str
= { "r", "ri" } };
2616 static const TCGTargetOpDef r_r_r
= { .args_ct_str
= { "r", "r", "r" } };
2617 static const TCGTargetOpDef r_L_L
= { .args_ct_str
= { "r", "L", "L" } };
2618 static const TCGTargetOpDef L_L_L
= { .args_ct_str
= { "L", "L", "L" } };
2619 static const TCGTargetOpDef S_S_S
= { .args_ct_str
= { "S", "S", "S" } };
2620 static const TCGTargetOpDef r_r_ri
= { .args_ct_str
= { "r", "r", "ri" } };
2621 static const TCGTargetOpDef r_r_rI
= { .args_ct_str
= { "r", "r", "rI" } };
2622 static const TCGTargetOpDef r_r_rT
= { .args_ct_str
= { "r", "r", "rT" } };
2623 static const TCGTargetOpDef r_r_rU
= { .args_ct_str
= { "r", "r", "rU" } };
2624 static const TCGTargetOpDef r_rI_ri
2625 = { .args_ct_str
= { "r", "rI", "ri" } };
2626 static const TCGTargetOpDef r_rI_rT
2627 = { .args_ct_str
= { "r", "rI", "rT" } };
2628 static const TCGTargetOpDef r_r_rZW
2629 = { .args_ct_str
= { "r", "r", "rZW" } };
2630 static const TCGTargetOpDef L_L_L_L
2631 = { .args_ct_str
= { "L", "L", "L", "L" } };
2632 static const TCGTargetOpDef S_S_S_S
2633 = { .args_ct_str
= { "S", "S", "S", "S" } };
2634 static const TCGTargetOpDef movc
2635 = { .args_ct_str
= { "r", "r", "ri", "rZ", "rZ" } };
2636 static const TCGTargetOpDef dep
2637 = { .args_ct_str
= { "r", "0", "rZ" } };
2638 static const TCGTargetOpDef br2
2639 = { .args_ct_str
= { "r", "r", "ri", "ri" } };
2640 static const TCGTargetOpDef setc2
2641 = { .args_ct_str
= { "r", "r", "r", "ri", "ri" } };
2642 static const TCGTargetOpDef add2
2643 = { .args_ct_str
= { "r", "r", "r", "r", "rI", "rZM" } };
2644 static const TCGTargetOpDef sub2
2645 = { .args_ct_str
= { "r", "r", "rI", "rZM", "r", "r" } };
2648 case INDEX_op_goto_ptr
:
2651 case INDEX_op_ld8u_i32
:
2652 case INDEX_op_ld8s_i32
:
2653 case INDEX_op_ld16u_i32
:
2654 case INDEX_op_ld16s_i32
:
2655 case INDEX_op_ld_i32
:
2656 case INDEX_op_st8_i32
:
2657 case INDEX_op_st16_i32
:
2658 case INDEX_op_st_i32
:
2659 case INDEX_op_ctpop_i32
:
2660 case INDEX_op_neg_i32
:
2661 case INDEX_op_not_i32
:
2662 case INDEX_op_ext8s_i32
:
2663 case INDEX_op_ext16s_i32
:
2664 case INDEX_op_bswap16_i32
:
2665 case INDEX_op_bswap32_i32
:
2666 case INDEX_op_extract_i32
:
2667 case INDEX_op_ld8u_i64
:
2668 case INDEX_op_ld8s_i64
:
2669 case INDEX_op_ld16u_i64
:
2670 case INDEX_op_ld16s_i64
:
2671 case INDEX_op_ld32u_i64
:
2672 case INDEX_op_ld32s_i64
:
2673 case INDEX_op_ld_i64
:
2674 case INDEX_op_st8_i64
:
2675 case INDEX_op_st16_i64
:
2676 case INDEX_op_st32_i64
:
2677 case INDEX_op_st_i64
:
2678 case INDEX_op_ctpop_i64
:
2679 case INDEX_op_neg_i64
:
2680 case INDEX_op_not_i64
:
2681 case INDEX_op_ext8s_i64
:
2682 case INDEX_op_ext16s_i64
:
2683 case INDEX_op_ext32s_i64
:
2684 case INDEX_op_ext_i32_i64
:
2685 case INDEX_op_extu_i32_i64
:
2686 case INDEX_op_bswap16_i64
:
2687 case INDEX_op_bswap32_i64
:
2688 case INDEX_op_bswap64_i64
:
2689 case INDEX_op_extract_i64
:
2692 case INDEX_op_add_i32
:
2693 case INDEX_op_and_i32
:
2694 case INDEX_op_or_i32
:
2695 case INDEX_op_xor_i32
:
2696 case INDEX_op_andc_i32
:
2697 case INDEX_op_orc_i32
:
2698 case INDEX_op_eqv_i32
:
2699 case INDEX_op_shl_i32
:
2700 case INDEX_op_shr_i32
:
2701 case INDEX_op_sar_i32
:
2702 case INDEX_op_rotl_i32
:
2703 case INDEX_op_rotr_i32
:
2704 case INDEX_op_setcond_i32
:
2705 case INDEX_op_and_i64
:
2706 case INDEX_op_andc_i64
:
2707 case INDEX_op_shl_i64
:
2708 case INDEX_op_shr_i64
:
2709 case INDEX_op_sar_i64
:
2710 case INDEX_op_rotl_i64
:
2711 case INDEX_op_rotr_i64
:
2712 case INDEX_op_setcond_i64
:
2714 case INDEX_op_mul_i32
:
2715 case INDEX_op_mul_i64
:
2717 case INDEX_op_div_i32
:
2718 case INDEX_op_divu_i32
:
2719 case INDEX_op_nand_i32
:
2720 case INDEX_op_nor_i32
:
2721 case INDEX_op_muluh_i32
:
2722 case INDEX_op_mulsh_i32
:
2723 case INDEX_op_orc_i64
:
2724 case INDEX_op_eqv_i64
:
2725 case INDEX_op_nand_i64
:
2726 case INDEX_op_nor_i64
:
2727 case INDEX_op_div_i64
:
2728 case INDEX_op_divu_i64
:
2729 case INDEX_op_mulsh_i64
:
2730 case INDEX_op_muluh_i64
:
2732 case INDEX_op_sub_i32
:
2734 case INDEX_op_add_i64
:
2736 case INDEX_op_or_i64
:
2737 case INDEX_op_xor_i64
:
2739 case INDEX_op_sub_i64
:
2741 case INDEX_op_clz_i32
:
2742 case INDEX_op_ctz_i32
:
2743 case INDEX_op_clz_i64
:
2744 case INDEX_op_ctz_i64
:
2747 case INDEX_op_brcond_i32
:
2748 case INDEX_op_brcond_i64
:
2751 case INDEX_op_movcond_i32
:
2752 case INDEX_op_movcond_i64
:
2754 case INDEX_op_deposit_i32
:
2755 case INDEX_op_deposit_i64
:
2757 case INDEX_op_brcond2_i32
:
2759 case INDEX_op_setcond2_i32
:
2761 case INDEX_op_add2_i64
:
2762 case INDEX_op_add2_i32
:
2764 case INDEX_op_sub2_i64
:
2765 case INDEX_op_sub2_i32
:
2768 case INDEX_op_qemu_ld_i32
:
2769 return (TCG_TARGET_REG_BITS
== 64 || TARGET_LONG_BITS
== 32
2771 case INDEX_op_qemu_st_i32
:
2772 return (TCG_TARGET_REG_BITS
== 64 || TARGET_LONG_BITS
== 32
2774 case INDEX_op_qemu_ld_i64
:
2775 return (TCG_TARGET_REG_BITS
== 64 ? &r_L
2776 : TARGET_LONG_BITS
== 32 ? &L_L_L
: &L_L_L_L
);
2777 case INDEX_op_qemu_st_i64
:
2778 return (TCG_TARGET_REG_BITS
== 64 ? &S_S
2779 : TARGET_LONG_BITS
== 32 ? &S_S_S
: &S_S_S_S
);
2786 static void tcg_target_init(TCGContext
*s
)
2788 unsigned long hwcap
= qemu_getauxval(AT_HWCAP
);
2789 unsigned long hwcap2
= qemu_getauxval(AT_HWCAP2
);
2791 if (hwcap
& PPC_FEATURE_ARCH_2_06
) {
2792 have_isa_2_06
= true;
2794 #ifdef PPC_FEATURE2_ARCH_3_00
2795 if (hwcap2
& PPC_FEATURE2_ARCH_3_00
) {
2796 have_isa_3_00
= true;
2800 tcg_target_available_regs
[TCG_TYPE_I32
] = 0xffffffff;
2801 tcg_target_available_regs
[TCG_TYPE_I64
] = 0xffffffff;
2803 tcg_target_call_clobber_regs
= 0;
2804 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R0
);
2805 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R2
);
2806 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R3
);
2807 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R4
);
2808 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R5
);
2809 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R6
);
2810 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R7
);
2811 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R8
);
2812 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R9
);
2813 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R10
);
2814 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R11
);
2815 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R12
);
2817 s
->reserved_regs
= 0;
2818 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R0
); /* tcg temp */
2819 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R1
); /* stack pointer */
2820 #if defined(_CALL_SYSV)
2821 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R2
); /* toc pointer */
2823 #if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
2824 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R13
); /* thread pointer */
2826 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_TMP1
); /* mem temp */
2828 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_TB
); /* tb->tc_ptr */
2835 DebugFrameFDEHeader fde
;
2836 uint8_t fde_def_cfa
[4];
2837 uint8_t fde_reg_ofs
[ARRAY_SIZE(tcg_target_callee_save_regs
) * 2 + 3];
2840 /* We're expecting a 2 byte uleb128 encoded value. */
2841 QEMU_BUILD_BUG_ON(FRAME_SIZE
>= (1 << 14));
2843 #if TCG_TARGET_REG_BITS == 64
2844 # define ELF_HOST_MACHINE EM_PPC64
2846 # define ELF_HOST_MACHINE EM_PPC
2849 static DebugFrame debug_frame
= {
2850 .cie
.len
= sizeof(DebugFrameCIE
)-4, /* length after .len member */
2853 .cie
.code_align
= 1,
2854 .cie
.data_align
= (-SZR
& 0x7f), /* sleb128 -SZR */
2855 .cie
.return_column
= 65,
2857 /* Total FDE size does not include the "len" member. */
2858 .fde
.len
= sizeof(DebugFrame
) - offsetof(DebugFrame
, fde
.cie_offset
),
2861 12, TCG_REG_R1
, /* DW_CFA_def_cfa r1, ... */
2862 (FRAME_SIZE
& 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2866 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2867 0x11, 65, (LR_OFFSET
/ -SZR
) & 0x7f,
2871 void tcg_register_jit(void *buf
, size_t buf_size
)
2873 uint8_t *p
= &debug_frame
.fde_reg_ofs
[3];
2876 for (i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); ++i
, p
+= 2) {
2877 p
[0] = 0x80 + tcg_target_callee_save_regs
[i
];
2878 p
[1] = (FRAME_SIZE
- (REG_SAVE_BOT
+ i
* SZR
)) / SZR
;
2881 debug_frame
.fde
.func_start
= (uintptr_t)buf
;
2882 debug_frame
.fde
.func_len
= buf_size
;
2884 tcg_register_jit_int(buf
, buf_size
, &debug_frame
, sizeof(debug_frame
));
2886 #endif /* __ELF__ */
2888 void flush_icache_range(uintptr_t start
, uintptr_t stop
)
2890 uintptr_t p
, start1
, stop1
;
2891 size_t dsize
= qemu_dcache_linesize
;
2892 size_t isize
= qemu_icache_linesize
;
2894 start1
= start
& ~(dsize
- 1);
2895 stop1
= (stop
+ dsize
- 1) & ~(dsize
- 1);
2896 for (p
= start1
; p
< stop1
; p
+= dsize
) {
2897 asm volatile ("dcbst 0,%0" : : "r"(p
) : "memory");
2899 asm volatile ("sync" : : : "memory");
2901 start
&= start
& ~(isize
- 1);
2902 stop1
= (stop
+ isize
- 1) & ~(isize
- 1);
2903 for (p
= start1
; p
< stop1
; p
+= isize
) {
2904 asm volatile ("icbi 0,%0" : : "r"(p
) : "memory");
2906 asm volatile ("sync" : : : "memory");
2907 asm volatile ("isync" : : : "memory");