2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #ifndef I386_TCG_TARGET_H
26 #define I386_TCG_TARGET_H
28 #include "host/cpuinfo.h"
30 #define TCG_TARGET_INSN_UNIT_SIZE 1
33 # define TCG_TARGET_NB_REGS 32
34 # define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB)
36 # define TCG_TARGET_NB_REGS 24
37 # define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX
50 /* 64-bit registers; always define the symbols to avoid
51 too much if-deffing. */
70 /* 64-bit registers; likewise always define. */
80 TCG_REG_RAX
= TCG_REG_EAX
,
81 TCG_REG_RCX
= TCG_REG_ECX
,
82 TCG_REG_RDX
= TCG_REG_EDX
,
83 TCG_REG_RBX
= TCG_REG_EBX
,
84 TCG_REG_RSP
= TCG_REG_ESP
,
85 TCG_REG_RBP
= TCG_REG_EBP
,
86 TCG_REG_RSI
= TCG_REG_ESI
,
87 TCG_REG_RDI
= TCG_REG_EDI
,
89 TCG_AREG0
= TCG_REG_EBP
,
90 TCG_REG_CALL_STACK
= TCG_REG_ESP
93 /* used for function call generation */
94 #define TCG_TARGET_STACK_ALIGN 16
96 #define TCG_TARGET_CALL_STACK_OFFSET 32
98 #define TCG_TARGET_CALL_STACK_OFFSET 0
100 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL
101 #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
103 # define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF
104 # define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_VEC
105 #elif TCG_TARGET_REG_BITS == 64
106 # define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
107 # define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
109 # define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
110 # define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF
113 #define have_bmi1 (cpuinfo & CPUINFO_BMI1)
114 #define have_popcnt (cpuinfo & CPUINFO_POPCNT)
115 #define have_avx1 (cpuinfo & CPUINFO_AVX1)
116 #define have_avx2 (cpuinfo & CPUINFO_AVX2)
117 #define have_movbe (cpuinfo & CPUINFO_MOVBE)
120 * There are interesting instructions in AVX512, so long as we have AVX512VL,
121 * which indicates support for EVEX on sizes smaller than 512 bits.
123 #define have_avx512vl ((cpuinfo & CPUINFO_AVX512VL) && \
124 (cpuinfo & CPUINFO_AVX512F))
125 #define have_avx512bw ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl)
126 #define have_avx512dq ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl)
127 #define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl)
129 /* optional instructions */
130 #define TCG_TARGET_HAS_div2_i32 1
131 #define TCG_TARGET_HAS_rot_i32 1
132 #define TCG_TARGET_HAS_ext8s_i32 1
133 #define TCG_TARGET_HAS_ext16s_i32 1
134 #define TCG_TARGET_HAS_ext8u_i32 1
135 #define TCG_TARGET_HAS_ext16u_i32 1
136 #define TCG_TARGET_HAS_bswap16_i32 1
137 #define TCG_TARGET_HAS_bswap32_i32 1
138 #define TCG_TARGET_HAS_not_i32 1
139 #define TCG_TARGET_HAS_andc_i32 have_bmi1
140 #define TCG_TARGET_HAS_orc_i32 0
141 #define TCG_TARGET_HAS_eqv_i32 0
142 #define TCG_TARGET_HAS_nand_i32 0
143 #define TCG_TARGET_HAS_nor_i32 0
144 #define TCG_TARGET_HAS_clz_i32 1
145 #define TCG_TARGET_HAS_ctz_i32 1
146 #define TCG_TARGET_HAS_ctpop_i32 have_popcnt
147 #define TCG_TARGET_HAS_deposit_i32 1
148 #define TCG_TARGET_HAS_extract_i32 1
149 #define TCG_TARGET_HAS_sextract_i32 1
150 #define TCG_TARGET_HAS_extract2_i32 1
151 #define TCG_TARGET_HAS_negsetcond_i32 1
152 #define TCG_TARGET_HAS_add2_i32 1
153 #define TCG_TARGET_HAS_sub2_i32 1
154 #define TCG_TARGET_HAS_mulu2_i32 1
155 #define TCG_TARGET_HAS_muls2_i32 1
156 #define TCG_TARGET_HAS_muluh_i32 0
157 #define TCG_TARGET_HAS_mulsh_i32 0
159 #if TCG_TARGET_REG_BITS == 64
160 /* Keep 32-bit values zero-extended in a register. */
161 #define TCG_TARGET_HAS_extr_i64_i32 1
162 #define TCG_TARGET_HAS_div2_i64 1
163 #define TCG_TARGET_HAS_rot_i64 1
164 #define TCG_TARGET_HAS_ext8s_i64 1
165 #define TCG_TARGET_HAS_ext16s_i64 1
166 #define TCG_TARGET_HAS_ext32s_i64 1
167 #define TCG_TARGET_HAS_ext8u_i64 1
168 #define TCG_TARGET_HAS_ext16u_i64 1
169 #define TCG_TARGET_HAS_ext32u_i64 1
170 #define TCG_TARGET_HAS_bswap16_i64 1
171 #define TCG_TARGET_HAS_bswap32_i64 1
172 #define TCG_TARGET_HAS_bswap64_i64 1
173 #define TCG_TARGET_HAS_not_i64 1
174 #define TCG_TARGET_HAS_andc_i64 have_bmi1
175 #define TCG_TARGET_HAS_orc_i64 0
176 #define TCG_TARGET_HAS_eqv_i64 0
177 #define TCG_TARGET_HAS_nand_i64 0
178 #define TCG_TARGET_HAS_nor_i64 0
179 #define TCG_TARGET_HAS_clz_i64 1
180 #define TCG_TARGET_HAS_ctz_i64 1
181 #define TCG_TARGET_HAS_ctpop_i64 have_popcnt
182 #define TCG_TARGET_HAS_deposit_i64 1
183 #define TCG_TARGET_HAS_extract_i64 1
184 #define TCG_TARGET_HAS_sextract_i64 0
185 #define TCG_TARGET_HAS_extract2_i64 1
186 #define TCG_TARGET_HAS_negsetcond_i64 1
187 #define TCG_TARGET_HAS_add2_i64 1
188 #define TCG_TARGET_HAS_sub2_i64 1
189 #define TCG_TARGET_HAS_mulu2_i64 1
190 #define TCG_TARGET_HAS_muls2_i64 1
191 #define TCG_TARGET_HAS_muluh_i64 0
192 #define TCG_TARGET_HAS_mulsh_i64 0
193 #define TCG_TARGET_HAS_qemu_st8_i32 0
195 #define TCG_TARGET_HAS_qemu_st8_i32 1
198 #define TCG_TARGET_HAS_qemu_ldst_i128 \
199 (TCG_TARGET_REG_BITS == 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA))
201 #define TCG_TARGET_HAS_tst 1
203 /* We do not support older SSE systems, only beginning with AVX1. */
204 #define TCG_TARGET_HAS_v64 have_avx1
205 #define TCG_TARGET_HAS_v128 have_avx1
206 #define TCG_TARGET_HAS_v256 have_avx2
208 #define TCG_TARGET_HAS_andc_vec 1
209 #define TCG_TARGET_HAS_orc_vec have_avx512vl
210 #define TCG_TARGET_HAS_nand_vec have_avx512vl
211 #define TCG_TARGET_HAS_nor_vec have_avx512vl
212 #define TCG_TARGET_HAS_eqv_vec have_avx512vl
213 #define TCG_TARGET_HAS_not_vec have_avx512vl
214 #define TCG_TARGET_HAS_neg_vec 0
215 #define TCG_TARGET_HAS_abs_vec 1
216 #define TCG_TARGET_HAS_roti_vec have_avx512vl
217 #define TCG_TARGET_HAS_rots_vec 0
218 #define TCG_TARGET_HAS_rotv_vec have_avx512vl
219 #define TCG_TARGET_HAS_shi_vec 1
220 #define TCG_TARGET_HAS_shs_vec 1
221 #define TCG_TARGET_HAS_shv_vec have_avx2
222 #define TCG_TARGET_HAS_mul_vec 1
223 #define TCG_TARGET_HAS_sat_vec 1
224 #define TCG_TARGET_HAS_minmax_vec 1
225 #define TCG_TARGET_HAS_bitsel_vec have_avx512vl
226 #define TCG_TARGET_HAS_cmpsel_vec -1
227 #define TCG_TARGET_HAS_tst_vec 0
229 #define TCG_TARGET_deposit_i32_valid(ofs, len) \
230 (((ofs) == 0 && ((len) == 8 || (len) == 16)) || \
231 (TCG_TARGET_REG_BITS == 32 && (ofs) == 8 && (len) == 8))
232 #define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid
234 /* Check for the possibility of high-byte extraction and, for 64-bit,
235 zero-extending 32-bit right-shift. */
236 #define TCG_TARGET_extract_i32_valid(ofs, len) ((ofs) == 8 && (len) == 8)
237 #define TCG_TARGET_extract_i64_valid(ofs, len) \
238 (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32)
240 /* This defines the natural memory order supported by this
241 * architecture before guarantees made by various barrier
244 * The x86 has a pretty strong memory ordering which only really
245 * allows for some stores to be re-ordered after loads.
247 #include "tcg/tcg-mo.h"
249 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
250 #define TCG_TARGET_NEED_LDST_LABELS
251 #define TCG_TARGET_NEED_POOL_LABELS