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target/riscv: vector narrowing fixed-point clip instructions
[qemu/ar7.git] / target / riscv / vector_helper.c
blobd7c51daca71c837d3546d59c91501f37f5c65ab7
1 /*
2 * RISC-V Vector Extension Helpers for QEMU.
3 *
4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "exec/memop.h"
22 #include "exec/exec-all.h"
23 #include "exec/helper-proto.h"
24 #include "tcg/tcg-gvec-desc.h"
25 #include "internals.h"
26 #include <math.h>
27
28 target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
29 target_ulong s2)
30 {
31 int vlmax, vl;
32 RISCVCPU *cpu = env_archcpu(env);
33 uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
34 uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
35 bool vill = FIELD_EX64(s2, VTYPE, VILL);
36 target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
37
38 if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
39 /* only set vill bit. */
40 env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
41 env->vl = 0;
42 env->vstart = 0;
43 return 0;
44 }
45
46 vlmax = vext_get_vlmax(cpu, s2);
47 if (s1 <= vlmax) {
48 vl = s1;
49 } else {
50 vl = vlmax;
51 }
52 env->vl = vl;
53 env->vtype = s2;
54 env->vstart = 0;
55 return vl;
56 }
57
58 /*
59 * Note that vector data is stored in host-endian 64-bit chunks,
60 * so addressing units smaller than that needs a host-endian fixup.
61 */
62 #ifdef HOST_WORDS_BIGENDIAN
63 #define H1(x) ((x) ^ 7)
64 #define H1_2(x) ((x) ^ 6)
65 #define H1_4(x) ((x) ^ 4)
66 #define H2(x) ((x) ^ 3)
67 #define H4(x) ((x) ^ 1)
68 #define H8(x) ((x))
69 #else
70 #define H1(x) (x)
71 #define H1_2(x) (x)
72 #define H1_4(x) (x)
73 #define H2(x) (x)
74 #define H4(x) (x)
75 #define H8(x) (x)
76 #endif
77
78 static inline uint32_t vext_nf(uint32_t desc)
79 {
80 return FIELD_EX32(simd_data(desc), VDATA, NF);
81 }
82
83 static inline uint32_t vext_mlen(uint32_t desc)
84 {
85 return FIELD_EX32(simd_data(desc), VDATA, MLEN);
86 }
87
88 static inline uint32_t vext_vm(uint32_t desc)
89 {
90 return FIELD_EX32(simd_data(desc), VDATA, VM);
91 }
92
93 static inline uint32_t vext_lmul(uint32_t desc)
94 {
95 return FIELD_EX32(simd_data(desc), VDATA, LMUL);
96 }
97
98 static uint32_t vext_wd(uint32_t desc)
99 {
100 return (simd_data(desc) >> 11) & 0x1;
101 }
102
103 /*
104 * Get vector group length in bytes. Its range is [64, 2048].
105 *
106 * As simd_desc support at most 256, the max vlen is 512 bits.
107 * So vlen in bytes is encoded as maxsz.
108 */
109 static inline uint32_t vext_maxsz(uint32_t desc)
110 {
111 return simd_maxsz(desc) << vext_lmul(desc);
112 }
113
114 /*
115 * This function checks watchpoint before real load operation.
116 *
117 * In softmmu mode, the TLB API probe_access is enough for watchpoint check.
118 * In user mode, there is no watchpoint support now.
119 *
120 * It will trigger an exception if there is no mapping in TLB
121 * and page table walk can't fill the TLB entry. Then the guest
122 * software can return here after process the exception or never return.
123 */
124 static void probe_pages(CPURISCVState *env, target_ulong addr,
125 target_ulong len, uintptr_t ra,
126 MMUAccessType access_type)
127 {
128 target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
129 target_ulong curlen = MIN(pagelen, len);
130
131 probe_access(env, addr, curlen, access_type,
132 cpu_mmu_index(env, false), ra);
133 if (len > curlen) {
134 addr += curlen;
135 curlen = len - curlen;
136 probe_access(env, addr, curlen, access_type,
137 cpu_mmu_index(env, false), ra);
138 }
139 }
140
141 #ifdef HOST_WORDS_BIGENDIAN
142 static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
143 {
144 /*
145 * Split the remaining range to two parts.
146 * The first part is in the last uint64_t unit.
147 * The second part start from the next uint64_t unit.
148 */
149 int part1 = 0, part2 = tot - cnt;
150 if (cnt % 8) {
151 part1 = 8 - (cnt % 8);
152 part2 = tot - cnt - part1;
153 memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1);
154 memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2);
155 } else {
156 memset(tail, 0, part2);
157 }
158 }
159 #else
160 static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
161 {
162 memset(tail, 0, tot - cnt);
163 }
164 #endif
165
166 static void clearb(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
167 {
168 int8_t *cur = ((int8_t *)vd + H1(idx));
169 vext_clear(cur, cnt, tot);
170 }
171
172 static void clearh(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
173 {
174 int16_t *cur = ((int16_t *)vd + H2(idx));
175 vext_clear(cur, cnt, tot);
176 }
177
178 static void clearl(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
179 {
180 int32_t *cur = ((int32_t *)vd + H4(idx));
181 vext_clear(cur, cnt, tot);
182 }
183
184 static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
185 {
186 int64_t *cur = (int64_t *)vd + idx;
187 vext_clear(cur, cnt, tot);
188 }
189
190 static inline void vext_set_elem_mask(void *v0, int mlen, int index,
191 uint8_t value)
192 {
193 int idx = (index * mlen) / 64;
194 int pos = (index * mlen) % 64;
195 uint64_t old = ((uint64_t *)v0)[idx];
196 ((uint64_t *)v0)[idx] = deposit64(old, pos, mlen, value);
197 }
198
199 static inline int vext_elem_mask(void *v0, int mlen, int index)
200 {
201 int idx = (index * mlen) / 64;
202 int pos = (index * mlen) % 64;
203 return (((uint64_t *)v0)[idx] >> pos) & 1;
204 }
205
206 /* elements operations for load and store */
207 typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr,
208 uint32_t idx, void *vd, uintptr_t retaddr);
209 typedef void clear_fn(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot);
210
211 #define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \
212 static void NAME(CPURISCVState *env, abi_ptr addr, \
213 uint32_t idx, void *vd, uintptr_t retaddr)\
214 { \
215 MTYPE data; \
216 ETYPE *cur = ((ETYPE *)vd + H(idx)); \
217 data = cpu_##LDSUF##_data_ra(env, addr, retaddr); \
218 *cur = data; \
219 } \
220
221 GEN_VEXT_LD_ELEM(ldb_b, int8_t, int8_t, H1, ldsb)
222 GEN_VEXT_LD_ELEM(ldb_h, int8_t, int16_t, H2, ldsb)
223 GEN_VEXT_LD_ELEM(ldb_w, int8_t, int32_t, H4, ldsb)
224 GEN_VEXT_LD_ELEM(ldb_d, int8_t, int64_t, H8, ldsb)
225 GEN_VEXT_LD_ELEM(ldh_h, int16_t, int16_t, H2, ldsw)
226 GEN_VEXT_LD_ELEM(ldh_w, int16_t, int32_t, H4, ldsw)
227 GEN_VEXT_LD_ELEM(ldh_d, int16_t, int64_t, H8, ldsw)
228 GEN_VEXT_LD_ELEM(ldw_w, int32_t, int32_t, H4, ldl)
229 GEN_VEXT_LD_ELEM(ldw_d, int32_t, int64_t, H8, ldl)
230 GEN_VEXT_LD_ELEM(lde_b, int8_t, int8_t, H1, ldsb)
231 GEN_VEXT_LD_ELEM(lde_h, int16_t, int16_t, H2, ldsw)
232 GEN_VEXT_LD_ELEM(lde_w, int32_t, int32_t, H4, ldl)
233 GEN_VEXT_LD_ELEM(lde_d, int64_t, int64_t, H8, ldq)
234 GEN_VEXT_LD_ELEM(ldbu_b, uint8_t, uint8_t, H1, ldub)
235 GEN_VEXT_LD_ELEM(ldbu_h, uint8_t, uint16_t, H2, ldub)
236 GEN_VEXT_LD_ELEM(ldbu_w, uint8_t, uint32_t, H4, ldub)
237 GEN_VEXT_LD_ELEM(ldbu_d, uint8_t, uint64_t, H8, ldub)
238 GEN_VEXT_LD_ELEM(ldhu_h, uint16_t, uint16_t, H2, lduw)
239 GEN_VEXT_LD_ELEM(ldhu_w, uint16_t, uint32_t, H4, lduw)
240 GEN_VEXT_LD_ELEM(ldhu_d, uint16_t, uint64_t, H8, lduw)
241 GEN_VEXT_LD_ELEM(ldwu_w, uint32_t, uint32_t, H4, ldl)
242 GEN_VEXT_LD_ELEM(ldwu_d, uint32_t, uint64_t, H8, ldl)
243
244 #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \
245 static void NAME(CPURISCVState *env, abi_ptr addr, \
246 uint32_t idx, void *vd, uintptr_t retaddr)\
247 { \
248 ETYPE data = *((ETYPE *)vd + H(idx)); \
249 cpu_##STSUF##_data_ra(env, addr, data, retaddr); \
250 }
251
252 GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb)
253 GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb)
254 GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb)
255 GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb)
256 GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw)
257 GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw)
258 GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw)
259 GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl)
260 GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl)
261 GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb)
262 GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw)
263 GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
264 GEN_VEXT_ST_ELEM(ste_d, int64_t, H8, stq)
265
266 /*
267 *** stride: access vector element from strided memory
268 */
269 static void
270 vext_ldst_stride(void *vd, void *v0, target_ulong base,
271 target_ulong stride, CPURISCVState *env,
272 uint32_t desc, uint32_t vm,
273 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
274 uint32_t esz, uint32_t msz, uintptr_t ra,
275 MMUAccessType access_type)
276 {
277 uint32_t i, k;
278 uint32_t nf = vext_nf(desc);
279 uint32_t mlen = vext_mlen(desc);
280 uint32_t vlmax = vext_maxsz(desc) / esz;
281
282 /* probe every access*/
283 for (i = 0; i < env->vl; i++) {
284 if (!vm && !vext_elem_mask(v0, mlen, i)) {
285 continue;
286 }
287 probe_pages(env, base + stride * i, nf * msz, ra, access_type);
288 }
289 /* do real access */
290 for (i = 0; i < env->vl; i++) {
291 k = 0;
292 if (!vm && !vext_elem_mask(v0, mlen, i)) {
293 continue;
294 }
295 while (k < nf) {
296 target_ulong addr = base + stride * i + k * msz;
297 ldst_elem(env, addr, i + k * vlmax, vd, ra);
298 k++;
299 }
300 }
301 /* clear tail elements */
302 if (clear_elem) {
303 for (k = 0; k < nf; k++) {
304 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
305 }
306 }
307 }
308
309 #define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
310 void HELPER(NAME)(void *vd, void * v0, target_ulong base, \
311 target_ulong stride, CPURISCVState *env, \
312 uint32_t desc) \
313 { \
314 uint32_t vm = vext_vm(desc); \
315 vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \
316 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
317 GETPC(), MMU_DATA_LOAD); \
318 }
319
320 GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b, clearb)
321 GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h, clearh)
322 GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w, clearl)
323 GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d, clearq)
324 GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h, clearh)
325 GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w, clearl)
326 GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d, clearq)
327 GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w, clearl)
328 GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d, clearq)
329 GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b, clearb)
330 GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h, clearh)
331 GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w, clearl)
332 GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d, clearq)
333 GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b, clearb)
334 GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h, clearh)
335 GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w, clearl)
336 GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d, clearq)
337 GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h, clearh)
338 GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w, clearl)
339 GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d, clearq)
340 GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w, clearl)
341 GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d, clearq)
342
343 #define GEN_VEXT_ST_STRIDE(NAME, MTYPE, ETYPE, STORE_FN) \
344 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
345 target_ulong stride, CPURISCVState *env, \
346 uint32_t desc) \
347 { \
348 uint32_t vm = vext_vm(desc); \
349 vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \
350 NULL, sizeof(ETYPE), sizeof(MTYPE), \
351 GETPC(), MMU_DATA_STORE); \
352 }
353
354 GEN_VEXT_ST_STRIDE(vssb_v_b, int8_t, int8_t, stb_b)
355 GEN_VEXT_ST_STRIDE(vssb_v_h, int8_t, int16_t, stb_h)
356 GEN_VEXT_ST_STRIDE(vssb_v_w, int8_t, int32_t, stb_w)
357 GEN_VEXT_ST_STRIDE(vssb_v_d, int8_t, int64_t, stb_d)
358 GEN_VEXT_ST_STRIDE(vssh_v_h, int16_t, int16_t, sth_h)
359 GEN_VEXT_ST_STRIDE(vssh_v_w, int16_t, int32_t, sth_w)
360 GEN_VEXT_ST_STRIDE(vssh_v_d, int16_t, int64_t, sth_d)
361 GEN_VEXT_ST_STRIDE(vssw_v_w, int32_t, int32_t, stw_w)
362 GEN_VEXT_ST_STRIDE(vssw_v_d, int32_t, int64_t, stw_d)
363 GEN_VEXT_ST_STRIDE(vsse_v_b, int8_t, int8_t, ste_b)
364 GEN_VEXT_ST_STRIDE(vsse_v_h, int16_t, int16_t, ste_h)
365 GEN_VEXT_ST_STRIDE(vsse_v_w, int32_t, int32_t, ste_w)
366 GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d)
367
368 /*
369 *** unit-stride: access elements stored contiguously in memory
370 */
371
372 /* unmasked unit-stride load and store operation*/
373 static void
374 vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
375 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
376 uint32_t esz, uint32_t msz, uintptr_t ra,
377 MMUAccessType access_type)
378 {
379 uint32_t i, k;
380 uint32_t nf = vext_nf(desc);
381 uint32_t vlmax = vext_maxsz(desc) / esz;
382
383 /* probe every access */
384 probe_pages(env, base, env->vl * nf * msz, ra, access_type);
385 /* load bytes from guest memory */
386 for (i = 0; i < env->vl; i++) {
387 k = 0;
388 while (k < nf) {
389 target_ulong addr = base + (i * nf + k) * msz;
390 ldst_elem(env, addr, i + k * vlmax, vd, ra);
391 k++;
392 }
393 }
394 /* clear tail elements */
395 if (clear_elem) {
396 for (k = 0; k < nf; k++) {
397 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
398 }
399 }
400 }
401
402 /*
403 * masked unit-stride load and store operation will be a special case of stride,
404 * stride = NF * sizeof (MTYPE)
405 */
406
407 #define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
408 void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
409 CPURISCVState *env, uint32_t desc) \
410 { \
411 uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
412 vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \
413 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
414 GETPC(), MMU_DATA_LOAD); \
415 } \
416 \
417 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
418 CPURISCVState *env, uint32_t desc) \
419 { \
420 vext_ldst_us(vd, base, env, desc, LOAD_FN, CLEAR_FN, \
421 sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_LOAD); \
422 }
423
424 GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b, clearb)
425 GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h, clearh)
426 GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w, clearl)
427 GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d, clearq)
428 GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h, clearh)
429 GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w, clearl)
430 GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d, clearq)
431 GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w, clearl)
432 GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d, clearq)
433 GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b, clearb)
434 GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h, clearh)
435 GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w, clearl)
436 GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d, clearq)
437 GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b, clearb)
438 GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h, clearh)
439 GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w, clearl)
440 GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d, clearq)
441 GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h, clearh)
442 GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w, clearl)
443 GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d, clearq)
444 GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w, clearl)
445 GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d, clearq)
446
447 #define GEN_VEXT_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \
448 void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
449 CPURISCVState *env, uint32_t desc) \
450 { \
451 uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
452 vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
453 NULL, sizeof(ETYPE), sizeof(MTYPE), \
454 GETPC(), MMU_DATA_STORE); \
455 } \
456 \
457 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
458 CPURISCVState *env, uint32_t desc) \
459 { \
460 vext_ldst_us(vd, base, env, desc, STORE_FN, NULL, \
461 sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_STORE);\
462 }
463
464 GEN_VEXT_ST_US(vsb_v_b, int8_t, int8_t , stb_b)
465 GEN_VEXT_ST_US(vsb_v_h, int8_t, int16_t, stb_h)
466 GEN_VEXT_ST_US(vsb_v_w, int8_t, int32_t, stb_w)
467 GEN_VEXT_ST_US(vsb_v_d, int8_t, int64_t, stb_d)
468 GEN_VEXT_ST_US(vsh_v_h, int16_t, int16_t, sth_h)
469 GEN_VEXT_ST_US(vsh_v_w, int16_t, int32_t, sth_w)
470 GEN_VEXT_ST_US(vsh_v_d, int16_t, int64_t, sth_d)
471 GEN_VEXT_ST_US(vsw_v_w, int32_t, int32_t, stw_w)
472 GEN_VEXT_ST_US(vsw_v_d, int32_t, int64_t, stw_d)
473 GEN_VEXT_ST_US(vse_v_b, int8_t, int8_t , ste_b)
474 GEN_VEXT_ST_US(vse_v_h, int16_t, int16_t, ste_h)
475 GEN_VEXT_ST_US(vse_v_w, int32_t, int32_t, ste_w)
476 GEN_VEXT_ST_US(vse_v_d, int64_t, int64_t, ste_d)
477
478 /*
479 *** index: access vector element from indexed memory
480 */
481 typedef target_ulong vext_get_index_addr(target_ulong base,
482 uint32_t idx, void *vs2);
483
484 #define GEN_VEXT_GET_INDEX_ADDR(NAME, ETYPE, H) \
485 static target_ulong NAME(target_ulong base, \
486 uint32_t idx, void *vs2) \
487 { \
488 return (base + *((ETYPE *)vs2 + H(idx))); \
489 }
490
491 GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
492 GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
493 GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
494 GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
495
496 static inline void
497 vext_ldst_index(void *vd, void *v0, target_ulong base,
498 void *vs2, CPURISCVState *env, uint32_t desc,
499 vext_get_index_addr get_index_addr,
500 vext_ldst_elem_fn *ldst_elem,
501 clear_fn *clear_elem,
502 uint32_t esz, uint32_t msz, uintptr_t ra,
503 MMUAccessType access_type)
504 {
505 uint32_t i, k;
506 uint32_t nf = vext_nf(desc);
507 uint32_t vm = vext_vm(desc);
508 uint32_t mlen = vext_mlen(desc);
509 uint32_t vlmax = vext_maxsz(desc) / esz;
510
511 /* probe every access*/
512 for (i = 0; i < env->vl; i++) {
513 if (!vm && !vext_elem_mask(v0, mlen, i)) {
514 continue;
515 }
516 probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
517 access_type);
518 }
519 /* load bytes from guest memory */
520 for (i = 0; i < env->vl; i++) {
521 k = 0;
522 if (!vm && !vext_elem_mask(v0, mlen, i)) {
523 continue;
524 }
525 while (k < nf) {
526 abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
527 ldst_elem(env, addr, i + k * vlmax, vd, ra);
528 k++;
529 }
530 }
531 /* clear tail elements */
532 if (clear_elem) {
533 for (k = 0; k < nf; k++) {
534 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
535 }
536 }
537 }
538
539 #define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN) \
540 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
541 void *vs2, CPURISCVState *env, uint32_t desc) \
542 { \
543 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
544 LOAD_FN, CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
545 GETPC(), MMU_DATA_LOAD); \
546 }
547
548 GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b, clearb)
549 GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h, clearh)
550 GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w, clearl)
551 GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d, clearq)
552 GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h, clearh)
553 GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w, clearl)
554 GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d, clearq)
555 GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w, clearl)
556 GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d, clearq)
557 GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b, clearb)
558 GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h, clearh)
559 GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w, clearl)
560 GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d, clearq)
561 GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b, clearb)
562 GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h, clearh)
563 GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w, clearl)
564 GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d, clearq)
565 GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h, clearh)
566 GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w, clearl)
567 GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d, clearq)
568 GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w, clearl)
569 GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d, clearq)
570
571 #define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\
572 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
573 void *vs2, CPURISCVState *env, uint32_t desc) \
574 { \
575 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
576 STORE_FN, NULL, sizeof(ETYPE), sizeof(MTYPE),\
577 GETPC(), MMU_DATA_STORE); \
578 }
579
580 GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b)
581 GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h)
582 GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w)
583 GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d)
584 GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h)
585 GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w)
586 GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d)
587 GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w)
588 GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d)
589 GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b)
590 GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h)
591 GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w)
592 GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d)
593
594 /*
595 *** unit-stride fault-only-fisrt load instructions
596 */
597 static inline void
598 vext_ldff(void *vd, void *v0, target_ulong base,
599 CPURISCVState *env, uint32_t desc,
600 vext_ldst_elem_fn *ldst_elem,
601 clear_fn *clear_elem,
602 uint32_t esz, uint32_t msz, uintptr_t ra)
603 {
604 void *host;
605 uint32_t i, k, vl = 0;
606 uint32_t mlen = vext_mlen(desc);
607 uint32_t nf = vext_nf(desc);
608 uint32_t vm = vext_vm(desc);
609 uint32_t vlmax = vext_maxsz(desc) / esz;
610 target_ulong addr, offset, remain;
611
612 /* probe every access*/
613 for (i = 0; i < env->vl; i++) {
614 if (!vm && !vext_elem_mask(v0, mlen, i)) {
615 continue;
616 }
617 addr = base + nf * i * msz;
618 if (i == 0) {
619 probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
620 } else {
621 /* if it triggers an exception, no need to check watchpoint */
622 remain = nf * msz;
623 while (remain > 0) {
624 offset = -(addr | TARGET_PAGE_MASK);
625 host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
626 cpu_mmu_index(env, false));
627 if (host) {
628 #ifdef CONFIG_USER_ONLY
629 if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
630 vl = i;
631 goto ProbeSuccess;
632 }
633 #else
634 probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
635 #endif
636 } else {
637 vl = i;
638 goto ProbeSuccess;
639 }
640 if (remain <= offset) {
641 break;
642 }
643 remain -= offset;
644 addr += offset;
645 }
646 }
647 }
648 ProbeSuccess:
649 /* load bytes from guest memory */
650 if (vl != 0) {
651 env->vl = vl;
652 }
653 for (i = 0; i < env->vl; i++) {
654 k = 0;
655 if (!vm && !vext_elem_mask(v0, mlen, i)) {
656 continue;
657 }
658 while (k < nf) {
659 target_ulong addr = base + (i * nf + k) * msz;
660 ldst_elem(env, addr, i + k * vlmax, vd, ra);
661 k++;
662 }
663 }
664 /* clear tail elements */
665 if (vl != 0) {
666 return;
667 }
668 for (k = 0; k < nf; k++) {
669 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
670 }
671 }
672
673 #define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
674 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
675 CPURISCVState *env, uint32_t desc) \
676 { \
677 vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \
678 sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
679 }
680
681 GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b, clearb)
682 GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h, clearh)
683 GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w, clearl)
684 GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d, clearq)
685 GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h, clearh)
686 GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w, clearl)
687 GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d, clearq)
688 GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w, clearl)
689 GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d, clearq)
690 GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b, clearb)
691 GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h, clearh)
692 GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w, clearl)
693 GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d, clearq)
694 GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b, clearb)
695 GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h, clearh)
696 GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w, clearl)
697 GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d, clearq)
698 GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h, clearh)
699 GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w, clearl)
700 GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d, clearq)
701 GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w, clearl)
702 GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d, clearq)
703
704 /*
705 *** Vector AMO Operations (Zvamo)
706 */
707 typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr,
708 uint32_t wd, uint32_t idx, CPURISCVState *env,
709 uintptr_t retaddr);
710
711 /* no atomic opreation for vector atomic insructions */
712 #define DO_SWAP(N, M) (M)
713 #define DO_AND(N, M) (N & M)
714 #define DO_XOR(N, M) (N ^ M)
715 #define DO_OR(N, M) (N | M)
716 #define DO_ADD(N, M) (N + M)
717
718 #define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ESZ, MSZ, H, DO_OP, SUF) \
719 static void \
720 vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
721 uint32_t wd, uint32_t idx, \
722 CPURISCVState *env, uintptr_t retaddr)\
723 { \
724 typedef int##ESZ##_t ETYPE; \
725 typedef int##MSZ##_t MTYPE; \
726 typedef uint##MSZ##_t UMTYPE __attribute__((unused)); \
727 ETYPE *pe3 = (ETYPE *)vs3 + H(idx); \
728 MTYPE a = cpu_ld##SUF##_data(env, addr), b = *pe3; \
729 \
730 cpu_st##SUF##_data(env, addr, DO_OP(a, b)); \
731 if (wd) { \
732 *pe3 = a; \
733 } \
734 }
735
736 /* Signed min/max */
737 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
738 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
739
740 /* Unsigned min/max */
741 #define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M)
742 #define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
743
744 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_w, 32, 32, H4, DO_SWAP, l)
745 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_w, 32, 32, H4, DO_ADD, l)
746 GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_w, 32, 32, H4, DO_XOR, l)
747 GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_w, 32, 32, H4, DO_AND, l)
748 GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_w, 32, 32, H4, DO_OR, l)
749 GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l)
750 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l)
751 GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
752 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
753 #ifdef TARGET_RISCV64
754 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
755 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
756 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l)
757 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddd_v_d, 64, 64, H8, DO_ADD, q)
758 GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_d, 64, 32, H8, DO_XOR, l)
759 GEN_VEXT_AMO_NOATOMIC_OP(vamoxord_v_d, 64, 64, H8, DO_XOR, q)
760 GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_d, 64, 32, H8, DO_AND, l)
761 GEN_VEXT_AMO_NOATOMIC_OP(vamoandd_v_d, 64, 64, H8, DO_AND, q)
762 GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_d, 64, 32, H8, DO_OR, l)
763 GEN_VEXT_AMO_NOATOMIC_OP(vamoord_v_d, 64, 64, H8, DO_OR, q)
764 GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_d, 64, 32, H8, DO_MIN, l)
765 GEN_VEXT_AMO_NOATOMIC_OP(vamomind_v_d, 64, 64, H8, DO_MIN, q)
766 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_d, 64, 32, H8, DO_MAX, l)
767 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxd_v_d, 64, 64, H8, DO_MAX, q)
768 GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
769 GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
770 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
771 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
772 #endif
773
774 static inline void
775 vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
776 void *vs2, CPURISCVState *env, uint32_t desc,
777 vext_get_index_addr get_index_addr,
778 vext_amo_noatomic_fn *noatomic_op,
779 clear_fn *clear_elem,
780 uint32_t esz, uint32_t msz, uintptr_t ra)
781 {
782 uint32_t i;
783 target_long addr;
784 uint32_t wd = vext_wd(desc);
785 uint32_t vm = vext_vm(desc);
786 uint32_t mlen = vext_mlen(desc);
787 uint32_t vlmax = vext_maxsz(desc) / esz;
788
789 for (i = 0; i < env->vl; i++) {
790 if (!vm && !vext_elem_mask(v0, mlen, i)) {
791 continue;
792 }
793 probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD);
794 probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE);
795 }
796 for (i = 0; i < env->vl; i++) {
797 if (!vm && !vext_elem_mask(v0, mlen, i)) {
798 continue;
799 }
800 addr = get_index_addr(base, i, vs2);
801 noatomic_op(vs3, addr, wd, i, env, ra);
802 }
803 clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz);
804 }
805
806 #define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \
807 void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \
808 void *vs2, CPURISCVState *env, uint32_t desc) \
809 { \
810 vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \
811 INDEX_FN, vext_##NAME##_noatomic_op, \
812 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
813 GETPC()); \
814 }
815
816 #ifdef TARGET_RISCV64
817 GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq)
818 GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq)
819 GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq)
820 GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d, clearq)
821 GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d, clearq)
822 GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d, clearq)
823 GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d, clearq)
824 GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d, clearq)
825 GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d, clearq)
826 GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d, clearq)
827 GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d, clearq)
828 GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d, clearq)
829 GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d, clearq)
830 GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d, clearq)
831 GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq)
832 GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq)
833 GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq)
834 GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq)
835 #endif
836 GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl)
837 GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl)
838 GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl)
839 GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w, clearl)
840 GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w, clearl)
841 GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w, clearl)
842 GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w, clearl)
843 GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w, clearl)
844 GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl)
845
846 /*
847 *** Vector Integer Arithmetic Instructions
848 */
849
850 /* expand macro args before macro */
851 #define RVVCALL(macro, ...) macro(__VA_ARGS__)
852
853 /* (TD, T1, T2, TX1, TX2) */
854 #define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t
855 #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t
856 #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t
857 #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t
858 #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
859 #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
860 #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
861 #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
862 #define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t
863 #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
864 #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
865 #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t
866 #define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
867 #define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
868 #define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
869 #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
870 #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
871 #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
872 #define WOP_SUS_B int16_t, uint8_t, int8_t, uint16_t, int16_t
873 #define WOP_SUS_H int32_t, uint16_t, int16_t, uint32_t, int32_t
874 #define WOP_SUS_W int64_t, uint32_t, int32_t, uint64_t, int64_t
875 #define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t
876 #define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t
877 #define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t
878 #define NOP_SSS_B int8_t, int8_t, int16_t, int8_t, int16_t
879 #define NOP_SSS_H int16_t, int16_t, int32_t, int16_t, int32_t
880 #define NOP_SSS_W int32_t, int32_t, int64_t, int32_t, int64_t
881 #define NOP_UUU_B uint8_t, uint8_t, uint16_t, uint8_t, uint16_t
882 #define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t
883 #define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t
884
885 /* operation of two vector elements */
886 typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
887
888 #define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
889 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
890 { \
891 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
892 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
893 *((TD *)vd + HD(i)) = OP(s2, s1); \
894 }
895 #define DO_SUB(N, M) (N - M)
896 #define DO_RSUB(N, M) (M - N)
897
898 RVVCALL(OPIVV2, vadd_vv_b, OP_SSS_B, H1, H1, H1, DO_ADD)
899 RVVCALL(OPIVV2, vadd_vv_h, OP_SSS_H, H2, H2, H2, DO_ADD)
900 RVVCALL(OPIVV2, vadd_vv_w, OP_SSS_W, H4, H4, H4, DO_ADD)
901 RVVCALL(OPIVV2, vadd_vv_d, OP_SSS_D, H8, H8, H8, DO_ADD)
902 RVVCALL(OPIVV2, vsub_vv_b, OP_SSS_B, H1, H1, H1, DO_SUB)
903 RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SUB)
904 RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB)
905 RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB)
906
907 static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
908 CPURISCVState *env, uint32_t desc,
909 uint32_t esz, uint32_t dsz,
910 opivv2_fn *fn, clear_fn *clearfn)
911 {
912 uint32_t vlmax = vext_maxsz(desc) / esz;
913 uint32_t mlen = vext_mlen(desc);
914 uint32_t vm = vext_vm(desc);
915 uint32_t vl = env->vl;
916 uint32_t i;
917
918 for (i = 0; i < vl; i++) {
919 if (!vm && !vext_elem_mask(v0, mlen, i)) {
920 continue;
921 }
922 fn(vd, vs1, vs2, i);
923 }
924 clearfn(vd, vl, vl * dsz, vlmax * dsz);
925 }
926
927 /* generate the helpers for OPIVV */
928 #define GEN_VEXT_VV(NAME, ESZ, DSZ, CLEAR_FN) \
929 void HELPER(NAME)(void *vd, void *v0, void *vs1, \
930 void *vs2, CPURISCVState *env, \
931 uint32_t desc) \
932 { \
933 do_vext_vv(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \
934 do_##NAME, CLEAR_FN); \
935 }
936
937 GEN_VEXT_VV(vadd_vv_b, 1, 1, clearb)
938 GEN_VEXT_VV(vadd_vv_h, 2, 2, clearh)
939 GEN_VEXT_VV(vadd_vv_w, 4, 4, clearl)
940 GEN_VEXT_VV(vadd_vv_d, 8, 8, clearq)
941 GEN_VEXT_VV(vsub_vv_b, 1, 1, clearb)
942 GEN_VEXT_VV(vsub_vv_h, 2, 2, clearh)
943 GEN_VEXT_VV(vsub_vv_w, 4, 4, clearl)
944 GEN_VEXT_VV(vsub_vv_d, 8, 8, clearq)
945
946 typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
947
948 /*
949 * (T1)s1 gives the real operator type.
950 * (TX1)(T1)s1 expands the operator type of widen or narrow operations.
951 */
952 #define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
953 static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \
954 { \
955 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
956 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \
957 }
958
959 RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD)
960 RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD)
961 RVVCALL(OPIVX2, vadd_vx_w, OP_SSS_W, H4, H4, DO_ADD)
962 RVVCALL(OPIVX2, vadd_vx_d, OP_SSS_D, H8, H8, DO_ADD)
963 RVVCALL(OPIVX2, vsub_vx_b, OP_SSS_B, H1, H1, DO_SUB)
964 RVVCALL(OPIVX2, vsub_vx_h, OP_SSS_H, H2, H2, DO_SUB)
965 RVVCALL(OPIVX2, vsub_vx_w, OP_SSS_W, H4, H4, DO_SUB)
966 RVVCALL(OPIVX2, vsub_vx_d, OP_SSS_D, H8, H8, DO_SUB)
967 RVVCALL(OPIVX2, vrsub_vx_b, OP_SSS_B, H1, H1, DO_RSUB)
968 RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB)
969 RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB)
970 RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB)
971
972 static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
973 CPURISCVState *env, uint32_t desc,
974 uint32_t esz, uint32_t dsz,
975 opivx2_fn fn, clear_fn *clearfn)
976 {
977 uint32_t vlmax = vext_maxsz(desc) / esz;
978 uint32_t mlen = vext_mlen(desc);
979 uint32_t vm = vext_vm(desc);
980 uint32_t vl = env->vl;
981 uint32_t i;
982
983 for (i = 0; i < vl; i++) {
984 if (!vm && !vext_elem_mask(v0, mlen, i)) {
985 continue;
986 }
987 fn(vd, s1, vs2, i);
988 }
989 clearfn(vd, vl, vl * dsz, vlmax * dsz);
990 }
991
992 /* generate the helpers for OPIVX */
993 #define GEN_VEXT_VX(NAME, ESZ, DSZ, CLEAR_FN) \
994 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
995 void *vs2, CPURISCVState *env, \
996 uint32_t desc) \
997 { \
998 do_vext_vx(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \
999 do_##NAME, CLEAR_FN); \
1000 }
1001
1002 GEN_VEXT_VX(vadd_vx_b, 1, 1, clearb)
1003 GEN_VEXT_VX(vadd_vx_h, 2, 2, clearh)
1004 GEN_VEXT_VX(vadd_vx_w, 4, 4, clearl)
1005 GEN_VEXT_VX(vadd_vx_d, 8, 8, clearq)
1006 GEN_VEXT_VX(vsub_vx_b, 1, 1, clearb)
1007 GEN_VEXT_VX(vsub_vx_h, 2, 2, clearh)
1008 GEN_VEXT_VX(vsub_vx_w, 4, 4, clearl)
1009 GEN_VEXT_VX(vsub_vx_d, 8, 8, clearq)
1010 GEN_VEXT_VX(vrsub_vx_b, 1, 1, clearb)
1011 GEN_VEXT_VX(vrsub_vx_h, 2, 2, clearh)
1012 GEN_VEXT_VX(vrsub_vx_w, 4, 4, clearl)
1013 GEN_VEXT_VX(vrsub_vx_d, 8, 8, clearq)
1014
1015 void HELPER(vec_rsubs8)(void *d, void *a, uint64_t b, uint32_t desc)
1016 {
1017 intptr_t oprsz = simd_oprsz(desc);
1018 intptr_t i;
1019
1020 for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
1021 *(uint8_t *)(d + i) = (uint8_t)b - *(uint8_t *)(a + i);
1022 }
1023 }
1024
1025 void HELPER(vec_rsubs16)(void *d, void *a, uint64_t b, uint32_t desc)
1026 {
1027 intptr_t oprsz = simd_oprsz(desc);
1028 intptr_t i;
1029
1030 for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
1031 *(uint16_t *)(d + i) = (uint16_t)b - *(uint16_t *)(a + i);
1032 }
1033 }
1034
1035 void HELPER(vec_rsubs32)(void *d, void *a, uint64_t b, uint32_t desc)
1036 {
1037 intptr_t oprsz = simd_oprsz(desc);
1038 intptr_t i;
1039
1040 for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
1041 *(uint32_t *)(d + i) = (uint32_t)b - *(uint32_t *)(a + i);
1042 }
1043 }
1044
1045 void HELPER(vec_rsubs64)(void *d, void *a, uint64_t b, uint32_t desc)
1046 {
1047 intptr_t oprsz = simd_oprsz(desc);
1048 intptr_t i;
1049
1050 for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
1051 *(uint64_t *)(d + i) = b - *(uint64_t *)(a + i);
1052 }
1053 }
1054
1055 /* Vector Widening Integer Add/Subtract */
1056 #define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
1057 #define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
1058 #define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
1059 #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
1060 #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
1061 #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
1062 #define WOP_WUUU_B uint16_t, uint8_t, uint16_t, uint16_t, uint16_t
1063 #define WOP_WUUU_H uint32_t, uint16_t, uint32_t, uint32_t, uint32_t
1064 #define WOP_WUUU_W uint64_t, uint32_t, uint64_t, uint64_t, uint64_t
1065 #define WOP_WSSS_B int16_t, int8_t, int16_t, int16_t, int16_t
1066 #define WOP_WSSS_H int32_t, int16_t, int32_t, int32_t, int32_t
1067 #define WOP_WSSS_W int64_t, int32_t, int64_t, int64_t, int64_t
1068 RVVCALL(OPIVV2, vwaddu_vv_b, WOP_UUU_B, H2, H1, H1, DO_ADD)
1069 RVVCALL(OPIVV2, vwaddu_vv_h, WOP_UUU_H, H4, H2, H2, DO_ADD)
1070 RVVCALL(OPIVV2, vwaddu_vv_w, WOP_UUU_W, H8, H4, H4, DO_ADD)
1071 RVVCALL(OPIVV2, vwsubu_vv_b, WOP_UUU_B, H2, H1, H1, DO_SUB)
1072 RVVCALL(OPIVV2, vwsubu_vv_h, WOP_UUU_H, H4, H2, H2, DO_SUB)
1073 RVVCALL(OPIVV2, vwsubu_vv_w, WOP_UUU_W, H8, H4, H4, DO_SUB)
1074 RVVCALL(OPIVV2, vwadd_vv_b, WOP_SSS_B, H2, H1, H1, DO_ADD)
1075 RVVCALL(OPIVV2, vwadd_vv_h, WOP_SSS_H, H4, H2, H2, DO_ADD)
1076 RVVCALL(OPIVV2, vwadd_vv_w, WOP_SSS_W, H8, H4, H4, DO_ADD)
1077 RVVCALL(OPIVV2, vwsub_vv_b, WOP_SSS_B, H2, H1, H1, DO_SUB)
1078 RVVCALL(OPIVV2, vwsub_vv_h, WOP_SSS_H, H4, H2, H2, DO_SUB)
1079 RVVCALL(OPIVV2, vwsub_vv_w, WOP_SSS_W, H8, H4, H4, DO_SUB)
1080 RVVCALL(OPIVV2, vwaddu_wv_b, WOP_WUUU_B, H2, H1, H1, DO_ADD)
1081 RVVCALL(OPIVV2, vwaddu_wv_h, WOP_WUUU_H, H4, H2, H2, DO_ADD)
1082 RVVCALL(OPIVV2, vwaddu_wv_w, WOP_WUUU_W, H8, H4, H4, DO_ADD)
1083 RVVCALL(OPIVV2, vwsubu_wv_b, WOP_WUUU_B, H2, H1, H1, DO_SUB)
1084 RVVCALL(OPIVV2, vwsubu_wv_h, WOP_WUUU_H, H4, H2, H2, DO_SUB)
1085 RVVCALL(OPIVV2, vwsubu_wv_w, WOP_WUUU_W, H8, H4, H4, DO_SUB)
1086 RVVCALL(OPIVV2, vwadd_wv_b, WOP_WSSS_B, H2, H1, H1, DO_ADD)
1087 RVVCALL(OPIVV2, vwadd_wv_h, WOP_WSSS_H, H4, H2, H2, DO_ADD)
1088 RVVCALL(OPIVV2, vwadd_wv_w, WOP_WSSS_W, H8, H4, H4, DO_ADD)
1089 RVVCALL(OPIVV2, vwsub_wv_b, WOP_WSSS_B, H2, H1, H1, DO_SUB)
1090 RVVCALL(OPIVV2, vwsub_wv_h, WOP_WSSS_H, H4, H2, H2, DO_SUB)
1091 RVVCALL(OPIVV2, vwsub_wv_w, WOP_WSSS_W, H8, H4, H4, DO_SUB)
1092 GEN_VEXT_VV(vwaddu_vv_b, 1, 2, clearh)
1093 GEN_VEXT_VV(vwaddu_vv_h, 2, 4, clearl)
1094 GEN_VEXT_VV(vwaddu_vv_w, 4, 8, clearq)
1095 GEN_VEXT_VV(vwsubu_vv_b, 1, 2, clearh)
1096 GEN_VEXT_VV(vwsubu_vv_h, 2, 4, clearl)
1097 GEN_VEXT_VV(vwsubu_vv_w, 4, 8, clearq)
1098 GEN_VEXT_VV(vwadd_vv_b, 1, 2, clearh)
1099 GEN_VEXT_VV(vwadd_vv_h, 2, 4, clearl)
1100 GEN_VEXT_VV(vwadd_vv_w, 4, 8, clearq)
1101 GEN_VEXT_VV(vwsub_vv_b, 1, 2, clearh)
1102 GEN_VEXT_VV(vwsub_vv_h, 2, 4, clearl)
1103 GEN_VEXT_VV(vwsub_vv_w, 4, 8, clearq)
1104 GEN_VEXT_VV(vwaddu_wv_b, 1, 2, clearh)
1105 GEN_VEXT_VV(vwaddu_wv_h, 2, 4, clearl)
1106 GEN_VEXT_VV(vwaddu_wv_w, 4, 8, clearq)
1107 GEN_VEXT_VV(vwsubu_wv_b, 1, 2, clearh)
1108 GEN_VEXT_VV(vwsubu_wv_h, 2, 4, clearl)
1109 GEN_VEXT_VV(vwsubu_wv_w, 4, 8, clearq)
1110 GEN_VEXT_VV(vwadd_wv_b, 1, 2, clearh)
1111 GEN_VEXT_VV(vwadd_wv_h, 2, 4, clearl)
1112 GEN_VEXT_VV(vwadd_wv_w, 4, 8, clearq)
1113 GEN_VEXT_VV(vwsub_wv_b, 1, 2, clearh)
1114 GEN_VEXT_VV(vwsub_wv_h, 2, 4, clearl)
1115 GEN_VEXT_VV(vwsub_wv_w, 4, 8, clearq)
1116
1117 RVVCALL(OPIVX2, vwaddu_vx_b, WOP_UUU_B, H2, H1, DO_ADD)
1118 RVVCALL(OPIVX2, vwaddu_vx_h, WOP_UUU_H, H4, H2, DO_ADD)
1119 RVVCALL(OPIVX2, vwaddu_vx_w, WOP_UUU_W, H8, H4, DO_ADD)
1120 RVVCALL(OPIVX2, vwsubu_vx_b, WOP_UUU_B, H2, H1, DO_SUB)
1121 RVVCALL(OPIVX2, vwsubu_vx_h, WOP_UUU_H, H4, H2, DO_SUB)
1122 RVVCALL(OPIVX2, vwsubu_vx_w, WOP_UUU_W, H8, H4, DO_SUB)
1123 RVVCALL(OPIVX2, vwadd_vx_b, WOP_SSS_B, H2, H1, DO_ADD)
1124 RVVCALL(OPIVX2, vwadd_vx_h, WOP_SSS_H, H4, H2, DO_ADD)
1125 RVVCALL(OPIVX2, vwadd_vx_w, WOP_SSS_W, H8, H4, DO_ADD)
1126 RVVCALL(OPIVX2, vwsub_vx_b, WOP_SSS_B, H2, H1, DO_SUB)
1127 RVVCALL(OPIVX2, vwsub_vx_h, WOP_SSS_H, H4, H2, DO_SUB)
1128 RVVCALL(OPIVX2, vwsub_vx_w, WOP_SSS_W, H8, H4, DO_SUB)
1129 RVVCALL(OPIVX2, vwaddu_wx_b, WOP_WUUU_B, H2, H1, DO_ADD)
1130 RVVCALL(OPIVX2, vwaddu_wx_h, WOP_WUUU_H, H4, H2, DO_ADD)
1131 RVVCALL(OPIVX2, vwaddu_wx_w, WOP_WUUU_W, H8, H4, DO_ADD)
1132 RVVCALL(OPIVX2, vwsubu_wx_b, WOP_WUUU_B, H2, H1, DO_SUB)
1133 RVVCALL(OPIVX2, vwsubu_wx_h, WOP_WUUU_H, H4, H2, DO_SUB)
1134 RVVCALL(OPIVX2, vwsubu_wx_w, WOP_WUUU_W, H8, H4, DO_SUB)
1135 RVVCALL(OPIVX2, vwadd_wx_b, WOP_WSSS_B, H2, H1, DO_ADD)
1136 RVVCALL(OPIVX2, vwadd_wx_h, WOP_WSSS_H, H4, H2, DO_ADD)
1137 RVVCALL(OPIVX2, vwadd_wx_w, WOP_WSSS_W, H8, H4, DO_ADD)
1138 RVVCALL(OPIVX2, vwsub_wx_b, WOP_WSSS_B, H2, H1, DO_SUB)
1139 RVVCALL(OPIVX2, vwsub_wx_h, WOP_WSSS_H, H4, H2, DO_SUB)
1140 RVVCALL(OPIVX2, vwsub_wx_w, WOP_WSSS_W, H8, H4, DO_SUB)
1141 GEN_VEXT_VX(vwaddu_vx_b, 1, 2, clearh)
1142 GEN_VEXT_VX(vwaddu_vx_h, 2, 4, clearl)
1143 GEN_VEXT_VX(vwaddu_vx_w, 4, 8, clearq)
1144 GEN_VEXT_VX(vwsubu_vx_b, 1, 2, clearh)
1145 GEN_VEXT_VX(vwsubu_vx_h, 2, 4, clearl)
1146 GEN_VEXT_VX(vwsubu_vx_w, 4, 8, clearq)
1147 GEN_VEXT_VX(vwadd_vx_b, 1, 2, clearh)
1148 GEN_VEXT_VX(vwadd_vx_h, 2, 4, clearl)
1149 GEN_VEXT_VX(vwadd_vx_w, 4, 8, clearq)
1150 GEN_VEXT_VX(vwsub_vx_b, 1, 2, clearh)
1151 GEN_VEXT_VX(vwsub_vx_h, 2, 4, clearl)
1152 GEN_VEXT_VX(vwsub_vx_w, 4, 8, clearq)
1153 GEN_VEXT_VX(vwaddu_wx_b, 1, 2, clearh)
1154 GEN_VEXT_VX(vwaddu_wx_h, 2, 4, clearl)
1155 GEN_VEXT_VX(vwaddu_wx_w, 4, 8, clearq)
1156 GEN_VEXT_VX(vwsubu_wx_b, 1, 2, clearh)
1157 GEN_VEXT_VX(vwsubu_wx_h, 2, 4, clearl)
1158 GEN_VEXT_VX(vwsubu_wx_w, 4, 8, clearq)
1159 GEN_VEXT_VX(vwadd_wx_b, 1, 2, clearh)
1160 GEN_VEXT_VX(vwadd_wx_h, 2, 4, clearl)
1161 GEN_VEXT_VX(vwadd_wx_w, 4, 8, clearq)
1162 GEN_VEXT_VX(vwsub_wx_b, 1, 2, clearh)
1163 GEN_VEXT_VX(vwsub_wx_h, 2, 4, clearl)
1164 GEN_VEXT_VX(vwsub_wx_w, 4, 8, clearq)
1165
1166 /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
1167 #define DO_VADC(N, M, C) (N + M + C)
1168 #define DO_VSBC(N, M, C) (N - M - C)
1169
1170 #define GEN_VEXT_VADC_VVM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \
1171 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1172 CPURISCVState *env, uint32_t desc) \
1173 { \
1174 uint32_t mlen = vext_mlen(desc); \
1175 uint32_t vl = env->vl; \
1176 uint32_t esz = sizeof(ETYPE); \
1177 uint32_t vlmax = vext_maxsz(desc) / esz; \
1178 uint32_t i; \
1179 \
1180 for (i = 0; i < vl; i++) { \
1181 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1182 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1183 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1184 \
1185 *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
1186 } \
1187 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1188 }
1189
1190 GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC, clearb)
1191 GEN_VEXT_VADC_VVM(vadc_vvm_h, uint16_t, H2, DO_VADC, clearh)
1192 GEN_VEXT_VADC_VVM(vadc_vvm_w, uint32_t, H4, DO_VADC, clearl)
1193 GEN_VEXT_VADC_VVM(vadc_vvm_d, uint64_t, H8, DO_VADC, clearq)
1194
1195 GEN_VEXT_VADC_VVM(vsbc_vvm_b, uint8_t, H1, DO_VSBC, clearb)
1196 GEN_VEXT_VADC_VVM(vsbc_vvm_h, uint16_t, H2, DO_VSBC, clearh)
1197 GEN_VEXT_VADC_VVM(vsbc_vvm_w, uint32_t, H4, DO_VSBC, clearl)
1198 GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC, clearq)
1199
1200 #define GEN_VEXT_VADC_VXM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \
1201 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
1202 CPURISCVState *env, uint32_t desc) \
1203 { \
1204 uint32_t mlen = vext_mlen(desc); \
1205 uint32_t vl = env->vl; \
1206 uint32_t esz = sizeof(ETYPE); \
1207 uint32_t vlmax = vext_maxsz(desc) / esz; \
1208 uint32_t i; \
1209 \
1210 for (i = 0; i < vl; i++) { \
1211 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1212 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1213 \
1214 *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
1215 } \
1216 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1217 }
1218
1219 GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC, clearb)
1220 GEN_VEXT_VADC_VXM(vadc_vxm_h, uint16_t, H2, DO_VADC, clearh)
1221 GEN_VEXT_VADC_VXM(vadc_vxm_w, uint32_t, H4, DO_VADC, clearl)
1222 GEN_VEXT_VADC_VXM(vadc_vxm_d, uint64_t, H8, DO_VADC, clearq)
1223
1224 GEN_VEXT_VADC_VXM(vsbc_vxm_b, uint8_t, H1, DO_VSBC, clearb)
1225 GEN_VEXT_VADC_VXM(vsbc_vxm_h, uint16_t, H2, DO_VSBC, clearh)
1226 GEN_VEXT_VADC_VXM(vsbc_vxm_w, uint32_t, H4, DO_VSBC, clearl)
1227 GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq)
1228
1229 #define DO_MADC(N, M, C) (C ? (__typeof(N))(N + M + 1) <= N : \
1230 (__typeof(N))(N + M) < N)
1231 #define DO_MSBC(N, M, C) (C ? N <= M : N < M)
1232
1233 #define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \
1234 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1235 CPURISCVState *env, uint32_t desc) \
1236 { \
1237 uint32_t mlen = vext_mlen(desc); \
1238 uint32_t vl = env->vl; \
1239 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1240 uint32_t i; \
1241 \
1242 for (i = 0; i < vl; i++) { \
1243 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1244 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1245 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1246 \
1247 vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1, carry));\
1248 } \
1249 for (; i < vlmax; i++) { \
1250 vext_set_elem_mask(vd, mlen, i, 0); \
1251 } \
1252 }
1253
1254 GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC)
1255 GEN_VEXT_VMADC_VVM(vmadc_vvm_h, uint16_t, H2, DO_MADC)
1256 GEN_VEXT_VMADC_VVM(vmadc_vvm_w, uint32_t, H4, DO_MADC)
1257 GEN_VEXT_VMADC_VVM(vmadc_vvm_d, uint64_t, H8, DO_MADC)
1258
1259 GEN_VEXT_VMADC_VVM(vmsbc_vvm_b, uint8_t, H1, DO_MSBC)
1260 GEN_VEXT_VMADC_VVM(vmsbc_vvm_h, uint16_t, H2, DO_MSBC)
1261 GEN_VEXT_VMADC_VVM(vmsbc_vvm_w, uint32_t, H4, DO_MSBC)
1262 GEN_VEXT_VMADC_VVM(vmsbc_vvm_d, uint64_t, H8, DO_MSBC)
1263
1264 #define GEN_VEXT_VMADC_VXM(NAME, ETYPE, H, DO_OP) \
1265 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
1266 void *vs2, CPURISCVState *env, uint32_t desc) \
1267 { \
1268 uint32_t mlen = vext_mlen(desc); \
1269 uint32_t vl = env->vl; \
1270 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1271 uint32_t i; \
1272 \
1273 for (i = 0; i < vl; i++) { \
1274 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1275 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1276 \
1277 vext_set_elem_mask(vd, mlen, i, \
1278 DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
1279 } \
1280 for (; i < vlmax; i++) { \
1281 vext_set_elem_mask(vd, mlen, i, 0); \
1282 } \
1283 }
1284
1285 GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t, H1, DO_MADC)
1286 GEN_VEXT_VMADC_VXM(vmadc_vxm_h, uint16_t, H2, DO_MADC)
1287 GEN_VEXT_VMADC_VXM(vmadc_vxm_w, uint32_t, H4, DO_MADC)
1288 GEN_VEXT_VMADC_VXM(vmadc_vxm_d, uint64_t, H8, DO_MADC)
1289
1290 GEN_VEXT_VMADC_VXM(vmsbc_vxm_b, uint8_t, H1, DO_MSBC)
1291 GEN_VEXT_VMADC_VXM(vmsbc_vxm_h, uint16_t, H2, DO_MSBC)
1292 GEN_VEXT_VMADC_VXM(vmsbc_vxm_w, uint32_t, H4, DO_MSBC)
1293 GEN_VEXT_VMADC_VXM(vmsbc_vxm_d, uint64_t, H8, DO_MSBC)
1294
1295 /* Vector Bitwise Logical Instructions */
1296 RVVCALL(OPIVV2, vand_vv_b, OP_SSS_B, H1, H1, H1, DO_AND)
1297 RVVCALL(OPIVV2, vand_vv_h, OP_SSS_H, H2, H2, H2, DO_AND)
1298 RVVCALL(OPIVV2, vand_vv_w, OP_SSS_W, H4, H4, H4, DO_AND)
1299 RVVCALL(OPIVV2, vand_vv_d, OP_SSS_D, H8, H8, H8, DO_AND)
1300 RVVCALL(OPIVV2, vor_vv_b, OP_SSS_B, H1, H1, H1, DO_OR)
1301 RVVCALL(OPIVV2, vor_vv_h, OP_SSS_H, H2, H2, H2, DO_OR)
1302 RVVCALL(OPIVV2, vor_vv_w, OP_SSS_W, H4, H4, H4, DO_OR)
1303 RVVCALL(OPIVV2, vor_vv_d, OP_SSS_D, H8, H8, H8, DO_OR)
1304 RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR)
1305 RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR)
1306 RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR)
1307 RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR)
1308 GEN_VEXT_VV(vand_vv_b, 1, 1, clearb)
1309 GEN_VEXT_VV(vand_vv_h, 2, 2, clearh)
1310 GEN_VEXT_VV(vand_vv_w, 4, 4, clearl)
1311 GEN_VEXT_VV(vand_vv_d, 8, 8, clearq)
1312 GEN_VEXT_VV(vor_vv_b, 1, 1, clearb)
1313 GEN_VEXT_VV(vor_vv_h, 2, 2, clearh)
1314 GEN_VEXT_VV(vor_vv_w, 4, 4, clearl)
1315 GEN_VEXT_VV(vor_vv_d, 8, 8, clearq)
1316 GEN_VEXT_VV(vxor_vv_b, 1, 1, clearb)
1317 GEN_VEXT_VV(vxor_vv_h, 2, 2, clearh)
1318 GEN_VEXT_VV(vxor_vv_w, 4, 4, clearl)
1319 GEN_VEXT_VV(vxor_vv_d, 8, 8, clearq)
1320
1321 RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND)
1322 RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND)
1323 RVVCALL(OPIVX2, vand_vx_w, OP_SSS_W, H4, H4, DO_AND)
1324 RVVCALL(OPIVX2, vand_vx_d, OP_SSS_D, H8, H8, DO_AND)
1325 RVVCALL(OPIVX2, vor_vx_b, OP_SSS_B, H1, H1, DO_OR)
1326 RVVCALL(OPIVX2, vor_vx_h, OP_SSS_H, H2, H2, DO_OR)
1327 RVVCALL(OPIVX2, vor_vx_w, OP_SSS_W, H4, H4, DO_OR)
1328 RVVCALL(OPIVX2, vor_vx_d, OP_SSS_D, H8, H8, DO_OR)
1329 RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR)
1330 RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR)
1331 RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR)
1332 RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR)
1333 GEN_VEXT_VX(vand_vx_b, 1, 1, clearb)
1334 GEN_VEXT_VX(vand_vx_h, 2, 2, clearh)
1335 GEN_VEXT_VX(vand_vx_w, 4, 4, clearl)
1336 GEN_VEXT_VX(vand_vx_d, 8, 8, clearq)
1337 GEN_VEXT_VX(vor_vx_b, 1, 1, clearb)
1338 GEN_VEXT_VX(vor_vx_h, 2, 2, clearh)
1339 GEN_VEXT_VX(vor_vx_w, 4, 4, clearl)
1340 GEN_VEXT_VX(vor_vx_d, 8, 8, clearq)
1341 GEN_VEXT_VX(vxor_vx_b, 1, 1, clearb)
1342 GEN_VEXT_VX(vxor_vx_h, 2, 2, clearh)
1343 GEN_VEXT_VX(vxor_vx_w, 4, 4, clearl)
1344 GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq)
1345
1346 /* Vector Single-Width Bit Shift Instructions */
1347 #define DO_SLL(N, M) (N << (M))
1348 #define DO_SRL(N, M) (N >> (M))
1349
1350 /* generate the helpers for shift instructions with two vector operators */
1351 #define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK, CLEAR_FN) \
1352 void HELPER(NAME)(void *vd, void *v0, void *vs1, \
1353 void *vs2, CPURISCVState *env, uint32_t desc) \
1354 { \
1355 uint32_t mlen = vext_mlen(desc); \
1356 uint32_t vm = vext_vm(desc); \
1357 uint32_t vl = env->vl; \
1358 uint32_t esz = sizeof(TS1); \
1359 uint32_t vlmax = vext_maxsz(desc) / esz; \
1360 uint32_t i; \
1361 \
1362 for (i = 0; i < vl; i++) { \
1363 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1364 continue; \
1365 } \
1366 TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
1367 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
1368 *((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \
1369 } \
1370 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1371 }
1372
1373 GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7, clearb)
1374 GEN_VEXT_SHIFT_VV(vsll_vv_h, uint16_t, uint16_t, H2, H2, DO_SLL, 0xf, clearh)
1375 GEN_VEXT_SHIFT_VV(vsll_vv_w, uint32_t, uint32_t, H4, H4, DO_SLL, 0x1f, clearl)
1376 GEN_VEXT_SHIFT_VV(vsll_vv_d, uint64_t, uint64_t, H8, H8, DO_SLL, 0x3f, clearq)
1377
1378 GEN_VEXT_SHIFT_VV(vsrl_vv_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb)
1379 GEN_VEXT_SHIFT_VV(vsrl_vv_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh)
1380 GEN_VEXT_SHIFT_VV(vsrl_vv_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl)
1381 GEN_VEXT_SHIFT_VV(vsrl_vv_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq)
1382
1383 GEN_VEXT_SHIFT_VV(vsra_vv_b, uint8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb)
1384 GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh)
1385 GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
1386 GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
1387
1388 /* generate the helpers for shift instructions with one vector and one scalar */
1389 #define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK, CLEAR_FN) \
1390 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
1391 void *vs2, CPURISCVState *env, uint32_t desc) \
1392 { \
1393 uint32_t mlen = vext_mlen(desc); \
1394 uint32_t vm = vext_vm(desc); \
1395 uint32_t vl = env->vl; \
1396 uint32_t esz = sizeof(TD); \
1397 uint32_t vlmax = vext_maxsz(desc) / esz; \
1398 uint32_t i; \
1399 \
1400 for (i = 0; i < vl; i++) { \
1401 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1402 continue; \
1403 } \
1404 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
1405 *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \
1406 } \
1407 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1408 }
1409
1410 GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7, clearb)
1411 GEN_VEXT_SHIFT_VX(vsll_vx_h, uint16_t, int16_t, H2, H2, DO_SLL, 0xf, clearh)
1412 GEN_VEXT_SHIFT_VX(vsll_vx_w, uint32_t, int32_t, H4, H4, DO_SLL, 0x1f, clearl)
1413 GEN_VEXT_SHIFT_VX(vsll_vx_d, uint64_t, int64_t, H8, H8, DO_SLL, 0x3f, clearq)
1414
1415 GEN_VEXT_SHIFT_VX(vsrl_vx_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb)
1416 GEN_VEXT_SHIFT_VX(vsrl_vx_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh)
1417 GEN_VEXT_SHIFT_VX(vsrl_vx_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl)
1418 GEN_VEXT_SHIFT_VX(vsrl_vx_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq)
1419
1420 GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb)
1421 GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh)
1422 GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
1423 GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
1424
1425 /* Vector Narrowing Integer Right Shift Instructions */
1426 GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
1427 GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
1428 GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
1429 GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
1430 GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
1431 GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
1432 GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
1433 GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
1434 GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
1435 GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
1436 GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
1437 GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
1438
1439 /* Vector Integer Comparison Instructions */
1440 #define DO_MSEQ(N, M) (N == M)
1441 #define DO_MSNE(N, M) (N != M)
1442 #define DO_MSLT(N, M) (N < M)
1443 #define DO_MSLE(N, M) (N <= M)
1444 #define DO_MSGT(N, M) (N > M)
1445
1446 #define GEN_VEXT_CMP_VV(NAME, ETYPE, H, DO_OP) \
1447 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1448 CPURISCVState *env, uint32_t desc) \
1449 { \
1450 uint32_t mlen = vext_mlen(desc); \
1451 uint32_t vm = vext_vm(desc); \
1452 uint32_t vl = env->vl; \
1453 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1454 uint32_t i; \
1455 \
1456 for (i = 0; i < vl; i++) { \
1457 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1458 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1459 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1460 continue; \
1461 } \
1462 vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1)); \
1463 } \
1464 for (; i < vlmax; i++) { \
1465 vext_set_elem_mask(vd, mlen, i, 0); \
1466 } \
1467 }
1468
1469 GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
1470 GEN_VEXT_CMP_VV(vmseq_vv_h, uint16_t, H2, DO_MSEQ)
1471 GEN_VEXT_CMP_VV(vmseq_vv_w, uint32_t, H4, DO_MSEQ)
1472 GEN_VEXT_CMP_VV(vmseq_vv_d, uint64_t, H8, DO_MSEQ)
1473
1474 GEN_VEXT_CMP_VV(vmsne_vv_b, uint8_t, H1, DO_MSNE)
1475 GEN_VEXT_CMP_VV(vmsne_vv_h, uint16_t, H2, DO_MSNE)
1476 GEN_VEXT_CMP_VV(vmsne_vv_w, uint32_t, H4, DO_MSNE)
1477 GEN_VEXT_CMP_VV(vmsne_vv_d, uint64_t, H8, DO_MSNE)
1478
1479 GEN_VEXT_CMP_VV(vmsltu_vv_b, uint8_t, H1, DO_MSLT)
1480 GEN_VEXT_CMP_VV(vmsltu_vv_h, uint16_t, H2, DO_MSLT)
1481 GEN_VEXT_CMP_VV(vmsltu_vv_w, uint32_t, H4, DO_MSLT)
1482 GEN_VEXT_CMP_VV(vmsltu_vv_d, uint64_t, H8, DO_MSLT)
1483
1484 GEN_VEXT_CMP_VV(vmslt_vv_b, int8_t, H1, DO_MSLT)
1485 GEN_VEXT_CMP_VV(vmslt_vv_h, int16_t, H2, DO_MSLT)
1486 GEN_VEXT_CMP_VV(vmslt_vv_w, int32_t, H4, DO_MSLT)
1487 GEN_VEXT_CMP_VV(vmslt_vv_d, int64_t, H8, DO_MSLT)
1488
1489 GEN_VEXT_CMP_VV(vmsleu_vv_b, uint8_t, H1, DO_MSLE)
1490 GEN_VEXT_CMP_VV(vmsleu_vv_h, uint16_t, H2, DO_MSLE)
1491 GEN_VEXT_CMP_VV(vmsleu_vv_w, uint32_t, H4, DO_MSLE)
1492 GEN_VEXT_CMP_VV(vmsleu_vv_d, uint64_t, H8, DO_MSLE)
1493
1494 GEN_VEXT_CMP_VV(vmsle_vv_b, int8_t, H1, DO_MSLE)
1495 GEN_VEXT_CMP_VV(vmsle_vv_h, int16_t, H2, DO_MSLE)
1496 GEN_VEXT_CMP_VV(vmsle_vv_w, int32_t, H4, DO_MSLE)
1497 GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE)
1498
1499 #define GEN_VEXT_CMP_VX(NAME, ETYPE, H, DO_OP) \
1500 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
1501 CPURISCVState *env, uint32_t desc) \
1502 { \
1503 uint32_t mlen = vext_mlen(desc); \
1504 uint32_t vm = vext_vm(desc); \
1505 uint32_t vl = env->vl; \
1506 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1507 uint32_t i; \
1508 \
1509 for (i = 0; i < vl; i++) { \
1510 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1511 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1512 continue; \
1513 } \
1514 vext_set_elem_mask(vd, mlen, i, \
1515 DO_OP(s2, (ETYPE)(target_long)s1)); \
1516 } \
1517 for (; i < vlmax; i++) { \
1518 vext_set_elem_mask(vd, mlen, i, 0); \
1519 } \
1520 }
1521
1522 GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)
1523 GEN_VEXT_CMP_VX(vmseq_vx_h, uint16_t, H2, DO_MSEQ)
1524 GEN_VEXT_CMP_VX(vmseq_vx_w, uint32_t, H4, DO_MSEQ)
1525 GEN_VEXT_CMP_VX(vmseq_vx_d, uint64_t, H8, DO_MSEQ)
1526
1527 GEN_VEXT_CMP_VX(vmsne_vx_b, uint8_t, H1, DO_MSNE)
1528 GEN_VEXT_CMP_VX(vmsne_vx_h, uint16_t, H2, DO_MSNE)
1529 GEN_VEXT_CMP_VX(vmsne_vx_w, uint32_t, H4, DO_MSNE)
1530 GEN_VEXT_CMP_VX(vmsne_vx_d, uint64_t, H8, DO_MSNE)
1531
1532 GEN_VEXT_CMP_VX(vmsltu_vx_b, uint8_t, H1, DO_MSLT)
1533 GEN_VEXT_CMP_VX(vmsltu_vx_h, uint16_t, H2, DO_MSLT)
1534 GEN_VEXT_CMP_VX(vmsltu_vx_w, uint32_t, H4, DO_MSLT)
1535 GEN_VEXT_CMP_VX(vmsltu_vx_d, uint64_t, H8, DO_MSLT)
1536
1537 GEN_VEXT_CMP_VX(vmslt_vx_b, int8_t, H1, DO_MSLT)
1538 GEN_VEXT_CMP_VX(vmslt_vx_h, int16_t, H2, DO_MSLT)
1539 GEN_VEXT_CMP_VX(vmslt_vx_w, int32_t, H4, DO_MSLT)
1540 GEN_VEXT_CMP_VX(vmslt_vx_d, int64_t, H8, DO_MSLT)
1541
1542 GEN_VEXT_CMP_VX(vmsleu_vx_b, uint8_t, H1, DO_MSLE)
1543 GEN_VEXT_CMP_VX(vmsleu_vx_h, uint16_t, H2, DO_MSLE)
1544 GEN_VEXT_CMP_VX(vmsleu_vx_w, uint32_t, H4, DO_MSLE)
1545 GEN_VEXT_CMP_VX(vmsleu_vx_d, uint64_t, H8, DO_MSLE)
1546
1547 GEN_VEXT_CMP_VX(vmsle_vx_b, int8_t, H1, DO_MSLE)
1548 GEN_VEXT_CMP_VX(vmsle_vx_h, int16_t, H2, DO_MSLE)
1549 GEN_VEXT_CMP_VX(vmsle_vx_w, int32_t, H4, DO_MSLE)
1550 GEN_VEXT_CMP_VX(vmsle_vx_d, int64_t, H8, DO_MSLE)
1551
1552 GEN_VEXT_CMP_VX(vmsgtu_vx_b, uint8_t, H1, DO_MSGT)
1553 GEN_VEXT_CMP_VX(vmsgtu_vx_h, uint16_t, H2, DO_MSGT)
1554 GEN_VEXT_CMP_VX(vmsgtu_vx_w, uint32_t, H4, DO_MSGT)
1555 GEN_VEXT_CMP_VX(vmsgtu_vx_d, uint64_t, H8, DO_MSGT)
1556
1557 GEN_VEXT_CMP_VX(vmsgt_vx_b, int8_t, H1, DO_MSGT)
1558 GEN_VEXT_CMP_VX(vmsgt_vx_h, int16_t, H2, DO_MSGT)
1559 GEN_VEXT_CMP_VX(vmsgt_vx_w, int32_t, H4, DO_MSGT)
1560 GEN_VEXT_CMP_VX(vmsgt_vx_d, int64_t, H8, DO_MSGT)
1561
1562 /* Vector Integer Min/Max Instructions */
1563 RVVCALL(OPIVV2, vminu_vv_b, OP_UUU_B, H1, H1, H1, DO_MIN)
1564 RVVCALL(OPIVV2, vminu_vv_h, OP_UUU_H, H2, H2, H2, DO_MIN)
1565 RVVCALL(OPIVV2, vminu_vv_w, OP_UUU_W, H4, H4, H4, DO_MIN)
1566 RVVCALL(OPIVV2, vminu_vv_d, OP_UUU_D, H8, H8, H8, DO_MIN)
1567 RVVCALL(OPIVV2, vmin_vv_b, OP_SSS_B, H1, H1, H1, DO_MIN)
1568 RVVCALL(OPIVV2, vmin_vv_h, OP_SSS_H, H2, H2, H2, DO_MIN)
1569 RVVCALL(OPIVV2, vmin_vv_w, OP_SSS_W, H4, H4, H4, DO_MIN)
1570 RVVCALL(OPIVV2, vmin_vv_d, OP_SSS_D, H8, H8, H8, DO_MIN)
1571 RVVCALL(OPIVV2, vmaxu_vv_b, OP_UUU_B, H1, H1, H1, DO_MAX)
1572 RVVCALL(OPIVV2, vmaxu_vv_h, OP_UUU_H, H2, H2, H2, DO_MAX)
1573 RVVCALL(OPIVV2, vmaxu_vv_w, OP_UUU_W, H4, H4, H4, DO_MAX)
1574 RVVCALL(OPIVV2, vmaxu_vv_d, OP_UUU_D, H8, H8, H8, DO_MAX)
1575 RVVCALL(OPIVV2, vmax_vv_b, OP_SSS_B, H1, H1, H1, DO_MAX)
1576 RVVCALL(OPIVV2, vmax_vv_h, OP_SSS_H, H2, H2, H2, DO_MAX)
1577 RVVCALL(OPIVV2, vmax_vv_w, OP_SSS_W, H4, H4, H4, DO_MAX)
1578 RVVCALL(OPIVV2, vmax_vv_d, OP_SSS_D, H8, H8, H8, DO_MAX)
1579 GEN_VEXT_VV(vminu_vv_b, 1, 1, clearb)
1580 GEN_VEXT_VV(vminu_vv_h, 2, 2, clearh)
1581 GEN_VEXT_VV(vminu_vv_w, 4, 4, clearl)
1582 GEN_VEXT_VV(vminu_vv_d, 8, 8, clearq)
1583 GEN_VEXT_VV(vmin_vv_b, 1, 1, clearb)
1584 GEN_VEXT_VV(vmin_vv_h, 2, 2, clearh)
1585 GEN_VEXT_VV(vmin_vv_w, 4, 4, clearl)
1586 GEN_VEXT_VV(vmin_vv_d, 8, 8, clearq)
1587 GEN_VEXT_VV(vmaxu_vv_b, 1, 1, clearb)
1588 GEN_VEXT_VV(vmaxu_vv_h, 2, 2, clearh)
1589 GEN_VEXT_VV(vmaxu_vv_w, 4, 4, clearl)
1590 GEN_VEXT_VV(vmaxu_vv_d, 8, 8, clearq)
1591 GEN_VEXT_VV(vmax_vv_b, 1, 1, clearb)
1592 GEN_VEXT_VV(vmax_vv_h, 2, 2, clearh)
1593 GEN_VEXT_VV(vmax_vv_w, 4, 4, clearl)
1594 GEN_VEXT_VV(vmax_vv_d, 8, 8, clearq)
1595
1596 RVVCALL(OPIVX2, vminu_vx_b, OP_UUU_B, H1, H1, DO_MIN)
1597 RVVCALL(OPIVX2, vminu_vx_h, OP_UUU_H, H2, H2, DO_MIN)
1598 RVVCALL(OPIVX2, vminu_vx_w, OP_UUU_W, H4, H4, DO_MIN)
1599 RVVCALL(OPIVX2, vminu_vx_d, OP_UUU_D, H8, H8, DO_MIN)
1600 RVVCALL(OPIVX2, vmin_vx_b, OP_SSS_B, H1, H1, DO_MIN)
1601 RVVCALL(OPIVX2, vmin_vx_h, OP_SSS_H, H2, H2, DO_MIN)
1602 RVVCALL(OPIVX2, vmin_vx_w, OP_SSS_W, H4, H4, DO_MIN)
1603 RVVCALL(OPIVX2, vmin_vx_d, OP_SSS_D, H8, H8, DO_MIN)
1604 RVVCALL(OPIVX2, vmaxu_vx_b, OP_UUU_B, H1, H1, DO_MAX)
1605 RVVCALL(OPIVX2, vmaxu_vx_h, OP_UUU_H, H2, H2, DO_MAX)
1606 RVVCALL(OPIVX2, vmaxu_vx_w, OP_UUU_W, H4, H4, DO_MAX)
1607 RVVCALL(OPIVX2, vmaxu_vx_d, OP_UUU_D, H8, H8, DO_MAX)
1608 RVVCALL(OPIVX2, vmax_vx_b, OP_SSS_B, H1, H1, DO_MAX)
1609 RVVCALL(OPIVX2, vmax_vx_h, OP_SSS_H, H2, H2, DO_MAX)
1610 RVVCALL(OPIVX2, vmax_vx_w, OP_SSS_W, H4, H4, DO_MAX)
1611 RVVCALL(OPIVX2, vmax_vx_d, OP_SSS_D, H8, H8, DO_MAX)
1612 GEN_VEXT_VX(vminu_vx_b, 1, 1, clearb)
1613 GEN_VEXT_VX(vminu_vx_h, 2, 2, clearh)
1614 GEN_VEXT_VX(vminu_vx_w, 4, 4, clearl)
1615 GEN_VEXT_VX(vminu_vx_d, 8, 8, clearq)
1616 GEN_VEXT_VX(vmin_vx_b, 1, 1, clearb)
1617 GEN_VEXT_VX(vmin_vx_h, 2, 2, clearh)
1618 GEN_VEXT_VX(vmin_vx_w, 4, 4, clearl)
1619 GEN_VEXT_VX(vmin_vx_d, 8, 8, clearq)
1620 GEN_VEXT_VX(vmaxu_vx_b, 1, 1, clearb)
1621 GEN_VEXT_VX(vmaxu_vx_h, 2, 2, clearh)
1622 GEN_VEXT_VX(vmaxu_vx_w, 4, 4, clearl)
1623 GEN_VEXT_VX(vmaxu_vx_d, 8, 8, clearq)
1624 GEN_VEXT_VX(vmax_vx_b, 1, 1, clearb)
1625 GEN_VEXT_VX(vmax_vx_h, 2, 2, clearh)
1626 GEN_VEXT_VX(vmax_vx_w, 4, 4, clearl)
1627 GEN_VEXT_VX(vmax_vx_d, 8, 8, clearq)
1628
1629 /* Vector Single-Width Integer Multiply Instructions */
1630 #define DO_MUL(N, M) (N * M)
1631 RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL)
1632 RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL)
1633 RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL)
1634 RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL)
1635 GEN_VEXT_VV(vmul_vv_b, 1, 1, clearb)
1636 GEN_VEXT_VV(vmul_vv_h, 2, 2, clearh)
1637 GEN_VEXT_VV(vmul_vv_w, 4, 4, clearl)
1638 GEN_VEXT_VV(vmul_vv_d, 8, 8, clearq)
1639
1640 static int8_t do_mulh_b(int8_t s2, int8_t s1)
1641 {
1642 return (int16_t)s2 * (int16_t)s1 >> 8;
1643 }
1644
1645 static int16_t do_mulh_h(int16_t s2, int16_t s1)
1646 {
1647 return (int32_t)s2 * (int32_t)s1 >> 16;
1648 }
1649
1650 static int32_t do_mulh_w(int32_t s2, int32_t s1)
1651 {
1652 return (int64_t)s2 * (int64_t)s1 >> 32;
1653 }
1654
1655 static int64_t do_mulh_d(int64_t s2, int64_t s1)
1656 {
1657 uint64_t hi_64, lo_64;
1658
1659 muls64(&lo_64, &hi_64, s1, s2);
1660 return hi_64;
1661 }
1662
1663 static uint8_t do_mulhu_b(uint8_t s2, uint8_t s1)
1664 {
1665 return (uint16_t)s2 * (uint16_t)s1 >> 8;
1666 }
1667
1668 static uint16_t do_mulhu_h(uint16_t s2, uint16_t s1)
1669 {
1670 return (uint32_t)s2 * (uint32_t)s1 >> 16;
1671 }
1672
1673 static uint32_t do_mulhu_w(uint32_t s2, uint32_t s1)
1674 {
1675 return (uint64_t)s2 * (uint64_t)s1 >> 32;
1676 }
1677
1678 static uint64_t do_mulhu_d(uint64_t s2, uint64_t s1)
1679 {
1680 uint64_t hi_64, lo_64;
1681
1682 mulu64(&lo_64, &hi_64, s2, s1);
1683 return hi_64;
1684 }
1685
1686 static int8_t do_mulhsu_b(int8_t s2, uint8_t s1)
1687 {
1688 return (int16_t)s2 * (uint16_t)s1 >> 8;
1689 }
1690
1691 static int16_t do_mulhsu_h(int16_t s2, uint16_t s1)
1692 {
1693 return (int32_t)s2 * (uint32_t)s1 >> 16;
1694 }
1695
1696 static int32_t do_mulhsu_w(int32_t s2, uint32_t s1)
1697 {
1698 return (int64_t)s2 * (uint64_t)s1 >> 32;
1699 }
1700
1701 /*
1702 * Let A = signed operand,
1703 * B = unsigned operand
1704 * P = mulu64(A, B), unsigned product
1705 *
1706 * LET X = 2 ** 64 - A, 2's complement of A
1707 * SP = signed product
1708 * THEN
1709 * IF A < 0
1710 * SP = -X * B
1711 * = -(2 ** 64 - A) * B
1712 * = A * B - 2 ** 64 * B
1713 * = P - 2 ** 64 * B
1714 * ELSE
1715 * SP = P
1716 * THEN
1717 * HI_P -= (A < 0 ? B : 0)
1718 */
1719
1720 static int64_t do_mulhsu_d(int64_t s2, uint64_t s1)
1721 {
1722 uint64_t hi_64, lo_64;
1723
1724 mulu64(&lo_64, &hi_64, s2, s1);
1725
1726 hi_64 -= s2 < 0 ? s1 : 0;
1727 return hi_64;
1728 }
1729
1730 RVVCALL(OPIVV2, vmulh_vv_b, OP_SSS_B, H1, H1, H1, do_mulh_b)
1731 RVVCALL(OPIVV2, vmulh_vv_h, OP_SSS_H, H2, H2, H2, do_mulh_h)
1732 RVVCALL(OPIVV2, vmulh_vv_w, OP_SSS_W, H4, H4, H4, do_mulh_w)
1733 RVVCALL(OPIVV2, vmulh_vv_d, OP_SSS_D, H8, H8, H8, do_mulh_d)
1734 RVVCALL(OPIVV2, vmulhu_vv_b, OP_UUU_B, H1, H1, H1, do_mulhu_b)
1735 RVVCALL(OPIVV2, vmulhu_vv_h, OP_UUU_H, H2, H2, H2, do_mulhu_h)
1736 RVVCALL(OPIVV2, vmulhu_vv_w, OP_UUU_W, H4, H4, H4, do_mulhu_w)
1737 RVVCALL(OPIVV2, vmulhu_vv_d, OP_UUU_D, H8, H8, H8, do_mulhu_d)
1738 RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b)
1739 RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h)
1740 RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w)
1741 RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d)
1742 GEN_VEXT_VV(vmulh_vv_b, 1, 1, clearb)
1743 GEN_VEXT_VV(vmulh_vv_h, 2, 2, clearh)
1744 GEN_VEXT_VV(vmulh_vv_w, 4, 4, clearl)
1745 GEN_VEXT_VV(vmulh_vv_d, 8, 8, clearq)
1746 GEN_VEXT_VV(vmulhu_vv_b, 1, 1, clearb)
1747 GEN_VEXT_VV(vmulhu_vv_h, 2, 2, clearh)
1748 GEN_VEXT_VV(vmulhu_vv_w, 4, 4, clearl)
1749 GEN_VEXT_VV(vmulhu_vv_d, 8, 8, clearq)
1750 GEN_VEXT_VV(vmulhsu_vv_b, 1, 1, clearb)
1751 GEN_VEXT_VV(vmulhsu_vv_h, 2, 2, clearh)
1752 GEN_VEXT_VV(vmulhsu_vv_w, 4, 4, clearl)
1753 GEN_VEXT_VV(vmulhsu_vv_d, 8, 8, clearq)
1754
1755 RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL)
1756 RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL)
1757 RVVCALL(OPIVX2, vmul_vx_w, OP_SSS_W, H4, H4, DO_MUL)
1758 RVVCALL(OPIVX2, vmul_vx_d, OP_SSS_D, H8, H8, DO_MUL)
1759 RVVCALL(OPIVX2, vmulh_vx_b, OP_SSS_B, H1, H1, do_mulh_b)
1760 RVVCALL(OPIVX2, vmulh_vx_h, OP_SSS_H, H2, H2, do_mulh_h)
1761 RVVCALL(OPIVX2, vmulh_vx_w, OP_SSS_W, H4, H4, do_mulh_w)
1762 RVVCALL(OPIVX2, vmulh_vx_d, OP_SSS_D, H8, H8, do_mulh_d)
1763 RVVCALL(OPIVX2, vmulhu_vx_b, OP_UUU_B, H1, H1, do_mulhu_b)
1764 RVVCALL(OPIVX2, vmulhu_vx_h, OP_UUU_H, H2, H2, do_mulhu_h)
1765 RVVCALL(OPIVX2, vmulhu_vx_w, OP_UUU_W, H4, H4, do_mulhu_w)
1766 RVVCALL(OPIVX2, vmulhu_vx_d, OP_UUU_D, H8, H8, do_mulhu_d)
1767 RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b)
1768 RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h)
1769 RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w)
1770 RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d)
1771 GEN_VEXT_VX(vmul_vx_b, 1, 1, clearb)
1772 GEN_VEXT_VX(vmul_vx_h, 2, 2, clearh)
1773 GEN_VEXT_VX(vmul_vx_w, 4, 4, clearl)
1774 GEN_VEXT_VX(vmul_vx_d, 8, 8, clearq)
1775 GEN_VEXT_VX(vmulh_vx_b, 1, 1, clearb)
1776 GEN_VEXT_VX(vmulh_vx_h, 2, 2, clearh)
1777 GEN_VEXT_VX(vmulh_vx_w, 4, 4, clearl)
1778 GEN_VEXT_VX(vmulh_vx_d, 8, 8, clearq)
1779 GEN_VEXT_VX(vmulhu_vx_b, 1, 1, clearb)
1780 GEN_VEXT_VX(vmulhu_vx_h, 2, 2, clearh)
1781 GEN_VEXT_VX(vmulhu_vx_w, 4, 4, clearl)
1782 GEN_VEXT_VX(vmulhu_vx_d, 8, 8, clearq)
1783 GEN_VEXT_VX(vmulhsu_vx_b, 1, 1, clearb)
1784 GEN_VEXT_VX(vmulhsu_vx_h, 2, 2, clearh)
1785 GEN_VEXT_VX(vmulhsu_vx_w, 4, 4, clearl)
1786 GEN_VEXT_VX(vmulhsu_vx_d, 8, 8, clearq)
1787
1788 /* Vector Integer Divide Instructions */
1789 #define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
1790 #define DO_REMU(N, M) (unlikely(M == 0) ? N : N % M)
1791 #define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) :\
1792 unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
1793 #define DO_REM(N, M) (unlikely(M == 0) ? N :\
1794 unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
1795
1796 RVVCALL(OPIVV2, vdivu_vv_b, OP_UUU_B, H1, H1, H1, DO_DIVU)
1797 RVVCALL(OPIVV2, vdivu_vv_h, OP_UUU_H, H2, H2, H2, DO_DIVU)
1798 RVVCALL(OPIVV2, vdivu_vv_w, OP_UUU_W, H4, H4, H4, DO_DIVU)
1799 RVVCALL(OPIVV2, vdivu_vv_d, OP_UUU_D, H8, H8, H8, DO_DIVU)
1800 RVVCALL(OPIVV2, vdiv_vv_b, OP_SSS_B, H1, H1, H1, DO_DIV)
1801 RVVCALL(OPIVV2, vdiv_vv_h, OP_SSS_H, H2, H2, H2, DO_DIV)
1802 RVVCALL(OPIVV2, vdiv_vv_w, OP_SSS_W, H4, H4, H4, DO_DIV)
1803 RVVCALL(OPIVV2, vdiv_vv_d, OP_SSS_D, H8, H8, H8, DO_DIV)
1804 RVVCALL(OPIVV2, vremu_vv_b, OP_UUU_B, H1, H1, H1, DO_REMU)
1805 RVVCALL(OPIVV2, vremu_vv_h, OP_UUU_H, H2, H2, H2, DO_REMU)
1806 RVVCALL(OPIVV2, vremu_vv_w, OP_UUU_W, H4, H4, H4, DO_REMU)
1807 RVVCALL(OPIVV2, vremu_vv_d, OP_UUU_D, H8, H8, H8, DO_REMU)
1808 RVVCALL(OPIVV2, vrem_vv_b, OP_SSS_B, H1, H1, H1, DO_REM)
1809 RVVCALL(OPIVV2, vrem_vv_h, OP_SSS_H, H2, H2, H2, DO_REM)
1810 RVVCALL(OPIVV2, vrem_vv_w, OP_SSS_W, H4, H4, H4, DO_REM)
1811 RVVCALL(OPIVV2, vrem_vv_d, OP_SSS_D, H8, H8, H8, DO_REM)
1812 GEN_VEXT_VV(vdivu_vv_b, 1, 1, clearb)
1813 GEN_VEXT_VV(vdivu_vv_h, 2, 2, clearh)
1814 GEN_VEXT_VV(vdivu_vv_w, 4, 4, clearl)
1815 GEN_VEXT_VV(vdivu_vv_d, 8, 8, clearq)
1816 GEN_VEXT_VV(vdiv_vv_b, 1, 1, clearb)
1817 GEN_VEXT_VV(vdiv_vv_h, 2, 2, clearh)
1818 GEN_VEXT_VV(vdiv_vv_w, 4, 4, clearl)
1819 GEN_VEXT_VV(vdiv_vv_d, 8, 8, clearq)
1820 GEN_VEXT_VV(vremu_vv_b, 1, 1, clearb)
1821 GEN_VEXT_VV(vremu_vv_h, 2, 2, clearh)
1822 GEN_VEXT_VV(vremu_vv_w, 4, 4, clearl)
1823 GEN_VEXT_VV(vremu_vv_d, 8, 8, clearq)
1824 GEN_VEXT_VV(vrem_vv_b, 1, 1, clearb)
1825 GEN_VEXT_VV(vrem_vv_h, 2, 2, clearh)
1826 GEN_VEXT_VV(vrem_vv_w, 4, 4, clearl)
1827 GEN_VEXT_VV(vrem_vv_d, 8, 8, clearq)
1828
1829 RVVCALL(OPIVX2, vdivu_vx_b, OP_UUU_B, H1, H1, DO_DIVU)
1830 RVVCALL(OPIVX2, vdivu_vx_h, OP_UUU_H, H2, H2, DO_DIVU)
1831 RVVCALL(OPIVX2, vdivu_vx_w, OP_UUU_W, H4, H4, DO_DIVU)
1832 RVVCALL(OPIVX2, vdivu_vx_d, OP_UUU_D, H8, H8, DO_DIVU)
1833 RVVCALL(OPIVX2, vdiv_vx_b, OP_SSS_B, H1, H1, DO_DIV)
1834 RVVCALL(OPIVX2, vdiv_vx_h, OP_SSS_H, H2, H2, DO_DIV)
1835 RVVCALL(OPIVX2, vdiv_vx_w, OP_SSS_W, H4, H4, DO_DIV)
1836 RVVCALL(OPIVX2, vdiv_vx_d, OP_SSS_D, H8, H8, DO_DIV)
1837 RVVCALL(OPIVX2, vremu_vx_b, OP_UUU_B, H1, H1, DO_REMU)
1838 RVVCALL(OPIVX2, vremu_vx_h, OP_UUU_H, H2, H2, DO_REMU)
1839 RVVCALL(OPIVX2, vremu_vx_w, OP_UUU_W, H4, H4, DO_REMU)
1840 RVVCALL(OPIVX2, vremu_vx_d, OP_UUU_D, H8, H8, DO_REMU)
1841 RVVCALL(OPIVX2, vrem_vx_b, OP_SSS_B, H1, H1, DO_REM)
1842 RVVCALL(OPIVX2, vrem_vx_h, OP_SSS_H, H2, H2, DO_REM)
1843 RVVCALL(OPIVX2, vrem_vx_w, OP_SSS_W, H4, H4, DO_REM)
1844 RVVCALL(OPIVX2, vrem_vx_d, OP_SSS_D, H8, H8, DO_REM)
1845 GEN_VEXT_VX(vdivu_vx_b, 1, 1, clearb)
1846 GEN_VEXT_VX(vdivu_vx_h, 2, 2, clearh)
1847 GEN_VEXT_VX(vdivu_vx_w, 4, 4, clearl)
1848 GEN_VEXT_VX(vdivu_vx_d, 8, 8, clearq)
1849 GEN_VEXT_VX(vdiv_vx_b, 1, 1, clearb)
1850 GEN_VEXT_VX(vdiv_vx_h, 2, 2, clearh)
1851 GEN_VEXT_VX(vdiv_vx_w, 4, 4, clearl)
1852 GEN_VEXT_VX(vdiv_vx_d, 8, 8, clearq)
1853 GEN_VEXT_VX(vremu_vx_b, 1, 1, clearb)
1854 GEN_VEXT_VX(vremu_vx_h, 2, 2, clearh)
1855 GEN_VEXT_VX(vremu_vx_w, 4, 4, clearl)
1856 GEN_VEXT_VX(vremu_vx_d, 8, 8, clearq)
1857 GEN_VEXT_VX(vrem_vx_b, 1, 1, clearb)
1858 GEN_VEXT_VX(vrem_vx_h, 2, 2, clearh)
1859 GEN_VEXT_VX(vrem_vx_w, 4, 4, clearl)
1860 GEN_VEXT_VX(vrem_vx_d, 8, 8, clearq)
1861
1862 /* Vector Widening Integer Multiply Instructions */
1863 RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL)
1864 RVVCALL(OPIVV2, vwmul_vv_h, WOP_SSS_H, H4, H2, H2, DO_MUL)
1865 RVVCALL(OPIVV2, vwmul_vv_w, WOP_SSS_W, H8, H4, H4, DO_MUL)
1866 RVVCALL(OPIVV2, vwmulu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MUL)
1867 RVVCALL(OPIVV2, vwmulu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MUL)
1868 RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL)
1869 RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL)
1870 RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL)
1871 RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL)
1872 GEN_VEXT_VV(vwmul_vv_b, 1, 2, clearh)
1873 GEN_VEXT_VV(vwmul_vv_h, 2, 4, clearl)
1874 GEN_VEXT_VV(vwmul_vv_w, 4, 8, clearq)
1875 GEN_VEXT_VV(vwmulu_vv_b, 1, 2, clearh)
1876 GEN_VEXT_VV(vwmulu_vv_h, 2, 4, clearl)
1877 GEN_VEXT_VV(vwmulu_vv_w, 4, 8, clearq)
1878 GEN_VEXT_VV(vwmulsu_vv_b, 1, 2, clearh)
1879 GEN_VEXT_VV(vwmulsu_vv_h, 2, 4, clearl)
1880 GEN_VEXT_VV(vwmulsu_vv_w, 4, 8, clearq)
1881
1882 RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL)
1883 RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL)
1884 RVVCALL(OPIVX2, vwmul_vx_w, WOP_SSS_W, H8, H4, DO_MUL)
1885 RVVCALL(OPIVX2, vwmulu_vx_b, WOP_UUU_B, H2, H1, DO_MUL)
1886 RVVCALL(OPIVX2, vwmulu_vx_h, WOP_UUU_H, H4, H2, DO_MUL)
1887 RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL)
1888 RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL)
1889 RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL)
1890 RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL)
1891 GEN_VEXT_VX(vwmul_vx_b, 1, 2, clearh)
1892 GEN_VEXT_VX(vwmul_vx_h, 2, 4, clearl)
1893 GEN_VEXT_VX(vwmul_vx_w, 4, 8, clearq)
1894 GEN_VEXT_VX(vwmulu_vx_b, 1, 2, clearh)
1895 GEN_VEXT_VX(vwmulu_vx_h, 2, 4, clearl)
1896 GEN_VEXT_VX(vwmulu_vx_w, 4, 8, clearq)
1897 GEN_VEXT_VX(vwmulsu_vx_b, 1, 2, clearh)
1898 GEN_VEXT_VX(vwmulsu_vx_h, 2, 4, clearl)
1899 GEN_VEXT_VX(vwmulsu_vx_w, 4, 8, clearq)
1900
1901 /* Vector Single-Width Integer Multiply-Add Instructions */
1902 #define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
1903 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
1904 { \
1905 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
1906 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
1907 TD d = *((TD *)vd + HD(i)); \
1908 *((TD *)vd + HD(i)) = OP(s2, s1, d); \
1909 }
1910
1911 #define DO_MACC(N, M, D) (M * N + D)
1912 #define DO_NMSAC(N, M, D) (-(M * N) + D)
1913 #define DO_MADD(N, M, D) (M * D + N)
1914 #define DO_NMSUB(N, M, D) (-(M * D) + N)
1915 RVVCALL(OPIVV3, vmacc_vv_b, OP_SSS_B, H1, H1, H1, DO_MACC)
1916 RVVCALL(OPIVV3, vmacc_vv_h, OP_SSS_H, H2, H2, H2, DO_MACC)
1917 RVVCALL(OPIVV3, vmacc_vv_w, OP_SSS_W, H4, H4, H4, DO_MACC)
1918 RVVCALL(OPIVV3, vmacc_vv_d, OP_SSS_D, H8, H8, H8, DO_MACC)
1919 RVVCALL(OPIVV3, vnmsac_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSAC)
1920 RVVCALL(OPIVV3, vnmsac_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSAC)
1921 RVVCALL(OPIVV3, vnmsac_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSAC)
1922 RVVCALL(OPIVV3, vnmsac_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSAC)
1923 RVVCALL(OPIVV3, vmadd_vv_b, OP_SSS_B, H1, H1, H1, DO_MADD)
1924 RVVCALL(OPIVV3, vmadd_vv_h, OP_SSS_H, H2, H2, H2, DO_MADD)
1925 RVVCALL(OPIVV3, vmadd_vv_w, OP_SSS_W, H4, H4, H4, DO_MADD)
1926 RVVCALL(OPIVV3, vmadd_vv_d, OP_SSS_D, H8, H8, H8, DO_MADD)
1927 RVVCALL(OPIVV3, vnmsub_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSUB)
1928 RVVCALL(OPIVV3, vnmsub_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSUB)
1929 RVVCALL(OPIVV3, vnmsub_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSUB)
1930 RVVCALL(OPIVV3, vnmsub_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSUB)
1931 GEN_VEXT_VV(vmacc_vv_b, 1, 1, clearb)
1932 GEN_VEXT_VV(vmacc_vv_h, 2, 2, clearh)
1933 GEN_VEXT_VV(vmacc_vv_w, 4, 4, clearl)
1934 GEN_VEXT_VV(vmacc_vv_d, 8, 8, clearq)
1935 GEN_VEXT_VV(vnmsac_vv_b, 1, 1, clearb)
1936 GEN_VEXT_VV(vnmsac_vv_h, 2, 2, clearh)
1937 GEN_VEXT_VV(vnmsac_vv_w, 4, 4, clearl)
1938 GEN_VEXT_VV(vnmsac_vv_d, 8, 8, clearq)
1939 GEN_VEXT_VV(vmadd_vv_b, 1, 1, clearb)
1940 GEN_VEXT_VV(vmadd_vv_h, 2, 2, clearh)
1941 GEN_VEXT_VV(vmadd_vv_w, 4, 4, clearl)
1942 GEN_VEXT_VV(vmadd_vv_d, 8, 8, clearq)
1943 GEN_VEXT_VV(vnmsub_vv_b, 1, 1, clearb)
1944 GEN_VEXT_VV(vnmsub_vv_h, 2, 2, clearh)
1945 GEN_VEXT_VV(vnmsub_vv_w, 4, 4, clearl)
1946 GEN_VEXT_VV(vnmsub_vv_d, 8, 8, clearq)
1947
1948 #define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
1949 static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \
1950 { \
1951 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
1952 TD d = *((TD *)vd + HD(i)); \
1953 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, d); \
1954 }
1955
1956 RVVCALL(OPIVX3, vmacc_vx_b, OP_SSS_B, H1, H1, DO_MACC)
1957 RVVCALL(OPIVX3, vmacc_vx_h, OP_SSS_H, H2, H2, DO_MACC)
1958 RVVCALL(OPIVX3, vmacc_vx_w, OP_SSS_W, H4, H4, DO_MACC)
1959 RVVCALL(OPIVX3, vmacc_vx_d, OP_SSS_D, H8, H8, DO_MACC)
1960 RVVCALL(OPIVX3, vnmsac_vx_b, OP_SSS_B, H1, H1, DO_NMSAC)
1961 RVVCALL(OPIVX3, vnmsac_vx_h, OP_SSS_H, H2, H2, DO_NMSAC)
1962 RVVCALL(OPIVX3, vnmsac_vx_w, OP_SSS_W, H4, H4, DO_NMSAC)
1963 RVVCALL(OPIVX3, vnmsac_vx_d, OP_SSS_D, H8, H8, DO_NMSAC)
1964 RVVCALL(OPIVX3, vmadd_vx_b, OP_SSS_B, H1, H1, DO_MADD)
1965 RVVCALL(OPIVX3, vmadd_vx_h, OP_SSS_H, H2, H2, DO_MADD)
1966 RVVCALL(OPIVX3, vmadd_vx_w, OP_SSS_W, H4, H4, DO_MADD)
1967 RVVCALL(OPIVX3, vmadd_vx_d, OP_SSS_D, H8, H8, DO_MADD)
1968 RVVCALL(OPIVX3, vnmsub_vx_b, OP_SSS_B, H1, H1, DO_NMSUB)
1969 RVVCALL(OPIVX3, vnmsub_vx_h, OP_SSS_H, H2, H2, DO_NMSUB)
1970 RVVCALL(OPIVX3, vnmsub_vx_w, OP_SSS_W, H4, H4, DO_NMSUB)
1971 RVVCALL(OPIVX3, vnmsub_vx_d, OP_SSS_D, H8, H8, DO_NMSUB)
1972 GEN_VEXT_VX(vmacc_vx_b, 1, 1, clearb)
1973 GEN_VEXT_VX(vmacc_vx_h, 2, 2, clearh)
1974 GEN_VEXT_VX(vmacc_vx_w, 4, 4, clearl)
1975 GEN_VEXT_VX(vmacc_vx_d, 8, 8, clearq)
1976 GEN_VEXT_VX(vnmsac_vx_b, 1, 1, clearb)
1977 GEN_VEXT_VX(vnmsac_vx_h, 2, 2, clearh)
1978 GEN_VEXT_VX(vnmsac_vx_w, 4, 4, clearl)
1979 GEN_VEXT_VX(vnmsac_vx_d, 8, 8, clearq)
1980 GEN_VEXT_VX(vmadd_vx_b, 1, 1, clearb)
1981 GEN_VEXT_VX(vmadd_vx_h, 2, 2, clearh)
1982 GEN_VEXT_VX(vmadd_vx_w, 4, 4, clearl)
1983 GEN_VEXT_VX(vmadd_vx_d, 8, 8, clearq)
1984 GEN_VEXT_VX(vnmsub_vx_b, 1, 1, clearb)
1985 GEN_VEXT_VX(vnmsub_vx_h, 2, 2, clearh)
1986 GEN_VEXT_VX(vnmsub_vx_w, 4, 4, clearl)
1987 GEN_VEXT_VX(vnmsub_vx_d, 8, 8, clearq)
1988
1989 /* Vector Widening Integer Multiply-Add Instructions */
1990 RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC)
1991 RVVCALL(OPIVV3, vwmaccu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MACC)
1992 RVVCALL(OPIVV3, vwmaccu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MACC)
1993 RVVCALL(OPIVV3, vwmacc_vv_b, WOP_SSS_B, H2, H1, H1, DO_MACC)
1994 RVVCALL(OPIVV3, vwmacc_vv_h, WOP_SSS_H, H4, H2, H2, DO_MACC)
1995 RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC)
1996 RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC)
1997 RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC)
1998 RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC)
1999 GEN_VEXT_VV(vwmaccu_vv_b, 1, 2, clearh)
2000 GEN_VEXT_VV(vwmaccu_vv_h, 2, 4, clearl)
2001 GEN_VEXT_VV(vwmaccu_vv_w, 4, 8, clearq)
2002 GEN_VEXT_VV(vwmacc_vv_b, 1, 2, clearh)
2003 GEN_VEXT_VV(vwmacc_vv_h, 2, 4, clearl)
2004 GEN_VEXT_VV(vwmacc_vv_w, 4, 8, clearq)
2005 GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2, clearh)
2006 GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4, clearl)
2007 GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8, clearq)
2008
2009 RVVCALL(OPIVX3, vwmaccu_vx_b, WOP_UUU_B, H2, H1, DO_MACC)
2010 RVVCALL(OPIVX3, vwmaccu_vx_h, WOP_UUU_H, H4, H2, DO_MACC)
2011 RVVCALL(OPIVX3, vwmaccu_vx_w, WOP_UUU_W, H8, H4, DO_MACC)
2012 RVVCALL(OPIVX3, vwmacc_vx_b, WOP_SSS_B, H2, H1, DO_MACC)
2013 RVVCALL(OPIVX3, vwmacc_vx_h, WOP_SSS_H, H4, H2, DO_MACC)
2014 RVVCALL(OPIVX3, vwmacc_vx_w, WOP_SSS_W, H8, H4, DO_MACC)
2015 RVVCALL(OPIVX3, vwmaccsu_vx_b, WOP_SSU_B, H2, H1, DO_MACC)
2016 RVVCALL(OPIVX3, vwmaccsu_vx_h, WOP_SSU_H, H4, H2, DO_MACC)
2017 RVVCALL(OPIVX3, vwmaccsu_vx_w, WOP_SSU_W, H8, H4, DO_MACC)
2018 RVVCALL(OPIVX3, vwmaccus_vx_b, WOP_SUS_B, H2, H1, DO_MACC)
2019 RVVCALL(OPIVX3, vwmaccus_vx_h, WOP_SUS_H, H4, H2, DO_MACC)
2020 RVVCALL(OPIVX3, vwmaccus_vx_w, WOP_SUS_W, H8, H4, DO_MACC)
2021 GEN_VEXT_VX(vwmaccu_vx_b, 1, 2, clearh)
2022 GEN_VEXT_VX(vwmaccu_vx_h, 2, 4, clearl)
2023 GEN_VEXT_VX(vwmaccu_vx_w, 4, 8, clearq)
2024 GEN_VEXT_VX(vwmacc_vx_b, 1, 2, clearh)
2025 GEN_VEXT_VX(vwmacc_vx_h, 2, 4, clearl)
2026 GEN_VEXT_VX(vwmacc_vx_w, 4, 8, clearq)
2027 GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2, clearh)
2028 GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4, clearl)
2029 GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8, clearq)
2030 GEN_VEXT_VX(vwmaccus_vx_b, 1, 2, clearh)
2031 GEN_VEXT_VX(vwmaccus_vx_h, 2, 4, clearl)
2032 GEN_VEXT_VX(vwmaccus_vx_w, 4, 8, clearq)
2033
2034 /* Vector Integer Merge and Move Instructions */
2035 #define GEN_VEXT_VMV_VV(NAME, ETYPE, H, CLEAR_FN) \
2036 void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \
2037 uint32_t desc) \
2038 { \
2039 uint32_t vl = env->vl; \
2040 uint32_t esz = sizeof(ETYPE); \
2041 uint32_t vlmax = vext_maxsz(desc) / esz; \
2042 uint32_t i; \
2043 \
2044 for (i = 0; i < vl; i++) { \
2045 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
2046 *((ETYPE *)vd + H(i)) = s1; \
2047 } \
2048 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
2049 }
2050
2051 GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1, clearb)
2052 GEN_VEXT_VMV_VV(vmv_v_v_h, int16_t, H2, clearh)
2053 GEN_VEXT_VMV_VV(vmv_v_v_w, int32_t, H4, clearl)
2054 GEN_VEXT_VMV_VV(vmv_v_v_d, int64_t, H8, clearq)
2055
2056 #define GEN_VEXT_VMV_VX(NAME, ETYPE, H, CLEAR_FN) \
2057 void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \
2058 uint32_t desc) \
2059 { \
2060 uint32_t vl = env->vl; \
2061 uint32_t esz = sizeof(ETYPE); \
2062 uint32_t vlmax = vext_maxsz(desc) / esz; \
2063 uint32_t i; \
2064 \
2065 for (i = 0; i < vl; i++) { \
2066 *((ETYPE *)vd + H(i)) = (ETYPE)s1; \
2067 } \
2068 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
2069 }
2070
2071 GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1, clearb)
2072 GEN_VEXT_VMV_VX(vmv_v_x_h, int16_t, H2, clearh)
2073 GEN_VEXT_VMV_VX(vmv_v_x_w, int32_t, H4, clearl)
2074 GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8, clearq)
2075
2076 #define GEN_VEXT_VMERGE_VV(NAME, ETYPE, H, CLEAR_FN) \
2077 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
2078 CPURISCVState *env, uint32_t desc) \
2079 { \
2080 uint32_t mlen = vext_mlen(desc); \
2081 uint32_t vl = env->vl; \
2082 uint32_t esz = sizeof(ETYPE); \
2083 uint32_t vlmax = vext_maxsz(desc) / esz; \
2084 uint32_t i; \
2085 \
2086 for (i = 0; i < vl; i++) { \
2087 ETYPE *vt = (!vext_elem_mask(v0, mlen, i) ? vs2 : vs1); \
2088 *((ETYPE *)vd + H(i)) = *(vt + H(i)); \
2089 } \
2090 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
2091 }
2092
2093 GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1, clearb)
2094 GEN_VEXT_VMERGE_VV(vmerge_vvm_h, int16_t, H2, clearh)
2095 GEN_VEXT_VMERGE_VV(vmerge_vvm_w, int32_t, H4, clearl)
2096 GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8, clearq)
2097
2098 #define GEN_VEXT_VMERGE_VX(NAME, ETYPE, H, CLEAR_FN) \
2099 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
2100 void *vs2, CPURISCVState *env, uint32_t desc) \
2101 { \
2102 uint32_t mlen = vext_mlen(desc); \
2103 uint32_t vl = env->vl; \
2104 uint32_t esz = sizeof(ETYPE); \
2105 uint32_t vlmax = vext_maxsz(desc) / esz; \
2106 uint32_t i; \
2107 \
2108 for (i = 0; i < vl; i++) { \
2109 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
2110 ETYPE d = (!vext_elem_mask(v0, mlen, i) ? s2 : \
2111 (ETYPE)(target_long)s1); \
2112 *((ETYPE *)vd + H(i)) = d; \
2113 } \
2114 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
2115 }
2116
2117 GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1, clearb)
2118 GEN_VEXT_VMERGE_VX(vmerge_vxm_h, int16_t, H2, clearh)
2119 GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4, clearl)
2120 GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8, clearq)
2121
2122 /*
2123 *** Vector Fixed-Point Arithmetic Instructions
2124 */
2125
2126 /* Vector Single-Width Saturating Add and Subtract */
2127
2128 /*
2129 * As fixed point instructions probably have round mode and saturation,
2130 * define common macros for fixed point here.
2131 */
2132 typedef void opivv2_rm_fn(void *vd, void *vs1, void *vs2, int i,
2133 CPURISCVState *env, int vxrm);
2134
2135 #define OPIVV2_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
2136 static inline void \
2137 do_##NAME(void *vd, void *vs1, void *vs2, int i, \
2138 CPURISCVState *env, int vxrm) \
2139 { \
2140 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
2141 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
2142 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1); \
2143 }
2144
2145 static inline void
2146 vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2,
2147 CPURISCVState *env,
2148 uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm,
2149 opivv2_rm_fn *fn)
2150 {
2151 for (uint32_t i = 0; i < vl; i++) {
2152 if (!vm && !vext_elem_mask(v0, mlen, i)) {
2153 continue;
2154 }
2155 fn(vd, vs1, vs2, i, env, vxrm);
2156 }
2157 }
2158
2159 static inline void
2160 vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
2161 CPURISCVState *env,
2162 uint32_t desc, uint32_t esz, uint32_t dsz,
2163 opivv2_rm_fn *fn, clear_fn *clearfn)
2164 {
2165 uint32_t vlmax = vext_maxsz(desc) / esz;
2166 uint32_t mlen = vext_mlen(desc);
2167 uint32_t vm = vext_vm(desc);
2168 uint32_t vl = env->vl;
2169
2170 switch (env->vxrm) {
2171 case 0: /* rnu */
2172 vext_vv_rm_1(vd, v0, vs1, vs2,
2173 env, vl, vm, mlen, 0, fn);
2174 break;
2175 case 1: /* rne */
2176 vext_vv_rm_1(vd, v0, vs1, vs2,
2177 env, vl, vm, mlen, 1, fn);
2178 break;
2179 case 2: /* rdn */
2180 vext_vv_rm_1(vd, v0, vs1, vs2,
2181 env, vl, vm, mlen, 2, fn);
2182 break;
2183 default: /* rod */
2184 vext_vv_rm_1(vd, v0, vs1, vs2,
2185 env, vl, vm, mlen, 3, fn);
2186 break;
2187 }
2188
2189 clearfn(vd, vl, vl * dsz, vlmax * dsz);
2190 }
2191
2192 /* generate helpers for fixed point instructions with OPIVV format */
2193 #define GEN_VEXT_VV_RM(NAME, ESZ, DSZ, CLEAR_FN) \
2194 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
2195 CPURISCVState *env, uint32_t desc) \
2196 { \
2197 vext_vv_rm_2(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \
2198 do_##NAME, CLEAR_FN); \
2199 }
2200
2201 static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
2202 {
2203 uint8_t res = a + b;
2204 if (res < a) {
2205 res = UINT8_MAX;
2206 env->vxsat = 0x1;
2207 }
2208 return res;
2209 }
2210
2211 static inline uint16_t saddu16(CPURISCVState *env, int vxrm, uint16_t a,
2212 uint16_t b)
2213 {
2214 uint16_t res = a + b;
2215 if (res < a) {
2216 res = UINT16_MAX;
2217 env->vxsat = 0x1;
2218 }
2219 return res;
2220 }
2221
2222 static inline uint32_t saddu32(CPURISCVState *env, int vxrm, uint32_t a,
2223 uint32_t b)
2224 {
2225 uint32_t res = a + b;
2226 if (res < a) {
2227 res = UINT32_MAX;
2228 env->vxsat = 0x1;
2229 }
2230 return res;
2231 }
2232
2233 static inline uint64_t saddu64(CPURISCVState *env, int vxrm, uint64_t a,
2234 uint64_t b)
2235 {
2236 uint64_t res = a + b;
2237 if (res < a) {
2238 res = UINT64_MAX;
2239 env->vxsat = 0x1;
2240 }
2241 return res;
2242 }
2243
2244 RVVCALL(OPIVV2_RM, vsaddu_vv_b, OP_UUU_B, H1, H1, H1, saddu8)
2245 RVVCALL(OPIVV2_RM, vsaddu_vv_h, OP_UUU_H, H2, H2, H2, saddu16)
2246 RVVCALL(OPIVV2_RM, vsaddu_vv_w, OP_UUU_W, H4, H4, H4, saddu32)
2247 RVVCALL(OPIVV2_RM, vsaddu_vv_d, OP_UUU_D, H8, H8, H8, saddu64)
2248 GEN_VEXT_VV_RM(vsaddu_vv_b, 1, 1, clearb)
2249 GEN_VEXT_VV_RM(vsaddu_vv_h, 2, 2, clearh)
2250 GEN_VEXT_VV_RM(vsaddu_vv_w, 4, 4, clearl)
2251 GEN_VEXT_VV_RM(vsaddu_vv_d, 8, 8, clearq)
2252
2253 typedef void opivx2_rm_fn(void *vd, target_long s1, void *vs2, int i,
2254 CPURISCVState *env, int vxrm);
2255
2256 #define OPIVX2_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
2257 static inline void \
2258 do_##NAME(void *vd, target_long s1, void *vs2, int i, \
2259 CPURISCVState *env, int vxrm) \
2260 { \
2261 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
2262 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1); \
2263 }
2264
2265 static inline void
2266 vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2,
2267 CPURISCVState *env,
2268 uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm,
2269 opivx2_rm_fn *fn)
2270 {
2271 for (uint32_t i = 0; i < vl; i++) {
2272 if (!vm && !vext_elem_mask(v0, mlen, i)) {
2273 continue;
2274 }
2275 fn(vd, s1, vs2, i, env, vxrm);
2276 }
2277 }
2278
2279 static inline void
2280 vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
2281 CPURISCVState *env,
2282 uint32_t desc, uint32_t esz, uint32_t dsz,
2283 opivx2_rm_fn *fn, clear_fn *clearfn)
2284 {
2285 uint32_t vlmax = vext_maxsz(desc) / esz;
2286 uint32_t mlen = vext_mlen(desc);
2287 uint32_t vm = vext_vm(desc);
2288 uint32_t vl = env->vl;
2289
2290 switch (env->vxrm) {
2291 case 0: /* rnu */
2292 vext_vx_rm_1(vd, v0, s1, vs2,
2293 env, vl, vm, mlen, 0, fn);
2294 break;
2295 case 1: /* rne */
2296 vext_vx_rm_1(vd, v0, s1, vs2,
2297 env, vl, vm, mlen, 1, fn);
2298 break;
2299 case 2: /* rdn */
2300 vext_vx_rm_1(vd, v0, s1, vs2,
2301 env, vl, vm, mlen, 2, fn);
2302 break;
2303 default: /* rod */
2304 vext_vx_rm_1(vd, v0, s1, vs2,
2305 env, vl, vm, mlen, 3, fn);
2306 break;
2307 }
2308
2309 clearfn(vd, vl, vl * dsz, vlmax * dsz);
2310 }
2311
2312 /* generate helpers for fixed point instructions with OPIVX format */
2313 #define GEN_VEXT_VX_RM(NAME, ESZ, DSZ, CLEAR_FN) \
2314 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
2315 void *vs2, CPURISCVState *env, uint32_t desc) \
2316 { \
2317 vext_vx_rm_2(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \
2318 do_##NAME, CLEAR_FN); \
2319 }
2320
2321 RVVCALL(OPIVX2_RM, vsaddu_vx_b, OP_UUU_B, H1, H1, saddu8)
2322 RVVCALL(OPIVX2_RM, vsaddu_vx_h, OP_UUU_H, H2, H2, saddu16)
2323 RVVCALL(OPIVX2_RM, vsaddu_vx_w, OP_UUU_W, H4, H4, saddu32)
2324 RVVCALL(OPIVX2_RM, vsaddu_vx_d, OP_UUU_D, H8, H8, saddu64)
2325 GEN_VEXT_VX_RM(vsaddu_vx_b, 1, 1, clearb)
2326 GEN_VEXT_VX_RM(vsaddu_vx_h, 2, 2, clearh)
2327 GEN_VEXT_VX_RM(vsaddu_vx_w, 4, 4, clearl)
2328 GEN_VEXT_VX_RM(vsaddu_vx_d, 8, 8, clearq)
2329
2330 static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
2331 {
2332 int8_t res = a + b;
2333 if ((res ^ a) & (res ^ b) & INT8_MIN) {
2334 res = a > 0 ? INT8_MAX : INT8_MIN;
2335 env->vxsat = 0x1;
2336 }
2337 return res;
2338 }
2339
2340 static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
2341 {
2342 int16_t res = a + b;
2343 if ((res ^ a) & (res ^ b) & INT16_MIN) {
2344 res = a > 0 ? INT16_MAX : INT16_MIN;
2345 env->vxsat = 0x1;
2346 }
2347 return res;
2348 }
2349
2350 static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
2351 {
2352 int32_t res = a + b;
2353 if ((res ^ a) & (res ^ b) & INT32_MIN) {
2354 res = a > 0 ? INT32_MAX : INT32_MIN;
2355 env->vxsat = 0x1;
2356 }
2357 return res;
2358 }
2359
2360 static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
2361 {
2362 int64_t res = a + b;
2363 if ((res ^ a) & (res ^ b) & INT64_MIN) {
2364 res = a > 0 ? INT64_MAX : INT64_MIN;
2365 env->vxsat = 0x1;
2366 }
2367 return res;
2368 }
2369
2370 RVVCALL(OPIVV2_RM, vsadd_vv_b, OP_SSS_B, H1, H1, H1, sadd8)
2371 RVVCALL(OPIVV2_RM, vsadd_vv_h, OP_SSS_H, H2, H2, H2, sadd16)
2372 RVVCALL(OPIVV2_RM, vsadd_vv_w, OP_SSS_W, H4, H4, H4, sadd32)
2373 RVVCALL(OPIVV2_RM, vsadd_vv_d, OP_SSS_D, H8, H8, H8, sadd64)
2374 GEN_VEXT_VV_RM(vsadd_vv_b, 1, 1, clearb)
2375 GEN_VEXT_VV_RM(vsadd_vv_h, 2, 2, clearh)
2376 GEN_VEXT_VV_RM(vsadd_vv_w, 4, 4, clearl)
2377 GEN_VEXT_VV_RM(vsadd_vv_d, 8, 8, clearq)
2378
2379 RVVCALL(OPIVX2_RM, vsadd_vx_b, OP_SSS_B, H1, H1, sadd8)
2380 RVVCALL(OPIVX2_RM, vsadd_vx_h, OP_SSS_H, H2, H2, sadd16)
2381 RVVCALL(OPIVX2_RM, vsadd_vx_w, OP_SSS_W, H4, H4, sadd32)
2382 RVVCALL(OPIVX2_RM, vsadd_vx_d, OP_SSS_D, H8, H8, sadd64)
2383 GEN_VEXT_VX_RM(vsadd_vx_b, 1, 1, clearb)
2384 GEN_VEXT_VX_RM(vsadd_vx_h, 2, 2, clearh)
2385 GEN_VEXT_VX_RM(vsadd_vx_w, 4, 4, clearl)
2386 GEN_VEXT_VX_RM(vsadd_vx_d, 8, 8, clearq)
2387
2388 static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
2389 {
2390 uint8_t res = a - b;
2391 if (res > a) {
2392 res = 0;
2393 env->vxsat = 0x1;
2394 }
2395 return res;
2396 }
2397
2398 static inline uint16_t ssubu16(CPURISCVState *env, int vxrm, uint16_t a,
2399 uint16_t b)
2400 {
2401 uint16_t res = a - b;
2402 if (res > a) {
2403 res = 0;
2404 env->vxsat = 0x1;
2405 }
2406 return res;
2407 }
2408
2409 static inline uint32_t ssubu32(CPURISCVState *env, int vxrm, uint32_t a,
2410 uint32_t b)
2411 {
2412 uint32_t res = a - b;
2413 if (res > a) {
2414 res = 0;
2415 env->vxsat = 0x1;
2416 }
2417 return res;
2418 }
2419
2420 static inline uint64_t ssubu64(CPURISCVState *env, int vxrm, uint64_t a,
2421 uint64_t b)
2422 {
2423 uint64_t res = a - b;
2424 if (res > a) {
2425 res = 0;
2426 env->vxsat = 0x1;
2427 }
2428 return res;
2429 }
2430
2431 RVVCALL(OPIVV2_RM, vssubu_vv_b, OP_UUU_B, H1, H1, H1, ssubu8)
2432 RVVCALL(OPIVV2_RM, vssubu_vv_h, OP_UUU_H, H2, H2, H2, ssubu16)
2433 RVVCALL(OPIVV2_RM, vssubu_vv_w, OP_UUU_W, H4, H4, H4, ssubu32)
2434 RVVCALL(OPIVV2_RM, vssubu_vv_d, OP_UUU_D, H8, H8, H8, ssubu64)
2435 GEN_VEXT_VV_RM(vssubu_vv_b, 1, 1, clearb)
2436 GEN_VEXT_VV_RM(vssubu_vv_h, 2, 2, clearh)
2437 GEN_VEXT_VV_RM(vssubu_vv_w, 4, 4, clearl)
2438 GEN_VEXT_VV_RM(vssubu_vv_d, 8, 8, clearq)
2439
2440 RVVCALL(OPIVX2_RM, vssubu_vx_b, OP_UUU_B, H1, H1, ssubu8)
2441 RVVCALL(OPIVX2_RM, vssubu_vx_h, OP_UUU_H, H2, H2, ssubu16)
2442 RVVCALL(OPIVX2_RM, vssubu_vx_w, OP_UUU_W, H4, H4, ssubu32)
2443 RVVCALL(OPIVX2_RM, vssubu_vx_d, OP_UUU_D, H8, H8, ssubu64)
2444 GEN_VEXT_VX_RM(vssubu_vx_b, 1, 1, clearb)
2445 GEN_VEXT_VX_RM(vssubu_vx_h, 2, 2, clearh)
2446 GEN_VEXT_VX_RM(vssubu_vx_w, 4, 4, clearl)
2447 GEN_VEXT_VX_RM(vssubu_vx_d, 8, 8, clearq)
2448
2449 static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
2450 {
2451 int8_t res = a - b;
2452 if ((res ^ a) & (a ^ b) & INT8_MIN) {
2453 res = a > 0 ? INT8_MAX : INT8_MIN;
2454 env->vxsat = 0x1;
2455 }
2456 return res;
2457 }
2458
2459 static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
2460 {
2461 int16_t res = a - b;
2462 if ((res ^ a) & (a ^ b) & INT16_MIN) {
2463 res = a > 0 ? INT16_MAX : INT16_MIN;
2464 env->vxsat = 0x1;
2465 }
2466 return res;
2467 }
2468
2469 static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
2470 {
2471 int32_t res = a - b;
2472 if ((res ^ a) & (a ^ b) & INT32_MIN) {
2473 res = a > 0 ? INT32_MAX : INT32_MIN;
2474 env->vxsat = 0x1;
2475 }
2476 return res;
2477 }
2478
2479 static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
2480 {
2481 int64_t res = a - b;
2482 if ((res ^ a) & (a ^ b) & INT64_MIN) {
2483 res = a > 0 ? INT64_MAX : INT64_MIN;
2484 env->vxsat = 0x1;
2485 }
2486 return res;
2487 }
2488
2489 RVVCALL(OPIVV2_RM, vssub_vv_b, OP_SSS_B, H1, H1, H1, ssub8)
2490 RVVCALL(OPIVV2_RM, vssub_vv_h, OP_SSS_H, H2, H2, H2, ssub16)
2491 RVVCALL(OPIVV2_RM, vssub_vv_w, OP_SSS_W, H4, H4, H4, ssub32)
2492 RVVCALL(OPIVV2_RM, vssub_vv_d, OP_SSS_D, H8, H8, H8, ssub64)
2493 GEN_VEXT_VV_RM(vssub_vv_b, 1, 1, clearb)
2494 GEN_VEXT_VV_RM(vssub_vv_h, 2, 2, clearh)
2495 GEN_VEXT_VV_RM(vssub_vv_w, 4, 4, clearl)
2496 GEN_VEXT_VV_RM(vssub_vv_d, 8, 8, clearq)
2497
2498 RVVCALL(OPIVX2_RM, vssub_vx_b, OP_SSS_B, H1, H1, ssub8)
2499 RVVCALL(OPIVX2_RM, vssub_vx_h, OP_SSS_H, H2, H2, ssub16)
2500 RVVCALL(OPIVX2_RM, vssub_vx_w, OP_SSS_W, H4, H4, ssub32)
2501 RVVCALL(OPIVX2_RM, vssub_vx_d, OP_SSS_D, H8, H8, ssub64)
2502 GEN_VEXT_VX_RM(vssub_vx_b, 1, 1, clearb)
2503 GEN_VEXT_VX_RM(vssub_vx_h, 2, 2, clearh)
2504 GEN_VEXT_VX_RM(vssub_vx_w, 4, 4, clearl)
2505 GEN_VEXT_VX_RM(vssub_vx_d, 8, 8, clearq)
2506
2507 /* Vector Single-Width Averaging Add and Subtract */
2508 static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift)
2509 {
2510 uint8_t d = extract64(v, shift, 1);
2511 uint8_t d1;
2512 uint64_t D1, D2;
2513
2514 if (shift == 0 || shift > 64) {
2515 return 0;
2516 }
2517
2518 d1 = extract64(v, shift - 1, 1);
2519 D1 = extract64(v, 0, shift);
2520 if (vxrm == 0) { /* round-to-nearest-up (add +0.5 LSB) */
2521 return d1;
2522 } else if (vxrm == 1) { /* round-to-nearest-even */
2523 if (shift > 1) {
2524 D2 = extract64(v, 0, shift - 1);
2525 return d1 & ((D2 != 0) | d);
2526 } else {
2527 return d1 & d;
2528 }
2529 } else if (vxrm == 3) { /* round-to-odd (OR bits into LSB, aka "jam") */
2530 return !d & (D1 != 0);
2531 }
2532 return 0; /* round-down (truncate) */
2533 }
2534
2535 static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
2536 {
2537 int64_t res = (int64_t)a + b;
2538 uint8_t round = get_round(vxrm, res, 1);
2539
2540 return (res >> 1) + round;
2541 }
2542
2543 static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
2544 {
2545 int64_t res = a + b;
2546 uint8_t round = get_round(vxrm, res, 1);
2547 int64_t over = (res ^ a) & (res ^ b) & INT64_MIN;
2548
2549 /* With signed overflow, bit 64 is inverse of bit 63. */
2550 return ((res >> 1) ^ over) + round;
2551 }
2552
2553 RVVCALL(OPIVV2_RM, vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd32)
2554 RVVCALL(OPIVV2_RM, vaadd_vv_h, OP_SSS_H, H2, H2, H2, aadd32)
2555 RVVCALL(OPIVV2_RM, vaadd_vv_w, OP_SSS_W, H4, H4, H4, aadd32)
2556 RVVCALL(OPIVV2_RM, vaadd_vv_d, OP_SSS_D, H8, H8, H8, aadd64)
2557 GEN_VEXT_VV_RM(vaadd_vv_b, 1, 1, clearb)
2558 GEN_VEXT_VV_RM(vaadd_vv_h, 2, 2, clearh)
2559 GEN_VEXT_VV_RM(vaadd_vv_w, 4, 4, clearl)
2560 GEN_VEXT_VV_RM(vaadd_vv_d, 8, 8, clearq)
2561
2562 RVVCALL(OPIVX2_RM, vaadd_vx_b, OP_SSS_B, H1, H1, aadd32)
2563 RVVCALL(OPIVX2_RM, vaadd_vx_h, OP_SSS_H, H2, H2, aadd32)
2564 RVVCALL(OPIVX2_RM, vaadd_vx_w, OP_SSS_W, H4, H4, aadd32)
2565 RVVCALL(OPIVX2_RM, vaadd_vx_d, OP_SSS_D, H8, H8, aadd64)
2566 GEN_VEXT_VX_RM(vaadd_vx_b, 1, 1, clearb)
2567 GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2, clearh)
2568 GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4, clearl)
2569 GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8, clearq)
2570
2571 static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
2572 {
2573 int64_t res = (int64_t)a - b;
2574 uint8_t round = get_round(vxrm, res, 1);
2575
2576 return (res >> 1) + round;
2577 }
2578
2579 static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
2580 {
2581 int64_t res = (int64_t)a - b;
2582 uint8_t round = get_round(vxrm, res, 1);
2583 int64_t over = (res ^ a) & (a ^ b) & INT64_MIN;
2584
2585 /* With signed overflow, bit 64 is inverse of bit 63. */
2586 return ((res >> 1) ^ over) + round;
2587 }
2588
2589 RVVCALL(OPIVV2_RM, vasub_vv_b, OP_SSS_B, H1, H1, H1, asub32)
2590 RVVCALL(OPIVV2_RM, vasub_vv_h, OP_SSS_H, H2, H2, H2, asub32)
2591 RVVCALL(OPIVV2_RM, vasub_vv_w, OP_SSS_W, H4, H4, H4, asub32)
2592 RVVCALL(OPIVV2_RM, vasub_vv_d, OP_SSS_D, H8, H8, H8, asub64)
2593 GEN_VEXT_VV_RM(vasub_vv_b, 1, 1, clearb)
2594 GEN_VEXT_VV_RM(vasub_vv_h, 2, 2, clearh)
2595 GEN_VEXT_VV_RM(vasub_vv_w, 4, 4, clearl)
2596 GEN_VEXT_VV_RM(vasub_vv_d, 8, 8, clearq)
2597
2598 RVVCALL(OPIVX2_RM, vasub_vx_b, OP_SSS_B, H1, H1, asub32)
2599 RVVCALL(OPIVX2_RM, vasub_vx_h, OP_SSS_H, H2, H2, asub32)
2600 RVVCALL(OPIVX2_RM, vasub_vx_w, OP_SSS_W, H4, H4, asub32)
2601 RVVCALL(OPIVX2_RM, vasub_vx_d, OP_SSS_D, H8, H8, asub64)
2602 GEN_VEXT_VX_RM(vasub_vx_b, 1, 1, clearb)
2603 GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh)
2604 GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl)
2605 GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq)
2606
2607 /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
2608 static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
2609 {
2610 uint8_t round;
2611 int16_t res;
2612
2613 res = (int16_t)a * (int16_t)b;
2614 round = get_round(vxrm, res, 7);
2615 res = (res >> 7) + round;
2616
2617 if (res > INT8_MAX) {
2618 env->vxsat = 0x1;
2619 return INT8_MAX;
2620 } else if (res < INT8_MIN) {
2621 env->vxsat = 0x1;
2622 return INT8_MIN;
2623 } else {
2624 return res;
2625 }
2626 }
2627
2628 static int16_t vsmul16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
2629 {
2630 uint8_t round;
2631 int32_t res;
2632
2633 res = (int32_t)a * (int32_t)b;
2634 round = get_round(vxrm, res, 15);
2635 res = (res >> 15) + round;
2636
2637 if (res > INT16_MAX) {
2638 env->vxsat = 0x1;
2639 return INT16_MAX;
2640 } else if (res < INT16_MIN) {
2641 env->vxsat = 0x1;
2642 return INT16_MIN;
2643 } else {
2644 return res;
2645 }
2646 }
2647
2648 static int32_t vsmul32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
2649 {
2650 uint8_t round;
2651 int64_t res;
2652
2653 res = (int64_t)a * (int64_t)b;
2654 round = get_round(vxrm, res, 31);
2655 res = (res >> 31) + round;
2656
2657 if (res > INT32_MAX) {
2658 env->vxsat = 0x1;
2659 return INT32_MAX;
2660 } else if (res < INT32_MIN) {
2661 env->vxsat = 0x1;
2662 return INT32_MIN;
2663 } else {
2664 return res;
2665 }
2666 }
2667
2668 static int64_t vsmul64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
2669 {
2670 uint8_t round;
2671 uint64_t hi_64, lo_64;
2672 int64_t res;
2673
2674 if (a == INT64_MIN && b == INT64_MIN) {
2675 env->vxsat = 1;
2676 return INT64_MAX;
2677 }
2678
2679 muls64(&lo_64, &hi_64, a, b);
2680 round = get_round(vxrm, lo_64, 63);
2681 /*
2682 * Cannot overflow, as there are always
2683 * 2 sign bits after multiply.
2684 */
2685 res = (hi_64 << 1) | (lo_64 >> 63);
2686 if (round) {
2687 if (res == INT64_MAX) {
2688 env->vxsat = 1;
2689 } else {
2690 res += 1;
2691 }
2692 }
2693 return res;
2694 }
2695
2696 RVVCALL(OPIVV2_RM, vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8)
2697 RVVCALL(OPIVV2_RM, vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16)
2698 RVVCALL(OPIVV2_RM, vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32)
2699 RVVCALL(OPIVV2_RM, vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64)
2700 GEN_VEXT_VV_RM(vsmul_vv_b, 1, 1, clearb)
2701 GEN_VEXT_VV_RM(vsmul_vv_h, 2, 2, clearh)
2702 GEN_VEXT_VV_RM(vsmul_vv_w, 4, 4, clearl)
2703 GEN_VEXT_VV_RM(vsmul_vv_d, 8, 8, clearq)
2704
2705 RVVCALL(OPIVX2_RM, vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8)
2706 RVVCALL(OPIVX2_RM, vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16)
2707 RVVCALL(OPIVX2_RM, vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32)
2708 RVVCALL(OPIVX2_RM, vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64)
2709 GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1, clearb)
2710 GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2, clearh)
2711 GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4, clearl)
2712 GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8, clearq)
2713
2714 /* Vector Widening Saturating Scaled Multiply-Add */
2715 static inline uint16_t
2716 vwsmaccu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b,
2717 uint16_t c)
2718 {
2719 uint8_t round;
2720 uint16_t res = (uint16_t)a * b;
2721
2722 round = get_round(vxrm, res, 4);
2723 res = (res >> 4) + round;
2724 return saddu16(env, vxrm, c, res);
2725 }
2726
2727 static inline uint32_t
2728 vwsmaccu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b,
2729 uint32_t c)
2730 {
2731 uint8_t round;
2732 uint32_t res = (uint32_t)a * b;
2733
2734 round = get_round(vxrm, res, 8);
2735 res = (res >> 8) + round;
2736 return saddu32(env, vxrm, c, res);
2737 }
2738
2739 static inline uint64_t
2740 vwsmaccu32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b,
2741 uint64_t c)
2742 {
2743 uint8_t round;
2744 uint64_t res = (uint64_t)a * b;
2745
2746 round = get_round(vxrm, res, 16);
2747 res = (res >> 16) + round;
2748 return saddu64(env, vxrm, c, res);
2749 }
2750
2751 #define OPIVV3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
2752 static inline void \
2753 do_##NAME(void *vd, void *vs1, void *vs2, int i, \
2754 CPURISCVState *env, int vxrm) \
2755 { \
2756 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
2757 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
2758 TD d = *((TD *)vd + HD(i)); \
2759 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1, d); \
2760 }
2761
2762 RVVCALL(OPIVV3_RM, vwsmaccu_vv_b, WOP_UUU_B, H2, H1, H1, vwsmaccu8)
2763 RVVCALL(OPIVV3_RM, vwsmaccu_vv_h, WOP_UUU_H, H4, H2, H2, vwsmaccu16)
2764 RVVCALL(OPIVV3_RM, vwsmaccu_vv_w, WOP_UUU_W, H8, H4, H4, vwsmaccu32)
2765 GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2, clearh)
2766 GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4, clearl)
2767 GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8, clearq)
2768
2769 #define OPIVX3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
2770 static inline void \
2771 do_##NAME(void *vd, target_long s1, void *vs2, int i, \
2772 CPURISCVState *env, int vxrm) \
2773 { \
2774 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
2775 TD d = *((TD *)vd + HD(i)); \
2776 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1, d); \
2777 }
2778
2779 RVVCALL(OPIVX3_RM, vwsmaccu_vx_b, WOP_UUU_B, H2, H1, vwsmaccu8)
2780 RVVCALL(OPIVX3_RM, vwsmaccu_vx_h, WOP_UUU_H, H4, H2, vwsmaccu16)
2781 RVVCALL(OPIVX3_RM, vwsmaccu_vx_w, WOP_UUU_W, H8, H4, vwsmaccu32)
2782 GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2, clearh)
2783 GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4, clearl)
2784 GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8, clearq)
2785
2786 static inline int16_t
2787 vwsmacc8(CPURISCVState *env, int vxrm, int8_t a, int8_t b, int16_t c)
2788 {
2789 uint8_t round;
2790 int16_t res = (int16_t)a * b;
2791
2792 round = get_round(vxrm, res, 4);
2793 res = (res >> 4) + round;
2794 return sadd16(env, vxrm, c, res);
2795 }
2796
2797 static inline int32_t
2798 vwsmacc16(CPURISCVState *env, int vxrm, int16_t a, int16_t b, int32_t c)
2799 {
2800 uint8_t round;
2801 int32_t res = (int32_t)a * b;
2802
2803 round = get_round(vxrm, res, 8);
2804 res = (res >> 8) + round;
2805 return sadd32(env, vxrm, c, res);
2806
2807 }
2808
2809 static inline int64_t
2810 vwsmacc32(CPURISCVState *env, int vxrm, int32_t a, int32_t b, int64_t c)
2811 {
2812 uint8_t round;
2813 int64_t res = (int64_t)a * b;
2814
2815 round = get_round(vxrm, res, 16);
2816 res = (res >> 16) + round;
2817 return sadd64(env, vxrm, c, res);
2818 }
2819
2820 RVVCALL(OPIVV3_RM, vwsmacc_vv_b, WOP_SSS_B, H2, H1, H1, vwsmacc8)
2821 RVVCALL(OPIVV3_RM, vwsmacc_vv_h, WOP_SSS_H, H4, H2, H2, vwsmacc16)
2822 RVVCALL(OPIVV3_RM, vwsmacc_vv_w, WOP_SSS_W, H8, H4, H4, vwsmacc32)
2823 GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2, clearh)
2824 GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4, clearl)
2825 GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8, clearq)
2826 RVVCALL(OPIVX3_RM, vwsmacc_vx_b, WOP_SSS_B, H2, H1, vwsmacc8)
2827 RVVCALL(OPIVX3_RM, vwsmacc_vx_h, WOP_SSS_H, H4, H2, vwsmacc16)
2828 RVVCALL(OPIVX3_RM, vwsmacc_vx_w, WOP_SSS_W, H8, H4, vwsmacc32)
2829 GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2, clearh)
2830 GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4, clearl)
2831 GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8, clearq)
2832
2833 static inline int16_t
2834 vwsmaccsu8(CPURISCVState *env, int vxrm, uint8_t a, int8_t b, int16_t c)
2835 {
2836 uint8_t round;
2837 int16_t res = a * (int16_t)b;
2838
2839 round = get_round(vxrm, res, 4);
2840 res = (res >> 4) + round;
2841 return ssub16(env, vxrm, c, res);
2842 }
2843
2844 static inline int32_t
2845 vwsmaccsu16(CPURISCVState *env, int vxrm, uint16_t a, int16_t b, uint32_t c)
2846 {
2847 uint8_t round;
2848 int32_t res = a * (int32_t)b;
2849
2850 round = get_round(vxrm, res, 8);
2851 res = (res >> 8) + round;
2852 return ssub32(env, vxrm, c, res);
2853 }
2854
2855 static inline int64_t
2856 vwsmaccsu32(CPURISCVState *env, int vxrm, uint32_t a, int32_t b, int64_t c)
2857 {
2858 uint8_t round;
2859 int64_t res = a * (int64_t)b;
2860
2861 round = get_round(vxrm, res, 16);
2862 res = (res >> 16) + round;
2863 return ssub64(env, vxrm, c, res);
2864 }
2865
2866 RVVCALL(OPIVV3_RM, vwsmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, vwsmaccsu8)
2867 RVVCALL(OPIVV3_RM, vwsmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, vwsmaccsu16)
2868 RVVCALL(OPIVV3_RM, vwsmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, vwsmaccsu32)
2869 GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2, clearh)
2870 GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4, clearl)
2871 GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8, clearq)
2872 RVVCALL(OPIVX3_RM, vwsmaccsu_vx_b, WOP_SSU_B, H2, H1, vwsmaccsu8)
2873 RVVCALL(OPIVX3_RM, vwsmaccsu_vx_h, WOP_SSU_H, H4, H2, vwsmaccsu16)
2874 RVVCALL(OPIVX3_RM, vwsmaccsu_vx_w, WOP_SSU_W, H8, H4, vwsmaccsu32)
2875 GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2, clearh)
2876 GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4, clearl)
2877 GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8, clearq)
2878
2879 static inline int16_t
2880 vwsmaccus8(CPURISCVState *env, int vxrm, int8_t a, uint8_t b, int16_t c)
2881 {
2882 uint8_t round;
2883 int16_t res = (int16_t)a * b;
2884
2885 round = get_round(vxrm, res, 4);
2886 res = (res >> 4) + round;
2887 return ssub16(env, vxrm, c, res);
2888 }
2889
2890 static inline int32_t
2891 vwsmaccus16(CPURISCVState *env, int vxrm, int16_t a, uint16_t b, int32_t c)
2892 {
2893 uint8_t round;
2894 int32_t res = (int32_t)a * b;
2895
2896 round = get_round(vxrm, res, 8);
2897 res = (res >> 8) + round;
2898 return ssub32(env, vxrm, c, res);
2899 }
2900
2901 static inline int64_t
2902 vwsmaccus32(CPURISCVState *env, int vxrm, int32_t a, uint32_t b, int64_t c)
2903 {
2904 uint8_t round;
2905 int64_t res = (int64_t)a * b;
2906
2907 round = get_round(vxrm, res, 16);
2908 res = (res >> 16) + round;
2909 return ssub64(env, vxrm, c, res);
2910 }
2911
2912 RVVCALL(OPIVX3_RM, vwsmaccus_vx_b, WOP_SUS_B, H2, H1, vwsmaccus8)
2913 RVVCALL(OPIVX3_RM, vwsmaccus_vx_h, WOP_SUS_H, H4, H2, vwsmaccus16)
2914 RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4, vwsmaccus32)
2915 GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2, clearh)
2916 GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4, clearl)
2917 GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8, clearq)
2918
2919 /* Vector Single-Width Scaling Shift Instructions */
2920 static inline uint8_t
2921 vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
2922 {
2923 uint8_t round, shift = b & 0x7;
2924 uint8_t res;
2925
2926 round = get_round(vxrm, a, shift);
2927 res = (a >> shift) + round;
2928 return res;
2929 }
2930 static inline uint16_t
2931 vssrl16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b)
2932 {
2933 uint8_t round, shift = b & 0xf;
2934 uint16_t res;
2935
2936 round = get_round(vxrm, a, shift);
2937 res = (a >> shift) + round;
2938 return res;
2939 }
2940 static inline uint32_t
2941 vssrl32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b)
2942 {
2943 uint8_t round, shift = b & 0x1f;
2944 uint32_t res;
2945
2946 round = get_round(vxrm, a, shift);
2947 res = (a >> shift) + round;
2948 return res;
2949 }
2950 static inline uint64_t
2951 vssrl64(CPURISCVState *env, int vxrm, uint64_t a, uint64_t b)
2952 {
2953 uint8_t round, shift = b & 0x3f;
2954 uint64_t res;
2955
2956 round = get_round(vxrm, a, shift);
2957 res = (a >> shift) + round;
2958 return res;
2959 }
2960 RVVCALL(OPIVV2_RM, vssrl_vv_b, OP_UUU_B, H1, H1, H1, vssrl8)
2961 RVVCALL(OPIVV2_RM, vssrl_vv_h, OP_UUU_H, H2, H2, H2, vssrl16)
2962 RVVCALL(OPIVV2_RM, vssrl_vv_w, OP_UUU_W, H4, H4, H4, vssrl32)
2963 RVVCALL(OPIVV2_RM, vssrl_vv_d, OP_UUU_D, H8, H8, H8, vssrl64)
2964 GEN_VEXT_VV_RM(vssrl_vv_b, 1, 1, clearb)
2965 GEN_VEXT_VV_RM(vssrl_vv_h, 2, 2, clearh)
2966 GEN_VEXT_VV_RM(vssrl_vv_w, 4, 4, clearl)
2967 GEN_VEXT_VV_RM(vssrl_vv_d, 8, 8, clearq)
2968
2969 RVVCALL(OPIVX2_RM, vssrl_vx_b, OP_UUU_B, H1, H1, vssrl8)
2970 RVVCALL(OPIVX2_RM, vssrl_vx_h, OP_UUU_H, H2, H2, vssrl16)
2971 RVVCALL(OPIVX2_RM, vssrl_vx_w, OP_UUU_W, H4, H4, vssrl32)
2972 RVVCALL(OPIVX2_RM, vssrl_vx_d, OP_UUU_D, H8, H8, vssrl64)
2973 GEN_VEXT_VX_RM(vssrl_vx_b, 1, 1, clearb)
2974 GEN_VEXT_VX_RM(vssrl_vx_h, 2, 2, clearh)
2975 GEN_VEXT_VX_RM(vssrl_vx_w, 4, 4, clearl)
2976 GEN_VEXT_VX_RM(vssrl_vx_d, 8, 8, clearq)
2977
2978 static inline int8_t
2979 vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
2980 {
2981 uint8_t round, shift = b & 0x7;
2982 int8_t res;
2983
2984 round = get_round(vxrm, a, shift);
2985 res = (a >> shift) + round;
2986 return res;
2987 }
2988 static inline int16_t
2989 vssra16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
2990 {
2991 uint8_t round, shift = b & 0xf;
2992 int16_t res;
2993
2994 round = get_round(vxrm, a, shift);
2995 res = (a >> shift) + round;
2996 return res;
2997 }
2998 static inline int32_t
2999 vssra32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
3000 {
3001 uint8_t round, shift = b & 0x1f;
3002 int32_t res;
3003
3004 round = get_round(vxrm, a, shift);
3005 res = (a >> shift) + round;
3006 return res;
3007 }
3008 static inline int64_t
3009 vssra64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
3010 {
3011 uint8_t round, shift = b & 0x3f;
3012 int64_t res;
3013
3014 round = get_round(vxrm, a, shift);
3015 res = (a >> shift) + round;
3016 return res;
3017 }
3018
3019 RVVCALL(OPIVV2_RM, vssra_vv_b, OP_SSS_B, H1, H1, H1, vssra8)
3020 RVVCALL(OPIVV2_RM, vssra_vv_h, OP_SSS_H, H2, H2, H2, vssra16)
3021 RVVCALL(OPIVV2_RM, vssra_vv_w, OP_SSS_W, H4, H4, H4, vssra32)
3022 RVVCALL(OPIVV2_RM, vssra_vv_d, OP_SSS_D, H8, H8, H8, vssra64)
3023 GEN_VEXT_VV_RM(vssra_vv_b, 1, 1, clearb)
3024 GEN_VEXT_VV_RM(vssra_vv_h, 2, 2, clearh)
3025 GEN_VEXT_VV_RM(vssra_vv_w, 4, 4, clearl)
3026 GEN_VEXT_VV_RM(vssra_vv_d, 8, 8, clearq)
3027
3028 RVVCALL(OPIVX2_RM, vssra_vx_b, OP_SSS_B, H1, H1, vssra8)
3029 RVVCALL(OPIVX2_RM, vssra_vx_h, OP_SSS_H, H2, H2, vssra16)
3030 RVVCALL(OPIVX2_RM, vssra_vx_w, OP_SSS_W, H4, H4, vssra32)
3031 RVVCALL(OPIVX2_RM, vssra_vx_d, OP_SSS_D, H8, H8, vssra64)
3032 GEN_VEXT_VX_RM(vssra_vx_b, 1, 1, clearb)
3033 GEN_VEXT_VX_RM(vssra_vx_h, 2, 2, clearh)
3034 GEN_VEXT_VX_RM(vssra_vx_w, 4, 4, clearl)
3035 GEN_VEXT_VX_RM(vssra_vx_d, 8, 8, clearq)
3036
3037 /* Vector Narrowing Fixed-Point Clip Instructions */
3038 static inline int8_t
3039 vnclip8(CPURISCVState *env, int vxrm, int16_t a, int8_t b)
3040 {
3041 uint8_t round, shift = b & 0xf;
3042 int16_t res;
3043
3044 round = get_round(vxrm, a, shift);
3045 res = (a >> shift) + round;
3046 if (res > INT8_MAX) {
3047 env->vxsat = 0x1;
3048 return INT8_MAX;
3049 } else if (res < INT8_MIN) {
3050 env->vxsat = 0x1;
3051 return INT8_MIN;
3052 } else {
3053 return res;
3054 }
3055 }
3056
3057 static inline int16_t
3058 vnclip16(CPURISCVState *env, int vxrm, int32_t a, int16_t b)
3059 {
3060 uint8_t round, shift = b & 0x1f;
3061 int32_t res;
3062
3063 round = get_round(vxrm, a, shift);
3064 res = (a >> shift) + round;
3065 if (res > INT16_MAX) {
3066 env->vxsat = 0x1;
3067 return INT16_MAX;
3068 } else if (res < INT16_MIN) {
3069 env->vxsat = 0x1;
3070 return INT16_MIN;
3071 } else {
3072 return res;
3073 }
3074 }
3075
3076 static inline int32_t
3077 vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b)
3078 {
3079 uint8_t round, shift = b & 0x3f;
3080 int64_t res;
3081
3082 round = get_round(vxrm, a, shift);
3083 res = (a >> shift) + round;
3084 if (res > INT32_MAX) {
3085 env->vxsat = 0x1;
3086 return INT32_MAX;
3087 } else if (res < INT32_MIN) {
3088 env->vxsat = 0x1;
3089 return INT32_MIN;
3090 } else {
3091 return res;
3092 }
3093 }
3094
3095 RVVCALL(OPIVV2_RM, vnclip_vv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
3096 RVVCALL(OPIVV2_RM, vnclip_vv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
3097 RVVCALL(OPIVV2_RM, vnclip_vv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
3098 GEN_VEXT_VV_RM(vnclip_vv_b, 1, 1, clearb)
3099 GEN_VEXT_VV_RM(vnclip_vv_h, 2, 2, clearh)
3100 GEN_VEXT_VV_RM(vnclip_vv_w, 4, 4, clearl)
3101
3102 RVVCALL(OPIVX2_RM, vnclip_vx_b, NOP_SSS_B, H1, H2, vnclip8)
3103 RVVCALL(OPIVX2_RM, vnclip_vx_h, NOP_SSS_H, H2, H4, vnclip16)
3104 RVVCALL(OPIVX2_RM, vnclip_vx_w, NOP_SSS_W, H4, H8, vnclip32)
3105 GEN_VEXT_VX_RM(vnclip_vx_b, 1, 1, clearb)
3106 GEN_VEXT_VX_RM(vnclip_vx_h, 2, 2, clearh)
3107 GEN_VEXT_VX_RM(vnclip_vx_w, 4, 4, clearl)
3108
3109 static inline uint8_t
3110 vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b)
3111 {
3112 uint8_t round, shift = b & 0xf;
3113 uint16_t res;
3114
3115 round = get_round(vxrm, a, shift);
3116 res = (a >> shift) + round;
3117 if (res > UINT8_MAX) {
3118 env->vxsat = 0x1;
3119 return UINT8_MAX;
3120 } else {
3121 return res;
3122 }
3123 }
3124
3125 static inline uint16_t
3126 vnclipu16(CPURISCVState *env, int vxrm, uint32_t a, uint16_t b)
3127 {
3128 uint8_t round, shift = b & 0x1f;
3129 uint32_t res;
3130
3131 round = get_round(vxrm, a, shift);
3132 res = (a >> shift) + round;
3133 if (res > UINT16_MAX) {
3134 env->vxsat = 0x1;
3135 return UINT16_MAX;
3136 } else {
3137 return res;
3138 }
3139 }
3140
3141 static inline uint32_t
3142 vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
3143 {
3144 uint8_t round, shift = b & 0x3f;
3145 int64_t res;
3146
3147 round = get_round(vxrm, a, shift);
3148 res = (a >> shift) + round;
3149 if (res > UINT32_MAX) {
3150 env->vxsat = 0x1;
3151 return UINT32_MAX;
3152 } else {
3153 return res;
3154 }
3155 }
3156
3157 RVVCALL(OPIVV2_RM, vnclipu_vv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
3158 RVVCALL(OPIVV2_RM, vnclipu_vv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
3159 RVVCALL(OPIVV2_RM, vnclipu_vv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
3160 GEN_VEXT_VV_RM(vnclipu_vv_b, 1, 1, clearb)
3161 GEN_VEXT_VV_RM(vnclipu_vv_h, 2, 2, clearh)
3162 GEN_VEXT_VV_RM(vnclipu_vv_w, 4, 4, clearl)
3163
3164 RVVCALL(OPIVX2_RM, vnclipu_vx_b, NOP_UUU_B, H1, H2, vnclipu8)
3165 RVVCALL(OPIVX2_RM, vnclipu_vx_h, NOP_UUU_H, H2, H4, vnclipu16)
3166 RVVCALL(OPIVX2_RM, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32)
3167 GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1, clearb)
3168 GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2, clearh)
3169 GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4, clearl)
AR7 emulation for QEMU