2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "qemu-common.h"
34 #include "qemu/timer.h"
35 #include "hw/ppc/xics.h"
36 #include "qemu/error-report.h"
37 #include "qapi/visitor.h"
38 #include "monitor/monitor.h"
39 #include "hw/intc/intc.h"
41 void icp_pic_print_info(ICPState
*icp
, Monitor
*mon
)
43 int cpu_index
= icp
->cs
? icp
->cs
->cpu_index
: -1;
48 monitor_printf(mon
, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
49 cpu_index
, icp
->xirr
, icp
->xirr_owner
,
50 icp
->pending_priority
, icp
->mfrr
);
53 void ics_pic_print_info(ICSState
*ics
, Monitor
*mon
)
57 monitor_printf(mon
, "ICS %4x..%4x %p\n",
58 ics
->offset
, ics
->offset
+ ics
->nr_irqs
- 1, ics
);
64 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
65 ICSIRQState
*irq
= ics
->irqs
+ i
;
67 if (!(irq
->flags
& XICS_FLAGS_IRQ_MASK
)) {
70 monitor_printf(mon
, " %4x %s %02x %02x\n",
72 (irq
->flags
& XICS_FLAGS_IRQ_LSI
) ?
74 irq
->priority
, irq
->status
);
79 * ICP: Presentation layer
82 #define XISR_MASK 0x00ffffff
83 #define CPPR_MASK 0xff000000
85 #define XISR(icp) (((icp)->xirr) & XISR_MASK)
86 #define CPPR(icp) (((icp)->xirr) >> 24)
88 static void ics_reject(ICSState
*ics
, uint32_t nr
)
90 ICSStateClass
*k
= ICS_BASE_GET_CLASS(ics
);
97 void ics_resend(ICSState
*ics
)
99 ICSStateClass
*k
= ICS_BASE_GET_CLASS(ics
);
106 static void ics_eoi(ICSState
*ics
, int nr
)
108 ICSStateClass
*k
= ICS_BASE_GET_CLASS(ics
);
115 static void icp_check_ipi(ICPState
*icp
)
117 if (XISR(icp
) && (icp
->pending_priority
<= icp
->mfrr
)) {
121 trace_xics_icp_check_ipi(icp
->cs
->cpu_index
, icp
->mfrr
);
123 if (XISR(icp
) && icp
->xirr_owner
) {
124 ics_reject(icp
->xirr_owner
, XISR(icp
));
127 icp
->xirr
= (icp
->xirr
& ~XISR_MASK
) | XICS_IPI
;
128 icp
->pending_priority
= icp
->mfrr
;
129 icp
->xirr_owner
= NULL
;
130 qemu_irq_raise(icp
->output
);
133 void icp_resend(ICPState
*icp
)
135 XICSFabric
*xi
= icp
->xics
;
136 XICSFabricClass
*xic
= XICS_FABRIC_GET_CLASS(xi
);
138 if (icp
->mfrr
< CPPR(icp
)) {
145 void icp_set_cppr(ICPState
*icp
, uint8_t cppr
)
150 old_cppr
= CPPR(icp
);
151 icp
->xirr
= (icp
->xirr
& ~CPPR_MASK
) | (cppr
<< 24);
153 if (cppr
< old_cppr
) {
154 if (XISR(icp
) && (cppr
<= icp
->pending_priority
)) {
155 old_xisr
= XISR(icp
);
156 icp
->xirr
&= ~XISR_MASK
; /* Clear XISR */
157 icp
->pending_priority
= 0xff;
158 qemu_irq_lower(icp
->output
);
159 if (icp
->xirr_owner
) {
160 ics_reject(icp
->xirr_owner
, old_xisr
);
161 icp
->xirr_owner
= NULL
;
171 void icp_set_mfrr(ICPState
*icp
, uint8_t mfrr
)
174 if (mfrr
< CPPR(icp
)) {
179 uint32_t icp_accept(ICPState
*icp
)
181 uint32_t xirr
= icp
->xirr
;
183 qemu_irq_lower(icp
->output
);
184 icp
->xirr
= icp
->pending_priority
<< 24;
185 icp
->pending_priority
= 0xff;
186 icp
->xirr_owner
= NULL
;
188 trace_xics_icp_accept(xirr
, icp
->xirr
);
193 uint32_t icp_ipoll(ICPState
*icp
, uint32_t *mfrr
)
201 void icp_eoi(ICPState
*icp
, uint32_t xirr
)
203 XICSFabric
*xi
= icp
->xics
;
204 XICSFabricClass
*xic
= XICS_FABRIC_GET_CLASS(xi
);
208 /* Send EOI -> ICS */
209 icp
->xirr
= (icp
->xirr
& ~CPPR_MASK
) | (xirr
& CPPR_MASK
);
210 trace_xics_icp_eoi(icp
->cs
->cpu_index
, xirr
, icp
->xirr
);
211 irq
= xirr
& XISR_MASK
;
213 ics
= xic
->ics_get(xi
, irq
);
222 static void icp_irq(ICSState
*ics
, int server
, int nr
, uint8_t priority
)
224 ICPState
*icp
= xics_icp_get(ics
->xics
, server
);
226 trace_xics_icp_irq(server
, nr
, priority
);
228 if ((priority
>= CPPR(icp
))
229 || (XISR(icp
) && (icp
->pending_priority
<= priority
))) {
232 if (XISR(icp
) && icp
->xirr_owner
) {
233 ics_reject(icp
->xirr_owner
, XISR(icp
));
234 icp
->xirr_owner
= NULL
;
236 icp
->xirr
= (icp
->xirr
& ~XISR_MASK
) | (nr
& XISR_MASK
);
237 icp
->xirr_owner
= ics
;
238 icp
->pending_priority
= priority
;
239 trace_xics_icp_raise(icp
->xirr
, icp
->pending_priority
);
240 qemu_irq_raise(icp
->output
);
244 static void icp_dispatch_pre_save(void *opaque
)
246 ICPState
*icp
= opaque
;
247 ICPStateClass
*info
= ICP_GET_CLASS(icp
);
249 if (info
->pre_save
) {
254 static int icp_dispatch_post_load(void *opaque
, int version_id
)
256 ICPState
*icp
= opaque
;
257 ICPStateClass
*info
= ICP_GET_CLASS(icp
);
259 if (info
->post_load
) {
260 return info
->post_load(icp
, version_id
);
266 static const VMStateDescription vmstate_icp_server
= {
267 .name
= "icp/server",
269 .minimum_version_id
= 1,
270 .pre_save
= icp_dispatch_pre_save
,
271 .post_load
= icp_dispatch_post_load
,
272 .fields
= (VMStateField
[]) {
274 VMSTATE_UINT32(xirr
, ICPState
),
275 VMSTATE_UINT8(pending_priority
, ICPState
),
276 VMSTATE_UINT8(mfrr
, ICPState
),
277 VMSTATE_END_OF_LIST()
281 static void icp_reset(void *dev
)
283 ICPState
*icp
= ICP(dev
);
284 ICPStateClass
*icpc
= ICP_GET_CLASS(icp
);
287 icp
->pending_priority
= 0xff;
290 /* Make all outputs are deasserted */
291 qemu_set_irq(icp
->output
, 0);
298 static void icp_realize(DeviceState
*dev
, Error
**errp
)
300 ICPState
*icp
= ICP(dev
);
301 ICPStateClass
*icpc
= ICP_GET_CLASS(dev
);
307 obj
= object_property_get_link(OBJECT(dev
), ICP_PROP_XICS
, &err
);
309 error_setg(errp
, "%s: required link '" ICP_PROP_XICS
"' not found: %s",
310 __func__
, error_get_pretty(err
));
314 icp
->xics
= XICS_FABRIC(obj
);
316 obj
= object_property_get_link(OBJECT(dev
), ICP_PROP_CPU
, &err
);
318 error_setg(errp
, "%s: required link '" ICP_PROP_CPU
"' not found: %s",
319 __func__
, error_get_pretty(err
));
323 cpu
= POWERPC_CPU(obj
);
324 cpu
->intc
= OBJECT(icp
);
327 if (icpc
->cpu_setup
) {
328 icpc
->cpu_setup(icp
, cpu
);
332 switch (PPC_INPUT(env
)) {
333 case PPC_FLAGS_INPUT_POWER7
:
334 icp
->output
= env
->irq_inputs
[POWER7_INPUT_INT
];
337 case PPC_FLAGS_INPUT_970
:
338 icp
->output
= env
->irq_inputs
[PPC970_INPUT_INT
];
342 error_setg(errp
, "XICS interrupt controller does not support this CPU bus model");
347 icpc
->realize(icp
, errp
);
350 qemu_register_reset(icp_reset
, dev
);
353 static void icp_unrealize(DeviceState
*dev
, Error
**errp
)
355 qemu_unregister_reset(icp_reset
, dev
);
358 static void icp_class_init(ObjectClass
*klass
, void *data
)
360 DeviceClass
*dc
= DEVICE_CLASS(klass
);
362 dc
->vmsd
= &vmstate_icp_server
;
363 dc
->realize
= icp_realize
;
364 dc
->unrealize
= icp_unrealize
;
367 static const TypeInfo icp_info
= {
369 .parent
= TYPE_DEVICE
,
370 .instance_size
= sizeof(ICPState
),
371 .class_init
= icp_class_init
,
372 .class_size
= sizeof(ICPStateClass
),
378 static void ics_simple_resend_msi(ICSState
*ics
, int srcno
)
380 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
382 /* FIXME: filter by server#? */
383 if (irq
->status
& XICS_STATUS_REJECTED
) {
384 irq
->status
&= ~XICS_STATUS_REJECTED
;
385 if (irq
->priority
!= 0xff) {
386 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
391 static void ics_simple_resend_lsi(ICSState
*ics
, int srcno
)
393 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
395 if ((irq
->priority
!= 0xff)
396 && (irq
->status
& XICS_STATUS_ASSERTED
)
397 && !(irq
->status
& XICS_STATUS_SENT
)) {
398 irq
->status
|= XICS_STATUS_SENT
;
399 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
403 static void ics_simple_set_irq_msi(ICSState
*ics
, int srcno
, int val
)
405 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
407 trace_xics_ics_simple_set_irq_msi(srcno
, srcno
+ ics
->offset
);
410 if (irq
->priority
== 0xff) {
411 irq
->status
|= XICS_STATUS_MASKED_PENDING
;
412 trace_xics_masked_pending();
414 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
419 static void ics_simple_set_irq_lsi(ICSState
*ics
, int srcno
, int val
)
421 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
423 trace_xics_ics_simple_set_irq_lsi(srcno
, srcno
+ ics
->offset
);
425 irq
->status
|= XICS_STATUS_ASSERTED
;
427 irq
->status
&= ~XICS_STATUS_ASSERTED
;
429 ics_simple_resend_lsi(ics
, srcno
);
432 static void ics_simple_set_irq(void *opaque
, int srcno
, int val
)
434 ICSState
*ics
= (ICSState
*)opaque
;
436 if (ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_LSI
) {
437 ics_simple_set_irq_lsi(ics
, srcno
, val
);
439 ics_simple_set_irq_msi(ics
, srcno
, val
);
443 static void ics_simple_write_xive_msi(ICSState
*ics
, int srcno
)
445 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
447 if (!(irq
->status
& XICS_STATUS_MASKED_PENDING
)
448 || (irq
->priority
== 0xff)) {
452 irq
->status
&= ~XICS_STATUS_MASKED_PENDING
;
453 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
456 static void ics_simple_write_xive_lsi(ICSState
*ics
, int srcno
)
458 ics_simple_resend_lsi(ics
, srcno
);
461 void ics_simple_write_xive(ICSState
*ics
, int srcno
, int server
,
462 uint8_t priority
, uint8_t saved_priority
)
464 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
466 irq
->server
= server
;
467 irq
->priority
= priority
;
468 irq
->saved_priority
= saved_priority
;
470 trace_xics_ics_simple_write_xive(ics
->offset
+ srcno
, srcno
, server
,
473 if (ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_LSI
) {
474 ics_simple_write_xive_lsi(ics
, srcno
);
476 ics_simple_write_xive_msi(ics
, srcno
);
480 static void ics_simple_reject(ICSState
*ics
, uint32_t nr
)
482 ICSIRQState
*irq
= ics
->irqs
+ nr
- ics
->offset
;
484 trace_xics_ics_simple_reject(nr
, nr
- ics
->offset
);
485 if (irq
->flags
& XICS_FLAGS_IRQ_MSI
) {
486 irq
->status
|= XICS_STATUS_REJECTED
;
487 } else if (irq
->flags
& XICS_FLAGS_IRQ_LSI
) {
488 irq
->status
&= ~XICS_STATUS_SENT
;
492 static void ics_simple_resend(ICSState
*ics
)
496 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
497 /* FIXME: filter by server#? */
498 if (ics
->irqs
[i
].flags
& XICS_FLAGS_IRQ_LSI
) {
499 ics_simple_resend_lsi(ics
, i
);
501 ics_simple_resend_msi(ics
, i
);
506 static void ics_simple_eoi(ICSState
*ics
, uint32_t nr
)
508 int srcno
= nr
- ics
->offset
;
509 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
511 trace_xics_ics_simple_eoi(nr
);
513 if (ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_LSI
) {
514 irq
->status
&= ~XICS_STATUS_SENT
;
518 static void ics_simple_reset(void *dev
)
520 ICSState
*ics
= ICS_SIMPLE(dev
);
522 uint8_t flags
[ics
->nr_irqs
];
524 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
525 flags
[i
] = ics
->irqs
[i
].flags
;
528 memset(ics
->irqs
, 0, sizeof(ICSIRQState
) * ics
->nr_irqs
);
530 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
531 ics
->irqs
[i
].priority
= 0xff;
532 ics
->irqs
[i
].saved_priority
= 0xff;
533 ics
->irqs
[i
].flags
= flags
[i
];
537 static void ics_simple_dispatch_pre_save(void *opaque
)
539 ICSState
*ics
= opaque
;
540 ICSStateClass
*info
= ICS_BASE_GET_CLASS(ics
);
542 if (info
->pre_save
) {
547 static int ics_simple_dispatch_post_load(void *opaque
, int version_id
)
549 ICSState
*ics
= opaque
;
550 ICSStateClass
*info
= ICS_BASE_GET_CLASS(ics
);
552 if (info
->post_load
) {
553 return info
->post_load(ics
, version_id
);
559 static const VMStateDescription vmstate_ics_simple_irq
= {
562 .minimum_version_id
= 1,
563 .fields
= (VMStateField
[]) {
564 VMSTATE_UINT32(server
, ICSIRQState
),
565 VMSTATE_UINT8(priority
, ICSIRQState
),
566 VMSTATE_UINT8(saved_priority
, ICSIRQState
),
567 VMSTATE_UINT8(status
, ICSIRQState
),
568 VMSTATE_UINT8(flags
, ICSIRQState
),
569 VMSTATE_END_OF_LIST()
573 static const VMStateDescription vmstate_ics_simple
= {
576 .minimum_version_id
= 1,
577 .pre_save
= ics_simple_dispatch_pre_save
,
578 .post_load
= ics_simple_dispatch_post_load
,
579 .fields
= (VMStateField
[]) {
581 VMSTATE_UINT32_EQUAL(nr_irqs
, ICSState
),
583 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs
, ICSState
, nr_irqs
,
584 vmstate_ics_simple_irq
,
586 VMSTATE_END_OF_LIST()
590 static void ics_simple_initfn(Object
*obj
)
592 ICSState
*ics
= ICS_SIMPLE(obj
);
594 ics
->offset
= XICS_IRQ_BASE
;
597 static void ics_simple_realize(ICSState
*ics
, Error
**errp
)
600 error_setg(errp
, "Number of interrupts needs to be greater 0");
603 ics
->irqs
= g_malloc0(ics
->nr_irqs
* sizeof(ICSIRQState
));
604 ics
->qirqs
= qemu_allocate_irqs(ics_simple_set_irq
, ics
, ics
->nr_irqs
);
606 qemu_register_reset(ics_simple_reset
, ics
);
609 static Property ics_simple_properties
[] = {
610 DEFINE_PROP_UINT32("nr-irqs", ICSState
, nr_irqs
, 0),
611 DEFINE_PROP_END_OF_LIST(),
614 static void ics_simple_class_init(ObjectClass
*klass
, void *data
)
616 DeviceClass
*dc
= DEVICE_CLASS(klass
);
617 ICSStateClass
*isc
= ICS_BASE_CLASS(klass
);
619 isc
->realize
= ics_simple_realize
;
620 dc
->props
= ics_simple_properties
;
621 dc
->vmsd
= &vmstate_ics_simple
;
622 isc
->reject
= ics_simple_reject
;
623 isc
->resend
= ics_simple_resend
;
624 isc
->eoi
= ics_simple_eoi
;
627 static const TypeInfo ics_simple_info
= {
628 .name
= TYPE_ICS_SIMPLE
,
629 .parent
= TYPE_ICS_BASE
,
630 .instance_size
= sizeof(ICSState
),
631 .class_init
= ics_simple_class_init
,
632 .class_size
= sizeof(ICSStateClass
),
633 .instance_init
= ics_simple_initfn
,
636 static void ics_base_realize(DeviceState
*dev
, Error
**errp
)
638 ICSStateClass
*icsc
= ICS_BASE_GET_CLASS(dev
);
639 ICSState
*ics
= ICS_BASE(dev
);
643 obj
= object_property_get_link(OBJECT(dev
), ICS_PROP_XICS
, &err
);
645 error_setg(errp
, "%s: required link '" ICS_PROP_XICS
"' not found: %s",
646 __func__
, error_get_pretty(err
));
649 ics
->xics
= XICS_FABRIC(obj
);
653 icsc
->realize(ics
, errp
);
657 static void ics_base_class_init(ObjectClass
*klass
, void *data
)
659 DeviceClass
*dc
= DEVICE_CLASS(klass
);
661 dc
->realize
= ics_base_realize
;
664 static const TypeInfo ics_base_info
= {
665 .name
= TYPE_ICS_BASE
,
666 .parent
= TYPE_DEVICE
,
668 .instance_size
= sizeof(ICSState
),
669 .class_init
= ics_base_class_init
,
670 .class_size
= sizeof(ICSStateClass
),
673 static const TypeInfo xics_fabric_info
= {
674 .name
= TYPE_XICS_FABRIC
,
675 .parent
= TYPE_INTERFACE
,
676 .class_size
= sizeof(XICSFabricClass
),
682 qemu_irq
xics_get_qirq(XICSFabric
*xi
, int irq
)
684 XICSFabricClass
*xic
= XICS_FABRIC_GET_CLASS(xi
);
685 ICSState
*ics
= xic
->ics_get(xi
, irq
);
688 return ics
->qirqs
[irq
- ics
->offset
];
694 ICPState
*xics_icp_get(XICSFabric
*xi
, int server
)
696 XICSFabricClass
*xic
= XICS_FABRIC_GET_CLASS(xi
);
698 return xic
->icp_get(xi
, server
);
701 void ics_set_irq_type(ICSState
*ics
, int srcno
, bool lsi
)
703 assert(!(ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_MASK
));
705 ics
->irqs
[srcno
].flags
|=
706 lsi
? XICS_FLAGS_IRQ_LSI
: XICS_FLAGS_IRQ_MSI
;
709 static void xics_register_types(void)
711 type_register_static(&ics_simple_info
);
712 type_register_static(&ics_base_info
);
713 type_register_static(&icp_info
);
714 type_register_static(&xics_fabric_info
);
717 type_init(xics_register_types
)