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target-ppc: Add Load Quadword and Reserve
[qemu/ar7.git] / target-ppc / translate.c
blob13c98026819fec24137b8f4e22a4a199cd754768
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 10*5 + 22*6 /* VSR */
55 + 8*5 /* CRF */];
56 static TCGv cpu_gpr[32];
57 #if !defined(TARGET_PPC64)
58 static TCGv cpu_gprh[32];
59 #endif
60 static TCGv_i64 cpu_fpr[32];
61 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
62 static TCGv_i64 cpu_vsr[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 #if defined(TARGET_PPC64)
69 static TCGv cpu_cfar;
70 #endif
71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
72 static TCGv cpu_reserve;
73 static TCGv cpu_fpscr;
74 static TCGv_i32 cpu_access_type;
75
76 #include "exec/gen-icount.h"
77
78 void ppc_translate_init(void)
79 {
80 int i;
81 char* p;
82 size_t cpu_reg_names_size;
83 static int done_init = 0;
84
85 if (done_init)
86 return;
87
88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
89
90 p = cpu_reg_names;
91 cpu_reg_names_size = sizeof(cpu_reg_names);
92
93 for (i = 0; i < 8; i++) {
94 snprintf(p, cpu_reg_names_size, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUPPCState, crf[i]), p);
97 p += 5;
98 cpu_reg_names_size -= 5;
99 }
100
101 for (i = 0; i < 32; i++) {
102 snprintf(p, cpu_reg_names_size, "r%d", i);
103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
104 offsetof(CPUPPCState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106 cpu_reg_names_size -= (i < 10) ? 3 : 4;
107 #if !defined(TARGET_PPC64)
108 snprintf(p, cpu_reg_names_size, "r%dH", i);
109 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUPPCState, gprh[i]), p);
111 p += (i < 10) ? 4 : 5;
112 cpu_reg_names_size -= (i < 10) ? 4 : 5;
113 #endif
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(TCG_AREG0,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(TCG_AREG0,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 typedef struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 int mem_idx;
196 int access_type;
197 /* Translation flags */
198 int le_mode;
199 #if defined(TARGET_PPC64)
200 int sf_mode;
201 int has_cfar;
202 #endif
203 int fpu_enabled;
204 int altivec_enabled;
205 int vsx_enabled;
206 int spe_enabled;
207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
208 int singlestep_enabled;
209 uint64_t insns_flags;
210 uint64_t insns_flags2;
211 } DisasContext;
212
213 /* True when active word size < size of target_long. */
214 #ifdef TARGET_PPC64
215 # define NARROW_MODE(C) (!(C)->sf_mode)
216 #else
217 # define NARROW_MODE(C) 0
218 #endif
219
220 struct opc_handler_t {
221 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
222 uint32_t inval1;
223 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
224 uint32_t inval2;
225 /* instruction type */
226 uint64_t type;
227 /* extended instruction type */
228 uint64_t type2;
229 /* handler */
230 void (*handler)(DisasContext *ctx);
231 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
232 const char *oname;
233 #endif
234 #if defined(DO_PPC_STATISTICS)
235 uint64_t count;
236 #endif
237 };
238
239 static inline void gen_reset_fpstatus(void)
240 {
241 gen_helper_reset_fpstatus(cpu_env);
242 }
243
244 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
245 {
246 TCGv_i32 t0 = tcg_temp_new_i32();
247
248 if (set_fprf != 0) {
249 /* This case might be optimized later */
250 tcg_gen_movi_i32(t0, 1);
251 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
252 if (unlikely(set_rc)) {
253 tcg_gen_mov_i32(cpu_crf[1], t0);
254 }
255 gen_helper_float_check_status(cpu_env);
256 } else if (unlikely(set_rc)) {
257 /* We always need to compute fpcc */
258 tcg_gen_movi_i32(t0, 0);
259 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
260 tcg_gen_mov_i32(cpu_crf[1], t0);
261 }
262
263 tcg_temp_free_i32(t0);
264 }
265
266 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
267 {
268 if (ctx->access_type != access_type) {
269 tcg_gen_movi_i32(cpu_access_type, access_type);
270 ctx->access_type = access_type;
271 }
272 }
273
274 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
275 {
276 if (NARROW_MODE(ctx)) {
277 nip = (uint32_t)nip;
278 }
279 tcg_gen_movi_tl(cpu_nip, nip);
280 }
281
282 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
283 {
284 TCGv_i32 t0, t1;
285 if (ctx->exception == POWERPC_EXCP_NONE) {
286 gen_update_nip(ctx, ctx->nip);
287 }
288 t0 = tcg_const_i32(excp);
289 t1 = tcg_const_i32(error);
290 gen_helper_raise_exception_err(cpu_env, t0, t1);
291 tcg_temp_free_i32(t0);
292 tcg_temp_free_i32(t1);
293 ctx->exception = (excp);
294 }
295
296 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
297 {
298 TCGv_i32 t0;
299 if (ctx->exception == POWERPC_EXCP_NONE) {
300 gen_update_nip(ctx, ctx->nip);
301 }
302 t0 = tcg_const_i32(excp);
303 gen_helper_raise_exception(cpu_env, t0);
304 tcg_temp_free_i32(t0);
305 ctx->exception = (excp);
306 }
307
308 static inline void gen_debug_exception(DisasContext *ctx)
309 {
310 TCGv_i32 t0;
311
312 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
313 (ctx->exception != POWERPC_EXCP_SYNC)) {
314 gen_update_nip(ctx, ctx->nip);
315 }
316 t0 = tcg_const_i32(EXCP_DEBUG);
317 gen_helper_raise_exception(cpu_env, t0);
318 tcg_temp_free_i32(t0);
319 }
320
321 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
322 {
323 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
324 }
325
326 /* Stop translation */
327 static inline void gen_stop_exception(DisasContext *ctx)
328 {
329 gen_update_nip(ctx, ctx->nip);
330 ctx->exception = POWERPC_EXCP_STOP;
331 }
332
333 /* No need to update nip here, as execution flow will change */
334 static inline void gen_sync_exception(DisasContext *ctx)
335 {
336 ctx->exception = POWERPC_EXCP_SYNC;
337 }
338
339 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
344
345 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
346 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
349 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
350
351 typedef struct opcode_t {
352 unsigned char opc1, opc2, opc3;
353 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
354 unsigned char pad[5];
355 #else
356 unsigned char pad[1];
357 #endif
358 opc_handler_t handler;
359 const char *oname;
360 } opcode_t;
361
362 /*****************************************************************************/
363 /*** Instruction decoding ***/
364 #define EXTRACT_HELPER(name, shift, nb) \
365 static inline uint32_t name(uint32_t opcode) \
366 { \
367 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
368 }
369
370 #define EXTRACT_SHELPER(name, shift, nb) \
371 static inline int32_t name(uint32_t opcode) \
372 { \
373 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
374 }
375
376 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
377 static inline uint32_t name(uint32_t opcode) \
378 { \
379 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
380 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
381 }
382 /* Opcode part 1 */
383 EXTRACT_HELPER(opc1, 26, 6);
384 /* Opcode part 2 */
385 EXTRACT_HELPER(opc2, 1, 5);
386 /* Opcode part 3 */
387 EXTRACT_HELPER(opc3, 6, 5);
388 /* Update Cr0 flags */
389 EXTRACT_HELPER(Rc, 0, 1);
390 /* Destination */
391 EXTRACT_HELPER(rD, 21, 5);
392 /* Source */
393 EXTRACT_HELPER(rS, 21, 5);
394 /* First operand */
395 EXTRACT_HELPER(rA, 16, 5);
396 /* Second operand */
397 EXTRACT_HELPER(rB, 11, 5);
398 /* Third operand */
399 EXTRACT_HELPER(rC, 6, 5);
400 /*** Get CRn ***/
401 EXTRACT_HELPER(crfD, 23, 3);
402 EXTRACT_HELPER(crfS, 18, 3);
403 EXTRACT_HELPER(crbD, 21, 5);
404 EXTRACT_HELPER(crbA, 16, 5);
405 EXTRACT_HELPER(crbB, 11, 5);
406 /* SPR / TBL */
407 EXTRACT_HELPER(_SPR, 11, 10);
408 static inline uint32_t SPR(uint32_t opcode)
409 {
410 uint32_t sprn = _SPR(opcode);
411
412 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
413 }
414 /*** Get constants ***/
415 EXTRACT_HELPER(IMM, 12, 8);
416 /* 16 bits signed immediate value */
417 EXTRACT_SHELPER(SIMM, 0, 16);
418 /* 16 bits unsigned immediate value */
419 EXTRACT_HELPER(UIMM, 0, 16);
420 /* 5 bits signed immediate value */
421 EXTRACT_HELPER(SIMM5, 16, 5);
422 /* 5 bits signed immediate value */
423 EXTRACT_HELPER(UIMM5, 16, 5);
424 /* Bit count */
425 EXTRACT_HELPER(NB, 11, 5);
426 /* Shift count */
427 EXTRACT_HELPER(SH, 11, 5);
428 /* Vector shift count */
429 EXTRACT_HELPER(VSH, 6, 4);
430 /* Mask start */
431 EXTRACT_HELPER(MB, 6, 5);
432 /* Mask end */
433 EXTRACT_HELPER(ME, 1, 5);
434 /* Trap operand */
435 EXTRACT_HELPER(TO, 21, 5);
436
437 EXTRACT_HELPER(CRM, 12, 8);
438 EXTRACT_HELPER(SR, 16, 4);
439
440 /* mtfsf/mtfsfi */
441 EXTRACT_HELPER(FPBF, 23, 3);
442 EXTRACT_HELPER(FPIMM, 12, 4);
443 EXTRACT_HELPER(FPL, 25, 1);
444 EXTRACT_HELPER(FPFLM, 17, 8);
445 EXTRACT_HELPER(FPW, 16, 1);
446
447 /*** Jump target decoding ***/
448 /* Displacement */
449 EXTRACT_SHELPER(d, 0, 16);
450 /* Immediate address */
451 static inline target_ulong LI(uint32_t opcode)
452 {
453 return (opcode >> 0) & 0x03FFFFFC;
454 }
455
456 static inline uint32_t BD(uint32_t opcode)
457 {
458 return (opcode >> 0) & 0xFFFC;
459 }
460
461 EXTRACT_HELPER(BO, 21, 5);
462 EXTRACT_HELPER(BI, 16, 5);
463 /* Absolute/relative address */
464 EXTRACT_HELPER(AA, 1, 1);
465 /* Link */
466 EXTRACT_HELPER(LK, 0, 1);
467
468 /* Create a mask between <start> and <end> bits */
469 static inline target_ulong MASK(uint32_t start, uint32_t end)
470 {
471 target_ulong ret;
472
473 #if defined(TARGET_PPC64)
474 if (likely(start == 0)) {
475 ret = UINT64_MAX << (63 - end);
476 } else if (likely(end == 63)) {
477 ret = UINT64_MAX >> start;
478 }
479 #else
480 if (likely(start == 0)) {
481 ret = UINT32_MAX << (31 - end);
482 } else if (likely(end == 31)) {
483 ret = UINT32_MAX >> start;
484 }
485 #endif
486 else {
487 ret = (((target_ulong)(-1ULL)) >> (start)) ^
488 (((target_ulong)(-1ULL) >> (end)) >> 1);
489 if (unlikely(start > end))
490 return ~ret;
491 }
492
493 return ret;
494 }
495
496 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
497 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
498 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
499 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
500 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
501 EXTRACT_HELPER(DM, 8, 2);
502 EXTRACT_HELPER(UIM, 16, 2);
503 EXTRACT_HELPER(SHW, 8, 2);
504 /*****************************************************************************/
505 /* PowerPC instructions table */
506
507 #if defined(DO_PPC_STATISTICS)
508 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
509 { \
510 .opc1 = op1, \
511 .opc2 = op2, \
512 .opc3 = op3, \
513 .pad = { 0, }, \
514 .handler = { \
515 .inval1 = invl, \
516 .type = _typ, \
517 .type2 = _typ2, \
518 .handler = &gen_##name, \
519 .oname = stringify(name), \
520 }, \
521 .oname = stringify(name), \
522 }
523 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
524 { \
525 .opc1 = op1, \
526 .opc2 = op2, \
527 .opc3 = op3, \
528 .pad = { 0, }, \
529 .handler = { \
530 .inval1 = invl1, \
531 .inval2 = invl2, \
532 .type = _typ, \
533 .type2 = _typ2, \
534 .handler = &gen_##name, \
535 .oname = stringify(name), \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl, \
547 .type = _typ, \
548 .type2 = _typ2, \
549 .handler = &gen_##name, \
550 .oname = onam, \
551 }, \
552 .oname = onam, \
553 }
554 #else
555 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
556 { \
557 .opc1 = op1, \
558 .opc2 = op2, \
559 .opc3 = op3, \
560 .pad = { 0, }, \
561 .handler = { \
562 .inval1 = invl, \
563 .type = _typ, \
564 .type2 = _typ2, \
565 .handler = &gen_##name, \
566 }, \
567 .oname = stringify(name), \
568 }
569 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
570 { \
571 .opc1 = op1, \
572 .opc2 = op2, \
573 .opc3 = op3, \
574 .pad = { 0, }, \
575 .handler = { \
576 .inval1 = invl1, \
577 .inval2 = invl2, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 }, \
582 .oname = stringify(name), \
583 }
584 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
585 { \
586 .opc1 = op1, \
587 .opc2 = op2, \
588 .opc3 = op3, \
589 .pad = { 0, }, \
590 .handler = { \
591 .inval1 = invl, \
592 .type = _typ, \
593 .type2 = _typ2, \
594 .handler = &gen_##name, \
595 }, \
596 .oname = onam, \
597 }
598 #endif
599
600 /* SPR load/store helpers */
601 static inline void gen_load_spr(TCGv t, int reg)
602 {
603 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
604 }
605
606 static inline void gen_store_spr(int reg, TCGv t)
607 {
608 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
609 }
610
611 /* Invalid instruction */
612 static void gen_invalid(DisasContext *ctx)
613 {
614 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
615 }
616
617 static opc_handler_t invalid_handler = {
618 .inval1 = 0xFFFFFFFF,
619 .inval2 = 0xFFFFFFFF,
620 .type = PPC_NONE,
621 .type2 = PPC_NONE,
622 .handler = gen_invalid,
623 };
624
625 #if defined(TARGET_PPC64)
626 /* NOTE: as this time, the only use of is_user_mode() is in 64 bit code. And */
627 /* so the function is wrapped in the standard 64-bit ifdef in order to */
628 /* avoid compiler warnings in 32-bit implementations. */
629 static bool is_user_mode(DisasContext *ctx)
630 {
631 #if defined(CONFIG_USER_ONLY)
632 return true;
633 #else
634 return ctx->mem_idx == 0;
635 #endif
636 }
637 #endif
638
639 /*** Integer comparison ***/
640
641 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
642 {
643 TCGv t0 = tcg_temp_new();
644 TCGv_i32 t1 = tcg_temp_new_i32();
645
646 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
647
648 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
649 tcg_gen_trunc_tl_i32(t1, t0);
650 tcg_gen_shli_i32(t1, t1, CRF_LT);
651 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
652
653 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
654 tcg_gen_trunc_tl_i32(t1, t0);
655 tcg_gen_shli_i32(t1, t1, CRF_GT);
656 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
657
658 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
659 tcg_gen_trunc_tl_i32(t1, t0);
660 tcg_gen_shli_i32(t1, t1, CRF_EQ);
661 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
662
663 tcg_temp_free(t0);
664 tcg_temp_free_i32(t1);
665 }
666
667 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
668 {
669 TCGv t0 = tcg_const_tl(arg1);
670 gen_op_cmp(arg0, t0, s, crf);
671 tcg_temp_free(t0);
672 }
673
674 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
675 {
676 TCGv t0, t1;
677 t0 = tcg_temp_new();
678 t1 = tcg_temp_new();
679 if (s) {
680 tcg_gen_ext32s_tl(t0, arg0);
681 tcg_gen_ext32s_tl(t1, arg1);
682 } else {
683 tcg_gen_ext32u_tl(t0, arg0);
684 tcg_gen_ext32u_tl(t1, arg1);
685 }
686 gen_op_cmp(t0, t1, s, crf);
687 tcg_temp_free(t1);
688 tcg_temp_free(t0);
689 }
690
691 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
692 {
693 TCGv t0 = tcg_const_tl(arg1);
694 gen_op_cmp32(arg0, t0, s, crf);
695 tcg_temp_free(t0);
696 }
697
698 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
699 {
700 if (NARROW_MODE(ctx)) {
701 gen_op_cmpi32(reg, 0, 1, 0);
702 } else {
703 gen_op_cmpi(reg, 0, 1, 0);
704 }
705 }
706
707 /* cmp */
708 static void gen_cmp(DisasContext *ctx)
709 {
710 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
711 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
712 1, crfD(ctx->opcode));
713 } else {
714 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
715 1, crfD(ctx->opcode));
716 }
717 }
718
719 /* cmpi */
720 static void gen_cmpi(DisasContext *ctx)
721 {
722 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
723 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
724 1, crfD(ctx->opcode));
725 } else {
726 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
727 1, crfD(ctx->opcode));
728 }
729 }
730
731 /* cmpl */
732 static void gen_cmpl(DisasContext *ctx)
733 {
734 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
735 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
736 0, crfD(ctx->opcode));
737 } else {
738 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
739 0, crfD(ctx->opcode));
740 }
741 }
742
743 /* cmpli */
744 static void gen_cmpli(DisasContext *ctx)
745 {
746 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
747 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
748 0, crfD(ctx->opcode));
749 } else {
750 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
751 0, crfD(ctx->opcode));
752 }
753 }
754
755 /* isel (PowerPC 2.03 specification) */
756 static void gen_isel(DisasContext *ctx)
757 {
758 int l1, l2;
759 uint32_t bi = rC(ctx->opcode);
760 uint32_t mask;
761 TCGv_i32 t0;
762
763 l1 = gen_new_label();
764 l2 = gen_new_label();
765
766 mask = 1 << (3 - (bi & 0x03));
767 t0 = tcg_temp_new_i32();
768 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
769 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
770 if (rA(ctx->opcode) == 0)
771 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
772 else
773 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
774 tcg_gen_br(l2);
775 gen_set_label(l1);
776 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
777 gen_set_label(l2);
778 tcg_temp_free_i32(t0);
779 }
780
781 /* cmpb: PowerPC 2.05 specification */
782 static void gen_cmpb(DisasContext *ctx)
783 {
784 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
785 cpu_gpr[rB(ctx->opcode)]);
786 }
787
788 /*** Integer arithmetic ***/
789
790 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
791 TCGv arg1, TCGv arg2, int sub)
792 {
793 TCGv t0 = tcg_temp_new();
794
795 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
796 tcg_gen_xor_tl(t0, arg1, arg2);
797 if (sub) {
798 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
799 } else {
800 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
801 }
802 tcg_temp_free(t0);
803 if (NARROW_MODE(ctx)) {
804 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
805 }
806 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
807 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
808 }
809
810 /* Common add function */
811 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
812 TCGv arg2, bool add_ca, bool compute_ca,
813 bool compute_ov, bool compute_rc0)
814 {
815 TCGv t0 = ret;
816
817 if (compute_ca || compute_ov) {
818 t0 = tcg_temp_new();
819 }
820
821 if (compute_ca) {
822 if (NARROW_MODE(ctx)) {
823 /* Caution: a non-obvious corner case of the spec is that we
824 must produce the *entire* 64-bit addition, but produce the
825 carry into bit 32. */
826 TCGv t1 = tcg_temp_new();
827 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
828 tcg_gen_add_tl(t0, arg1, arg2);
829 if (add_ca) {
830 tcg_gen_add_tl(t0, t0, cpu_ca);
831 }
832 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
833 tcg_temp_free(t1);
834 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
835 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
836 } else {
837 TCGv zero = tcg_const_tl(0);
838 if (add_ca) {
839 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
840 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
841 } else {
842 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
843 }
844 tcg_temp_free(zero);
845 }
846 } else {
847 tcg_gen_add_tl(t0, arg1, arg2);
848 if (add_ca) {
849 tcg_gen_add_tl(t0, t0, cpu_ca);
850 }
851 }
852
853 if (compute_ov) {
854 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
855 }
856 if (unlikely(compute_rc0)) {
857 gen_set_Rc0(ctx, t0);
858 }
859
860 if (!TCGV_EQUAL(t0, ret)) {
861 tcg_gen_mov_tl(ret, t0);
862 tcg_temp_free(t0);
863 }
864 }
865 /* Add functions with two operands */
866 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
867 static void glue(gen_, name)(DisasContext *ctx) \
868 { \
869 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
870 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
871 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
872 }
873 /* Add functions with one operand and one immediate */
874 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
875 add_ca, compute_ca, compute_ov) \
876 static void glue(gen_, name)(DisasContext *ctx) \
877 { \
878 TCGv t0 = tcg_const_tl(const_val); \
879 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
880 cpu_gpr[rA(ctx->opcode)], t0, \
881 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
882 tcg_temp_free(t0); \
883 }
884
885 /* add add. addo addo. */
886 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
887 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
888 /* addc addc. addco addco. */
889 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
890 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
891 /* adde adde. addeo addeo. */
892 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
893 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
894 /* addme addme. addmeo addmeo. */
895 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
896 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
897 /* addze addze. addzeo addzeo.*/
898 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
899 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
900 /* addi */
901 static void gen_addi(DisasContext *ctx)
902 {
903 target_long simm = SIMM(ctx->opcode);
904
905 if (rA(ctx->opcode) == 0) {
906 /* li case */
907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
908 } else {
909 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
910 cpu_gpr[rA(ctx->opcode)], simm);
911 }
912 }
913 /* addic addic.*/
914 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
915 {
916 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
917 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
918 c, 0, 1, 0, compute_rc0);
919 tcg_temp_free(c);
920 }
921
922 static void gen_addic(DisasContext *ctx)
923 {
924 gen_op_addic(ctx, 0);
925 }
926
927 static void gen_addic_(DisasContext *ctx)
928 {
929 gen_op_addic(ctx, 1);
930 }
931
932 /* addis */
933 static void gen_addis(DisasContext *ctx)
934 {
935 target_long simm = SIMM(ctx->opcode);
936
937 if (rA(ctx->opcode) == 0) {
938 /* lis case */
939 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
940 } else {
941 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
942 cpu_gpr[rA(ctx->opcode)], simm << 16);
943 }
944 }
945
946 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
947 TCGv arg2, int sign, int compute_ov)
948 {
949 int l1 = gen_new_label();
950 int l2 = gen_new_label();
951 TCGv_i32 t0 = tcg_temp_local_new_i32();
952 TCGv_i32 t1 = tcg_temp_local_new_i32();
953
954 tcg_gen_trunc_tl_i32(t0, arg1);
955 tcg_gen_trunc_tl_i32(t1, arg2);
956 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
957 if (sign) {
958 int l3 = gen_new_label();
959 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
960 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
961 gen_set_label(l3);
962 tcg_gen_div_i32(t0, t0, t1);
963 } else {
964 tcg_gen_divu_i32(t0, t0, t1);
965 }
966 if (compute_ov) {
967 tcg_gen_movi_tl(cpu_ov, 0);
968 }
969 tcg_gen_br(l2);
970 gen_set_label(l1);
971 if (sign) {
972 tcg_gen_sari_i32(t0, t0, 31);
973 } else {
974 tcg_gen_movi_i32(t0, 0);
975 }
976 if (compute_ov) {
977 tcg_gen_movi_tl(cpu_ov, 1);
978 tcg_gen_movi_tl(cpu_so, 1);
979 }
980 gen_set_label(l2);
981 tcg_gen_extu_i32_tl(ret, t0);
982 tcg_temp_free_i32(t0);
983 tcg_temp_free_i32(t1);
984 if (unlikely(Rc(ctx->opcode) != 0))
985 gen_set_Rc0(ctx, ret);
986 }
987 /* Div functions */
988 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
989 static void glue(gen_, name)(DisasContext *ctx) \
990 { \
991 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
992 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
993 sign, compute_ov); \
994 }
995 /* divwu divwu. divwuo divwuo. */
996 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
997 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
998 /* divw divw. divwo divwo. */
999 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1000 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1001
1002 /* div[wd]eu[o][.] */
1003 #define GEN_DIVE(name, hlpr, compute_ov) \
1004 static void gen_##name(DisasContext *ctx) \
1005 { \
1006 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1007 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1008 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1009 tcg_temp_free_i32(t0); \
1010 if (unlikely(Rc(ctx->opcode) != 0)) { \
1011 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1012 } \
1013 }
1014
1015 GEN_DIVE(divweu, divweu, 0);
1016 GEN_DIVE(divweuo, divweu, 1);
1017 GEN_DIVE(divwe, divwe, 0);
1018 GEN_DIVE(divweo, divwe, 1);
1019
1020 #if defined(TARGET_PPC64)
1021 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1022 TCGv arg2, int sign, int compute_ov)
1023 {
1024 int l1 = gen_new_label();
1025 int l2 = gen_new_label();
1026
1027 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1028 if (sign) {
1029 int l3 = gen_new_label();
1030 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1031 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1032 gen_set_label(l3);
1033 tcg_gen_div_i64(ret, arg1, arg2);
1034 } else {
1035 tcg_gen_divu_i64(ret, arg1, arg2);
1036 }
1037 if (compute_ov) {
1038 tcg_gen_movi_tl(cpu_ov, 0);
1039 }
1040 tcg_gen_br(l2);
1041 gen_set_label(l1);
1042 if (sign) {
1043 tcg_gen_sari_i64(ret, arg1, 63);
1044 } else {
1045 tcg_gen_movi_i64(ret, 0);
1046 }
1047 if (compute_ov) {
1048 tcg_gen_movi_tl(cpu_ov, 1);
1049 tcg_gen_movi_tl(cpu_so, 1);
1050 }
1051 gen_set_label(l2);
1052 if (unlikely(Rc(ctx->opcode) != 0))
1053 gen_set_Rc0(ctx, ret);
1054 }
1055 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1056 static void glue(gen_, name)(DisasContext *ctx) \
1057 { \
1058 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1059 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1060 sign, compute_ov); \
1061 }
1062 /* divwu divwu. divwuo divwuo. */
1063 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1064 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1065 /* divw divw. divwo divwo. */
1066 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1067 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1068
1069 GEN_DIVE(divdeu, divdeu, 0);
1070 GEN_DIVE(divdeuo, divdeu, 1);
1071 GEN_DIVE(divde, divde, 0);
1072 GEN_DIVE(divdeo, divde, 1);
1073 #endif
1074
1075 /* mulhw mulhw. */
1076 static void gen_mulhw(DisasContext *ctx)
1077 {
1078 TCGv_i32 t0 = tcg_temp_new_i32();
1079 TCGv_i32 t1 = tcg_temp_new_i32();
1080
1081 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1082 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1083 tcg_gen_muls2_i32(t0, t1, t0, t1);
1084 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1085 tcg_temp_free_i32(t0);
1086 tcg_temp_free_i32(t1);
1087 if (unlikely(Rc(ctx->opcode) != 0))
1088 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1089 }
1090
1091 /* mulhwu mulhwu. */
1092 static void gen_mulhwu(DisasContext *ctx)
1093 {
1094 TCGv_i32 t0 = tcg_temp_new_i32();
1095 TCGv_i32 t1 = tcg_temp_new_i32();
1096
1097 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1098 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1099 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1100 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1101 tcg_temp_free_i32(t0);
1102 tcg_temp_free_i32(t1);
1103 if (unlikely(Rc(ctx->opcode) != 0))
1104 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1105 }
1106
1107 /* mullw mullw. */
1108 static void gen_mullw(DisasContext *ctx)
1109 {
1110 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1111 cpu_gpr[rB(ctx->opcode)]);
1112 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1113 if (unlikely(Rc(ctx->opcode) != 0))
1114 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1115 }
1116
1117 /* mullwo mullwo. */
1118 static void gen_mullwo(DisasContext *ctx)
1119 {
1120 TCGv_i32 t0 = tcg_temp_new_i32();
1121 TCGv_i32 t1 = tcg_temp_new_i32();
1122
1123 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1124 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1125 tcg_gen_muls2_i32(t0, t1, t0, t1);
1126 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1127
1128 tcg_gen_sari_i32(t0, t0, 31);
1129 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1130 tcg_gen_extu_i32_tl(cpu_ov, t0);
1131 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1132
1133 tcg_temp_free_i32(t0);
1134 tcg_temp_free_i32(t1);
1135 if (unlikely(Rc(ctx->opcode) != 0))
1136 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1137 }
1138
1139 /* mulli */
1140 static void gen_mulli(DisasContext *ctx)
1141 {
1142 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1143 SIMM(ctx->opcode));
1144 }
1145
1146 #if defined(TARGET_PPC64)
1147 /* mulhd mulhd. */
1148 static void gen_mulhd(DisasContext *ctx)
1149 {
1150 TCGv lo = tcg_temp_new();
1151 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1152 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1153 tcg_temp_free(lo);
1154 if (unlikely(Rc(ctx->opcode) != 0)) {
1155 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1156 }
1157 }
1158
1159 /* mulhdu mulhdu. */
1160 static void gen_mulhdu(DisasContext *ctx)
1161 {
1162 TCGv lo = tcg_temp_new();
1163 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1164 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1165 tcg_temp_free(lo);
1166 if (unlikely(Rc(ctx->opcode) != 0)) {
1167 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1168 }
1169 }
1170
1171 /* mulld mulld. */
1172 static void gen_mulld(DisasContext *ctx)
1173 {
1174 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1175 cpu_gpr[rB(ctx->opcode)]);
1176 if (unlikely(Rc(ctx->opcode) != 0))
1177 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1178 }
1179
1180 /* mulldo mulldo. */
1181 static void gen_mulldo(DisasContext *ctx)
1182 {
1183 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1184 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1185 if (unlikely(Rc(ctx->opcode) != 0)) {
1186 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1187 }
1188 }
1189 #endif
1190
1191 /* Common subf function */
1192 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1193 TCGv arg2, bool add_ca, bool compute_ca,
1194 bool compute_ov, bool compute_rc0)
1195 {
1196 TCGv t0 = ret;
1197
1198 if (compute_ca || compute_ov) {
1199 t0 = tcg_temp_new();
1200 }
1201
1202 if (compute_ca) {
1203 /* dest = ~arg1 + arg2 [+ ca]. */
1204 if (NARROW_MODE(ctx)) {
1205 /* Caution: a non-obvious corner case of the spec is that we
1206 must produce the *entire* 64-bit addition, but produce the
1207 carry into bit 32. */
1208 TCGv inv1 = tcg_temp_new();
1209 TCGv t1 = tcg_temp_new();
1210 tcg_gen_not_tl(inv1, arg1);
1211 if (add_ca) {
1212 tcg_gen_add_tl(t0, arg2, cpu_ca);
1213 } else {
1214 tcg_gen_addi_tl(t0, arg2, 1);
1215 }
1216 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1217 tcg_gen_add_tl(t0, t0, inv1);
1218 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1219 tcg_temp_free(t1);
1220 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1221 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1222 } else if (add_ca) {
1223 TCGv zero, inv1 = tcg_temp_new();
1224 tcg_gen_not_tl(inv1, arg1);
1225 zero = tcg_const_tl(0);
1226 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1227 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1228 tcg_temp_free(zero);
1229 tcg_temp_free(inv1);
1230 } else {
1231 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1232 tcg_gen_sub_tl(t0, arg2, arg1);
1233 }
1234 } else if (add_ca) {
1235 /* Since we're ignoring carry-out, we can simplify the
1236 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1237 tcg_gen_sub_tl(t0, arg2, arg1);
1238 tcg_gen_add_tl(t0, t0, cpu_ca);
1239 tcg_gen_subi_tl(t0, t0, 1);
1240 } else {
1241 tcg_gen_sub_tl(t0, arg2, arg1);
1242 }
1243
1244 if (compute_ov) {
1245 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1246 }
1247 if (unlikely(compute_rc0)) {
1248 gen_set_Rc0(ctx, t0);
1249 }
1250
1251 if (!TCGV_EQUAL(t0, ret)) {
1252 tcg_gen_mov_tl(ret, t0);
1253 tcg_temp_free(t0);
1254 }
1255 }
1256 /* Sub functions with Two operands functions */
1257 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1258 static void glue(gen_, name)(DisasContext *ctx) \
1259 { \
1260 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1261 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1262 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1263 }
1264 /* Sub functions with one operand and one immediate */
1265 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1266 add_ca, compute_ca, compute_ov) \
1267 static void glue(gen_, name)(DisasContext *ctx) \
1268 { \
1269 TCGv t0 = tcg_const_tl(const_val); \
1270 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1271 cpu_gpr[rA(ctx->opcode)], t0, \
1272 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1273 tcg_temp_free(t0); \
1274 }
1275 /* subf subf. subfo subfo. */
1276 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1277 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1278 /* subfc subfc. subfco subfco. */
1279 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1280 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1281 /* subfe subfe. subfeo subfo. */
1282 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1283 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1284 /* subfme subfme. subfmeo subfmeo. */
1285 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1286 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1287 /* subfze subfze. subfzeo subfzeo.*/
1288 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1289 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1290
1291 /* subfic */
1292 static void gen_subfic(DisasContext *ctx)
1293 {
1294 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1295 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1296 c, 0, 1, 0, 0);
1297 tcg_temp_free(c);
1298 }
1299
1300 /* neg neg. nego nego. */
1301 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1302 {
1303 TCGv zero = tcg_const_tl(0);
1304 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1305 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1306 tcg_temp_free(zero);
1307 }
1308
1309 static void gen_neg(DisasContext *ctx)
1310 {
1311 gen_op_arith_neg(ctx, 0);
1312 }
1313
1314 static void gen_nego(DisasContext *ctx)
1315 {
1316 gen_op_arith_neg(ctx, 1);
1317 }
1318
1319 /*** Integer logical ***/
1320 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1321 static void glue(gen_, name)(DisasContext *ctx) \
1322 { \
1323 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1324 cpu_gpr[rB(ctx->opcode)]); \
1325 if (unlikely(Rc(ctx->opcode) != 0)) \
1326 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1327 }
1328
1329 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1330 static void glue(gen_, name)(DisasContext *ctx) \
1331 { \
1332 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1333 if (unlikely(Rc(ctx->opcode) != 0)) \
1334 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1335 }
1336
1337 /* and & and. */
1338 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1339 /* andc & andc. */
1340 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1341
1342 /* andi. */
1343 static void gen_andi_(DisasContext *ctx)
1344 {
1345 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1346 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1347 }
1348
1349 /* andis. */
1350 static void gen_andis_(DisasContext *ctx)
1351 {
1352 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1353 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1354 }
1355
1356 /* cntlzw */
1357 static void gen_cntlzw(DisasContext *ctx)
1358 {
1359 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1360 if (unlikely(Rc(ctx->opcode) != 0))
1361 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1362 }
1363 /* eqv & eqv. */
1364 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1365 /* extsb & extsb. */
1366 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1367 /* extsh & extsh. */
1368 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1369 /* nand & nand. */
1370 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1371 /* nor & nor. */
1372 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1373
1374 /* or & or. */
1375 static void gen_or(DisasContext *ctx)
1376 {
1377 int rs, ra, rb;
1378
1379 rs = rS(ctx->opcode);
1380 ra = rA(ctx->opcode);
1381 rb = rB(ctx->opcode);
1382 /* Optimisation for mr. ri case */
1383 if (rs != ra || rs != rb) {
1384 if (rs != rb)
1385 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1386 else
1387 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1388 if (unlikely(Rc(ctx->opcode) != 0))
1389 gen_set_Rc0(ctx, cpu_gpr[ra]);
1390 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1391 gen_set_Rc0(ctx, cpu_gpr[rs]);
1392 #if defined(TARGET_PPC64)
1393 } else {
1394 int prio = 0;
1395
1396 switch (rs) {
1397 case 1:
1398 /* Set process priority to low */
1399 prio = 2;
1400 break;
1401 case 6:
1402 /* Set process priority to medium-low */
1403 prio = 3;
1404 break;
1405 case 2:
1406 /* Set process priority to normal */
1407 prio = 4;
1408 break;
1409 #if !defined(CONFIG_USER_ONLY)
1410 case 31:
1411 if (ctx->mem_idx > 0) {
1412 /* Set process priority to very low */
1413 prio = 1;
1414 }
1415 break;
1416 case 5:
1417 if (ctx->mem_idx > 0) {
1418 /* Set process priority to medium-hight */
1419 prio = 5;
1420 }
1421 break;
1422 case 3:
1423 if (ctx->mem_idx > 0) {
1424 /* Set process priority to high */
1425 prio = 6;
1426 }
1427 break;
1428 case 7:
1429 if (ctx->mem_idx > 1) {
1430 /* Set process priority to very high */
1431 prio = 7;
1432 }
1433 break;
1434 #endif
1435 default:
1436 /* nop */
1437 break;
1438 }
1439 if (prio) {
1440 TCGv t0 = tcg_temp_new();
1441 gen_load_spr(t0, SPR_PPR);
1442 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1443 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1444 gen_store_spr(SPR_PPR, t0);
1445 tcg_temp_free(t0);
1446 }
1447 #endif
1448 }
1449 }
1450 /* orc & orc. */
1451 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1452
1453 /* xor & xor. */
1454 static void gen_xor(DisasContext *ctx)
1455 {
1456 /* Optimisation for "set to zero" case */
1457 if (rS(ctx->opcode) != rB(ctx->opcode))
1458 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1459 else
1460 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1461 if (unlikely(Rc(ctx->opcode) != 0))
1462 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1463 }
1464
1465 /* ori */
1466 static void gen_ori(DisasContext *ctx)
1467 {
1468 target_ulong uimm = UIMM(ctx->opcode);
1469
1470 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1471 /* NOP */
1472 /* XXX: should handle special NOPs for POWER series */
1473 return;
1474 }
1475 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1476 }
1477
1478 /* oris */
1479 static void gen_oris(DisasContext *ctx)
1480 {
1481 target_ulong uimm = UIMM(ctx->opcode);
1482
1483 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1484 /* NOP */
1485 return;
1486 }
1487 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1488 }
1489
1490 /* xori */
1491 static void gen_xori(DisasContext *ctx)
1492 {
1493 target_ulong uimm = UIMM(ctx->opcode);
1494
1495 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1496 /* NOP */
1497 return;
1498 }
1499 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1500 }
1501
1502 /* xoris */
1503 static void gen_xoris(DisasContext *ctx)
1504 {
1505 target_ulong uimm = UIMM(ctx->opcode);
1506
1507 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1508 /* NOP */
1509 return;
1510 }
1511 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1512 }
1513
1514 /* popcntb : PowerPC 2.03 specification */
1515 static void gen_popcntb(DisasContext *ctx)
1516 {
1517 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1518 }
1519
1520 static void gen_popcntw(DisasContext *ctx)
1521 {
1522 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1523 }
1524
1525 #if defined(TARGET_PPC64)
1526 /* popcntd: PowerPC 2.06 specification */
1527 static void gen_popcntd(DisasContext *ctx)
1528 {
1529 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1530 }
1531 #endif
1532
1533 /* prtyw: PowerPC 2.05 specification */
1534 static void gen_prtyw(DisasContext *ctx)
1535 {
1536 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1537 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1538 TCGv t0 = tcg_temp_new();
1539 tcg_gen_shri_tl(t0, rs, 16);
1540 tcg_gen_xor_tl(ra, rs, t0);
1541 tcg_gen_shri_tl(t0, ra, 8);
1542 tcg_gen_xor_tl(ra, ra, t0);
1543 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1544 tcg_temp_free(t0);
1545 }
1546
1547 #if defined(TARGET_PPC64)
1548 /* prtyd: PowerPC 2.05 specification */
1549 static void gen_prtyd(DisasContext *ctx)
1550 {
1551 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1552 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1553 TCGv t0 = tcg_temp_new();
1554 tcg_gen_shri_tl(t0, rs, 32);
1555 tcg_gen_xor_tl(ra, rs, t0);
1556 tcg_gen_shri_tl(t0, ra, 16);
1557 tcg_gen_xor_tl(ra, ra, t0);
1558 tcg_gen_shri_tl(t0, ra, 8);
1559 tcg_gen_xor_tl(ra, ra, t0);
1560 tcg_gen_andi_tl(ra, ra, 1);
1561 tcg_temp_free(t0);
1562 }
1563 #endif
1564
1565 #if defined(TARGET_PPC64)
1566 /* bpermd */
1567 static void gen_bpermd(DisasContext *ctx)
1568 {
1569 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1570 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1571 }
1572 #endif
1573
1574 #if defined(TARGET_PPC64)
1575 /* extsw & extsw. */
1576 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1577
1578 /* cntlzd */
1579 static void gen_cntlzd(DisasContext *ctx)
1580 {
1581 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1582 if (unlikely(Rc(ctx->opcode) != 0))
1583 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1584 }
1585 #endif
1586
1587 /*** Integer rotate ***/
1588
1589 /* rlwimi & rlwimi. */
1590 static void gen_rlwimi(DisasContext *ctx)
1591 {
1592 uint32_t mb, me, sh;
1593
1594 mb = MB(ctx->opcode);
1595 me = ME(ctx->opcode);
1596 sh = SH(ctx->opcode);
1597 if (likely(sh == 0 && mb == 0 && me == 31)) {
1598 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1599 } else {
1600 target_ulong mask;
1601 TCGv t1;
1602 TCGv t0 = tcg_temp_new();
1603 #if defined(TARGET_PPC64)
1604 TCGv_i32 t2 = tcg_temp_new_i32();
1605 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1606 tcg_gen_rotli_i32(t2, t2, sh);
1607 tcg_gen_extu_i32_i64(t0, t2);
1608 tcg_temp_free_i32(t2);
1609 #else
1610 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1611 #endif
1612 #if defined(TARGET_PPC64)
1613 mb += 32;
1614 me += 32;
1615 #endif
1616 mask = MASK(mb, me);
1617 t1 = tcg_temp_new();
1618 tcg_gen_andi_tl(t0, t0, mask);
1619 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1620 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1621 tcg_temp_free(t0);
1622 tcg_temp_free(t1);
1623 }
1624 if (unlikely(Rc(ctx->opcode) != 0))
1625 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1626 }
1627
1628 /* rlwinm & rlwinm. */
1629 static void gen_rlwinm(DisasContext *ctx)
1630 {
1631 uint32_t mb, me, sh;
1632
1633 sh = SH(ctx->opcode);
1634 mb = MB(ctx->opcode);
1635 me = ME(ctx->opcode);
1636
1637 if (likely(mb == 0 && me == (31 - sh))) {
1638 if (likely(sh == 0)) {
1639 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1640 } else {
1641 TCGv t0 = tcg_temp_new();
1642 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1643 tcg_gen_shli_tl(t0, t0, sh);
1644 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1645 tcg_temp_free(t0);
1646 }
1647 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1648 TCGv t0 = tcg_temp_new();
1649 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1650 tcg_gen_shri_tl(t0, t0, mb);
1651 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1652 tcg_temp_free(t0);
1653 } else {
1654 TCGv t0 = tcg_temp_new();
1655 #if defined(TARGET_PPC64)
1656 TCGv_i32 t1 = tcg_temp_new_i32();
1657 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1658 tcg_gen_rotli_i32(t1, t1, sh);
1659 tcg_gen_extu_i32_i64(t0, t1);
1660 tcg_temp_free_i32(t1);
1661 #else
1662 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1663 #endif
1664 #if defined(TARGET_PPC64)
1665 mb += 32;
1666 me += 32;
1667 #endif
1668 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1669 tcg_temp_free(t0);
1670 }
1671 if (unlikely(Rc(ctx->opcode) != 0))
1672 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1673 }
1674
1675 /* rlwnm & rlwnm. */
1676 static void gen_rlwnm(DisasContext *ctx)
1677 {
1678 uint32_t mb, me;
1679 TCGv t0;
1680 #if defined(TARGET_PPC64)
1681 TCGv_i32 t1, t2;
1682 #endif
1683
1684 mb = MB(ctx->opcode);
1685 me = ME(ctx->opcode);
1686 t0 = tcg_temp_new();
1687 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1688 #if defined(TARGET_PPC64)
1689 t1 = tcg_temp_new_i32();
1690 t2 = tcg_temp_new_i32();
1691 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1692 tcg_gen_trunc_i64_i32(t2, t0);
1693 tcg_gen_rotl_i32(t1, t1, t2);
1694 tcg_gen_extu_i32_i64(t0, t1);
1695 tcg_temp_free_i32(t1);
1696 tcg_temp_free_i32(t2);
1697 #else
1698 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1699 #endif
1700 if (unlikely(mb != 0 || me != 31)) {
1701 #if defined(TARGET_PPC64)
1702 mb += 32;
1703 me += 32;
1704 #endif
1705 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1706 } else {
1707 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1708 }
1709 tcg_temp_free(t0);
1710 if (unlikely(Rc(ctx->opcode) != 0))
1711 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1712 }
1713
1714 #if defined(TARGET_PPC64)
1715 #define GEN_PPC64_R2(name, opc1, opc2) \
1716 static void glue(gen_, name##0)(DisasContext *ctx) \
1717 { \
1718 gen_##name(ctx, 0); \
1719 } \
1720 \
1721 static void glue(gen_, name##1)(DisasContext *ctx) \
1722 { \
1723 gen_##name(ctx, 1); \
1724 }
1725 #define GEN_PPC64_R4(name, opc1, opc2) \
1726 static void glue(gen_, name##0)(DisasContext *ctx) \
1727 { \
1728 gen_##name(ctx, 0, 0); \
1729 } \
1730 \
1731 static void glue(gen_, name##1)(DisasContext *ctx) \
1732 { \
1733 gen_##name(ctx, 0, 1); \
1734 } \
1735 \
1736 static void glue(gen_, name##2)(DisasContext *ctx) \
1737 { \
1738 gen_##name(ctx, 1, 0); \
1739 } \
1740 \
1741 static void glue(gen_, name##3)(DisasContext *ctx) \
1742 { \
1743 gen_##name(ctx, 1, 1); \
1744 }
1745
1746 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1747 uint32_t sh)
1748 {
1749 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1750 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1751 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1752 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1753 } else {
1754 TCGv t0 = tcg_temp_new();
1755 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1756 if (likely(mb == 0 && me == 63)) {
1757 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1758 } else {
1759 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1760 }
1761 tcg_temp_free(t0);
1762 }
1763 if (unlikely(Rc(ctx->opcode) != 0))
1764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1765 }
1766 /* rldicl - rldicl. */
1767 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1768 {
1769 uint32_t sh, mb;
1770
1771 sh = SH(ctx->opcode) | (shn << 5);
1772 mb = MB(ctx->opcode) | (mbn << 5);
1773 gen_rldinm(ctx, mb, 63, sh);
1774 }
1775 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1776 /* rldicr - rldicr. */
1777 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1778 {
1779 uint32_t sh, me;
1780
1781 sh = SH(ctx->opcode) | (shn << 5);
1782 me = MB(ctx->opcode) | (men << 5);
1783 gen_rldinm(ctx, 0, me, sh);
1784 }
1785 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1786 /* rldic - rldic. */
1787 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1788 {
1789 uint32_t sh, mb;
1790
1791 sh = SH(ctx->opcode) | (shn << 5);
1792 mb = MB(ctx->opcode) | (mbn << 5);
1793 gen_rldinm(ctx, mb, 63 - sh, sh);
1794 }
1795 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1796
1797 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1798 {
1799 TCGv t0;
1800
1801 t0 = tcg_temp_new();
1802 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1803 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1804 if (unlikely(mb != 0 || me != 63)) {
1805 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1806 } else {
1807 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1808 }
1809 tcg_temp_free(t0);
1810 if (unlikely(Rc(ctx->opcode) != 0))
1811 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1812 }
1813
1814 /* rldcl - rldcl. */
1815 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1816 {
1817 uint32_t mb;
1818
1819 mb = MB(ctx->opcode) | (mbn << 5);
1820 gen_rldnm(ctx, mb, 63);
1821 }
1822 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1823 /* rldcr - rldcr. */
1824 static inline void gen_rldcr(DisasContext *ctx, int men)
1825 {
1826 uint32_t me;
1827
1828 me = MB(ctx->opcode) | (men << 5);
1829 gen_rldnm(ctx, 0, me);
1830 }
1831 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1832 /* rldimi - rldimi. */
1833 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1834 {
1835 uint32_t sh, mb, me;
1836
1837 sh = SH(ctx->opcode) | (shn << 5);
1838 mb = MB(ctx->opcode) | (mbn << 5);
1839 me = 63 - sh;
1840 if (unlikely(sh == 0 && mb == 0)) {
1841 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1842 } else {
1843 TCGv t0, t1;
1844 target_ulong mask;
1845
1846 t0 = tcg_temp_new();
1847 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1848 t1 = tcg_temp_new();
1849 mask = MASK(mb, me);
1850 tcg_gen_andi_tl(t0, t0, mask);
1851 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1852 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1853 tcg_temp_free(t0);
1854 tcg_temp_free(t1);
1855 }
1856 if (unlikely(Rc(ctx->opcode) != 0))
1857 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1858 }
1859 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1860 #endif
1861
1862 /*** Integer shift ***/
1863
1864 /* slw & slw. */
1865 static void gen_slw(DisasContext *ctx)
1866 {
1867 TCGv t0, t1;
1868
1869 t0 = tcg_temp_new();
1870 /* AND rS with a mask that is 0 when rB >= 0x20 */
1871 #if defined(TARGET_PPC64)
1872 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1873 tcg_gen_sari_tl(t0, t0, 0x3f);
1874 #else
1875 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1876 tcg_gen_sari_tl(t0, t0, 0x1f);
1877 #endif
1878 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1879 t1 = tcg_temp_new();
1880 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1881 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1882 tcg_temp_free(t1);
1883 tcg_temp_free(t0);
1884 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1885 if (unlikely(Rc(ctx->opcode) != 0))
1886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1887 }
1888
1889 /* sraw & sraw. */
1890 static void gen_sraw(DisasContext *ctx)
1891 {
1892 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1893 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1894 if (unlikely(Rc(ctx->opcode) != 0))
1895 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1896 }
1897
1898 /* srawi & srawi. */
1899 static void gen_srawi(DisasContext *ctx)
1900 {
1901 int sh = SH(ctx->opcode);
1902 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1903 TCGv src = cpu_gpr[rS(ctx->opcode)];
1904 if (sh == 0) {
1905 tcg_gen_mov_tl(dst, src);
1906 tcg_gen_movi_tl(cpu_ca, 0);
1907 } else {
1908 TCGv t0;
1909 tcg_gen_ext32s_tl(dst, src);
1910 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1911 t0 = tcg_temp_new();
1912 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1913 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1914 tcg_temp_free(t0);
1915 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1916 tcg_gen_sari_tl(dst, dst, sh);
1917 }
1918 if (unlikely(Rc(ctx->opcode) != 0)) {
1919 gen_set_Rc0(ctx, dst);
1920 }
1921 }
1922
1923 /* srw & srw. */
1924 static void gen_srw(DisasContext *ctx)
1925 {
1926 TCGv t0, t1;
1927
1928 t0 = tcg_temp_new();
1929 /* AND rS with a mask that is 0 when rB >= 0x20 */
1930 #if defined(TARGET_PPC64)
1931 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1932 tcg_gen_sari_tl(t0, t0, 0x3f);
1933 #else
1934 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1935 tcg_gen_sari_tl(t0, t0, 0x1f);
1936 #endif
1937 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1938 tcg_gen_ext32u_tl(t0, t0);
1939 t1 = tcg_temp_new();
1940 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1941 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1942 tcg_temp_free(t1);
1943 tcg_temp_free(t0);
1944 if (unlikely(Rc(ctx->opcode) != 0))
1945 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1946 }
1947
1948 #if defined(TARGET_PPC64)
1949 /* sld & sld. */
1950 static void gen_sld(DisasContext *ctx)
1951 {
1952 TCGv t0, t1;
1953
1954 t0 = tcg_temp_new();
1955 /* AND rS with a mask that is 0 when rB >= 0x40 */
1956 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1957 tcg_gen_sari_tl(t0, t0, 0x3f);
1958 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1959 t1 = tcg_temp_new();
1960 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1961 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1962 tcg_temp_free(t1);
1963 tcg_temp_free(t0);
1964 if (unlikely(Rc(ctx->opcode) != 0))
1965 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1966 }
1967
1968 /* srad & srad. */
1969 static void gen_srad(DisasContext *ctx)
1970 {
1971 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1972 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1973 if (unlikely(Rc(ctx->opcode) != 0))
1974 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1975 }
1976 /* sradi & sradi. */
1977 static inline void gen_sradi(DisasContext *ctx, int n)
1978 {
1979 int sh = SH(ctx->opcode) + (n << 5);
1980 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1981 TCGv src = cpu_gpr[rS(ctx->opcode)];
1982 if (sh == 0) {
1983 tcg_gen_mov_tl(dst, src);
1984 tcg_gen_movi_tl(cpu_ca, 0);
1985 } else {
1986 TCGv t0;
1987 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1988 t0 = tcg_temp_new();
1989 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1990 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1991 tcg_temp_free(t0);
1992 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1993 tcg_gen_sari_tl(dst, src, sh);
1994 }
1995 if (unlikely(Rc(ctx->opcode) != 0)) {
1996 gen_set_Rc0(ctx, dst);
1997 }
1998 }
1999
2000 static void gen_sradi0(DisasContext *ctx)
2001 {
2002 gen_sradi(ctx, 0);
2003 }
2004
2005 static void gen_sradi1(DisasContext *ctx)
2006 {
2007 gen_sradi(ctx, 1);
2008 }
2009
2010 /* srd & srd. */
2011 static void gen_srd(DisasContext *ctx)
2012 {
2013 TCGv t0, t1;
2014
2015 t0 = tcg_temp_new();
2016 /* AND rS with a mask that is 0 when rB >= 0x40 */
2017 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2018 tcg_gen_sari_tl(t0, t0, 0x3f);
2019 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2020 t1 = tcg_temp_new();
2021 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2022 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2023 tcg_temp_free(t1);
2024 tcg_temp_free(t0);
2025 if (unlikely(Rc(ctx->opcode) != 0))
2026 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2027 }
2028 #endif
2029
2030 /*** Floating-Point arithmetic ***/
2031 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2032 static void gen_f##name(DisasContext *ctx) \
2033 { \
2034 if (unlikely(!ctx->fpu_enabled)) { \
2035 gen_exception(ctx, POWERPC_EXCP_FPU); \
2036 return; \
2037 } \
2038 /* NIP cannot be restored if the memory exception comes from an helper */ \
2039 gen_update_nip(ctx, ctx->nip - 4); \
2040 gen_reset_fpstatus(); \
2041 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2042 cpu_fpr[rA(ctx->opcode)], \
2043 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2044 if (isfloat) { \
2045 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2046 cpu_fpr[rD(ctx->opcode)]); \
2047 } \
2048 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2049 Rc(ctx->opcode) != 0); \
2050 }
2051
2052 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2053 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2054 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2055
2056 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2057 static void gen_f##name(DisasContext *ctx) \
2058 { \
2059 if (unlikely(!ctx->fpu_enabled)) { \
2060 gen_exception(ctx, POWERPC_EXCP_FPU); \
2061 return; \
2062 } \
2063 /* NIP cannot be restored if the memory exception comes from an helper */ \
2064 gen_update_nip(ctx, ctx->nip - 4); \
2065 gen_reset_fpstatus(); \
2066 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2067 cpu_fpr[rA(ctx->opcode)], \
2068 cpu_fpr[rB(ctx->opcode)]); \
2069 if (isfloat) { \
2070 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2071 cpu_fpr[rD(ctx->opcode)]); \
2072 } \
2073 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2074 set_fprf, Rc(ctx->opcode) != 0); \
2075 }
2076 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2077 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2078 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2079
2080 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2081 static void gen_f##name(DisasContext *ctx) \
2082 { \
2083 if (unlikely(!ctx->fpu_enabled)) { \
2084 gen_exception(ctx, POWERPC_EXCP_FPU); \
2085 return; \
2086 } \
2087 /* NIP cannot be restored if the memory exception comes from an helper */ \
2088 gen_update_nip(ctx, ctx->nip - 4); \
2089 gen_reset_fpstatus(); \
2090 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2091 cpu_fpr[rA(ctx->opcode)], \
2092 cpu_fpr[rC(ctx->opcode)]); \
2093 if (isfloat) { \
2094 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2095 cpu_fpr[rD(ctx->opcode)]); \
2096 } \
2097 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2098 set_fprf, Rc(ctx->opcode) != 0); \
2099 }
2100 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2101 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2102 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2103
2104 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2105 static void gen_f##name(DisasContext *ctx) \
2106 { \
2107 if (unlikely(!ctx->fpu_enabled)) { \
2108 gen_exception(ctx, POWERPC_EXCP_FPU); \
2109 return; \
2110 } \
2111 /* NIP cannot be restored if the memory exception comes from an helper */ \
2112 gen_update_nip(ctx, ctx->nip - 4); \
2113 gen_reset_fpstatus(); \
2114 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2115 cpu_fpr[rB(ctx->opcode)]); \
2116 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2117 set_fprf, Rc(ctx->opcode) != 0); \
2118 }
2119
2120 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2121 static void gen_f##name(DisasContext *ctx) \
2122 { \
2123 if (unlikely(!ctx->fpu_enabled)) { \
2124 gen_exception(ctx, POWERPC_EXCP_FPU); \
2125 return; \
2126 } \
2127 /* NIP cannot be restored if the memory exception comes from an helper */ \
2128 gen_update_nip(ctx, ctx->nip - 4); \
2129 gen_reset_fpstatus(); \
2130 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2131 cpu_fpr[rB(ctx->opcode)]); \
2132 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2133 set_fprf, Rc(ctx->opcode) != 0); \
2134 }
2135
2136 /* fadd - fadds */
2137 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2138 /* fdiv - fdivs */
2139 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2140 /* fmul - fmuls */
2141 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2142
2143 /* fre */
2144 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2145
2146 /* fres */
2147 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2148
2149 /* frsqrte */
2150 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2151
2152 /* frsqrtes */
2153 static void gen_frsqrtes(DisasContext *ctx)
2154 {
2155 if (unlikely(!ctx->fpu_enabled)) {
2156 gen_exception(ctx, POWERPC_EXCP_FPU);
2157 return;
2158 }
2159 /* NIP cannot be restored if the memory exception comes from an helper */
2160 gen_update_nip(ctx, ctx->nip - 4);
2161 gen_reset_fpstatus();
2162 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2163 cpu_fpr[rB(ctx->opcode)]);
2164 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2165 cpu_fpr[rD(ctx->opcode)]);
2166 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2167 }
2168
2169 /* fsel */
2170 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2171 /* fsub - fsubs */
2172 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2173 /* Optional: */
2174
2175 /* fsqrt */
2176 static void gen_fsqrt(DisasContext *ctx)
2177 {
2178 if (unlikely(!ctx->fpu_enabled)) {
2179 gen_exception(ctx, POWERPC_EXCP_FPU);
2180 return;
2181 }
2182 /* NIP cannot be restored if the memory exception comes from an helper */
2183 gen_update_nip(ctx, ctx->nip - 4);
2184 gen_reset_fpstatus();
2185 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2186 cpu_fpr[rB(ctx->opcode)]);
2187 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2188 }
2189
2190 static void gen_fsqrts(DisasContext *ctx)
2191 {
2192 if (unlikely(!ctx->fpu_enabled)) {
2193 gen_exception(ctx, POWERPC_EXCP_FPU);
2194 return;
2195 }
2196 /* NIP cannot be restored if the memory exception comes from an helper */
2197 gen_update_nip(ctx, ctx->nip - 4);
2198 gen_reset_fpstatus();
2199 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2200 cpu_fpr[rB(ctx->opcode)]);
2201 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2202 cpu_fpr[rD(ctx->opcode)]);
2203 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2204 }
2205
2206 /*** Floating-Point multiply-and-add ***/
2207 /* fmadd - fmadds */
2208 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2209 /* fmsub - fmsubs */
2210 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2211 /* fnmadd - fnmadds */
2212 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2213 /* fnmsub - fnmsubs */
2214 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2215
2216 /*** Floating-Point round & convert ***/
2217 /* fctiw */
2218 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2219 /* fctiwu */
2220 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2221 /* fctiwz */
2222 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2223 /* fctiwuz */
2224 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2225 /* frsp */
2226 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2227 #if defined(TARGET_PPC64)
2228 /* fcfid */
2229 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2230 /* fcfids */
2231 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2232 /* fcfidu */
2233 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2234 /* fcfidus */
2235 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2236 /* fctid */
2237 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2238 /* fctidu */
2239 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2240 /* fctidz */
2241 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2242 /* fctidu */
2243 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2244 #endif
2245
2246 /* frin */
2247 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2248 /* friz */
2249 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2250 /* frip */
2251 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2252 /* frim */
2253 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2254
2255 static void gen_ftdiv(DisasContext *ctx)
2256 {
2257 if (unlikely(!ctx->fpu_enabled)) {
2258 gen_exception(ctx, POWERPC_EXCP_FPU);
2259 return;
2260 }
2261 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2262 cpu_fpr[rB(ctx->opcode)]);
2263 }
2264
2265 static void gen_ftsqrt(DisasContext *ctx)
2266 {
2267 if (unlikely(!ctx->fpu_enabled)) {
2268 gen_exception(ctx, POWERPC_EXCP_FPU);
2269 return;
2270 }
2271 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2272 }
2273
2274
2275
2276 /*** Floating-Point compare ***/
2277
2278 /* fcmpo */
2279 static void gen_fcmpo(DisasContext *ctx)
2280 {
2281 TCGv_i32 crf;
2282 if (unlikely(!ctx->fpu_enabled)) {
2283 gen_exception(ctx, POWERPC_EXCP_FPU);
2284 return;
2285 }
2286 /* NIP cannot be restored if the memory exception comes from an helper */
2287 gen_update_nip(ctx, ctx->nip - 4);
2288 gen_reset_fpstatus();
2289 crf = tcg_const_i32(crfD(ctx->opcode));
2290 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2291 cpu_fpr[rB(ctx->opcode)], crf);
2292 tcg_temp_free_i32(crf);
2293 gen_helper_float_check_status(cpu_env);
2294 }
2295
2296 /* fcmpu */
2297 static void gen_fcmpu(DisasContext *ctx)
2298 {
2299 TCGv_i32 crf;
2300 if (unlikely(!ctx->fpu_enabled)) {
2301 gen_exception(ctx, POWERPC_EXCP_FPU);
2302 return;
2303 }
2304 /* NIP cannot be restored if the memory exception comes from an helper */
2305 gen_update_nip(ctx, ctx->nip - 4);
2306 gen_reset_fpstatus();
2307 crf = tcg_const_i32(crfD(ctx->opcode));
2308 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2309 cpu_fpr[rB(ctx->opcode)], crf);
2310 tcg_temp_free_i32(crf);
2311 gen_helper_float_check_status(cpu_env);
2312 }
2313
2314 /*** Floating-point move ***/
2315 /* fabs */
2316 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2317 static void gen_fabs(DisasContext *ctx)
2318 {
2319 if (unlikely(!ctx->fpu_enabled)) {
2320 gen_exception(ctx, POWERPC_EXCP_FPU);
2321 return;
2322 }
2323 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2324 ~(1ULL << 63));
2325 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2326 }
2327
2328 /* fmr - fmr. */
2329 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2330 static void gen_fmr(DisasContext *ctx)
2331 {
2332 if (unlikely(!ctx->fpu_enabled)) {
2333 gen_exception(ctx, POWERPC_EXCP_FPU);
2334 return;
2335 }
2336 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2337 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2338 }
2339
2340 /* fnabs */
2341 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2342 static void gen_fnabs(DisasContext *ctx)
2343 {
2344 if (unlikely(!ctx->fpu_enabled)) {
2345 gen_exception(ctx, POWERPC_EXCP_FPU);
2346 return;
2347 }
2348 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2349 1ULL << 63);
2350 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2351 }
2352
2353 /* fneg */
2354 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2355 static void gen_fneg(DisasContext *ctx)
2356 {
2357 if (unlikely(!ctx->fpu_enabled)) {
2358 gen_exception(ctx, POWERPC_EXCP_FPU);
2359 return;
2360 }
2361 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2362 1ULL << 63);
2363 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2364 }
2365
2366 /* fcpsgn: PowerPC 2.05 specification */
2367 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2368 static void gen_fcpsgn(DisasContext *ctx)
2369 {
2370 if (unlikely(!ctx->fpu_enabled)) {
2371 gen_exception(ctx, POWERPC_EXCP_FPU);
2372 return;
2373 }
2374 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2375 cpu_fpr[rB(ctx->opcode)], 0, 63);
2376 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2377 }
2378
2379 static void gen_fmrgew(DisasContext *ctx)
2380 {
2381 TCGv_i64 b0;
2382 if (unlikely(!ctx->fpu_enabled)) {
2383 gen_exception(ctx, POWERPC_EXCP_FPU);
2384 return;
2385 }
2386 b0 = tcg_temp_new_i64();
2387 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2388 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2389 b0, 0, 32);
2390 tcg_temp_free_i64(b0);
2391 }
2392
2393 static void gen_fmrgow(DisasContext *ctx)
2394 {
2395 if (unlikely(!ctx->fpu_enabled)) {
2396 gen_exception(ctx, POWERPC_EXCP_FPU);
2397 return;
2398 }
2399 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2400 cpu_fpr[rB(ctx->opcode)],
2401 cpu_fpr[rA(ctx->opcode)],
2402 32, 32);
2403 }
2404
2405 /*** Floating-Point status & ctrl register ***/
2406
2407 /* mcrfs */
2408 static void gen_mcrfs(DisasContext *ctx)
2409 {
2410 TCGv tmp = tcg_temp_new();
2411 int bfa;
2412
2413 if (unlikely(!ctx->fpu_enabled)) {
2414 gen_exception(ctx, POWERPC_EXCP_FPU);
2415 return;
2416 }
2417 bfa = 4 * (7 - crfS(ctx->opcode));
2418 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2419 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2420 tcg_temp_free(tmp);
2421 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2422 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2423 }
2424
2425 /* mffs */
2426 static void gen_mffs(DisasContext *ctx)
2427 {
2428 if (unlikely(!ctx->fpu_enabled)) {
2429 gen_exception(ctx, POWERPC_EXCP_FPU);
2430 return;
2431 }
2432 gen_reset_fpstatus();
2433 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2434 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2435 }
2436
2437 /* mtfsb0 */
2438 static void gen_mtfsb0(DisasContext *ctx)
2439 {
2440 uint8_t crb;
2441
2442 if (unlikely(!ctx->fpu_enabled)) {
2443 gen_exception(ctx, POWERPC_EXCP_FPU);
2444 return;
2445 }
2446 crb = 31 - crbD(ctx->opcode);
2447 gen_reset_fpstatus();
2448 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2449 TCGv_i32 t0;
2450 /* NIP cannot be restored if the memory exception comes from an helper */
2451 gen_update_nip(ctx, ctx->nip - 4);
2452 t0 = tcg_const_i32(crb);
2453 gen_helper_fpscr_clrbit(cpu_env, t0);
2454 tcg_temp_free_i32(t0);
2455 }
2456 if (unlikely(Rc(ctx->opcode) != 0)) {
2457 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2458 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2459 }
2460 }
2461
2462 /* mtfsb1 */
2463 static void gen_mtfsb1(DisasContext *ctx)
2464 {
2465 uint8_t crb;
2466
2467 if (unlikely(!ctx->fpu_enabled)) {
2468 gen_exception(ctx, POWERPC_EXCP_FPU);
2469 return;
2470 }
2471 crb = 31 - crbD(ctx->opcode);
2472 gen_reset_fpstatus();
2473 /* XXX: we pretend we can only do IEEE floating-point computations */
2474 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2475 TCGv_i32 t0;
2476 /* NIP cannot be restored if the memory exception comes from an helper */
2477 gen_update_nip(ctx, ctx->nip - 4);
2478 t0 = tcg_const_i32(crb);
2479 gen_helper_fpscr_setbit(cpu_env, t0);
2480 tcg_temp_free_i32(t0);
2481 }
2482 if (unlikely(Rc(ctx->opcode) != 0)) {
2483 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2484 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2485 }
2486 /* We can raise a differed exception */
2487 gen_helper_float_check_status(cpu_env);
2488 }
2489
2490 /* mtfsf */
2491 static void gen_mtfsf(DisasContext *ctx)
2492 {
2493 TCGv_i32 t0;
2494 int flm, l, w;
2495
2496 if (unlikely(!ctx->fpu_enabled)) {
2497 gen_exception(ctx, POWERPC_EXCP_FPU);
2498 return;
2499 }
2500 flm = FPFLM(ctx->opcode);
2501 l = FPL(ctx->opcode);
2502 w = FPW(ctx->opcode);
2503 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2504 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2505 return;
2506 }
2507 /* NIP cannot be restored if the memory exception comes from an helper */
2508 gen_update_nip(ctx, ctx->nip - 4);
2509 gen_reset_fpstatus();
2510 if (l) {
2511 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2512 } else {
2513 t0 = tcg_const_i32(flm << (w * 8));
2514 }
2515 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2516 tcg_temp_free_i32(t0);
2517 if (unlikely(Rc(ctx->opcode) != 0)) {
2518 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2519 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2520 }
2521 /* We can raise a differed exception */
2522 gen_helper_float_check_status(cpu_env);
2523 }
2524
2525 /* mtfsfi */
2526 static void gen_mtfsfi(DisasContext *ctx)
2527 {
2528 int bf, sh, w;
2529 TCGv_i64 t0;
2530 TCGv_i32 t1;
2531
2532 if (unlikely(!ctx->fpu_enabled)) {
2533 gen_exception(ctx, POWERPC_EXCP_FPU);
2534 return;
2535 }
2536 w = FPW(ctx->opcode);
2537 bf = FPBF(ctx->opcode);
2538 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2539 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2540 return;
2541 }
2542 sh = (8 * w) + 7 - bf;
2543 /* NIP cannot be restored if the memory exception comes from an helper */
2544 gen_update_nip(ctx, ctx->nip - 4);
2545 gen_reset_fpstatus();
2546 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2547 t1 = tcg_const_i32(1 << sh);
2548 gen_helper_store_fpscr(cpu_env, t0, t1);
2549 tcg_temp_free_i64(t0);
2550 tcg_temp_free_i32(t1);
2551 if (unlikely(Rc(ctx->opcode) != 0)) {
2552 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2553 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2554 }
2555 /* We can raise a differed exception */
2556 gen_helper_float_check_status(cpu_env);
2557 }
2558
2559 /*** Addressing modes ***/
2560 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2561 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2562 target_long maskl)
2563 {
2564 target_long simm = SIMM(ctx->opcode);
2565
2566 simm &= ~maskl;
2567 if (rA(ctx->opcode) == 0) {
2568 if (NARROW_MODE(ctx)) {
2569 simm = (uint32_t)simm;
2570 }
2571 tcg_gen_movi_tl(EA, simm);
2572 } else if (likely(simm != 0)) {
2573 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2574 if (NARROW_MODE(ctx)) {
2575 tcg_gen_ext32u_tl(EA, EA);
2576 }
2577 } else {
2578 if (NARROW_MODE(ctx)) {
2579 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2580 } else {
2581 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2582 }
2583 }
2584 }
2585
2586 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2587 {
2588 if (rA(ctx->opcode) == 0) {
2589 if (NARROW_MODE(ctx)) {
2590 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2591 } else {
2592 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2593 }
2594 } else {
2595 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2596 if (NARROW_MODE(ctx)) {
2597 tcg_gen_ext32u_tl(EA, EA);
2598 }
2599 }
2600 }
2601
2602 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2603 {
2604 if (rA(ctx->opcode) == 0) {
2605 tcg_gen_movi_tl(EA, 0);
2606 } else if (NARROW_MODE(ctx)) {
2607 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2608 } else {
2609 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2610 }
2611 }
2612
2613 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2614 target_long val)
2615 {
2616 tcg_gen_addi_tl(ret, arg1, val);
2617 if (NARROW_MODE(ctx)) {
2618 tcg_gen_ext32u_tl(ret, ret);
2619 }
2620 }
2621
2622 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2623 {
2624 int l1 = gen_new_label();
2625 TCGv t0 = tcg_temp_new();
2626 TCGv_i32 t1, t2;
2627 /* NIP cannot be restored if the memory exception comes from an helper */
2628 gen_update_nip(ctx, ctx->nip - 4);
2629 tcg_gen_andi_tl(t0, EA, mask);
2630 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2631 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2632 t2 = tcg_const_i32(0);
2633 gen_helper_raise_exception_err(cpu_env, t1, t2);
2634 tcg_temp_free_i32(t1);
2635 tcg_temp_free_i32(t2);
2636 gen_set_label(l1);
2637 tcg_temp_free(t0);
2638 }
2639
2640 /*** Integer load ***/
2641 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2642 {
2643 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2644 }
2645
2646 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2647 {
2648 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2649 }
2650
2651 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2652 {
2653 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2654 if (unlikely(ctx->le_mode)) {
2655 tcg_gen_bswap16_tl(arg1, arg1);
2656 }
2657 }
2658
2659 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2660 {
2661 if (unlikely(ctx->le_mode)) {
2662 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2663 tcg_gen_bswap16_tl(arg1, arg1);
2664 tcg_gen_ext16s_tl(arg1, arg1);
2665 } else {
2666 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2667 }
2668 }
2669
2670 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2671 {
2672 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2673 if (unlikely(ctx->le_mode)) {
2674 tcg_gen_bswap32_tl(arg1, arg1);
2675 }
2676 }
2677
2678 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2679 {
2680 TCGv tmp = tcg_temp_new();
2681 gen_qemu_ld32u(ctx, tmp, addr);
2682 tcg_gen_extu_tl_i64(val, tmp);
2683 tcg_temp_free(tmp);
2684 }
2685
2686 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2687 {
2688 if (unlikely(ctx->le_mode)) {
2689 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2690 tcg_gen_bswap32_tl(arg1, arg1);
2691 tcg_gen_ext32s_tl(arg1, arg1);
2692 } else
2693 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2694 }
2695
2696 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2697 {
2698 TCGv tmp = tcg_temp_new();
2699 gen_qemu_ld32s(ctx, tmp, addr);
2700 tcg_gen_ext_tl_i64(val, tmp);
2701 tcg_temp_free(tmp);
2702 }
2703
2704 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2705 {
2706 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2707 if (unlikely(ctx->le_mode)) {
2708 tcg_gen_bswap64_i64(arg1, arg1);
2709 }
2710 }
2711
2712 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2713 {
2714 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2715 }
2716
2717 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2718 {
2719 if (unlikely(ctx->le_mode)) {
2720 TCGv t0 = tcg_temp_new();
2721 tcg_gen_ext16u_tl(t0, arg1);
2722 tcg_gen_bswap16_tl(t0, t0);
2723 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2724 tcg_temp_free(t0);
2725 } else {
2726 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2727 }
2728 }
2729
2730 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2731 {
2732 if (unlikely(ctx->le_mode)) {
2733 TCGv t0 = tcg_temp_new();
2734 tcg_gen_ext32u_tl(t0, arg1);
2735 tcg_gen_bswap32_tl(t0, t0);
2736 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2737 tcg_temp_free(t0);
2738 } else {
2739 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2740 }
2741 }
2742
2743 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2744 {
2745 TCGv tmp = tcg_temp_new();
2746 tcg_gen_trunc_i64_tl(tmp, val);
2747 gen_qemu_st32(ctx, tmp, addr);
2748 tcg_temp_free(tmp);
2749 }
2750
2751 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2752 {
2753 if (unlikely(ctx->le_mode)) {
2754 TCGv_i64 t0 = tcg_temp_new_i64();
2755 tcg_gen_bswap64_i64(t0, arg1);
2756 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2757 tcg_temp_free_i64(t0);
2758 } else
2759 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2760 }
2761
2762 #define GEN_LD(name, ldop, opc, type) \
2763 static void glue(gen_, name)(DisasContext *ctx) \
2764 { \
2765 TCGv EA; \
2766 gen_set_access_type(ctx, ACCESS_INT); \
2767 EA = tcg_temp_new(); \
2768 gen_addr_imm_index(ctx, EA, 0); \
2769 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2770 tcg_temp_free(EA); \
2771 }
2772
2773 #define GEN_LDU(name, ldop, opc, type) \
2774 static void glue(gen_, name##u)(DisasContext *ctx) \
2775 { \
2776 TCGv EA; \
2777 if (unlikely(rA(ctx->opcode) == 0 || \
2778 rA(ctx->opcode) == rD(ctx->opcode))) { \
2779 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2780 return; \
2781 } \
2782 gen_set_access_type(ctx, ACCESS_INT); \
2783 EA = tcg_temp_new(); \
2784 if (type == PPC_64B) \
2785 gen_addr_imm_index(ctx, EA, 0x03); \
2786 else \
2787 gen_addr_imm_index(ctx, EA, 0); \
2788 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2789 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2790 tcg_temp_free(EA); \
2791 }
2792
2793 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2794 static void glue(gen_, name##ux)(DisasContext *ctx) \
2795 { \
2796 TCGv EA; \
2797 if (unlikely(rA(ctx->opcode) == 0 || \
2798 rA(ctx->opcode) == rD(ctx->opcode))) { \
2799 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2800 return; \
2801 } \
2802 gen_set_access_type(ctx, ACCESS_INT); \
2803 EA = tcg_temp_new(); \
2804 gen_addr_reg_index(ctx, EA); \
2805 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2806 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2807 tcg_temp_free(EA); \
2808 }
2809
2810 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2811 static void glue(gen_, name##x)(DisasContext *ctx) \
2812 { \
2813 TCGv EA; \
2814 gen_set_access_type(ctx, ACCESS_INT); \
2815 EA = tcg_temp_new(); \
2816 gen_addr_reg_index(ctx, EA); \
2817 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2818 tcg_temp_free(EA); \
2819 }
2820 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2821 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2822
2823 #define GEN_LDS(name, ldop, op, type) \
2824 GEN_LD(name, ldop, op | 0x20, type); \
2825 GEN_LDU(name, ldop, op | 0x21, type); \
2826 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2827 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2828
2829 /* lbz lbzu lbzux lbzx */
2830 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2831 /* lha lhau lhaux lhax */
2832 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2833 /* lhz lhzu lhzux lhzx */
2834 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2835 /* lwz lwzu lwzux lwzx */
2836 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2837 #if defined(TARGET_PPC64)
2838 /* lwaux */
2839 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2840 /* lwax */
2841 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2842 /* ldux */
2843 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2844 /* ldx */
2845 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2846
2847 static void gen_ld(DisasContext *ctx)
2848 {
2849 TCGv EA;
2850 if (Rc(ctx->opcode)) {
2851 if (unlikely(rA(ctx->opcode) == 0 ||
2852 rA(ctx->opcode) == rD(ctx->opcode))) {
2853 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2854 return;
2855 }
2856 }
2857 gen_set_access_type(ctx, ACCESS_INT);
2858 EA = tcg_temp_new();
2859 gen_addr_imm_index(ctx, EA, 0x03);
2860 if (ctx->opcode & 0x02) {
2861 /* lwa (lwau is undefined) */
2862 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2863 } else {
2864 /* ld - ldu */
2865 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2866 }
2867 if (Rc(ctx->opcode))
2868 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2869 tcg_temp_free(EA);
2870 }
2871
2872 /* lq */
2873 static void gen_lq(DisasContext *ctx)
2874 {
2875 int ra, rd;
2876 TCGv EA;
2877
2878 /* lq is a legal user mode instruction starting in ISA 2.07 */
2879 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2880 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2881
2882 if (!legal_in_user_mode && is_user_mode(ctx)) {
2883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2884 return;
2885 }
2886
2887 if (!le_is_supported && ctx->le_mode) {
2888 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2889 return;
2890 }
2891
2892 ra = rA(ctx->opcode);
2893 rd = rD(ctx->opcode);
2894 if (unlikely((rd & 1) || rd == ra)) {
2895 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2896 return;
2897 }
2898
2899 gen_set_access_type(ctx, ACCESS_INT);
2900 EA = tcg_temp_new();
2901 gen_addr_imm_index(ctx, EA, 0x0F);
2902
2903 if (unlikely(ctx->le_mode)) {
2904 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2905 gen_addr_add(ctx, EA, EA, 8);
2906 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2907 } else {
2908 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2909 gen_addr_add(ctx, EA, EA, 8);
2910 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2911 }
2912 tcg_temp_free(EA);
2913 }
2914 #endif
2915
2916 /*** Integer store ***/
2917 #define GEN_ST(name, stop, opc, type) \
2918 static void glue(gen_, name)(DisasContext *ctx) \
2919 { \
2920 TCGv EA; \
2921 gen_set_access_type(ctx, ACCESS_INT); \
2922 EA = tcg_temp_new(); \
2923 gen_addr_imm_index(ctx, EA, 0); \
2924 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2925 tcg_temp_free(EA); \
2926 }
2927
2928 #define GEN_STU(name, stop, opc, type) \
2929 static void glue(gen_, stop##u)(DisasContext *ctx) \
2930 { \
2931 TCGv EA; \
2932 if (unlikely(rA(ctx->opcode) == 0)) { \
2933 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2934 return; \
2935 } \
2936 gen_set_access_type(ctx, ACCESS_INT); \
2937 EA = tcg_temp_new(); \
2938 if (type == PPC_64B) \
2939 gen_addr_imm_index(ctx, EA, 0x03); \
2940 else \
2941 gen_addr_imm_index(ctx, EA, 0); \
2942 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2943 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2944 tcg_temp_free(EA); \
2945 }
2946
2947 #define GEN_STUX(name, stop, opc2, opc3, type) \
2948 static void glue(gen_, name##ux)(DisasContext *ctx) \
2949 { \
2950 TCGv EA; \
2951 if (unlikely(rA(ctx->opcode) == 0)) { \
2952 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2953 return; \
2954 } \
2955 gen_set_access_type(ctx, ACCESS_INT); \
2956 EA = tcg_temp_new(); \
2957 gen_addr_reg_index(ctx, EA); \
2958 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2959 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2960 tcg_temp_free(EA); \
2961 }
2962
2963 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2964 static void glue(gen_, name##x)(DisasContext *ctx) \
2965 { \
2966 TCGv EA; \
2967 gen_set_access_type(ctx, ACCESS_INT); \
2968 EA = tcg_temp_new(); \
2969 gen_addr_reg_index(ctx, EA); \
2970 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2971 tcg_temp_free(EA); \
2972 }
2973 #define GEN_STX(name, stop, opc2, opc3, type) \
2974 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2975
2976 #define GEN_STS(name, stop, op, type) \
2977 GEN_ST(name, stop, op | 0x20, type); \
2978 GEN_STU(name, stop, op | 0x21, type); \
2979 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2980 GEN_STX(name, stop, 0x17, op | 0x00, type)
2981
2982 /* stb stbu stbux stbx */
2983 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2984 /* sth sthu sthux sthx */
2985 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2986 /* stw stwu stwux stwx */
2987 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2988 #if defined(TARGET_PPC64)
2989 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2990 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2991
2992 static void gen_std(DisasContext *ctx)
2993 {
2994 int rs;
2995 TCGv EA;
2996
2997 rs = rS(ctx->opcode);
2998 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2999
3000 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3001 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3002
3003 if (!legal_in_user_mode && is_user_mode(ctx)) {
3004 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3005 return;
3006 }
3007
3008 if (!le_is_supported && ctx->le_mode) {
3009 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3010 return;
3011 }
3012
3013 if (unlikely(rs & 1)) {
3014 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3015 return;
3016 }
3017 gen_set_access_type(ctx, ACCESS_INT);
3018 EA = tcg_temp_new();
3019 gen_addr_imm_index(ctx, EA, 0x03);
3020
3021 if (unlikely(ctx->le_mode)) {
3022 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3023 gen_addr_add(ctx, EA, EA, 8);
3024 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3025 } else {
3026 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3027 gen_addr_add(ctx, EA, EA, 8);
3028 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3029 }
3030 tcg_temp_free(EA);
3031 } else {
3032 /* std / stdu*/
3033 if (Rc(ctx->opcode)) {
3034 if (unlikely(rA(ctx->opcode) == 0)) {
3035 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3036 return;
3037 }
3038 }
3039 gen_set_access_type(ctx, ACCESS_INT);
3040 EA = tcg_temp_new();
3041 gen_addr_imm_index(ctx, EA, 0x03);
3042 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3043 if (Rc(ctx->opcode))
3044 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3045 tcg_temp_free(EA);
3046 }
3047 }
3048 #endif
3049 /*** Integer load and store with byte reverse ***/
3050 /* lhbrx */
3051 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3052 {
3053 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
3054 if (likely(!ctx->le_mode)) {
3055 tcg_gen_bswap16_tl(arg1, arg1);
3056 }
3057 }
3058 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3059
3060 /* lwbrx */
3061 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3062 {
3063 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3064 if (likely(!ctx->le_mode)) {
3065 tcg_gen_bswap32_tl(arg1, arg1);
3066 }
3067 }
3068 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3069
3070 #if defined(TARGET_PPC64)
3071 /* ldbrx */
3072 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3073 {
3074 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
3075 if (likely(!ctx->le_mode)) {
3076 tcg_gen_bswap64_tl(arg1, arg1);
3077 }
3078 }
3079 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3080 #endif /* TARGET_PPC64 */
3081
3082 /* sthbrx */
3083 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3084 {
3085 if (likely(!ctx->le_mode)) {
3086 TCGv t0 = tcg_temp_new();
3087 tcg_gen_ext16u_tl(t0, arg1);
3088 tcg_gen_bswap16_tl(t0, t0);
3089 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3090 tcg_temp_free(t0);
3091 } else {
3092 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3093 }
3094 }
3095 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3096
3097 /* stwbrx */
3098 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3099 {
3100 if (likely(!ctx->le_mode)) {
3101 TCGv t0 = tcg_temp_new();
3102 tcg_gen_ext32u_tl(t0, arg1);
3103 tcg_gen_bswap32_tl(t0, t0);
3104 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3105 tcg_temp_free(t0);
3106 } else {
3107 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3108 }
3109 }
3110 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3111
3112 #if defined(TARGET_PPC64)
3113 /* stdbrx */
3114 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3115 {
3116 if (likely(!ctx->le_mode)) {
3117 TCGv t0 = tcg_temp_new();
3118 tcg_gen_bswap64_tl(t0, arg1);
3119 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
3120 tcg_temp_free(t0);
3121 } else {
3122 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
3123 }
3124 }
3125 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3126 #endif /* TARGET_PPC64 */
3127
3128 /*** Integer load and store multiple ***/
3129
3130 /* lmw */
3131 static void gen_lmw(DisasContext *ctx)
3132 {
3133 TCGv t0;
3134 TCGv_i32 t1;
3135 gen_set_access_type(ctx, ACCESS_INT);
3136 /* NIP cannot be restored if the memory exception comes from an helper */
3137 gen_update_nip(ctx, ctx->nip - 4);
3138 t0 = tcg_temp_new();
3139 t1 = tcg_const_i32(rD(ctx->opcode));
3140 gen_addr_imm_index(ctx, t0, 0);
3141 gen_helper_lmw(cpu_env, t0, t1);
3142 tcg_temp_free(t0);
3143 tcg_temp_free_i32(t1);
3144 }
3145
3146 /* stmw */
3147 static void gen_stmw(DisasContext *ctx)
3148 {
3149 TCGv t0;
3150 TCGv_i32 t1;
3151 gen_set_access_type(ctx, ACCESS_INT);
3152 /* NIP cannot be restored if the memory exception comes from an helper */
3153 gen_update_nip(ctx, ctx->nip - 4);
3154 t0 = tcg_temp_new();
3155 t1 = tcg_const_i32(rS(ctx->opcode));
3156 gen_addr_imm_index(ctx, t0, 0);
3157 gen_helper_stmw(cpu_env, t0, t1);
3158 tcg_temp_free(t0);
3159 tcg_temp_free_i32(t1);
3160 }
3161
3162 /*** Integer load and store strings ***/
3163
3164 /* lswi */
3165 /* PowerPC32 specification says we must generate an exception if
3166 * rA is in the range of registers to be loaded.
3167 * In an other hand, IBM says this is valid, but rA won't be loaded.
3168 * For now, I'll follow the spec...
3169 */
3170 static void gen_lswi(DisasContext *ctx)
3171 {
3172 TCGv t0;
3173 TCGv_i32 t1, t2;
3174 int nb = NB(ctx->opcode);
3175 int start = rD(ctx->opcode);
3176 int ra = rA(ctx->opcode);
3177 int nr;
3178
3179 if (nb == 0)
3180 nb = 32;
3181 nr = nb / 4;
3182 if (unlikely(((start + nr) > 32 &&
3183 start <= ra && (start + nr - 32) > ra) ||
3184 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3185 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3186 return;
3187 }
3188 gen_set_access_type(ctx, ACCESS_INT);
3189 /* NIP cannot be restored if the memory exception comes from an helper */
3190 gen_update_nip(ctx, ctx->nip - 4);
3191 t0 = tcg_temp_new();
3192 gen_addr_register(ctx, t0);
3193 t1 = tcg_const_i32(nb);
3194 t2 = tcg_const_i32(start);
3195 gen_helper_lsw(cpu_env, t0, t1, t2);
3196 tcg_temp_free(t0);
3197 tcg_temp_free_i32(t1);
3198 tcg_temp_free_i32(t2);
3199 }
3200
3201 /* lswx */
3202 static void gen_lswx(DisasContext *ctx)
3203 {
3204 TCGv t0;
3205 TCGv_i32 t1, t2, t3;
3206 gen_set_access_type(ctx, ACCESS_INT);
3207 /* NIP cannot be restored if the memory exception comes from an helper */
3208 gen_update_nip(ctx, ctx->nip - 4);
3209 t0 = tcg_temp_new();
3210 gen_addr_reg_index(ctx, t0);
3211 t1 = tcg_const_i32(rD(ctx->opcode));
3212 t2 = tcg_const_i32(rA(ctx->opcode));
3213 t3 = tcg_const_i32(rB(ctx->opcode));
3214 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3215 tcg_temp_free(t0);
3216 tcg_temp_free_i32(t1);
3217 tcg_temp_free_i32(t2);
3218 tcg_temp_free_i32(t3);
3219 }
3220
3221 /* stswi */
3222 static void gen_stswi(DisasContext *ctx)
3223 {
3224 TCGv t0;
3225 TCGv_i32 t1, t2;
3226 int nb = NB(ctx->opcode);
3227 gen_set_access_type(ctx, ACCESS_INT);
3228 /* NIP cannot be restored if the memory exception comes from an helper */
3229 gen_update_nip(ctx, ctx->nip - 4);
3230 t0 = tcg_temp_new();
3231 gen_addr_register(ctx, t0);
3232 if (nb == 0)
3233 nb = 32;
3234 t1 = tcg_const_i32(nb);
3235 t2 = tcg_const_i32(rS(ctx->opcode));
3236 gen_helper_stsw(cpu_env, t0, t1, t2);
3237 tcg_temp_free(t0);
3238 tcg_temp_free_i32(t1);
3239 tcg_temp_free_i32(t2);
3240 }
3241
3242 /* stswx */
3243 static void gen_stswx(DisasContext *ctx)
3244 {
3245 TCGv t0;
3246 TCGv_i32 t1, t2;
3247 gen_set_access_type(ctx, ACCESS_INT);
3248 /* NIP cannot be restored if the memory exception comes from an helper */
3249 gen_update_nip(ctx, ctx->nip - 4);
3250 t0 = tcg_temp_new();
3251 gen_addr_reg_index(ctx, t0);
3252 t1 = tcg_temp_new_i32();
3253 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3254 tcg_gen_andi_i32(t1, t1, 0x7F);
3255 t2 = tcg_const_i32(rS(ctx->opcode));
3256 gen_helper_stsw(cpu_env, t0, t1, t2);
3257 tcg_temp_free(t0);
3258 tcg_temp_free_i32(t1);
3259 tcg_temp_free_i32(t2);
3260 }
3261
3262 /*** Memory synchronisation ***/
3263 /* eieio */
3264 static void gen_eieio(DisasContext *ctx)
3265 {
3266 }
3267
3268 /* isync */
3269 static void gen_isync(DisasContext *ctx)
3270 {
3271 gen_stop_exception(ctx);
3272 }
3273
3274 #define LARX(name, len, loadop) \
3275 static void gen_##name(DisasContext *ctx) \
3276 { \
3277 TCGv t0; \
3278 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3279 gen_set_access_type(ctx, ACCESS_RES); \
3280 t0 = tcg_temp_local_new(); \
3281 gen_addr_reg_index(ctx, t0); \
3282 if ((len) > 1) { \
3283 gen_check_align(ctx, t0, (len)-1); \
3284 } \
3285 gen_qemu_##loadop(ctx, gpr, t0); \
3286 tcg_gen_mov_tl(cpu_reserve, t0); \
3287 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3288 tcg_temp_free(t0); \
3289 }
3290
3291 /* lwarx */
3292 LARX(lbarx, 1, ld8u);
3293 LARX(lharx, 2, ld16u);
3294 LARX(lwarx, 4, ld32u);
3295
3296
3297 #if defined(CONFIG_USER_ONLY)
3298 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3299 int reg, int size)
3300 {
3301 TCGv t0 = tcg_temp_new();
3302 uint32_t save_exception = ctx->exception;
3303
3304 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3305 tcg_gen_movi_tl(t0, (size << 5) | reg);
3306 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3307 tcg_temp_free(t0);
3308 gen_update_nip(ctx, ctx->nip-4);
3309 ctx->exception = POWERPC_EXCP_BRANCH;
3310 gen_exception(ctx, POWERPC_EXCP_STCX);
3311 ctx->exception = save_exception;
3312 }
3313 #else
3314 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3315 int reg, int size)
3316 {
3317 int l1;
3318
3319 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3320 l1 = gen_new_label();
3321 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3322 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3323 #if defined(TARGET_PPC64)
3324 if (size == 8) {
3325 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3326 } else
3327 #endif
3328 if (size == 4) {
3329 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3330 } else if (size == 2) {
3331 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3332 } else {
3333 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3334 }
3335 gen_set_label(l1);
3336 tcg_gen_movi_tl(cpu_reserve, -1);
3337 }
3338 #endif
3339
3340 #define STCX(name, len) \
3341 static void gen_##name(DisasContext *ctx) \
3342 { \
3343 TCGv t0; \
3344 gen_set_access_type(ctx, ACCESS_RES); \
3345 t0 = tcg_temp_local_new(); \
3346 gen_addr_reg_index(ctx, t0); \
3347 if (len > 1) { \
3348 gen_check_align(ctx, t0, (len)-1); \
3349 } \
3350 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3351 tcg_temp_free(t0); \
3352 }
3353
3354 STCX(stbcx_, 1);
3355 STCX(sthcx_, 2);
3356 STCX(stwcx_, 4);
3357
3358 #if defined(TARGET_PPC64)
3359 /* ldarx */
3360 LARX(ldarx, 8, ld64);
3361
3362 /* lqarx */
3363 static void gen_lqarx(DisasContext *ctx)
3364 {
3365 TCGv EA;
3366 int rd = rD(ctx->opcode);
3367 TCGv gpr1, gpr2;
3368
3369 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3370 (rd == rB(ctx->opcode)))) {
3371 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3372 return;
3373 }
3374
3375 gen_set_access_type(ctx, ACCESS_RES);
3376 EA = tcg_temp_local_new();
3377 gen_addr_reg_index(ctx, EA);
3378 gen_check_align(ctx, EA, 15);
3379 if (unlikely(ctx->le_mode)) {
3380 gpr1 = cpu_gpr[rd+1];
3381 gpr2 = cpu_gpr[rd];
3382 } else {
3383 gpr1 = cpu_gpr[rd];
3384 gpr2 = cpu_gpr[rd+1];
3385 }
3386 gen_qemu_ld64(ctx, gpr1, EA);
3387 tcg_gen_mov_tl(cpu_reserve, EA);
3388
3389 gen_addr_add(ctx, EA, EA, 8);
3390 gen_qemu_ld64(ctx, gpr2, EA);
3391
3392 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3393 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3394
3395 tcg_temp_free(EA);
3396 }
3397
3398 /* stdcx. */
3399 STCX(stdcx_, 8);
3400 #endif /* defined(TARGET_PPC64) */
3401
3402 /* sync */
3403 static void gen_sync(DisasContext *ctx)
3404 {
3405 }
3406
3407 /* wait */
3408 static void gen_wait(DisasContext *ctx)
3409 {
3410 TCGv_i32 t0 = tcg_temp_new_i32();
3411 tcg_gen_st_i32(t0, cpu_env,
3412 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3413 tcg_temp_free_i32(t0);
3414 /* Stop translation, as the CPU is supposed to sleep from now */
3415 gen_exception_err(ctx, EXCP_HLT, 1);
3416 }
3417
3418 /*** Floating-point load ***/
3419 #define GEN_LDF(name, ldop, opc, type) \
3420 static void glue(gen_, name)(DisasContext *ctx) \
3421 { \
3422 TCGv EA; \
3423 if (unlikely(!ctx->fpu_enabled)) { \
3424 gen_exception(ctx, POWERPC_EXCP_FPU); \
3425 return; \
3426 } \
3427 gen_set_access_type(ctx, ACCESS_FLOAT); \
3428 EA = tcg_temp_new(); \
3429 gen_addr_imm_index(ctx, EA, 0); \
3430 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3431 tcg_temp_free(EA); \
3432 }
3433
3434 #define GEN_LDUF(name, ldop, opc, type) \
3435 static void glue(gen_, name##u)(DisasContext *ctx) \
3436 { \
3437 TCGv EA; \
3438 if (unlikely(!ctx->fpu_enabled)) { \
3439 gen_exception(ctx, POWERPC_EXCP_FPU); \
3440 return; \
3441 } \
3442 if (unlikely(rA(ctx->opcode) == 0)) { \
3443 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3444 return; \
3445 } \
3446 gen_set_access_type(ctx, ACCESS_FLOAT); \
3447 EA = tcg_temp_new(); \
3448 gen_addr_imm_index(ctx, EA, 0); \
3449 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3450 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3451 tcg_temp_free(EA); \
3452 }
3453
3454 #define GEN_LDUXF(name, ldop, opc, type) \
3455 static void glue(gen_, name##ux)(DisasContext *ctx) \
3456 { \
3457 TCGv EA; \
3458 if (unlikely(!ctx->fpu_enabled)) { \
3459 gen_exception(ctx, POWERPC_EXCP_FPU); \
3460 return; \
3461 } \
3462 if (unlikely(rA(ctx->opcode) == 0)) { \
3463 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3464 return; \
3465 } \
3466 gen_set_access_type(ctx, ACCESS_FLOAT); \
3467 EA = tcg_temp_new(); \
3468 gen_addr_reg_index(ctx, EA); \
3469 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3470 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3471 tcg_temp_free(EA); \
3472 }
3473
3474 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3475 static void glue(gen_, name##x)(DisasContext *ctx) \
3476 { \
3477 TCGv EA; \
3478 if (unlikely(!ctx->fpu_enabled)) { \
3479 gen_exception(ctx, POWERPC_EXCP_FPU); \
3480 return; \
3481 } \
3482 gen_set_access_type(ctx, ACCESS_FLOAT); \
3483 EA = tcg_temp_new(); \
3484 gen_addr_reg_index(ctx, EA); \
3485 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3486 tcg_temp_free(EA); \
3487 }
3488
3489 #define GEN_LDFS(name, ldop, op, type) \
3490 GEN_LDF(name, ldop, op | 0x20, type); \
3491 GEN_LDUF(name, ldop, op | 0x21, type); \
3492 GEN_LDUXF(name, ldop, op | 0x01, type); \
3493 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3494
3495 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3496 {
3497 TCGv t0 = tcg_temp_new();
3498 TCGv_i32 t1 = tcg_temp_new_i32();
3499 gen_qemu_ld32u(ctx, t0, arg2);
3500 tcg_gen_trunc_tl_i32(t1, t0);
3501 tcg_temp_free(t0);
3502 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3503 tcg_temp_free_i32(t1);
3504 }
3505
3506 /* lfd lfdu lfdux lfdx */
3507 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3508 /* lfs lfsu lfsux lfsx */
3509 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3510
3511 /* lfdp */
3512 static void gen_lfdp(DisasContext *ctx)
3513 {
3514 TCGv EA;
3515 if (unlikely(!ctx->fpu_enabled)) {
3516 gen_exception(ctx, POWERPC_EXCP_FPU);
3517 return;
3518 }
3519 gen_set_access_type(ctx, ACCESS_FLOAT);
3520 EA = tcg_temp_new();
3521 gen_addr_imm_index(ctx, EA, 0); \
3522 if (unlikely(ctx->le_mode)) {
3523 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3524 tcg_gen_addi_tl(EA, EA, 8);
3525 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3526 } else {
3527 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3528 tcg_gen_addi_tl(EA, EA, 8);
3529 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3530 }
3531 tcg_temp_free(EA);
3532 }
3533
3534 /* lfdpx */
3535 static void gen_lfdpx(DisasContext *ctx)
3536 {
3537 TCGv EA;
3538 if (unlikely(!ctx->fpu_enabled)) {
3539 gen_exception(ctx, POWERPC_EXCP_FPU);
3540 return;
3541 }
3542 gen_set_access_type(ctx, ACCESS_FLOAT);
3543 EA = tcg_temp_new();
3544 gen_addr_reg_index(ctx, EA);
3545 if (unlikely(ctx->le_mode)) {
3546 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3547 tcg_gen_addi_tl(EA, EA, 8);
3548 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3549 } else {
3550 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3551 tcg_gen_addi_tl(EA, EA, 8);
3552 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3553 }
3554 tcg_temp_free(EA);
3555 }
3556
3557 /* lfiwax */
3558 static void gen_lfiwax(DisasContext *ctx)
3559 {
3560 TCGv EA;
3561 TCGv t0;
3562 if (unlikely(!ctx->fpu_enabled)) {
3563 gen_exception(ctx, POWERPC_EXCP_FPU);
3564 return;
3565 }
3566 gen_set_access_type(ctx, ACCESS_FLOAT);
3567 EA = tcg_temp_new();
3568 t0 = tcg_temp_new();
3569 gen_addr_reg_index(ctx, EA);
3570 gen_qemu_ld32s(ctx, t0, EA);
3571 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3572 tcg_temp_free(EA);
3573 tcg_temp_free(t0);
3574 }
3575
3576 /* lfiwzx */
3577 static void gen_lfiwzx(DisasContext *ctx)
3578 {
3579 TCGv EA;
3580 if (unlikely(!ctx->fpu_enabled)) {
3581 gen_exception(ctx, POWERPC_EXCP_FPU);
3582 return;
3583 }
3584 gen_set_access_type(ctx, ACCESS_FLOAT);
3585 EA = tcg_temp_new();
3586 gen_addr_reg_index(ctx, EA);
3587 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3588 tcg_temp_free(EA);
3589 }
3590 /*** Floating-point store ***/
3591 #define GEN_STF(name, stop, opc, type) \
3592 static void glue(gen_, name)(DisasContext *ctx) \
3593 { \
3594 TCGv EA; \
3595 if (unlikely(!ctx->fpu_enabled)) { \
3596 gen_exception(ctx, POWERPC_EXCP_FPU); \
3597 return; \
3598 } \
3599 gen_set_access_type(ctx, ACCESS_FLOAT); \
3600 EA = tcg_temp_new(); \
3601 gen_addr_imm_index(ctx, EA, 0); \
3602 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3603 tcg_temp_free(EA); \
3604 }
3605
3606 #define GEN_STUF(name, stop, opc, type) \
3607 static void glue(gen_, name##u)(DisasContext *ctx) \
3608 { \
3609 TCGv EA; \
3610 if (unlikely(!ctx->fpu_enabled)) { \
3611 gen_exception(ctx, POWERPC_EXCP_FPU); \
3612 return; \
3613 } \
3614 if (unlikely(rA(ctx->opcode) == 0)) { \
3615 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3616 return; \
3617 } \
3618 gen_set_access_type(ctx, ACCESS_FLOAT); \
3619 EA = tcg_temp_new(); \
3620 gen_addr_imm_index(ctx, EA, 0); \
3621 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3622 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3623 tcg_temp_free(EA); \
3624 }
3625
3626 #define GEN_STUXF(name, stop, opc, type) \
3627 static void glue(gen_, name##ux)(DisasContext *ctx) \
3628 { \
3629 TCGv EA; \
3630 if (unlikely(!ctx->fpu_enabled)) { \
3631 gen_exception(ctx, POWERPC_EXCP_FPU); \
3632 return; \
3633 } \
3634 if (unlikely(rA(ctx->opcode) == 0)) { \
3635 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3636 return; \
3637 } \
3638 gen_set_access_type(ctx, ACCESS_FLOAT); \
3639 EA = tcg_temp_new(); \
3640 gen_addr_reg_index(ctx, EA); \
3641 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3642 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3643 tcg_temp_free(EA); \
3644 }
3645
3646 #define GEN_STXF(name, stop, opc2, opc3, type) \
3647 static void glue(gen_, name##x)(DisasContext *ctx) \
3648 { \
3649 TCGv EA; \
3650 if (unlikely(!ctx->fpu_enabled)) { \
3651 gen_exception(ctx, POWERPC_EXCP_FPU); \
3652 return; \
3653 } \
3654 gen_set_access_type(ctx, ACCESS_FLOAT); \
3655 EA = tcg_temp_new(); \
3656 gen_addr_reg_index(ctx, EA); \
3657 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3658 tcg_temp_free(EA); \
3659 }
3660
3661 #define GEN_STFS(name, stop, op, type) \
3662 GEN_STF(name, stop, op | 0x20, type); \
3663 GEN_STUF(name, stop, op | 0x21, type); \
3664 GEN_STUXF(name, stop, op | 0x01, type); \
3665 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3666
3667 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3668 {
3669 TCGv_i32 t0 = tcg_temp_new_i32();
3670 TCGv t1 = tcg_temp_new();
3671 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3672 tcg_gen_extu_i32_tl(t1, t0);
3673 tcg_temp_free_i32(t0);
3674 gen_qemu_st32(ctx, t1, arg2);
3675 tcg_temp_free(t1);
3676 }
3677
3678 /* stfd stfdu stfdux stfdx */
3679 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3680 /* stfs stfsu stfsux stfsx */
3681 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3682
3683 /* stfdp */
3684 static void gen_stfdp(DisasContext *ctx)
3685 {
3686 TCGv EA;
3687 if (unlikely(!ctx->fpu_enabled)) {
3688 gen_exception(ctx, POWERPC_EXCP_FPU);
3689 return;
3690 }
3691 gen_set_access_type(ctx, ACCESS_FLOAT);
3692 EA = tcg_temp_new();
3693 gen_addr_imm_index(ctx, EA, 0); \
3694 if (unlikely(ctx->le_mode)) {
3695 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3696 tcg_gen_addi_tl(EA, EA, 8);
3697 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3698 } else {
3699 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3700 tcg_gen_addi_tl(EA, EA, 8);
3701 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3702 }
3703 tcg_temp_free(EA);
3704 }
3705
3706 /* stfdpx */
3707 static void gen_stfdpx(DisasContext *ctx)
3708 {
3709 TCGv EA;
3710 if (unlikely(!ctx->fpu_enabled)) {
3711 gen_exception(ctx, POWERPC_EXCP_FPU);
3712 return;
3713 }
3714 gen_set_access_type(ctx, ACCESS_FLOAT);
3715 EA = tcg_temp_new();
3716 gen_addr_reg_index(ctx, EA);
3717 if (unlikely(ctx->le_mode)) {
3718 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3719 tcg_gen_addi_tl(EA, EA, 8);
3720 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3721 } else {
3722 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3723 tcg_gen_addi_tl(EA, EA, 8);
3724 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3725 }
3726 tcg_temp_free(EA);
3727 }
3728
3729 /* Optional: */
3730 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3731 {
3732 TCGv t0 = tcg_temp_new();
3733 tcg_gen_trunc_i64_tl(t0, arg1),
3734 gen_qemu_st32(ctx, t0, arg2);
3735 tcg_temp_free(t0);
3736 }
3737 /* stfiwx */
3738 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3739
3740 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3741 {
3742 #if defined(TARGET_PPC64)
3743 if (ctx->has_cfar)
3744 tcg_gen_movi_tl(cpu_cfar, nip);
3745 #endif
3746 }
3747
3748 /*** Branch ***/
3749 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3750 {
3751 TranslationBlock *tb;
3752 tb = ctx->tb;
3753 if (NARROW_MODE(ctx)) {
3754 dest = (uint32_t) dest;
3755 }
3756 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3757 likely(!ctx->singlestep_enabled)) {
3758 tcg_gen_goto_tb(n);
3759 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3760 tcg_gen_exit_tb((uintptr_t)tb + n);
3761 } else {
3762 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3763 if (unlikely(ctx->singlestep_enabled)) {
3764 if ((ctx->singlestep_enabled &
3765 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3766 (ctx->exception == POWERPC_EXCP_BRANCH ||
3767 ctx->exception == POWERPC_EXCP_TRACE)) {
3768 target_ulong tmp = ctx->nip;
3769 ctx->nip = dest;
3770 gen_exception(ctx, POWERPC_EXCP_TRACE);
3771 ctx->nip = tmp;
3772 }
3773 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3774 gen_debug_exception(ctx);
3775 }
3776 }
3777 tcg_gen_exit_tb(0);
3778 }
3779 }
3780
3781 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3782 {
3783 if (NARROW_MODE(ctx)) {
3784 nip = (uint32_t)nip;
3785 }
3786 tcg_gen_movi_tl(cpu_lr, nip);
3787 }
3788
3789 /* b ba bl bla */
3790 static void gen_b(DisasContext *ctx)
3791 {
3792 target_ulong li, target;
3793
3794 ctx->exception = POWERPC_EXCP_BRANCH;
3795 /* sign extend LI */
3796 li = LI(ctx->opcode);
3797 li = (li ^ 0x02000000) - 0x02000000;
3798 if (likely(AA(ctx->opcode) == 0)) {
3799 target = ctx->nip + li - 4;
3800 } else {
3801 target = li;
3802 }
3803 if (LK(ctx->opcode)) {
3804 gen_setlr(ctx, ctx->nip);
3805 }
3806 gen_update_cfar(ctx, ctx->nip);
3807 gen_goto_tb(ctx, 0, target);
3808 }
3809
3810 #define BCOND_IM 0
3811 #define BCOND_LR 1
3812 #define BCOND_CTR 2
3813 #define BCOND_TAR 3
3814
3815 static inline void gen_bcond(DisasContext *ctx, int type)
3816 {
3817 uint32_t bo = BO(ctx->opcode);
3818 int l1;
3819 TCGv target;
3820
3821 ctx->exception = POWERPC_EXCP_BRANCH;
3822 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3823 target = tcg_temp_local_new();
3824 if (type == BCOND_CTR)
3825 tcg_gen_mov_tl(target, cpu_ctr);
3826 else if (type == BCOND_TAR)
3827 gen_load_spr(target, SPR_TAR);
3828 else
3829 tcg_gen_mov_tl(target, cpu_lr);
3830 } else {
3831 TCGV_UNUSED(target);
3832 }
3833 if (LK(ctx->opcode))
3834 gen_setlr(ctx, ctx->nip);
3835 l1 = gen_new_label();
3836 if ((bo & 0x4) == 0) {
3837 /* Decrement and test CTR */
3838 TCGv temp = tcg_temp_new();
3839 if (unlikely(type == BCOND_CTR)) {
3840 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3841 return;
3842 }
3843 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3844 if (NARROW_MODE(ctx)) {
3845 tcg_gen_ext32u_tl(temp, cpu_ctr);
3846 } else {
3847 tcg_gen_mov_tl(temp, cpu_ctr);
3848 }
3849 if (bo & 0x2) {
3850 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3851 } else {
3852 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3853 }
3854 tcg_temp_free(temp);
3855 }
3856 if ((bo & 0x10) == 0) {
3857 /* Test CR */
3858 uint32_t bi = BI(ctx->opcode);
3859 uint32_t mask = 1 << (3 - (bi & 0x03));
3860 TCGv_i32 temp = tcg_temp_new_i32();
3861
3862 if (bo & 0x8) {
3863 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3864 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3865 } else {
3866 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3867 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3868 }
3869 tcg_temp_free_i32(temp);
3870 }
3871 gen_update_cfar(ctx, ctx->nip);
3872 if (type == BCOND_IM) {
3873 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3874 if (likely(AA(ctx->opcode) == 0)) {
3875 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3876 } else {
3877 gen_goto_tb(ctx, 0, li);
3878 }
3879 gen_set_label(l1);
3880 gen_goto_tb(ctx, 1, ctx->nip);
3881 } else {
3882 if (NARROW_MODE(ctx)) {
3883 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3884 } else {
3885 tcg_gen_andi_tl(cpu_nip, target, ~3);
3886 }
3887 tcg_gen_exit_tb(0);
3888 gen_set_label(l1);
3889 gen_update_nip(ctx, ctx->nip);
3890 tcg_gen_exit_tb(0);
3891 }
3892 }
3893
3894 static void gen_bc(DisasContext *ctx)
3895 {
3896 gen_bcond(ctx, BCOND_IM);
3897 }
3898
3899 static void gen_bcctr(DisasContext *ctx)
3900 {
3901 gen_bcond(ctx, BCOND_CTR);
3902 }
3903
3904 static void gen_bclr(DisasContext *ctx)
3905 {
3906 gen_bcond(ctx, BCOND_LR);
3907 }
3908
3909 static void gen_bctar(DisasContext *ctx)
3910 {
3911 gen_bcond(ctx, BCOND_TAR);
3912 }
3913
3914 /*** Condition register logical ***/
3915 #define GEN_CRLOGIC(name, tcg_op, opc) \
3916 static void glue(gen_, name)(DisasContext *ctx) \
3917 { \
3918 uint8_t bitmask; \
3919 int sh; \
3920 TCGv_i32 t0, t1; \
3921 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3922 t0 = tcg_temp_new_i32(); \
3923 if (sh > 0) \
3924 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3925 else if (sh < 0) \
3926 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3927 else \
3928 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3929 t1 = tcg_temp_new_i32(); \
3930 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3931 if (sh > 0) \
3932 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3933 else if (sh < 0) \
3934 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3935 else \
3936 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3937 tcg_op(t0, t0, t1); \
3938 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3939 tcg_gen_andi_i32(t0, t0, bitmask); \
3940 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3941 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3942 tcg_temp_free_i32(t0); \
3943 tcg_temp_free_i32(t1); \
3944 }
3945
3946 /* crand */
3947 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3948 /* crandc */
3949 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3950 /* creqv */
3951 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3952 /* crnand */
3953 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3954 /* crnor */
3955 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3956 /* cror */
3957 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3958 /* crorc */
3959 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3960 /* crxor */
3961 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3962
3963 /* mcrf */
3964 static void gen_mcrf(DisasContext *ctx)
3965 {
3966 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3967 }
3968
3969 /*** System linkage ***/
3970
3971 /* rfi (mem_idx only) */
3972 static void gen_rfi(DisasContext *ctx)
3973 {
3974 #if defined(CONFIG_USER_ONLY)
3975 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3976 #else
3977 /* Restore CPU state */
3978 if (unlikely(!ctx->mem_idx)) {
3979 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3980 return;
3981 }
3982 gen_update_cfar(ctx, ctx->nip);
3983 gen_helper_rfi(cpu_env);
3984 gen_sync_exception(ctx);
3985 #endif
3986 }
3987
3988 #if defined(TARGET_PPC64)
3989 static void gen_rfid(DisasContext *ctx)
3990 {
3991 #if defined(CONFIG_USER_ONLY)
3992 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3993 #else
3994 /* Restore CPU state */
3995 if (unlikely(!ctx->mem_idx)) {
3996 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3997 return;
3998 }
3999 gen_update_cfar(ctx, ctx->nip);
4000 gen_helper_rfid(cpu_env);
4001 gen_sync_exception(ctx);
4002 #endif
4003 }
4004
4005 static void gen_hrfid(DisasContext *ctx)
4006 {
4007 #if defined(CONFIG_USER_ONLY)
4008 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4009 #else
4010 /* Restore CPU state */
4011 if (unlikely(ctx->mem_idx <= 1)) {
4012 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4013 return;
4014 }
4015 gen_helper_hrfid(cpu_env);
4016 gen_sync_exception(ctx);
4017 #endif
4018 }
4019 #endif
4020
4021 /* sc */
4022 #if defined(CONFIG_USER_ONLY)
4023 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4024 #else
4025 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4026 #endif
4027 static void gen_sc(DisasContext *ctx)
4028 {
4029 uint32_t lev;
4030
4031 lev = (ctx->opcode >> 5) & 0x7F;
4032 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4033 }
4034
4035 /*** Trap ***/
4036
4037 /* tw */
4038 static void gen_tw(DisasContext *ctx)
4039 {
4040 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4041 /* Update the nip since this might generate a trap exception */
4042 gen_update_nip(ctx, ctx->nip);
4043 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4044 t0);
4045 tcg_temp_free_i32(t0);
4046 }
4047
4048 /* twi */
4049 static void gen_twi(DisasContext *ctx)
4050 {
4051 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4052 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4053 /* Update the nip since this might generate a trap exception */
4054 gen_update_nip(ctx, ctx->nip);
4055 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4056 tcg_temp_free(t0);
4057 tcg_temp_free_i32(t1);
4058 }
4059
4060 #if defined(TARGET_PPC64)
4061 /* td */
4062 static void gen_td(DisasContext *ctx)
4063 {
4064 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4065 /* Update the nip since this might generate a trap exception */
4066 gen_update_nip(ctx, ctx->nip);
4067 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4068 t0);
4069 tcg_temp_free_i32(t0);
4070 }
4071
4072 /* tdi */
4073 static void gen_tdi(DisasContext *ctx)
4074 {
4075 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4076 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4077 /* Update the nip since this might generate a trap exception */
4078 gen_update_nip(ctx, ctx->nip);
4079 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4080 tcg_temp_free(t0);
4081 tcg_temp_free_i32(t1);
4082 }
4083 #endif
4084
4085 /*** Processor control ***/
4086
4087 static void gen_read_xer(TCGv dst)
4088 {
4089 TCGv t0 = tcg_temp_new();
4090 TCGv t1 = tcg_temp_new();
4091 TCGv t2 = tcg_temp_new();
4092 tcg_gen_mov_tl(dst, cpu_xer);
4093 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4094 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4095 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4096 tcg_gen_or_tl(t0, t0, t1);
4097 tcg_gen_or_tl(dst, dst, t2);
4098 tcg_gen_or_tl(dst, dst, t0);
4099 tcg_temp_free(t0);
4100 tcg_temp_free(t1);
4101 tcg_temp_free(t2);
4102 }
4103
4104 static void gen_write_xer(TCGv src)
4105 {
4106 tcg_gen_andi_tl(cpu_xer, src,
4107 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4108 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4109 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4110 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4111 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4112 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4113 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4114 }
4115
4116 /* mcrxr */
4117 static void gen_mcrxr(DisasContext *ctx)
4118 {
4119 TCGv_i32 t0 = tcg_temp_new_i32();
4120 TCGv_i32 t1 = tcg_temp_new_i32();
4121 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4122
4123 tcg_gen_trunc_tl_i32(t0, cpu_so);
4124 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4125 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4126 tcg_gen_shri_i32(t0, t0, 2);
4127 tcg_gen_shri_i32(t1, t1, 1);
4128 tcg_gen_or_i32(dst, dst, t0);
4129 tcg_gen_or_i32(dst, dst, t1);
4130 tcg_temp_free_i32(t0);
4131 tcg_temp_free_i32(t1);
4132
4133 tcg_gen_movi_tl(cpu_so, 0);
4134 tcg_gen_movi_tl(cpu_ov, 0);
4135 tcg_gen_movi_tl(cpu_ca, 0);
4136 }
4137
4138 /* mfcr mfocrf */
4139 static void gen_mfcr(DisasContext *ctx)
4140 {
4141 uint32_t crm, crn;
4142
4143 if (likely(ctx->opcode & 0x00100000)) {
4144 crm = CRM(ctx->opcode);
4145 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4146 crn = ctz32 (crm);
4147 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4148 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4149 cpu_gpr[rD(ctx->opcode)], crn * 4);
4150 }
4151 } else {
4152 TCGv_i32 t0 = tcg_temp_new_i32();
4153 tcg_gen_mov_i32(t0, cpu_crf[0]);
4154 tcg_gen_shli_i32(t0, t0, 4);
4155 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4156 tcg_gen_shli_i32(t0, t0, 4);
4157 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4158 tcg_gen_shli_i32(t0, t0, 4);
4159 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4160 tcg_gen_shli_i32(t0, t0, 4);
4161 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4162 tcg_gen_shli_i32(t0, t0, 4);
4163 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4164 tcg_gen_shli_i32(t0, t0, 4);
4165 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4166 tcg_gen_shli_i32(t0, t0, 4);
4167 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4168 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4169 tcg_temp_free_i32(t0);
4170 }
4171 }
4172
4173 /* mfmsr */
4174 static void gen_mfmsr(DisasContext *ctx)
4175 {
4176 #if defined(CONFIG_USER_ONLY)
4177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4178 #else
4179 if (unlikely(!ctx->mem_idx)) {
4180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4181 return;
4182 }
4183 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4184 #endif
4185 }
4186
4187 static void spr_noaccess(void *opaque, int gprn, int sprn)
4188 {
4189 #if 0
4190 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4191 printf("ERROR: try to access SPR %d !\n", sprn);
4192 #endif
4193 }
4194 #define SPR_NOACCESS (&spr_noaccess)
4195
4196 /* mfspr */
4197 static inline void gen_op_mfspr(DisasContext *ctx)
4198 {
4199 void (*read_cb)(void *opaque, int gprn, int sprn);
4200 uint32_t sprn = SPR(ctx->opcode);
4201
4202 #if !defined(CONFIG_USER_ONLY)
4203 if (ctx->mem_idx == 2)
4204 read_cb = ctx->spr_cb[sprn].hea_read;
4205 else if (ctx->mem_idx)
4206 read_cb = ctx->spr_cb[sprn].oea_read;
4207 else
4208 #endif
4209 read_cb = ctx->spr_cb[sprn].uea_read;
4210 if (likely(read_cb != NULL)) {
4211 if (likely(read_cb != SPR_NOACCESS)) {
4212 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4213 } else {
4214 /* Privilege exception */
4215 /* This is a hack to avoid warnings when running Linux:
4216 * this OS breaks the PowerPC virtualisation model,
4217 * allowing userland application to read the PVR
4218 */
4219 if (sprn != SPR_PVR) {
4220 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4221 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4222 printf("Trying to read privileged spr %d (0x%03x) at "
4223 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4224 }
4225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4226 }
4227 } else {
4228 /* Not defined */
4229 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4230 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4231 printf("Trying to read invalid spr %d (0x%03x) at "
4232 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4233 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4234 }
4235 }
4236
4237 static void gen_mfspr(DisasContext *ctx)
4238 {
4239 gen_op_mfspr(ctx);
4240 }
4241
4242 /* mftb */
4243 static void gen_mftb(DisasContext *ctx)
4244 {
4245 gen_op_mfspr(ctx);
4246 }
4247
4248 /* mtcrf mtocrf*/
4249 static void gen_mtcrf(DisasContext *ctx)
4250 {
4251 uint32_t crm, crn;
4252
4253 crm = CRM(ctx->opcode);
4254 if (likely((ctx->opcode & 0x00100000))) {
4255 if (crm && ((crm & (crm - 1)) == 0)) {
4256 TCGv_i32 temp = tcg_temp_new_i32();
4257 crn = ctz32 (crm);
4258 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4259 tcg_gen_shri_i32(temp, temp, crn * 4);
4260 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4261 tcg_temp_free_i32(temp);
4262 }
4263 } else {
4264 TCGv_i32 temp = tcg_temp_new_i32();
4265 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4266 for (crn = 0 ; crn < 8 ; crn++) {
4267 if (crm & (1 << crn)) {
4268 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4269 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4270 }
4271 }
4272 tcg_temp_free_i32(temp);
4273 }
4274 }
4275
4276 /* mtmsr */
4277 #if defined(TARGET_PPC64)
4278 static void gen_mtmsrd(DisasContext *ctx)
4279 {
4280 #if defined(CONFIG_USER_ONLY)
4281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4282 #else
4283 if (unlikely(!ctx->mem_idx)) {
4284 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4285 return;
4286 }
4287 if (ctx->opcode & 0x00010000) {
4288 /* Special form that does not need any synchronisation */
4289 TCGv t0 = tcg_temp_new();
4290 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4291 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4292 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4293 tcg_temp_free(t0);
4294 } else {
4295 /* XXX: we need to update nip before the store
4296 * if we enter power saving mode, we will exit the loop
4297 * directly from ppc_store_msr
4298 */
4299 gen_update_nip(ctx, ctx->nip);
4300 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4301 /* Must stop the translation as machine state (may have) changed */
4302 /* Note that mtmsr is not always defined as context-synchronizing */
4303 gen_stop_exception(ctx);
4304 }
4305 #endif
4306 }
4307 #endif
4308
4309 static void gen_mtmsr(DisasContext *ctx)
4310 {
4311 #if defined(CONFIG_USER_ONLY)
4312 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4313 #else
4314 if (unlikely(!ctx->mem_idx)) {
4315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4316 return;
4317 }
4318 if (ctx->opcode & 0x00010000) {
4319 /* Special form that does not need any synchronisation */
4320 TCGv t0 = tcg_temp_new();
4321 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4322 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4323 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4324 tcg_temp_free(t0);
4325 } else {
4326 TCGv msr = tcg_temp_new();
4327
4328 /* XXX: we need to update nip before the store
4329 * if we enter power saving mode, we will exit the loop
4330 * directly from ppc_store_msr
4331 */
4332 gen_update_nip(ctx, ctx->nip);
4333 #if defined(TARGET_PPC64)
4334 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4335 #else
4336 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4337 #endif
4338 gen_helper_store_msr(cpu_env, msr);
4339 /* Must stop the translation as machine state (may have) changed */
4340 /* Note that mtmsr is not always defined as context-synchronizing */
4341 gen_stop_exception(ctx);
4342 }
4343 #endif
4344 }
4345
4346 /* mtspr */
4347 static void gen_mtspr(DisasContext *ctx)
4348 {
4349 void (*write_cb)(void *opaque, int sprn, int gprn);
4350 uint32_t sprn = SPR(ctx->opcode);
4351
4352 #if !defined(CONFIG_USER_ONLY)
4353 if (ctx->mem_idx == 2)
4354 write_cb = ctx->spr_cb[sprn].hea_write;
4355 else if (ctx->mem_idx)
4356 write_cb = ctx->spr_cb[sprn].oea_write;
4357 else
4358 #endif
4359 write_cb = ctx->spr_cb[sprn].uea_write;
4360 if (likely(write_cb != NULL)) {
4361 if (likely(write_cb != SPR_NOACCESS)) {
4362 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4363 } else {
4364 /* Privilege exception */
4365 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4366 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4367 printf("Trying to write privileged spr %d (0x%03x) at "
4368 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4369 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4370 }
4371 } else {
4372 /* Not defined */
4373 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4374 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4375 printf("Trying to write invalid spr %d (0x%03x) at "
4376 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4377 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4378 }
4379 }
4380
4381 /*** Cache management ***/
4382
4383 /* dcbf */
4384 static void gen_dcbf(DisasContext *ctx)
4385 {
4386 /* XXX: specification says this is treated as a load by the MMU */
4387 TCGv t0;
4388 gen_set_access_type(ctx, ACCESS_CACHE);
4389 t0 = tcg_temp_new();
4390 gen_addr_reg_index(ctx, t0);
4391 gen_qemu_ld8u(ctx, t0, t0);
4392 tcg_temp_free(t0);
4393 }
4394
4395 /* dcbi (Supervisor only) */
4396 static void gen_dcbi(DisasContext *ctx)
4397 {
4398 #if defined(CONFIG_USER_ONLY)
4399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4400 #else
4401 TCGv EA, val;
4402 if (unlikely(!ctx->mem_idx)) {
4403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4404 return;
4405 }
4406 EA = tcg_temp_new();
4407 gen_set_access_type(ctx, ACCESS_CACHE);
4408 gen_addr_reg_index(ctx, EA);
4409 val = tcg_temp_new();
4410 /* XXX: specification says this should be treated as a store by the MMU */
4411 gen_qemu_ld8u(ctx, val, EA);
4412 gen_qemu_st8(ctx, val, EA);
4413 tcg_temp_free(val);
4414 tcg_temp_free(EA);
4415 #endif
4416 }
4417
4418 /* dcdst */
4419 static void gen_dcbst(DisasContext *ctx)
4420 {
4421 /* XXX: specification say this is treated as a load by the MMU */
4422 TCGv t0;
4423 gen_set_access_type(ctx, ACCESS_CACHE);
4424 t0 = tcg_temp_new();
4425 gen_addr_reg_index(ctx, t0);
4426 gen_qemu_ld8u(ctx, t0, t0);
4427 tcg_temp_free(t0);
4428 }
4429
4430 /* dcbt */
4431 static void gen_dcbt(DisasContext *ctx)
4432 {
4433 /* interpreted as no-op */
4434 /* XXX: specification say this is treated as a load by the MMU
4435 * but does not generate any exception
4436 */
4437 }
4438
4439 /* dcbtst */
4440 static void gen_dcbtst(DisasContext *ctx)
4441 {
4442 /* interpreted as no-op */
4443 /* XXX: specification say this is treated as a load by the MMU
4444 * but does not generate any exception
4445 */
4446 }
4447
4448 /* dcbz */
4449 static void gen_dcbz(DisasContext *ctx)
4450 {
4451 TCGv tcgv_addr;
4452 TCGv_i32 tcgv_is_dcbzl;
4453 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4454
4455 gen_set_access_type(ctx, ACCESS_CACHE);
4456 /* NIP cannot be restored if the memory exception comes from an helper */
4457 gen_update_nip(ctx, ctx->nip - 4);
4458 tcgv_addr = tcg_temp_new();
4459 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4460
4461 gen_addr_reg_index(ctx, tcgv_addr);
4462 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4463
4464 tcg_temp_free(tcgv_addr);
4465 tcg_temp_free_i32(tcgv_is_dcbzl);
4466 }
4467
4468 /* dst / dstt */
4469 static void gen_dst(DisasContext *ctx)
4470 {
4471 if (rA(ctx->opcode) == 0) {
4472 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4473 } else {
4474 /* interpreted as no-op */
4475 }
4476 }
4477
4478 /* dstst /dststt */
4479 static void gen_dstst(DisasContext *ctx)
4480 {
4481 if (rA(ctx->opcode) == 0) {
4482 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4483 } else {
4484 /* interpreted as no-op */
4485 }
4486
4487 }
4488
4489 /* dss / dssall */
4490 static void gen_dss(DisasContext *ctx)
4491 {
4492 /* interpreted as no-op */
4493 }
4494
4495 /* icbi */
4496 static void gen_icbi(DisasContext *ctx)
4497 {
4498 TCGv t0;
4499 gen_set_access_type(ctx, ACCESS_CACHE);
4500 /* NIP cannot be restored if the memory exception comes from an helper */
4501 gen_update_nip(ctx, ctx->nip - 4);
4502 t0 = tcg_temp_new();
4503 gen_addr_reg_index(ctx, t0);
4504 gen_helper_icbi(cpu_env, t0);
4505 tcg_temp_free(t0);
4506 }
4507
4508 /* Optional: */
4509 /* dcba */
4510 static void gen_dcba(DisasContext *ctx)
4511 {
4512 /* interpreted as no-op */
4513 /* XXX: specification say this is treated as a store by the MMU
4514 * but does not generate any exception
4515 */
4516 }
4517
4518 /*** Segment register manipulation ***/
4519 /* Supervisor only: */
4520
4521 /* mfsr */
4522 static void gen_mfsr(DisasContext *ctx)
4523 {
4524 #if defined(CONFIG_USER_ONLY)
4525 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4526 #else
4527 TCGv t0;
4528 if (unlikely(!ctx->mem_idx)) {
4529 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4530 return;
4531 }
4532 t0 = tcg_const_tl(SR(ctx->opcode));
4533 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4534 tcg_temp_free(t0);
4535 #endif
4536 }
4537
4538 /* mfsrin */
4539 static void gen_mfsrin(DisasContext *ctx)
4540 {
4541 #if defined(CONFIG_USER_ONLY)
4542 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4543 #else
4544 TCGv t0;
4545 if (unlikely(!ctx->mem_idx)) {
4546 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4547 return;
4548 }
4549 t0 = tcg_temp_new();
4550 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4551 tcg_gen_andi_tl(t0, t0, 0xF);
4552 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4553 tcg_temp_free(t0);
4554 #endif
4555 }
4556
4557 /* mtsr */
4558 static void gen_mtsr(DisasContext *ctx)
4559 {
4560 #if defined(CONFIG_USER_ONLY)
4561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4562 #else
4563 TCGv t0;
4564 if (unlikely(!ctx->mem_idx)) {
4565 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4566 return;
4567 }
4568 t0 = tcg_const_tl(SR(ctx->opcode));
4569 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4570 tcg_temp_free(t0);
4571 #endif
4572 }
4573
4574 /* mtsrin */
4575 static void gen_mtsrin(DisasContext *ctx)
4576 {
4577 #if defined(CONFIG_USER_ONLY)
4578 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4579 #else
4580 TCGv t0;
4581 if (unlikely(!ctx->mem_idx)) {
4582 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4583 return;
4584 }
4585 t0 = tcg_temp_new();
4586 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4587 tcg_gen_andi_tl(t0, t0, 0xF);
4588 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4589 tcg_temp_free(t0);
4590 #endif
4591 }
4592
4593 #if defined(TARGET_PPC64)
4594 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4595
4596 /* mfsr */
4597 static void gen_mfsr_64b(DisasContext *ctx)
4598 {
4599 #if defined(CONFIG_USER_ONLY)
4600 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4601 #else
4602 TCGv t0;
4603 if (unlikely(!ctx->mem_idx)) {
4604 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4605 return;
4606 }
4607 t0 = tcg_const_tl(SR(ctx->opcode));
4608 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4609 tcg_temp_free(t0);
4610 #endif
4611 }
4612
4613 /* mfsrin */
4614 static void gen_mfsrin_64b(DisasContext *ctx)
4615 {
4616 #if defined(CONFIG_USER_ONLY)
4617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4618 #else
4619 TCGv t0;
4620 if (unlikely(!ctx->mem_idx)) {
4621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4622 return;
4623 }
4624 t0 = tcg_temp_new();
4625 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4626 tcg_gen_andi_tl(t0, t0, 0xF);
4627 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4628 tcg_temp_free(t0);
4629 #endif
4630 }
4631
4632 /* mtsr */
4633 static void gen_mtsr_64b(DisasContext *ctx)
4634 {
4635 #if defined(CONFIG_USER_ONLY)
4636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4637 #else
4638 TCGv t0;
4639 if (unlikely(!ctx->mem_idx)) {
4640 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4641 return;
4642 }
4643 t0 = tcg_const_tl(SR(ctx->opcode));
4644 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4645 tcg_temp_free(t0);
4646 #endif
4647 }
4648
4649 /* mtsrin */
4650 static void gen_mtsrin_64b(DisasContext *ctx)
4651 {
4652 #if defined(CONFIG_USER_ONLY)
4653 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4654 #else
4655 TCGv t0;
4656 if (unlikely(!ctx->mem_idx)) {
4657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4658 return;
4659 }
4660 t0 = tcg_temp_new();
4661 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4662 tcg_gen_andi_tl(t0, t0, 0xF);
4663 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4664 tcg_temp_free(t0);
4665 #endif
4666 }
4667
4668 /* slbmte */
4669 static void gen_slbmte(DisasContext *ctx)
4670 {
4671 #if defined(CONFIG_USER_ONLY)
4672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4673 #else
4674 if (unlikely(!ctx->mem_idx)) {
4675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4676 return;
4677 }
4678 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4679 cpu_gpr[rS(ctx->opcode)]);
4680 #endif
4681 }
4682
4683 static void gen_slbmfee(DisasContext *ctx)
4684 {
4685 #if defined(CONFIG_USER_ONLY)
4686 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4687 #else
4688 if (unlikely(!ctx->mem_idx)) {
4689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4690 return;
4691 }
4692 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4693 cpu_gpr[rB(ctx->opcode)]);
4694 #endif
4695 }
4696
4697 static void gen_slbmfev(DisasContext *ctx)
4698 {
4699 #if defined(CONFIG_USER_ONLY)
4700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4701 #else
4702 if (unlikely(!ctx->mem_idx)) {
4703 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4704 return;
4705 }
4706 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4707 cpu_gpr[rB(ctx->opcode)]);
4708 #endif
4709 }
4710 #endif /* defined(TARGET_PPC64) */
4711
4712 /*** Lookaside buffer management ***/
4713 /* Optional & mem_idx only: */
4714
4715 /* tlbia */
4716 static void gen_tlbia(DisasContext *ctx)
4717 {
4718 #if defined(CONFIG_USER_ONLY)
4719 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4720 #else
4721 if (unlikely(!ctx->mem_idx)) {
4722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4723 return;
4724 }
4725 gen_helper_tlbia(cpu_env);
4726 #endif
4727 }
4728
4729 /* tlbiel */
4730 static void gen_tlbiel(DisasContext *ctx)
4731 {
4732 #if defined(CONFIG_USER_ONLY)
4733 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4734 #else
4735 if (unlikely(!ctx->mem_idx)) {
4736 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4737 return;
4738 }
4739 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4740 #endif
4741 }
4742
4743 /* tlbie */
4744 static void gen_tlbie(DisasContext *ctx)
4745 {
4746 #if defined(CONFIG_USER_ONLY)
4747 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4748 #else
4749 if (unlikely(!ctx->mem_idx)) {
4750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4751 return;
4752 }
4753 if (NARROW_MODE(ctx)) {
4754 TCGv t0 = tcg_temp_new();
4755 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4756 gen_helper_tlbie(cpu_env, t0);
4757 tcg_temp_free(t0);
4758 } else {
4759 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4760 }
4761 #endif
4762 }
4763
4764 /* tlbsync */
4765 static void gen_tlbsync(DisasContext *ctx)
4766 {
4767 #if defined(CONFIG_USER_ONLY)
4768 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4769 #else
4770 if (unlikely(!ctx->mem_idx)) {
4771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4772 return;
4773 }
4774 /* This has no effect: it should ensure that all previous
4775 * tlbie have completed
4776 */
4777 gen_stop_exception(ctx);
4778 #endif
4779 }
4780
4781 #if defined(TARGET_PPC64)
4782 /* slbia */
4783 static void gen_slbia(DisasContext *ctx)
4784 {
4785 #if defined(CONFIG_USER_ONLY)
4786 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4787 #else
4788 if (unlikely(!ctx->mem_idx)) {
4789 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4790 return;
4791 }
4792 gen_helper_slbia(cpu_env);
4793 #endif
4794 }
4795
4796 /* slbie */
4797 static void gen_slbie(DisasContext *ctx)
4798 {
4799 #if defined(CONFIG_USER_ONLY)
4800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4801 #else
4802 if (unlikely(!ctx->mem_idx)) {
4803 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4804 return;
4805 }
4806 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4807 #endif
4808 }
4809 #endif
4810
4811 /*** External control ***/
4812 /* Optional: */
4813
4814 /* eciwx */
4815 static void gen_eciwx(DisasContext *ctx)
4816 {
4817 TCGv t0;
4818 /* Should check EAR[E] ! */
4819 gen_set_access_type(ctx, ACCESS_EXT);
4820 t0 = tcg_temp_new();
4821 gen_addr_reg_index(ctx, t0);
4822 gen_check_align(ctx, t0, 0x03);
4823 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4824 tcg_temp_free(t0);
4825 }
4826
4827 /* ecowx */
4828 static void gen_ecowx(DisasContext *ctx)
4829 {
4830 TCGv t0;
4831 /* Should check EAR[E] ! */
4832 gen_set_access_type(ctx, ACCESS_EXT);
4833 t0 = tcg_temp_new();
4834 gen_addr_reg_index(ctx, t0);
4835 gen_check_align(ctx, t0, 0x03);
4836 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4837 tcg_temp_free(t0);
4838 }
4839
4840 /* PowerPC 601 specific instructions */
4841
4842 /* abs - abs. */
4843 static void gen_abs(DisasContext *ctx)
4844 {
4845 int l1 = gen_new_label();
4846 int l2 = gen_new_label();
4847 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4848 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4849 tcg_gen_br(l2);
4850 gen_set_label(l1);
4851 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4852 gen_set_label(l2);
4853 if (unlikely(Rc(ctx->opcode) != 0))
4854 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4855 }
4856
4857 /* abso - abso. */
4858 static void gen_abso(DisasContext *ctx)
4859 {
4860 int l1 = gen_new_label();
4861 int l2 = gen_new_label();
4862 int l3 = gen_new_label();
4863 /* Start with XER OV disabled, the most likely case */
4864 tcg_gen_movi_tl(cpu_ov, 0);
4865 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4866 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4867 tcg_gen_movi_tl(cpu_ov, 1);
4868 tcg_gen_movi_tl(cpu_so, 1);
4869 tcg_gen_br(l2);
4870 gen_set_label(l1);
4871 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4872 tcg_gen_br(l3);
4873 gen_set_label(l2);
4874 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4875 gen_set_label(l3);
4876 if (unlikely(Rc(ctx->opcode) != 0))
4877 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4878 }
4879
4880 /* clcs */
4881 static void gen_clcs(DisasContext *ctx)
4882 {
4883 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4884 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4885 tcg_temp_free_i32(t0);
4886 /* Rc=1 sets CR0 to an undefined state */
4887 }
4888
4889 /* div - div. */
4890 static void gen_div(DisasContext *ctx)
4891 {
4892 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4893 cpu_gpr[rB(ctx->opcode)]);
4894 if (unlikely(Rc(ctx->opcode) != 0))
4895 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4896 }
4897
4898 /* divo - divo. */
4899 static void gen_divo(DisasContext *ctx)
4900 {
4901 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4902 cpu_gpr[rB(ctx->opcode)]);
4903 if (unlikely(Rc(ctx->opcode) != 0))
4904 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4905 }
4906
4907 /* divs - divs. */
4908 static void gen_divs(DisasContext *ctx)
4909 {
4910 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4911 cpu_gpr[rB(ctx->opcode)]);
4912 if (unlikely(Rc(ctx->opcode) != 0))
4913 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4914 }
4915
4916 /* divso - divso. */
4917 static void gen_divso(DisasContext *ctx)
4918 {
4919 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4920 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4921 if (unlikely(Rc(ctx->opcode) != 0))
4922 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4923 }
4924
4925 /* doz - doz. */
4926 static void gen_doz(DisasContext *ctx)
4927 {
4928 int l1 = gen_new_label();
4929 int l2 = gen_new_label();
4930 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4931 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4932 tcg_gen_br(l2);
4933 gen_set_label(l1);
4934 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4935 gen_set_label(l2);
4936 if (unlikely(Rc(ctx->opcode) != 0))
4937 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4938 }
4939
4940 /* dozo - dozo. */
4941 static void gen_dozo(DisasContext *ctx)
4942 {
4943 int l1 = gen_new_label();
4944 int l2 = gen_new_label();
4945 TCGv t0 = tcg_temp_new();
4946 TCGv t1 = tcg_temp_new();
4947 TCGv t2 = tcg_temp_new();
4948 /* Start with XER OV disabled, the most likely case */
4949 tcg_gen_movi_tl(cpu_ov, 0);
4950 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4951 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4952 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4953 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4954 tcg_gen_andc_tl(t1, t1, t2);
4955 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4956 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4957 tcg_gen_movi_tl(cpu_ov, 1);
4958 tcg_gen_movi_tl(cpu_so, 1);
4959 tcg_gen_br(l2);
4960 gen_set_label(l1);
4961 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4962 gen_set_label(l2);
4963 tcg_temp_free(t0);
4964 tcg_temp_free(t1);
4965 tcg_temp_free(t2);
4966 if (unlikely(Rc(ctx->opcode) != 0))
4967 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4968 }
4969
4970 /* dozi */
4971 static void gen_dozi(DisasContext *ctx)
4972 {
4973 target_long simm = SIMM(ctx->opcode);
4974 int l1 = gen_new_label();
4975 int l2 = gen_new_label();
4976 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4977 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4978 tcg_gen_br(l2);
4979 gen_set_label(l1);
4980 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4981 gen_set_label(l2);
4982 if (unlikely(Rc(ctx->opcode) != 0))
4983 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4984 }
4985
4986 /* lscbx - lscbx. */
4987 static void gen_lscbx(DisasContext *ctx)
4988 {
4989 TCGv t0 = tcg_temp_new();
4990 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4991 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4992 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4993
4994 gen_addr_reg_index(ctx, t0);
4995 /* NIP cannot be restored if the memory exception comes from an helper */
4996 gen_update_nip(ctx, ctx->nip - 4);
4997 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4998 tcg_temp_free_i32(t1);
4999 tcg_temp_free_i32(t2);
5000 tcg_temp_free_i32(t3);
5001 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5002 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5003 if (unlikely(Rc(ctx->opcode) != 0))
5004 gen_set_Rc0(ctx, t0);
5005 tcg_temp_free(t0);
5006 }
5007
5008 /* maskg - maskg. */
5009 static void gen_maskg(DisasContext *ctx)
5010 {
5011 int l1 = gen_new_label();
5012 TCGv t0 = tcg_temp_new();
5013 TCGv t1 = tcg_temp_new();
5014 TCGv t2 = tcg_temp_new();
5015 TCGv t3 = tcg_temp_new();
5016 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5017 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5018 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5019 tcg_gen_addi_tl(t2, t0, 1);
5020 tcg_gen_shr_tl(t2, t3, t2);
5021 tcg_gen_shr_tl(t3, t3, t1);
5022 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5023 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5024 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5025 gen_set_label(l1);
5026 tcg_temp_free(t0);
5027 tcg_temp_free(t1);
5028 tcg_temp_free(t2);
5029 tcg_temp_free(t3);
5030 if (unlikely(Rc(ctx->opcode) != 0))
5031 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5032 }
5033
5034 /* maskir - maskir. */
5035 static void gen_maskir(DisasContext *ctx)
5036 {
5037 TCGv t0 = tcg_temp_new();
5038 TCGv t1 = tcg_temp_new();
5039 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5040 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5041 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5042 tcg_temp_free(t0);
5043 tcg_temp_free(t1);
5044 if (unlikely(Rc(ctx->opcode) != 0))
5045 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5046 }
5047
5048 /* mul - mul. */
5049 static void gen_mul(DisasContext *ctx)
5050 {
5051 TCGv_i64 t0 = tcg_temp_new_i64();
5052 TCGv_i64 t1 = tcg_temp_new_i64();
5053 TCGv t2 = tcg_temp_new();
5054 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5055 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5056 tcg_gen_mul_i64(t0, t0, t1);
5057 tcg_gen_trunc_i64_tl(t2, t0);
5058 gen_store_spr(SPR_MQ, t2);
5059 tcg_gen_shri_i64(t1, t0, 32);
5060 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5061 tcg_temp_free_i64(t0);
5062 tcg_temp_free_i64(t1);
5063 tcg_temp_free(t2);
5064 if (unlikely(Rc(ctx->opcode) != 0))
5065 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5066 }
5067
5068 /* mulo - mulo. */
5069 static void gen_mulo(DisasContext *ctx)
5070 {
5071 int l1 = gen_new_label();
5072 TCGv_i64 t0 = tcg_temp_new_i64();
5073 TCGv_i64 t1 = tcg_temp_new_i64();
5074 TCGv t2 = tcg_temp_new();
5075 /* Start with XER OV disabled, the most likely case */
5076 tcg_gen_movi_tl(cpu_ov, 0);
5077 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5078 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5079 tcg_gen_mul_i64(t0, t0, t1);
5080 tcg_gen_trunc_i64_tl(t2, t0);
5081 gen_store_spr(SPR_MQ, t2);
5082 tcg_gen_shri_i64(t1, t0, 32);
5083 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5084 tcg_gen_ext32s_i64(t1, t0);
5085 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5086 tcg_gen_movi_tl(cpu_ov, 1);
5087 tcg_gen_movi_tl(cpu_so, 1);
5088 gen_set_label(l1);
5089 tcg_temp_free_i64(t0);
5090 tcg_temp_free_i64(t1);
5091 tcg_temp_free(t2);
5092 if (unlikely(Rc(ctx->opcode) != 0))
5093 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5094 }
5095
5096 /* nabs - nabs. */
5097 static void gen_nabs(DisasContext *ctx)
5098 {
5099 int l1 = gen_new_label();
5100 int l2 = gen_new_label();
5101 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5102 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5103 tcg_gen_br(l2);
5104 gen_set_label(l1);
5105 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5106 gen_set_label(l2);
5107 if (unlikely(Rc(ctx->opcode) != 0))
5108 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5109 }
5110
5111 /* nabso - nabso. */
5112 static void gen_nabso(DisasContext *ctx)
5113 {
5114 int l1 = gen_new_label();
5115 int l2 = gen_new_label();
5116 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5117 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5118 tcg_gen_br(l2);
5119 gen_set_label(l1);
5120 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5121 gen_set_label(l2);
5122 /* nabs never overflows */
5123 tcg_gen_movi_tl(cpu_ov, 0);
5124 if (unlikely(Rc(ctx->opcode) != 0))
5125 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5126 }
5127
5128 /* rlmi - rlmi. */
5129 static void gen_rlmi(DisasContext *ctx)
5130 {
5131 uint32_t mb = MB(ctx->opcode);
5132 uint32_t me = ME(ctx->opcode);
5133 TCGv t0 = tcg_temp_new();
5134 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5135 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5136 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5137 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5138 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5139 tcg_temp_free(t0);
5140 if (unlikely(Rc(ctx->opcode) != 0))
5141 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5142 }
5143
5144 /* rrib - rrib. */
5145 static void gen_rrib(DisasContext *ctx)
5146 {
5147 TCGv t0 = tcg_temp_new();
5148 TCGv t1 = tcg_temp_new();
5149 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5150 tcg_gen_movi_tl(t1, 0x80000000);
5151 tcg_gen_shr_tl(t1, t1, t0);
5152 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5153 tcg_gen_and_tl(t0, t0, t1);
5154 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5155 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5156 tcg_temp_free(t0);
5157 tcg_temp_free(t1);
5158 if (unlikely(Rc(ctx->opcode) != 0))
5159 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5160 }
5161
5162 /* sle - sle. */
5163 static void gen_sle(DisasContext *ctx)
5164 {
5165 TCGv t0 = tcg_temp_new();
5166 TCGv t1 = tcg_temp_new();
5167 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5168 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5169 tcg_gen_subfi_tl(t1, 32, t1);
5170 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5171 tcg_gen_or_tl(t1, t0, t1);
5172 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5173 gen_store_spr(SPR_MQ, t1);
5174 tcg_temp_free(t0);
5175 tcg_temp_free(t1);
5176 if (unlikely(Rc(ctx->opcode) != 0))
5177 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5178 }
5179
5180 /* sleq - sleq. */
5181 static void gen_sleq(DisasContext *ctx)
5182 {
5183 TCGv t0 = tcg_temp_new();
5184 TCGv t1 = tcg_temp_new();
5185 TCGv t2 = tcg_temp_new();
5186 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5187 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5188 tcg_gen_shl_tl(t2, t2, t0);
5189 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5190 gen_load_spr(t1, SPR_MQ);
5191 gen_store_spr(SPR_MQ, t0);
5192 tcg_gen_and_tl(t0, t0, t2);
5193 tcg_gen_andc_tl(t1, t1, t2);
5194 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5195 tcg_temp_free(t0);
5196 tcg_temp_free(t1);
5197 tcg_temp_free(t2);
5198 if (unlikely(Rc(ctx->opcode) != 0))
5199 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5200 }
5201
5202 /* sliq - sliq. */
5203 static void gen_sliq(DisasContext *ctx)
5204 {
5205 int sh = SH(ctx->opcode);
5206 TCGv t0 = tcg_temp_new();
5207 TCGv t1 = tcg_temp_new();
5208 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5209 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5210 tcg_gen_or_tl(t1, t0, t1);
5211 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5212 gen_store_spr(SPR_MQ, t1);
5213 tcg_temp_free(t0);
5214 tcg_temp_free(t1);
5215 if (unlikely(Rc(ctx->opcode) != 0))
5216 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5217 }
5218
5219 /* slliq - slliq. */
5220 static void gen_slliq(DisasContext *ctx)
5221 {
5222 int sh = SH(ctx->opcode);
5223 TCGv t0 = tcg_temp_new();
5224 TCGv t1 = tcg_temp_new();
5225 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5226 gen_load_spr(t1, SPR_MQ);
5227 gen_store_spr(SPR_MQ, t0);
5228 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5229 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5230 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5231 tcg_temp_free(t0);
5232 tcg_temp_free(t1);
5233 if (unlikely(Rc(ctx->opcode) != 0))
5234 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5235 }
5236
5237 /* sllq - sllq. */
5238 static void gen_sllq(DisasContext *ctx)
5239 {
5240 int l1 = gen_new_label();
5241 int l2 = gen_new_label();
5242 TCGv t0 = tcg_temp_local_new();
5243 TCGv t1 = tcg_temp_local_new();
5244 TCGv t2 = tcg_temp_local_new();
5245 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5246 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5247 tcg_gen_shl_tl(t1, t1, t2);
5248 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5249 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5250 gen_load_spr(t0, SPR_MQ);
5251 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5252 tcg_gen_br(l2);
5253 gen_set_label(l1);
5254 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5255 gen_load_spr(t2, SPR_MQ);
5256 tcg_gen_andc_tl(t1, t2, t1);
5257 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5258 gen_set_label(l2);
5259 tcg_temp_free(t0);
5260 tcg_temp_free(t1);
5261 tcg_temp_free(t2);
5262 if (unlikely(Rc(ctx->opcode) != 0))
5263 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5264 }
5265
5266 /* slq - slq. */
5267 static void gen_slq(DisasContext *ctx)
5268 {
5269 int l1 = gen_new_label();
5270 TCGv t0 = tcg_temp_new();
5271 TCGv t1 = tcg_temp_new();
5272 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5273 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5274 tcg_gen_subfi_tl(t1, 32, t1);
5275 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5276 tcg_gen_or_tl(t1, t0, t1);
5277 gen_store_spr(SPR_MQ, t1);
5278 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5279 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5280 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5281 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5282 gen_set_label(l1);
5283 tcg_temp_free(t0);
5284 tcg_temp_free(t1);
5285 if (unlikely(Rc(ctx->opcode) != 0))
5286 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5287 }
5288
5289 /* sraiq - sraiq. */
5290 static void gen_sraiq(DisasContext *ctx)
5291 {
5292 int sh = SH(ctx->opcode);
5293 int l1 = gen_new_label();
5294 TCGv t0 = tcg_temp_new();
5295 TCGv t1 = tcg_temp_new();
5296 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5297 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5298 tcg_gen_or_tl(t0, t0, t1);
5299 gen_store_spr(SPR_MQ, t0);
5300 tcg_gen_movi_tl(cpu_ca, 0);
5301 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5302 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5303 tcg_gen_movi_tl(cpu_ca, 1);
5304 gen_set_label(l1);
5305 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5306 tcg_temp_free(t0);
5307 tcg_temp_free(t1);
5308 if (unlikely(Rc(ctx->opcode) != 0))
5309 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5310 }
5311
5312 /* sraq - sraq. */
5313 static void gen_sraq(DisasContext *ctx)
5314 {
5315 int l1 = gen_new_label();
5316 int l2 = gen_new_label();
5317 TCGv t0 = tcg_temp_new();
5318 TCGv t1 = tcg_temp_local_new();
5319 TCGv t2 = tcg_temp_local_new();
5320 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5321 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5322 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5323 tcg_gen_subfi_tl(t2, 32, t2);
5324 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5325 tcg_gen_or_tl(t0, t0, t2);
5326 gen_store_spr(SPR_MQ, t0);
5327 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5328 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5329 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5330 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5331 gen_set_label(l1);
5332 tcg_temp_free(t0);
5333 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5334 tcg_gen_movi_tl(cpu_ca, 0);
5335 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5336 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5337 tcg_gen_movi_tl(cpu_ca, 1);
5338 gen_set_label(l2);
5339 tcg_temp_free(t1);
5340 tcg_temp_free(t2);
5341 if (unlikely(Rc(ctx->opcode) != 0))
5342 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5343 }
5344
5345 /* sre - sre. */
5346 static void gen_sre(DisasContext *ctx)
5347 {
5348 TCGv t0 = tcg_temp_new();
5349 TCGv t1 = tcg_temp_new();
5350 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5351 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5352 tcg_gen_subfi_tl(t1, 32, t1);
5353 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5354 tcg_gen_or_tl(t1, t0, t1);
5355 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5356 gen_store_spr(SPR_MQ, t1);
5357 tcg_temp_free(t0);
5358 tcg_temp_free(t1);
5359 if (unlikely(Rc(ctx->opcode) != 0))
5360 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5361 }
5362
5363 /* srea - srea. */
5364 static void gen_srea(DisasContext *ctx)
5365 {
5366 TCGv t0 = tcg_temp_new();
5367 TCGv t1 = tcg_temp_new();
5368 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5369 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5370 gen_store_spr(SPR_MQ, t0);
5371 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5372 tcg_temp_free(t0);
5373 tcg_temp_free(t1);
5374 if (unlikely(Rc(ctx->opcode) != 0))
5375 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5376 }
5377
5378 /* sreq */
5379 static void gen_sreq(DisasContext *ctx)
5380 {
5381 TCGv t0 = tcg_temp_new();
5382 TCGv t1 = tcg_temp_new();
5383 TCGv t2 = tcg_temp_new();
5384 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5385 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5386 tcg_gen_shr_tl(t1, t1, t0);
5387 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5388 gen_load_spr(t2, SPR_MQ);
5389 gen_store_spr(SPR_MQ, t0);
5390 tcg_gen_and_tl(t0, t0, t1);
5391 tcg_gen_andc_tl(t2, t2, t1);
5392 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5393 tcg_temp_free(t0);
5394 tcg_temp_free(t1);
5395 tcg_temp_free(t2);
5396 if (unlikely(Rc(ctx->opcode) != 0))
5397 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5398 }
5399
5400 /* sriq */
5401 static void gen_sriq(DisasContext *ctx)
5402 {
5403 int sh = SH(ctx->opcode);
5404 TCGv t0 = tcg_temp_new();
5405 TCGv t1 = tcg_temp_new();
5406 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5407 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5408 tcg_gen_or_tl(t1, t0, t1);
5409 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5410 gen_store_spr(SPR_MQ, t1);
5411 tcg_temp_free(t0);
5412 tcg_temp_free(t1);
5413 if (unlikely(Rc(ctx->opcode) != 0))
5414 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5415 }
5416
5417 /* srliq */
5418 static void gen_srliq(DisasContext *ctx)
5419 {
5420 int sh = SH(ctx->opcode);
5421 TCGv t0 = tcg_temp_new();
5422 TCGv t1 = tcg_temp_new();
5423 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5424 gen_load_spr(t1, SPR_MQ);
5425 gen_store_spr(SPR_MQ, t0);
5426 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5427 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5428 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5429 tcg_temp_free(t0);
5430 tcg_temp_free(t1);
5431 if (unlikely(Rc(ctx->opcode) != 0))
5432 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5433 }
5434
5435 /* srlq */
5436 static void gen_srlq(DisasContext *ctx)
5437 {
5438 int l1 = gen_new_label();
5439 int l2 = gen_new_label();
5440 TCGv t0 = tcg_temp_local_new();
5441 TCGv t1 = tcg_temp_local_new();
5442 TCGv t2 = tcg_temp_local_new();
5443 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5444 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5445 tcg_gen_shr_tl(t2, t1, t2);
5446 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5447 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5448 gen_load_spr(t0, SPR_MQ);
5449 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5450 tcg_gen_br(l2);
5451 gen_set_label(l1);
5452 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5453 tcg_gen_and_tl(t0, t0, t2);
5454 gen_load_spr(t1, SPR_MQ);
5455 tcg_gen_andc_tl(t1, t1, t2);
5456 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5457 gen_set_label(l2);
5458 tcg_temp_free(t0);
5459 tcg_temp_free(t1);
5460 tcg_temp_free(t2);
5461 if (unlikely(Rc(ctx->opcode) != 0))
5462 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5463 }
5464
5465 /* srq */
5466 static void gen_srq(DisasContext *ctx)
5467 {
5468 int l1 = gen_new_label();
5469 TCGv t0 = tcg_temp_new();
5470 TCGv t1 = tcg_temp_new();
5471 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5472 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5473 tcg_gen_subfi_tl(t1, 32, t1);
5474 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5475 tcg_gen_or_tl(t1, t0, t1);
5476 gen_store_spr(SPR_MQ, t1);
5477 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5478 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5479 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5480 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5481 gen_set_label(l1);
5482 tcg_temp_free(t0);
5483 tcg_temp_free(t1);
5484 if (unlikely(Rc(ctx->opcode) != 0))
5485 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5486 }
5487
5488 /* PowerPC 602 specific instructions */
5489
5490 /* dsa */
5491 static void gen_dsa(DisasContext *ctx)
5492 {
5493 /* XXX: TODO */
5494 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5495 }
5496
5497 /* esa */
5498 static void gen_esa(DisasContext *ctx)
5499 {
5500 /* XXX: TODO */
5501 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5502 }
5503
5504 /* mfrom */
5505 static void gen_mfrom(DisasContext *ctx)
5506 {
5507 #if defined(CONFIG_USER_ONLY)
5508 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5509 #else
5510 if (unlikely(!ctx->mem_idx)) {
5511 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5512 return;
5513 }
5514 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5515 #endif
5516 }
5517
5518 /* 602 - 603 - G2 TLB management */
5519
5520 /* tlbld */
5521 static void gen_tlbld_6xx(DisasContext *ctx)
5522 {
5523 #if defined(CONFIG_USER_ONLY)
5524 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5525 #else
5526 if (unlikely(!ctx->mem_idx)) {
5527 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5528 return;
5529 }
5530 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5531 #endif
5532 }
5533
5534 /* tlbli */
5535 static void gen_tlbli_6xx(DisasContext *ctx)
5536 {
5537 #if defined(CONFIG_USER_ONLY)
5538 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5539 #else
5540 if (unlikely(!ctx->mem_idx)) {
5541 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5542 return;
5543 }
5544 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5545 #endif
5546 }
5547
5548 /* 74xx TLB management */
5549
5550 /* tlbld */
5551 static void gen_tlbld_74xx(DisasContext *ctx)
5552 {
5553 #if defined(CONFIG_USER_ONLY)
5554 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5555 #else
5556 if (unlikely(!ctx->mem_idx)) {
5557 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5558 return;
5559 }
5560 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5561 #endif
5562 }
5563
5564 /* tlbli */
5565 static void gen_tlbli_74xx(DisasContext *ctx)
5566 {
5567 #if defined(CONFIG_USER_ONLY)
5568 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5569 #else
5570 if (unlikely(!ctx->mem_idx)) {
5571 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5572 return;
5573 }
5574 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5575 #endif
5576 }
5577
5578 /* POWER instructions not in PowerPC 601 */
5579
5580 /* clf */
5581 static void gen_clf(DisasContext *ctx)
5582 {
5583 /* Cache line flush: implemented as no-op */
5584 }
5585
5586 /* cli */
5587 static void gen_cli(DisasContext *ctx)
5588 {
5589 /* Cache line invalidate: privileged and treated as no-op */
5590 #if defined(CONFIG_USER_ONLY)
5591 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5592 #else
5593 if (unlikely(!ctx->mem_idx)) {
5594 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5595 return;
5596 }
5597 #endif
5598 }
5599
5600 /* dclst */
5601 static void gen_dclst(DisasContext *ctx)
5602 {
5603 /* Data cache line store: treated as no-op */
5604 }
5605
5606 static void gen_mfsri(DisasContext *ctx)
5607 {
5608 #if defined(CONFIG_USER_ONLY)
5609 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5610 #else
5611 int ra = rA(ctx->opcode);
5612 int rd = rD(ctx->opcode);
5613 TCGv t0;
5614 if (unlikely(!ctx->mem_idx)) {
5615 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5616 return;
5617 }
5618 t0 = tcg_temp_new();
5619 gen_addr_reg_index(ctx, t0);
5620 tcg_gen_shri_tl(t0, t0, 28);
5621 tcg_gen_andi_tl(t0, t0, 0xF);
5622 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5623 tcg_temp_free(t0);
5624 if (ra != 0 && ra != rd)
5625 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5626 #endif
5627 }
5628
5629 static void gen_rac(DisasContext *ctx)
5630 {
5631 #if defined(CONFIG_USER_ONLY)
5632 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5633 #else
5634 TCGv t0;
5635 if (unlikely(!ctx->mem_idx)) {
5636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5637 return;
5638 }
5639 t0 = tcg_temp_new();
5640 gen_addr_reg_index(ctx, t0);
5641 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5642 tcg_temp_free(t0);
5643 #endif
5644 }
5645
5646 static void gen_rfsvc(DisasContext *ctx)
5647 {
5648 #if defined(CONFIG_USER_ONLY)
5649 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5650 #else
5651 if (unlikely(!ctx->mem_idx)) {
5652 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5653 return;
5654 }
5655 gen_helper_rfsvc(cpu_env);
5656 gen_sync_exception(ctx);
5657 #endif
5658 }
5659
5660 /* svc is not implemented for now */
5661
5662 /* POWER2 specific instructions */
5663 /* Quad manipulation (load/store two floats at a time) */
5664
5665 /* lfq */
5666 static void gen_lfq(DisasContext *ctx)
5667 {
5668 int rd = rD(ctx->opcode);
5669 TCGv t0;
5670 gen_set_access_type(ctx, ACCESS_FLOAT);
5671 t0 = tcg_temp_new();
5672 gen_addr_imm_index(ctx, t0, 0);
5673 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5674 gen_addr_add(ctx, t0, t0, 8);
5675 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5676 tcg_temp_free(t0);
5677 }
5678
5679 /* lfqu */
5680 static void gen_lfqu(DisasContext *ctx)
5681 {
5682 int ra = rA(ctx->opcode);
5683 int rd = rD(ctx->opcode);
5684 TCGv t0, t1;
5685 gen_set_access_type(ctx, ACCESS_FLOAT);
5686 t0 = tcg_temp_new();
5687 t1 = tcg_temp_new();
5688 gen_addr_imm_index(ctx, t0, 0);
5689 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5690 gen_addr_add(ctx, t1, t0, 8);
5691 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5692 if (ra != 0)
5693 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5694 tcg_temp_free(t0);
5695 tcg_temp_free(t1);
5696 }
5697
5698 /* lfqux */
5699 static void gen_lfqux(DisasContext *ctx)
5700 {
5701 int ra = rA(ctx->opcode);
5702 int rd = rD(ctx->opcode);
5703 gen_set_access_type(ctx, ACCESS_FLOAT);
5704 TCGv t0, t1;
5705 t0 = tcg_temp_new();
5706 gen_addr_reg_index(ctx, t0);
5707 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5708 t1 = tcg_temp_new();
5709 gen_addr_add(ctx, t1, t0, 8);
5710 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5711 tcg_temp_free(t1);
5712 if (ra != 0)
5713 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5714 tcg_temp_free(t0);
5715 }
5716
5717 /* lfqx */
5718 static void gen_lfqx(DisasContext *ctx)
5719 {
5720 int rd = rD(ctx->opcode);
5721 TCGv t0;
5722 gen_set_access_type(ctx, ACCESS_FLOAT);
5723 t0 = tcg_temp_new();
5724 gen_addr_reg_index(ctx, t0);
5725 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5726 gen_addr_add(ctx, t0, t0, 8);
5727 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5728 tcg_temp_free(t0);
5729 }
5730
5731 /* stfq */
5732 static void gen_stfq(DisasContext *ctx)
5733 {
5734 int rd = rD(ctx->opcode);
5735 TCGv t0;
5736 gen_set_access_type(ctx, ACCESS_FLOAT);
5737 t0 = tcg_temp_new();
5738 gen_addr_imm_index(ctx, t0, 0);
5739 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5740 gen_addr_add(ctx, t0, t0, 8);
5741 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5742 tcg_temp_free(t0);
5743 }
5744
5745 /* stfqu */
5746 static void gen_stfqu(DisasContext *ctx)
5747 {
5748 int ra = rA(ctx->opcode);
5749 int rd = rD(ctx->opcode);
5750 TCGv t0, t1;
5751 gen_set_access_type(ctx, ACCESS_FLOAT);
5752 t0 = tcg_temp_new();
5753 gen_addr_imm_index(ctx, t0, 0);
5754 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5755 t1 = tcg_temp_new();
5756 gen_addr_add(ctx, t1, t0, 8);
5757 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5758 tcg_temp_free(t1);
5759 if (ra != 0)
5760 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5761 tcg_temp_free(t0);
5762 }
5763
5764 /* stfqux */
5765 static void gen_stfqux(DisasContext *ctx)
5766 {
5767 int ra = rA(ctx->opcode);
5768 int rd = rD(ctx->opcode);
5769 TCGv t0, t1;
5770 gen_set_access_type(ctx, ACCESS_FLOAT);
5771 t0 = tcg_temp_new();
5772 gen_addr_reg_index(ctx, t0);
5773 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5774 t1 = tcg_temp_new();
5775 gen_addr_add(ctx, t1, t0, 8);
5776 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5777 tcg_temp_free(t1);
5778 if (ra != 0)
5779 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5780 tcg_temp_free(t0);
5781 }
5782
5783 /* stfqx */
5784 static void gen_stfqx(DisasContext *ctx)
5785 {
5786 int rd = rD(ctx->opcode);
5787 TCGv t0;
5788 gen_set_access_type(ctx, ACCESS_FLOAT);
5789 t0 = tcg_temp_new();
5790 gen_addr_reg_index(ctx, t0);
5791 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5792 gen_addr_add(ctx, t0, t0, 8);
5793 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5794 tcg_temp_free(t0);
5795 }
5796
5797 /* BookE specific instructions */
5798
5799 /* XXX: not implemented on 440 ? */
5800 static void gen_mfapidi(DisasContext *ctx)
5801 {
5802 /* XXX: TODO */
5803 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5804 }
5805
5806 /* XXX: not implemented on 440 ? */
5807 static void gen_tlbiva(DisasContext *ctx)
5808 {
5809 #if defined(CONFIG_USER_ONLY)
5810 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5811 #else
5812 TCGv t0;
5813 if (unlikely(!ctx->mem_idx)) {
5814 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5815 return;
5816 }
5817 t0 = tcg_temp_new();
5818 gen_addr_reg_index(ctx, t0);
5819 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5820 tcg_temp_free(t0);
5821 #endif
5822 }
5823
5824 /* All 405 MAC instructions are translated here */
5825 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5826 int ra, int rb, int rt, int Rc)
5827 {
5828 TCGv t0, t1;
5829
5830 t0 = tcg_temp_local_new();
5831 t1 = tcg_temp_local_new();
5832
5833 switch (opc3 & 0x0D) {
5834 case 0x05:
5835 /* macchw - macchw. - macchwo - macchwo. */
5836 /* macchws - macchws. - macchwso - macchwso. */
5837 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5838 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5839 /* mulchw - mulchw. */
5840 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5841 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5842 tcg_gen_ext16s_tl(t1, t1);
5843 break;
5844 case 0x04:
5845 /* macchwu - macchwu. - macchwuo - macchwuo. */
5846 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5847 /* mulchwu - mulchwu. */
5848 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5849 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5850 tcg_gen_ext16u_tl(t1, t1);
5851 break;
5852 case 0x01:
5853 /* machhw - machhw. - machhwo - machhwo. */
5854 /* machhws - machhws. - machhwso - machhwso. */
5855 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5856 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5857 /* mulhhw - mulhhw. */
5858 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5859 tcg_gen_ext16s_tl(t0, t0);
5860 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5861 tcg_gen_ext16s_tl(t1, t1);
5862 break;
5863 case 0x00:
5864 /* machhwu - machhwu. - machhwuo - machhwuo. */
5865 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5866 /* mulhhwu - mulhhwu. */
5867 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5868 tcg_gen_ext16u_tl(t0, t0);
5869 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5870 tcg_gen_ext16u_tl(t1, t1);
5871 break;
5872 case 0x0D:
5873 /* maclhw - maclhw. - maclhwo - maclhwo. */
5874 /* maclhws - maclhws. - maclhwso - maclhwso. */
5875 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5876 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5877 /* mullhw - mullhw. */
5878 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5879 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5880 break;
5881 case 0x0C:
5882 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5883 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5884 /* mullhwu - mullhwu. */
5885 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5886 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5887 break;
5888 }
5889 if (opc2 & 0x04) {
5890 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5891 tcg_gen_mul_tl(t1, t0, t1);
5892 if (opc2 & 0x02) {
5893 /* nmultiply-and-accumulate (0x0E) */
5894 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5895 } else {
5896 /* multiply-and-accumulate (0x0C) */
5897 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5898 }
5899
5900 if (opc3 & 0x12) {
5901 /* Check overflow and/or saturate */
5902 int l1 = gen_new_label();
5903
5904 if (opc3 & 0x10) {
5905 /* Start with XER OV disabled, the most likely case */
5906 tcg_gen_movi_tl(cpu_ov, 0);
5907 }
5908 if (opc3 & 0x01) {
5909 /* Signed */
5910 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5911 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5912 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5913 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5914 if (opc3 & 0x02) {
5915 /* Saturate */
5916 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5917 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5918 }
5919 } else {
5920 /* Unsigned */
5921 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5922 if (opc3 & 0x02) {
5923 /* Saturate */
5924 tcg_gen_movi_tl(t0, UINT32_MAX);
5925 }
5926 }
5927 if (opc3 & 0x10) {
5928 /* Check overflow */
5929 tcg_gen_movi_tl(cpu_ov, 1);
5930 tcg_gen_movi_tl(cpu_so, 1);
5931 }
5932 gen_set_label(l1);
5933 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5934 }
5935 } else {
5936 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5937 }
5938 tcg_temp_free(t0);
5939 tcg_temp_free(t1);
5940 if (unlikely(Rc) != 0) {
5941 /* Update Rc0 */
5942 gen_set_Rc0(ctx, cpu_gpr[rt]);
5943 }
5944 }
5945
5946 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5947 static void glue(gen_, name)(DisasContext *ctx) \
5948 { \
5949 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5950 rD(ctx->opcode), Rc(ctx->opcode)); \
5951 }
5952
5953 /* macchw - macchw. */
5954 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5955 /* macchwo - macchwo. */
5956 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5957 /* macchws - macchws. */
5958 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5959 /* macchwso - macchwso. */
5960 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5961 /* macchwsu - macchwsu. */
5962 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5963 /* macchwsuo - macchwsuo. */
5964 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5965 /* macchwu - macchwu. */
5966 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5967 /* macchwuo - macchwuo. */
5968 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5969 /* machhw - machhw. */
5970 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5971 /* machhwo - machhwo. */
5972 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5973 /* machhws - machhws. */
5974 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5975 /* machhwso - machhwso. */
5976 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5977 /* machhwsu - machhwsu. */
5978 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5979 /* machhwsuo - machhwsuo. */
5980 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5981 /* machhwu - machhwu. */
5982 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5983 /* machhwuo - machhwuo. */
5984 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5985 /* maclhw - maclhw. */
5986 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5987 /* maclhwo - maclhwo. */
5988 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5989 /* maclhws - maclhws. */
5990 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5991 /* maclhwso - maclhwso. */
5992 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5993 /* maclhwu - maclhwu. */
5994 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5995 /* maclhwuo - maclhwuo. */
5996 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5997 /* maclhwsu - maclhwsu. */
5998 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5999 /* maclhwsuo - maclhwsuo. */
6000 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6001 /* nmacchw - nmacchw. */
6002 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6003 /* nmacchwo - nmacchwo. */
6004 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6005 /* nmacchws - nmacchws. */
6006 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6007 /* nmacchwso - nmacchwso. */
6008 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6009 /* nmachhw - nmachhw. */
6010 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6011 /* nmachhwo - nmachhwo. */
6012 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6013 /* nmachhws - nmachhws. */
6014 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6015 /* nmachhwso - nmachhwso. */
6016 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6017 /* nmaclhw - nmaclhw. */
6018 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6019 /* nmaclhwo - nmaclhwo. */
6020 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6021 /* nmaclhws - nmaclhws. */
6022 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6023 /* nmaclhwso - nmaclhwso. */
6024 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6025
6026 /* mulchw - mulchw. */
6027 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6028 /* mulchwu - mulchwu. */
6029 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6030 /* mulhhw - mulhhw. */
6031 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6032 /* mulhhwu - mulhhwu. */
6033 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6034 /* mullhw - mullhw. */
6035 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6036 /* mullhwu - mullhwu. */
6037 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6038
6039 /* mfdcr */
6040 static void gen_mfdcr(DisasContext *ctx)
6041 {
6042 #if defined(CONFIG_USER_ONLY)
6043 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6044 #else
6045 TCGv dcrn;
6046 if (unlikely(!ctx->mem_idx)) {
6047 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6048 return;
6049 }
6050 /* NIP cannot be restored if the memory exception comes from an helper */
6051 gen_update_nip(ctx, ctx->nip - 4);
6052 dcrn = tcg_const_tl(SPR(ctx->opcode));
6053 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6054 tcg_temp_free(dcrn);
6055 #endif
6056 }
6057
6058 /* mtdcr */
6059 static void gen_mtdcr(DisasContext *ctx)
6060 {
6061 #if defined(CONFIG_USER_ONLY)
6062 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6063 #else
6064 TCGv dcrn;
6065 if (unlikely(!ctx->mem_idx)) {
6066 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6067 return;
6068 }
6069 /* NIP cannot be restored if the memory exception comes from an helper */
6070 gen_update_nip(ctx, ctx->nip - 4);
6071 dcrn = tcg_const_tl(SPR(ctx->opcode));
6072 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6073 tcg_temp_free(dcrn);
6074 #endif
6075 }
6076
6077 /* mfdcrx */
6078 /* XXX: not implemented on 440 ? */
6079 static void gen_mfdcrx(DisasContext *ctx)
6080 {
6081 #if defined(CONFIG_USER_ONLY)
6082 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6083 #else
6084 if (unlikely(!ctx->mem_idx)) {
6085 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6086 return;
6087 }
6088 /* NIP cannot be restored if the memory exception comes from an helper */
6089 gen_update_nip(ctx, ctx->nip - 4);
6090 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6091 cpu_gpr[rA(ctx->opcode)]);
6092 /* Note: Rc update flag set leads to undefined state of Rc0 */
6093 #endif
6094 }
6095
6096 /* mtdcrx */
6097 /* XXX: not implemented on 440 ? */
6098 static void gen_mtdcrx(DisasContext *ctx)
6099 {
6100 #if defined(CONFIG_USER_ONLY)
6101 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6102 #else
6103 if (unlikely(!ctx->mem_idx)) {
6104 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6105 return;
6106 }
6107 /* NIP cannot be restored if the memory exception comes from an helper */
6108 gen_update_nip(ctx, ctx->nip - 4);
6109 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6110 cpu_gpr[rS(ctx->opcode)]);
6111 /* Note: Rc update flag set leads to undefined state of Rc0 */
6112 #endif
6113 }
6114
6115 /* mfdcrux (PPC 460) : user-mode access to DCR */
6116 static void gen_mfdcrux(DisasContext *ctx)
6117 {
6118 /* NIP cannot be restored if the memory exception comes from an helper */
6119 gen_update_nip(ctx, ctx->nip - 4);
6120 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6121 cpu_gpr[rA(ctx->opcode)]);
6122 /* Note: Rc update flag set leads to undefined state of Rc0 */
6123 }
6124
6125 /* mtdcrux (PPC 460) : user-mode access to DCR */
6126 static void gen_mtdcrux(DisasContext *ctx)
6127 {
6128 /* NIP cannot be restored if the memory exception comes from an helper */
6129 gen_update_nip(ctx, ctx->nip - 4);
6130 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6131 cpu_gpr[rS(ctx->opcode)]);
6132 /* Note: Rc update flag set leads to undefined state of Rc0 */
6133 }
6134
6135 /* dccci */
6136 static void gen_dccci(DisasContext *ctx)
6137 {
6138 #if defined(CONFIG_USER_ONLY)
6139 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6140 #else
6141 if (unlikely(!ctx->mem_idx)) {
6142 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6143 return;
6144 }
6145 /* interpreted as no-op */
6146 #endif
6147 }
6148
6149 /* dcread */
6150 static void gen_dcread(DisasContext *ctx)
6151 {
6152 #if defined(CONFIG_USER_ONLY)
6153 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6154 #else
6155 TCGv EA, val;
6156 if (unlikely(!ctx->mem_idx)) {
6157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6158 return;
6159 }
6160 gen_set_access_type(ctx, ACCESS_CACHE);
6161 EA = tcg_temp_new();
6162 gen_addr_reg_index(ctx, EA);
6163 val = tcg_temp_new();
6164 gen_qemu_ld32u(ctx, val, EA);
6165 tcg_temp_free(val);
6166 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6167 tcg_temp_free(EA);
6168 #endif
6169 }
6170
6171 /* icbt */
6172 static void gen_icbt_40x(DisasContext *ctx)
6173 {
6174 /* interpreted as no-op */
6175 /* XXX: specification say this is treated as a load by the MMU
6176 * but does not generate any exception
6177 */
6178 }
6179
6180 /* iccci */
6181 static void gen_iccci(DisasContext *ctx)
6182 {
6183 #if defined(CONFIG_USER_ONLY)
6184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6185 #else
6186 if (unlikely(!ctx->mem_idx)) {
6187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6188 return;
6189 }
6190 /* interpreted as no-op */
6191 #endif
6192 }
6193
6194 /* icread */
6195 static void gen_icread(DisasContext *ctx)
6196 {
6197 #if defined(CONFIG_USER_ONLY)
6198 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6199 #else
6200 if (unlikely(!ctx->mem_idx)) {
6201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6202 return;
6203 }
6204 /* interpreted as no-op */
6205 #endif
6206 }
6207
6208 /* rfci (mem_idx only) */
6209 static void gen_rfci_40x(DisasContext *ctx)
6210 {
6211 #if defined(CONFIG_USER_ONLY)
6212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6213 #else
6214 if (unlikely(!ctx->mem_idx)) {
6215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6216 return;
6217 }
6218 /* Restore CPU state */
6219 gen_helper_40x_rfci(cpu_env);
6220 gen_sync_exception(ctx);
6221 #endif
6222 }
6223
6224 static void gen_rfci(DisasContext *ctx)
6225 {
6226 #if defined(CONFIG_USER_ONLY)
6227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6228 #else
6229 if (unlikely(!ctx->mem_idx)) {
6230 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6231 return;
6232 }
6233 /* Restore CPU state */
6234 gen_helper_rfci(cpu_env);
6235 gen_sync_exception(ctx);
6236 #endif
6237 }
6238
6239 /* BookE specific */
6240
6241 /* XXX: not implemented on 440 ? */
6242 static void gen_rfdi(DisasContext *ctx)
6243 {
6244 #if defined(CONFIG_USER_ONLY)
6245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6246 #else
6247 if (unlikely(!ctx->mem_idx)) {
6248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6249 return;
6250 }
6251 /* Restore CPU state */
6252 gen_helper_rfdi(cpu_env);
6253 gen_sync_exception(ctx);
6254 #endif
6255 }
6256
6257 /* XXX: not implemented on 440 ? */
6258 static void gen_rfmci(DisasContext *ctx)
6259 {
6260 #if defined(CONFIG_USER_ONLY)
6261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6262 #else
6263 if (unlikely(!ctx->mem_idx)) {
6264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6265 return;
6266 }
6267 /* Restore CPU state */
6268 gen_helper_rfmci(cpu_env);
6269 gen_sync_exception(ctx);
6270 #endif
6271 }
6272
6273 /* TLB management - PowerPC 405 implementation */
6274
6275 /* tlbre */
6276 static void gen_tlbre_40x(DisasContext *ctx)
6277 {
6278 #if defined(CONFIG_USER_ONLY)
6279 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6280 #else
6281 if (unlikely(!ctx->mem_idx)) {
6282 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6283 return;
6284 }
6285 switch (rB(ctx->opcode)) {
6286 case 0:
6287 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6288 cpu_gpr[rA(ctx->opcode)]);
6289 break;
6290 case 1:
6291 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6292 cpu_gpr[rA(ctx->opcode)]);
6293 break;
6294 default:
6295 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6296 break;
6297 }
6298 #endif
6299 }
6300
6301 /* tlbsx - tlbsx. */
6302 static void gen_tlbsx_40x(DisasContext *ctx)
6303 {
6304 #if defined(CONFIG_USER_ONLY)
6305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6306 #else
6307 TCGv t0;
6308 if (unlikely(!ctx->mem_idx)) {
6309 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6310 return;
6311 }
6312 t0 = tcg_temp_new();
6313 gen_addr_reg_index(ctx, t0);
6314 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6315 tcg_temp_free(t0);
6316 if (Rc(ctx->opcode)) {
6317 int l1 = gen_new_label();
6318 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6319 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6320 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6321 gen_set_label(l1);
6322 }
6323 #endif
6324 }
6325
6326 /* tlbwe */
6327 static void gen_tlbwe_40x(DisasContext *ctx)
6328 {
6329 #if defined(CONFIG_USER_ONLY)
6330 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6331 #else
6332 if (unlikely(!ctx->mem_idx)) {
6333 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6334 return;
6335 }
6336 switch (rB(ctx->opcode)) {
6337 case 0:
6338 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6339 cpu_gpr[rS(ctx->opcode)]);
6340 break;
6341 case 1:
6342 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6343 cpu_gpr[rS(ctx->opcode)]);
6344 break;
6345 default:
6346 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6347 break;
6348 }
6349 #endif
6350 }
6351
6352 /* TLB management - PowerPC 440 implementation */
6353
6354 /* tlbre */
6355 static void gen_tlbre_440(DisasContext *ctx)
6356 {
6357 #if defined(CONFIG_USER_ONLY)
6358 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6359 #else
6360 if (unlikely(!ctx->mem_idx)) {
6361 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6362 return;
6363 }
6364 switch (rB(ctx->opcode)) {
6365 case 0:
6366 case 1:
6367 case 2:
6368 {
6369 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6370 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6371 t0, cpu_gpr[rA(ctx->opcode)]);
6372 tcg_temp_free_i32(t0);
6373 }
6374 break;
6375 default:
6376 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6377 break;
6378 }
6379 #endif
6380 }
6381
6382 /* tlbsx - tlbsx. */
6383 static void gen_tlbsx_440(DisasContext *ctx)
6384 {
6385 #if defined(CONFIG_USER_ONLY)
6386 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6387 #else
6388 TCGv t0;
6389 if (unlikely(!ctx->mem_idx)) {
6390 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6391 return;
6392 }
6393 t0 = tcg_temp_new();
6394 gen_addr_reg_index(ctx, t0);
6395 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6396 tcg_temp_free(t0);
6397 if (Rc(ctx->opcode)) {
6398 int l1 = gen_new_label();
6399 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6400 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6401 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6402 gen_set_label(l1);
6403 }
6404 #endif
6405 }
6406
6407 /* tlbwe */
6408 static void gen_tlbwe_440(DisasContext *ctx)
6409 {
6410 #if defined(CONFIG_USER_ONLY)
6411 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6412 #else
6413 if (unlikely(!ctx->mem_idx)) {
6414 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6415 return;
6416 }
6417 switch (rB(ctx->opcode)) {
6418 case 0:
6419 case 1:
6420 case 2:
6421 {
6422 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6423 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6424 cpu_gpr[rS(ctx->opcode)]);
6425 tcg_temp_free_i32(t0);
6426 }
6427 break;
6428 default:
6429 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6430 break;
6431 }
6432 #endif
6433 }
6434
6435 /* TLB management - PowerPC BookE 2.06 implementation */
6436
6437 /* tlbre */
6438 static void gen_tlbre_booke206(DisasContext *ctx)
6439 {
6440 #if defined(CONFIG_USER_ONLY)
6441 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6442 #else
6443 if (unlikely(!ctx->mem_idx)) {
6444 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6445 return;
6446 }
6447
6448 gen_helper_booke206_tlbre(cpu_env);
6449 #endif
6450 }
6451
6452 /* tlbsx - tlbsx. */
6453 static void gen_tlbsx_booke206(DisasContext *ctx)
6454 {
6455 #if defined(CONFIG_USER_ONLY)
6456 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6457 #else
6458 TCGv t0;
6459 if (unlikely(!ctx->mem_idx)) {
6460 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6461 return;
6462 }
6463
6464 if (rA(ctx->opcode)) {
6465 t0 = tcg_temp_new();
6466 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6467 } else {
6468 t0 = tcg_const_tl(0);
6469 }
6470
6471 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6472 gen_helper_booke206_tlbsx(cpu_env, t0);
6473 #endif
6474 }
6475
6476 /* tlbwe */
6477 static void gen_tlbwe_booke206(DisasContext *ctx)
6478 {
6479 #if defined(CONFIG_USER_ONLY)
6480 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6481 #else
6482 if (unlikely(!ctx->mem_idx)) {
6483 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6484 return;
6485 }
6486 gen_update_nip(ctx, ctx->nip - 4);
6487 gen_helper_booke206_tlbwe(cpu_env);
6488 #endif
6489 }
6490
6491 static void gen_tlbivax_booke206(DisasContext *ctx)
6492 {
6493 #if defined(CONFIG_USER_ONLY)
6494 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6495 #else
6496 TCGv t0;
6497 if (unlikely(!ctx->mem_idx)) {
6498 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6499 return;
6500 }
6501
6502 t0 = tcg_temp_new();
6503 gen_addr_reg_index(ctx, t0);
6504
6505 gen_helper_booke206_tlbivax(cpu_env, t0);
6506 #endif
6507 }
6508
6509 static void gen_tlbilx_booke206(DisasContext *ctx)
6510 {
6511 #if defined(CONFIG_USER_ONLY)
6512 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6513 #else
6514 TCGv t0;
6515 if (unlikely(!ctx->mem_idx)) {
6516 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6517 return;
6518 }
6519
6520 t0 = tcg_temp_new();
6521 gen_addr_reg_index(ctx, t0);
6522
6523 switch((ctx->opcode >> 21) & 0x3) {
6524 case 0:
6525 gen_helper_booke206_tlbilx0(cpu_env, t0);
6526 break;
6527 case 1:
6528 gen_helper_booke206_tlbilx1(cpu_env, t0);
6529 break;
6530 case 3:
6531 gen_helper_booke206_tlbilx3(cpu_env, t0);
6532 break;
6533 default:
6534 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6535 break;
6536 }
6537
6538 tcg_temp_free(t0);
6539 #endif
6540 }
6541
6542
6543 /* wrtee */
6544 static void gen_wrtee(DisasContext *ctx)
6545 {
6546 #if defined(CONFIG_USER_ONLY)
6547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6548 #else
6549 TCGv t0;
6550 if (unlikely(!ctx->mem_idx)) {
6551 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6552 return;
6553 }
6554 t0 = tcg_temp_new();
6555 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6556 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6557 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6558 tcg_temp_free(t0);
6559 /* Stop translation to have a chance to raise an exception
6560 * if we just set msr_ee to 1
6561 */
6562 gen_stop_exception(ctx);
6563 #endif
6564 }
6565
6566 /* wrteei */
6567 static void gen_wrteei(DisasContext *ctx)
6568 {
6569 #if defined(CONFIG_USER_ONLY)
6570 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6571 #else
6572 if (unlikely(!ctx->mem_idx)) {
6573 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6574 return;
6575 }
6576 if (ctx->opcode & 0x00008000) {
6577 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6578 /* Stop translation to have a chance to raise an exception */
6579 gen_stop_exception(ctx);
6580 } else {
6581 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6582 }
6583 #endif
6584 }
6585
6586 /* PowerPC 440 specific instructions */
6587
6588 /* dlmzb */
6589 static void gen_dlmzb(DisasContext *ctx)
6590 {
6591 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6592 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6593 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6594 tcg_temp_free_i32(t0);
6595 }
6596
6597 /* mbar replaces eieio on 440 */
6598 static void gen_mbar(DisasContext *ctx)
6599 {
6600 /* interpreted as no-op */
6601 }
6602
6603 /* msync replaces sync on 440 */
6604 static void gen_msync_4xx(DisasContext *ctx)
6605 {
6606 /* interpreted as no-op */
6607 }
6608
6609 /* icbt */
6610 static void gen_icbt_440(DisasContext *ctx)
6611 {
6612 /* interpreted as no-op */
6613 /* XXX: specification say this is treated as a load by the MMU
6614 * but does not generate any exception
6615 */
6616 }
6617
6618 /* Embedded.Processor Control */
6619
6620 static void gen_msgclr(DisasContext *ctx)
6621 {
6622 #if defined(CONFIG_USER_ONLY)
6623 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6624 #else
6625 if (unlikely(ctx->mem_idx == 0)) {
6626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6627 return;
6628 }
6629
6630 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6631 #endif
6632 }
6633
6634 static void gen_msgsnd(DisasContext *ctx)
6635 {
6636 #if defined(CONFIG_USER_ONLY)
6637 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6638 #else
6639 if (unlikely(ctx->mem_idx == 0)) {
6640 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6641 return;
6642 }
6643
6644 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6645 #endif
6646 }
6647
6648 /*** Altivec vector extension ***/
6649 /* Altivec registers moves */
6650
6651 static inline TCGv_ptr gen_avr_ptr(int reg)
6652 {
6653 TCGv_ptr r = tcg_temp_new_ptr();
6654 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6655 return r;
6656 }
6657
6658 #define GEN_VR_LDX(name, opc2, opc3) \
6659 static void glue(gen_, name)(DisasContext *ctx) \
6660 { \
6661 TCGv EA; \
6662 if (unlikely(!ctx->altivec_enabled)) { \
6663 gen_exception(ctx, POWERPC_EXCP_VPU); \
6664 return; \
6665 } \
6666 gen_set_access_type(ctx, ACCESS_INT); \
6667 EA = tcg_temp_new(); \
6668 gen_addr_reg_index(ctx, EA); \
6669 tcg_gen_andi_tl(EA, EA, ~0xf); \
6670 if (ctx->le_mode) { \
6671 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6672 tcg_gen_addi_tl(EA, EA, 8); \
6673 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6674 } else { \
6675 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6676 tcg_gen_addi_tl(EA, EA, 8); \
6677 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6678 } \
6679 tcg_temp_free(EA); \
6680 }
6681
6682 #define GEN_VR_STX(name, opc2, opc3) \
6683 static void gen_st##name(DisasContext *ctx) \
6684 { \
6685 TCGv EA; \
6686 if (unlikely(!ctx->altivec_enabled)) { \
6687 gen_exception(ctx, POWERPC_EXCP_VPU); \
6688 return; \
6689 } \
6690 gen_set_access_type(ctx, ACCESS_INT); \
6691 EA = tcg_temp_new(); \
6692 gen_addr_reg_index(ctx, EA); \
6693 tcg_gen_andi_tl(EA, EA, ~0xf); \
6694 if (ctx->le_mode) { \
6695 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6696 tcg_gen_addi_tl(EA, EA, 8); \
6697 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6698 } else { \
6699 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6700 tcg_gen_addi_tl(EA, EA, 8); \
6701 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6702 } \
6703 tcg_temp_free(EA); \
6704 }
6705
6706 #define GEN_VR_LVE(name, opc2, opc3) \
6707 static void gen_lve##name(DisasContext *ctx) \
6708 { \
6709 TCGv EA; \
6710 TCGv_ptr rs; \
6711 if (unlikely(!ctx->altivec_enabled)) { \
6712 gen_exception(ctx, POWERPC_EXCP_VPU); \
6713 return; \
6714 } \
6715 gen_set_access_type(ctx, ACCESS_INT); \
6716 EA = tcg_temp_new(); \
6717 gen_addr_reg_index(ctx, EA); \
6718 rs = gen_avr_ptr(rS(ctx->opcode)); \
6719 gen_helper_lve##name(cpu_env, rs, EA); \
6720 tcg_temp_free(EA); \
6721 tcg_temp_free_ptr(rs); \
6722 }
6723
6724 #define GEN_VR_STVE(name, opc2, opc3) \
6725 static void gen_stve##name(DisasContext *ctx) \
6726 { \
6727 TCGv EA; \
6728 TCGv_ptr rs; \
6729 if (unlikely(!ctx->altivec_enabled)) { \
6730 gen_exception(ctx, POWERPC_EXCP_VPU); \
6731 return; \
6732 } \
6733 gen_set_access_type(ctx, ACCESS_INT); \
6734 EA = tcg_temp_new(); \
6735 gen_addr_reg_index(ctx, EA); \
6736 rs = gen_avr_ptr(rS(ctx->opcode)); \
6737 gen_helper_stve##name(cpu_env, rs, EA); \
6738 tcg_temp_free(EA); \
6739 tcg_temp_free_ptr(rs); \
6740 }
6741
6742 GEN_VR_LDX(lvx, 0x07, 0x03);
6743 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6744 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6745
6746 GEN_VR_LVE(bx, 0x07, 0x00);
6747 GEN_VR_LVE(hx, 0x07, 0x01);
6748 GEN_VR_LVE(wx, 0x07, 0x02);
6749
6750 GEN_VR_STX(svx, 0x07, 0x07);
6751 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6752 GEN_VR_STX(svxl, 0x07, 0x0F);
6753
6754 GEN_VR_STVE(bx, 0x07, 0x04);
6755 GEN_VR_STVE(hx, 0x07, 0x05);
6756 GEN_VR_STVE(wx, 0x07, 0x06);
6757
6758 static void gen_lvsl(DisasContext *ctx)
6759 {
6760 TCGv_ptr rd;
6761 TCGv EA;
6762 if (unlikely(!ctx->altivec_enabled)) {
6763 gen_exception(ctx, POWERPC_EXCP_VPU);
6764 return;
6765 }
6766 EA = tcg_temp_new();
6767 gen_addr_reg_index(ctx, EA);
6768 rd = gen_avr_ptr(rD(ctx->opcode));
6769 gen_helper_lvsl(rd, EA);
6770 tcg_temp_free(EA);
6771 tcg_temp_free_ptr(rd);
6772 }
6773
6774 static void gen_lvsr(DisasContext *ctx)
6775 {
6776 TCGv_ptr rd;
6777 TCGv EA;
6778 if (unlikely(!ctx->altivec_enabled)) {
6779 gen_exception(ctx, POWERPC_EXCP_VPU);
6780 return;
6781 }
6782 EA = tcg_temp_new();
6783 gen_addr_reg_index(ctx, EA);
6784 rd = gen_avr_ptr(rD(ctx->opcode));
6785 gen_helper_lvsr(rd, EA);
6786 tcg_temp_free(EA);
6787 tcg_temp_free_ptr(rd);
6788 }
6789
6790 static void gen_mfvscr(DisasContext *ctx)
6791 {
6792 TCGv_i32 t;
6793 if (unlikely(!ctx->altivec_enabled)) {
6794 gen_exception(ctx, POWERPC_EXCP_VPU);
6795 return;
6796 }
6797 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6798 t = tcg_temp_new_i32();
6799 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6800 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6801 tcg_temp_free_i32(t);
6802 }
6803
6804 static void gen_mtvscr(DisasContext *ctx)
6805 {
6806 TCGv_ptr p;
6807 if (unlikely(!ctx->altivec_enabled)) {
6808 gen_exception(ctx, POWERPC_EXCP_VPU);
6809 return;
6810 }
6811 p = gen_avr_ptr(rD(ctx->opcode));
6812 gen_helper_mtvscr(cpu_env, p);
6813 tcg_temp_free_ptr(p);
6814 }
6815
6816 /* Logical operations */
6817 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6818 static void glue(gen_, name)(DisasContext *ctx) \
6819 { \
6820 if (unlikely(!ctx->altivec_enabled)) { \
6821 gen_exception(ctx, POWERPC_EXCP_VPU); \
6822 return; \
6823 } \
6824 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6825 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6826 }
6827
6828 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6829 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6830 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6831 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6832 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6833
6834 #define GEN_VXFORM(name, opc2, opc3) \
6835 static void glue(gen_, name)(DisasContext *ctx) \
6836 { \
6837 TCGv_ptr ra, rb, rd; \
6838 if (unlikely(!ctx->altivec_enabled)) { \
6839 gen_exception(ctx, POWERPC_EXCP_VPU); \
6840 return; \
6841 } \
6842 ra = gen_avr_ptr(rA(ctx->opcode)); \
6843 rb = gen_avr_ptr(rB(ctx->opcode)); \
6844 rd = gen_avr_ptr(rD(ctx->opcode)); \
6845 gen_helper_##name (rd, ra, rb); \
6846 tcg_temp_free_ptr(ra); \
6847 tcg_temp_free_ptr(rb); \
6848 tcg_temp_free_ptr(rd); \
6849 }
6850
6851 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6852 static void glue(gen_, name)(DisasContext *ctx) \
6853 { \
6854 TCGv_ptr ra, rb, rd; \
6855 if (unlikely(!ctx->altivec_enabled)) { \
6856 gen_exception(ctx, POWERPC_EXCP_VPU); \
6857 return; \
6858 } \
6859 ra = gen_avr_ptr(rA(ctx->opcode)); \
6860 rb = gen_avr_ptr(rB(ctx->opcode)); \
6861 rd = gen_avr_ptr(rD(ctx->opcode)); \
6862 gen_helper_##name(cpu_env, rd, ra, rb); \
6863 tcg_temp_free_ptr(ra); \
6864 tcg_temp_free_ptr(rb); \
6865 tcg_temp_free_ptr(rd); \
6866 }
6867
6868 GEN_VXFORM(vaddubm, 0, 0);
6869 GEN_VXFORM(vadduhm, 0, 1);
6870 GEN_VXFORM(vadduwm, 0, 2);
6871 GEN_VXFORM(vsububm, 0, 16);
6872 GEN_VXFORM(vsubuhm, 0, 17);
6873 GEN_VXFORM(vsubuwm, 0, 18);
6874 GEN_VXFORM(vmaxub, 1, 0);
6875 GEN_VXFORM(vmaxuh, 1, 1);
6876 GEN_VXFORM(vmaxuw, 1, 2);
6877 GEN_VXFORM(vmaxsb, 1, 4);
6878 GEN_VXFORM(vmaxsh, 1, 5);
6879 GEN_VXFORM(vmaxsw, 1, 6);
6880 GEN_VXFORM(vminub, 1, 8);
6881 GEN_VXFORM(vminuh, 1, 9);
6882 GEN_VXFORM(vminuw, 1, 10);
6883 GEN_VXFORM(vminsb, 1, 12);
6884 GEN_VXFORM(vminsh, 1, 13);
6885 GEN_VXFORM(vminsw, 1, 14);
6886 GEN_VXFORM(vavgub, 1, 16);
6887 GEN_VXFORM(vavguh, 1, 17);
6888 GEN_VXFORM(vavguw, 1, 18);
6889 GEN_VXFORM(vavgsb, 1, 20);
6890 GEN_VXFORM(vavgsh, 1, 21);
6891 GEN_VXFORM(vavgsw, 1, 22);
6892 GEN_VXFORM(vmrghb, 6, 0);
6893 GEN_VXFORM(vmrghh, 6, 1);
6894 GEN_VXFORM(vmrghw, 6, 2);
6895 GEN_VXFORM(vmrglb, 6, 4);
6896 GEN_VXFORM(vmrglh, 6, 5);
6897 GEN_VXFORM(vmrglw, 6, 6);
6898 GEN_VXFORM(vmuloub, 4, 0);
6899 GEN_VXFORM(vmulouh, 4, 1);
6900 GEN_VXFORM(vmulosb, 4, 4);
6901 GEN_VXFORM(vmulosh, 4, 5);
6902 GEN_VXFORM(vmuleub, 4, 8);
6903 GEN_VXFORM(vmuleuh, 4, 9);
6904 GEN_VXFORM(vmulesb, 4, 12);
6905 GEN_VXFORM(vmulesh, 4, 13);
6906 GEN_VXFORM(vslb, 2, 4);
6907 GEN_VXFORM(vslh, 2, 5);
6908 GEN_VXFORM(vslw, 2, 6);
6909 GEN_VXFORM(vsrb, 2, 8);
6910 GEN_VXFORM(vsrh, 2, 9);
6911 GEN_VXFORM(vsrw, 2, 10);
6912 GEN_VXFORM(vsrab, 2, 12);
6913 GEN_VXFORM(vsrah, 2, 13);
6914 GEN_VXFORM(vsraw, 2, 14);
6915 GEN_VXFORM(vslo, 6, 16);
6916 GEN_VXFORM(vsro, 6, 17);
6917 GEN_VXFORM(vaddcuw, 0, 6);
6918 GEN_VXFORM(vsubcuw, 0, 22);
6919 GEN_VXFORM_ENV(vaddubs, 0, 8);
6920 GEN_VXFORM_ENV(vadduhs, 0, 9);
6921 GEN_VXFORM_ENV(vadduws, 0, 10);
6922 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6923 GEN_VXFORM_ENV(vaddshs, 0, 13);
6924 GEN_VXFORM_ENV(vaddsws, 0, 14);
6925 GEN_VXFORM_ENV(vsububs, 0, 24);
6926 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6927 GEN_VXFORM_ENV(vsubuws, 0, 26);
6928 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6929 GEN_VXFORM_ENV(vsubshs, 0, 29);
6930 GEN_VXFORM_ENV(vsubsws, 0, 30);
6931 GEN_VXFORM(vrlb, 2, 0);
6932 GEN_VXFORM(vrlh, 2, 1);
6933 GEN_VXFORM(vrlw, 2, 2);
6934 GEN_VXFORM(vsl, 2, 7);
6935 GEN_VXFORM(vsr, 2, 11);
6936 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6937 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6938 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6939 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6940 GEN_VXFORM_ENV(vpkshus, 7, 4);
6941 GEN_VXFORM_ENV(vpkswus, 7, 5);
6942 GEN_VXFORM_ENV(vpkshss, 7, 6);
6943 GEN_VXFORM_ENV(vpkswss, 7, 7);
6944 GEN_VXFORM(vpkpx, 7, 12);
6945 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6946 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6947 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6948 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6949 GEN_VXFORM_ENV(vsumsws, 4, 30);
6950 GEN_VXFORM_ENV(vaddfp, 5, 0);
6951 GEN_VXFORM_ENV(vsubfp, 5, 1);
6952 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6953 GEN_VXFORM_ENV(vminfp, 5, 17);
6954
6955 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6956 static void glue(gen_, name)(DisasContext *ctx) \
6957 { \
6958 TCGv_ptr ra, rb, rd; \
6959 if (unlikely(!ctx->altivec_enabled)) { \
6960 gen_exception(ctx, POWERPC_EXCP_VPU); \
6961 return; \
6962 } \
6963 ra = gen_avr_ptr(rA(ctx->opcode)); \
6964 rb = gen_avr_ptr(rB(ctx->opcode)); \
6965 rd = gen_avr_ptr(rD(ctx->opcode)); \
6966 gen_helper_##opname(cpu_env, rd, ra, rb); \
6967 tcg_temp_free_ptr(ra); \
6968 tcg_temp_free_ptr(rb); \
6969 tcg_temp_free_ptr(rd); \
6970 }
6971
6972 #define GEN_VXRFORM(name, opc2, opc3) \
6973 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6974 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6975
6976 GEN_VXRFORM(vcmpequb, 3, 0)
6977 GEN_VXRFORM(vcmpequh, 3, 1)
6978 GEN_VXRFORM(vcmpequw, 3, 2)
6979 GEN_VXRFORM(vcmpgtsb, 3, 12)
6980 GEN_VXRFORM(vcmpgtsh, 3, 13)
6981 GEN_VXRFORM(vcmpgtsw, 3, 14)
6982 GEN_VXRFORM(vcmpgtub, 3, 8)
6983 GEN_VXRFORM(vcmpgtuh, 3, 9)
6984 GEN_VXRFORM(vcmpgtuw, 3, 10)
6985 GEN_VXRFORM(vcmpeqfp, 3, 3)
6986 GEN_VXRFORM(vcmpgefp, 3, 7)
6987 GEN_VXRFORM(vcmpgtfp, 3, 11)
6988 GEN_VXRFORM(vcmpbfp, 3, 15)
6989
6990 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6991 static void glue(gen_, name)(DisasContext *ctx) \
6992 { \
6993 TCGv_ptr rd; \
6994 TCGv_i32 simm; \
6995 if (unlikely(!ctx->altivec_enabled)) { \
6996 gen_exception(ctx, POWERPC_EXCP_VPU); \
6997 return; \
6998 } \
6999 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7000 rd = gen_avr_ptr(rD(ctx->opcode)); \
7001 gen_helper_##name (rd, simm); \
7002 tcg_temp_free_i32(simm); \
7003 tcg_temp_free_ptr(rd); \
7004 }
7005
7006 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7007 GEN_VXFORM_SIMM(vspltish, 6, 13);
7008 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7009
7010 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7011 static void glue(gen_, name)(DisasContext *ctx) \
7012 { \
7013 TCGv_ptr rb, rd; \
7014 if (unlikely(!ctx->altivec_enabled)) { \
7015 gen_exception(ctx, POWERPC_EXCP_VPU); \
7016 return; \
7017 } \
7018 rb = gen_avr_ptr(rB(ctx->opcode)); \
7019 rd = gen_avr_ptr(rD(ctx->opcode)); \
7020 gen_helper_##name (rd, rb); \
7021 tcg_temp_free_ptr(rb); \
7022 tcg_temp_free_ptr(rd); \
7023 }
7024
7025 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7026 static void glue(gen_, name)(DisasContext *ctx) \
7027 { \
7028 TCGv_ptr rb, rd; \
7029 \
7030 if (unlikely(!ctx->altivec_enabled)) { \
7031 gen_exception(ctx, POWERPC_EXCP_VPU); \
7032 return; \
7033 } \
7034 rb = gen_avr_ptr(rB(ctx->opcode)); \
7035 rd = gen_avr_ptr(rD(ctx->opcode)); \
7036 gen_helper_##name(cpu_env, rd, rb); \
7037 tcg_temp_free_ptr(rb); \
7038 tcg_temp_free_ptr(rd); \
7039 }
7040
7041 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7042 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7043 GEN_VXFORM_NOA(vupklsb, 7, 10);
7044 GEN_VXFORM_NOA(vupklsh, 7, 11);
7045 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7046 GEN_VXFORM_NOA(vupklpx, 7, 15);
7047 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7048 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7049 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7050 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7051 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
7052 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
7053 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7054 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
7055
7056 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7057 static void glue(gen_, name)(DisasContext *ctx) \
7058 { \
7059 TCGv_ptr rd; \
7060 TCGv_i32 simm; \
7061 if (unlikely(!ctx->altivec_enabled)) { \
7062 gen_exception(ctx, POWERPC_EXCP_VPU); \
7063 return; \
7064 } \
7065 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7066 rd = gen_avr_ptr(rD(ctx->opcode)); \
7067 gen_helper_##name (rd, simm); \
7068 tcg_temp_free_i32(simm); \
7069 tcg_temp_free_ptr(rd); \
7070 }
7071
7072 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7073 static void glue(gen_, name)(DisasContext *ctx) \
7074 { \
7075 TCGv_ptr rb, rd; \
7076 TCGv_i32 uimm; \
7077 if (unlikely(!ctx->altivec_enabled)) { \
7078 gen_exception(ctx, POWERPC_EXCP_VPU); \
7079 return; \
7080 } \
7081 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7082 rb = gen_avr_ptr(rB(ctx->opcode)); \
7083 rd = gen_avr_ptr(rD(ctx->opcode)); \
7084 gen_helper_##name (rd, rb, uimm); \
7085 tcg_temp_free_i32(uimm); \
7086 tcg_temp_free_ptr(rb); \
7087 tcg_temp_free_ptr(rd); \
7088 }
7089
7090 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7091 static void glue(gen_, name)(DisasContext *ctx) \
7092 { \
7093 TCGv_ptr rb, rd; \
7094 TCGv_i32 uimm; \
7095 \
7096 if (unlikely(!ctx->altivec_enabled)) { \
7097 gen_exception(ctx, POWERPC_EXCP_VPU); \
7098 return; \
7099 } \
7100 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7101 rb = gen_avr_ptr(rB(ctx->opcode)); \
7102 rd = gen_avr_ptr(rD(ctx->opcode)); \
7103 gen_helper_##name(cpu_env, rd, rb, uimm); \
7104 tcg_temp_free_i32(uimm); \
7105 tcg_temp_free_ptr(rb); \
7106 tcg_temp_free_ptr(rd); \
7107 }
7108
7109 GEN_VXFORM_UIMM(vspltb, 6, 8);
7110 GEN_VXFORM_UIMM(vsplth, 6, 9);
7111 GEN_VXFORM_UIMM(vspltw, 6, 10);
7112 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7113 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7114 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7115 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7116
7117 static void gen_vsldoi(DisasContext *ctx)
7118 {
7119 TCGv_ptr ra, rb, rd;
7120 TCGv_i32 sh;
7121 if (unlikely(!ctx->altivec_enabled)) {
7122 gen_exception(ctx, POWERPC_EXCP_VPU);
7123 return;
7124 }
7125 ra = gen_avr_ptr(rA(ctx->opcode));
7126 rb = gen_avr_ptr(rB(ctx->opcode));
7127 rd = gen_avr_ptr(rD(ctx->opcode));
7128 sh = tcg_const_i32(VSH(ctx->opcode));
7129 gen_helper_vsldoi (rd, ra, rb, sh);
7130 tcg_temp_free_ptr(ra);
7131 tcg_temp_free_ptr(rb);
7132 tcg_temp_free_ptr(rd);
7133 tcg_temp_free_i32(sh);
7134 }
7135
7136 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7137 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7138 { \
7139 TCGv_ptr ra, rb, rc, rd; \
7140 if (unlikely(!ctx->altivec_enabled)) { \
7141 gen_exception(ctx, POWERPC_EXCP_VPU); \
7142 return; \
7143 } \
7144 ra = gen_avr_ptr(rA(ctx->opcode)); \
7145 rb = gen_avr_ptr(rB(ctx->opcode)); \
7146 rc = gen_avr_ptr(rC(ctx->opcode)); \
7147 rd = gen_avr_ptr(rD(ctx->opcode)); \
7148 if (Rc(ctx->opcode)) { \
7149 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7150 } else { \
7151 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7152 } \
7153 tcg_temp_free_ptr(ra); \
7154 tcg_temp_free_ptr(rb); \
7155 tcg_temp_free_ptr(rc); \
7156 tcg_temp_free_ptr(rd); \
7157 }
7158
7159 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7160
7161 static void gen_vmladduhm(DisasContext *ctx)
7162 {
7163 TCGv_ptr ra, rb, rc, rd;
7164 if (unlikely(!ctx->altivec_enabled)) {
7165 gen_exception(ctx, POWERPC_EXCP_VPU);
7166 return;
7167 }
7168 ra = gen_avr_ptr(rA(ctx->opcode));
7169 rb = gen_avr_ptr(rB(ctx->opcode));
7170 rc = gen_avr_ptr(rC(ctx->opcode));
7171 rd = gen_avr_ptr(rD(ctx->opcode));
7172 gen_helper_vmladduhm(rd, ra, rb, rc);
7173 tcg_temp_free_ptr(ra);
7174 tcg_temp_free_ptr(rb);
7175 tcg_temp_free_ptr(rc);
7176 tcg_temp_free_ptr(rd);
7177 }
7178
7179 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7180 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7181 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7182 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7183 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7184
7185 /*** VSX extension ***/
7186
7187 static inline TCGv_i64 cpu_vsrh(int n)
7188 {
7189 if (n < 32) {
7190 return cpu_fpr[n];
7191 } else {
7192 return cpu_avrh[n-32];
7193 }
7194 }
7195
7196 static inline TCGv_i64 cpu_vsrl(int n)
7197 {
7198 if (n < 32) {
7199 return cpu_vsr[n];
7200 } else {
7201 return cpu_avrl[n-32];
7202 }
7203 }
7204
7205 #define VSX_LOAD_SCALAR(name, operation) \
7206 static void gen_##name(DisasContext *ctx) \
7207 { \
7208 TCGv EA; \
7209 if (unlikely(!ctx->vsx_enabled)) { \
7210 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7211 return; \
7212 } \
7213 gen_set_access_type(ctx, ACCESS_INT); \
7214 EA = tcg_temp_new(); \
7215 gen_addr_reg_index(ctx, EA); \
7216 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7217 /* NOTE: cpu_vsrl is undefined */ \
7218 tcg_temp_free(EA); \
7219 }
7220
7221 VSX_LOAD_SCALAR(lxsdx, ld64)
7222 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7223 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7224 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7225
7226 static void gen_lxvd2x(DisasContext *ctx)
7227 {
7228 TCGv EA;
7229 if (unlikely(!ctx->vsx_enabled)) {
7230 gen_exception(ctx, POWERPC_EXCP_VSXU);
7231 return;
7232 }
7233 gen_set_access_type(ctx, ACCESS_INT);
7234 EA = tcg_temp_new();
7235 gen_addr_reg_index(ctx, EA);
7236 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7237 tcg_gen_addi_tl(EA, EA, 8);
7238 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7239 tcg_temp_free(EA);
7240 }
7241
7242 static void gen_lxvdsx(DisasContext *ctx)
7243 {
7244 TCGv EA;
7245 if (unlikely(!ctx->vsx_enabled)) {
7246 gen_exception(ctx, POWERPC_EXCP_VSXU);
7247 return;
7248 }
7249 gen_set_access_type(ctx, ACCESS_INT);
7250 EA = tcg_temp_new();
7251 gen_addr_reg_index(ctx, EA);
7252 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7253 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7254 tcg_temp_free(EA);
7255 }
7256
7257 static void gen_lxvw4x(DisasContext *ctx)
7258 {
7259 TCGv EA;
7260 TCGv_i64 tmp;
7261 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7262 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7263 if (unlikely(!ctx->vsx_enabled)) {
7264 gen_exception(ctx, POWERPC_EXCP_VSXU);
7265 return;
7266 }
7267 gen_set_access_type(ctx, ACCESS_INT);
7268 EA = tcg_temp_new();
7269 tmp = tcg_temp_new_i64();
7270
7271 gen_addr_reg_index(ctx, EA);
7272 gen_qemu_ld32u_i64(ctx, tmp, EA);
7273 tcg_gen_addi_tl(EA, EA, 4);
7274 gen_qemu_ld32u_i64(ctx, xth, EA);
7275 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7276
7277 tcg_gen_addi_tl(EA, EA, 4);
7278 gen_qemu_ld32u_i64(ctx, tmp, EA);
7279 tcg_gen_addi_tl(EA, EA, 4);
7280 gen_qemu_ld32u_i64(ctx, xtl, EA);
7281 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7282
7283 tcg_temp_free(EA);
7284 tcg_temp_free_i64(tmp);
7285 }
7286
7287 #define VSX_STORE_SCALAR(name, operation) \
7288 static void gen_##name(DisasContext *ctx) \
7289 { \
7290 TCGv EA; \
7291 if (unlikely(!ctx->vsx_enabled)) { \
7292 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7293 return; \
7294 } \
7295 gen_set_access_type(ctx, ACCESS_INT); \
7296 EA = tcg_temp_new(); \
7297 gen_addr_reg_index(ctx, EA); \
7298 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7299 tcg_temp_free(EA); \
7300 }
7301
7302 VSX_STORE_SCALAR(stxsdx, st64)
7303 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7304 VSX_STORE_SCALAR(stxsspx, st32fs)
7305
7306 static void gen_stxvd2x(DisasContext *ctx)
7307 {
7308 TCGv EA;
7309 if (unlikely(!ctx->vsx_enabled)) {
7310 gen_exception(ctx, POWERPC_EXCP_VSXU);
7311 return;
7312 }
7313 gen_set_access_type(ctx, ACCESS_INT);
7314 EA = tcg_temp_new();
7315 gen_addr_reg_index(ctx, EA);
7316 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7317 tcg_gen_addi_tl(EA, EA, 8);
7318 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7319 tcg_temp_free(EA);
7320 }
7321
7322 static void gen_stxvw4x(DisasContext *ctx)
7323 {
7324 TCGv_i64 tmp;
7325 TCGv EA;
7326 if (unlikely(!ctx->vsx_enabled)) {
7327 gen_exception(ctx, POWERPC_EXCP_VSXU);
7328 return;
7329 }
7330 gen_set_access_type(ctx, ACCESS_INT);
7331 EA = tcg_temp_new();
7332 gen_addr_reg_index(ctx, EA);
7333 tmp = tcg_temp_new_i64();
7334
7335 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7336 gen_qemu_st32_i64(ctx, tmp, EA);
7337 tcg_gen_addi_tl(EA, EA, 4);
7338 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7339
7340 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7341 tcg_gen_addi_tl(EA, EA, 4);
7342 gen_qemu_st32_i64(ctx, tmp, EA);
7343 tcg_gen_addi_tl(EA, EA, 4);
7344 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7345
7346 tcg_temp_free(EA);
7347 tcg_temp_free_i64(tmp);
7348 }
7349
7350 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7351 static void gen_##name(DisasContext *ctx) \
7352 { \
7353 if (xS(ctx->opcode) < 32) { \
7354 if (unlikely(!ctx->fpu_enabled)) { \
7355 gen_exception(ctx, POWERPC_EXCP_FPU); \
7356 return; \
7357 } \
7358 } else { \
7359 if (unlikely(!ctx->altivec_enabled)) { \
7360 gen_exception(ctx, POWERPC_EXCP_VPU); \
7361 return; \
7362 } \
7363 } \
7364 TCGv_i64 tmp = tcg_temp_new_i64(); \
7365 tcg_gen_##tcgop1(tmp, source); \
7366 tcg_gen_##tcgop2(target, tmp); \
7367 tcg_temp_free_i64(tmp); \
7368 }
7369
7370
7371 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7372 cpu_vsrh(xS(ctx->opcode)))
7373 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7374 cpu_gpr[rA(ctx->opcode)])
7375 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7376 cpu_gpr[rA(ctx->opcode)])
7377
7378 #if defined(TARGET_PPC64)
7379 #define MV_VSRD(name, target, source) \
7380 static void gen_##name(DisasContext *ctx) \
7381 { \
7382 if (xS(ctx->opcode) < 32) { \
7383 if (unlikely(!ctx->fpu_enabled)) { \
7384 gen_exception(ctx, POWERPC_EXCP_FPU); \
7385 return; \
7386 } \
7387 } else { \
7388 if (unlikely(!ctx->altivec_enabled)) { \
7389 gen_exception(ctx, POWERPC_EXCP_VPU); \
7390 return; \
7391 } \
7392 } \
7393 tcg_gen_mov_i64(target, source); \
7394 }
7395
7396 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7397 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7398
7399 #endif
7400
7401 static void gen_xxpermdi(DisasContext *ctx)
7402 {
7403 if (unlikely(!ctx->vsx_enabled)) {
7404 gen_exception(ctx, POWERPC_EXCP_VSXU);
7405 return;
7406 }
7407
7408 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7409 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7410 TCGv_i64 xh, xl;
7411
7412 xh = tcg_temp_new_i64();
7413 xl = tcg_temp_new_i64();
7414
7415 if ((DM(ctx->opcode) & 2) == 0) {
7416 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7417 } else {
7418 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7419 }
7420 if ((DM(ctx->opcode) & 1) == 0) {
7421 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7422 } else {
7423 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7424 }
7425
7426 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7427 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7428
7429 tcg_temp_free_i64(xh);
7430 tcg_temp_free_i64(xl);
7431 } else {
7432 if ((DM(ctx->opcode) & 2) == 0) {
7433 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7434 } else {
7435 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7436 }
7437 if ((DM(ctx->opcode) & 1) == 0) {
7438 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7439 } else {
7440 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7441 }
7442 }
7443 }
7444
7445 #define OP_ABS 1
7446 #define OP_NABS 2
7447 #define OP_NEG 3
7448 #define OP_CPSGN 4
7449 #define SGN_MASK_DP 0x8000000000000000ul
7450 #define SGN_MASK_SP 0x8000000080000000ul
7451
7452 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7453 static void glue(gen_, name)(DisasContext * ctx) \
7454 { \
7455 TCGv_i64 xb, sgm; \
7456 if (unlikely(!ctx->vsx_enabled)) { \
7457 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7458 return; \
7459 } \
7460 xb = tcg_temp_new_i64(); \
7461 sgm = tcg_temp_new_i64(); \
7462 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7463 tcg_gen_movi_i64(sgm, sgn_mask); \
7464 switch (op) { \
7465 case OP_ABS: { \
7466 tcg_gen_andc_i64(xb, xb, sgm); \
7467 break; \
7468 } \
7469 case OP_NABS: { \
7470 tcg_gen_or_i64(xb, xb, sgm); \
7471 break; \
7472 } \
7473 case OP_NEG: { \
7474 tcg_gen_xor_i64(xb, xb, sgm); \
7475 break; \
7476 } \
7477 case OP_CPSGN: { \
7478 TCGv_i64 xa = tcg_temp_new_i64(); \
7479 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7480 tcg_gen_and_i64(xa, xa, sgm); \
7481 tcg_gen_andc_i64(xb, xb, sgm); \
7482 tcg_gen_or_i64(xb, xb, xa); \
7483 tcg_temp_free_i64(xa); \
7484 break; \
7485 } \
7486 } \
7487 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7488 tcg_temp_free_i64(xb); \
7489 tcg_temp_free_i64(sgm); \
7490 }
7491
7492 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7493 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7494 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7495 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7496
7497 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7498 static void glue(gen_, name)(DisasContext * ctx) \
7499 { \
7500 TCGv_i64 xbh, xbl, sgm; \
7501 if (unlikely(!ctx->vsx_enabled)) { \
7502 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7503 return; \
7504 } \
7505 xbh = tcg_temp_new_i64(); \
7506 xbl = tcg_temp_new_i64(); \
7507 sgm = tcg_temp_new_i64(); \
7508 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7509 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7510 tcg_gen_movi_i64(sgm, sgn_mask); \
7511 switch (op) { \
7512 case OP_ABS: { \
7513 tcg_gen_andc_i64(xbh, xbh, sgm); \
7514 tcg_gen_andc_i64(xbl, xbl, sgm); \
7515 break; \
7516 } \
7517 case OP_NABS: { \
7518 tcg_gen_or_i64(xbh, xbh, sgm); \
7519 tcg_gen_or_i64(xbl, xbl, sgm); \
7520 break; \
7521 } \
7522 case OP_NEG: { \
7523 tcg_gen_xor_i64(xbh, xbh, sgm); \
7524 tcg_gen_xor_i64(xbl, xbl, sgm); \
7525 break; \
7526 } \
7527 case OP_CPSGN: { \
7528 TCGv_i64 xah = tcg_temp_new_i64(); \
7529 TCGv_i64 xal = tcg_temp_new_i64(); \
7530 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7531 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7532 tcg_gen_and_i64(xah, xah, sgm); \
7533 tcg_gen_and_i64(xal, xal, sgm); \
7534 tcg_gen_andc_i64(xbh, xbh, sgm); \
7535 tcg_gen_andc_i64(xbl, xbl, sgm); \
7536 tcg_gen_or_i64(xbh, xbh, xah); \
7537 tcg_gen_or_i64(xbl, xbl, xal); \
7538 tcg_temp_free_i64(xah); \
7539 tcg_temp_free_i64(xal); \
7540 break; \
7541 } \
7542 } \
7543 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7544 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7545 tcg_temp_free_i64(xbh); \
7546 tcg_temp_free_i64(xbl); \
7547 tcg_temp_free_i64(sgm); \
7548 }
7549
7550 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7551 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7552 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7553 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7554 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7555 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7556 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7557 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7558
7559 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7560 static void gen_##name(DisasContext * ctx) \
7561 { \
7562 TCGv_i32 opc; \
7563 if (unlikely(!ctx->vsx_enabled)) { \
7564 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7565 return; \
7566 } \
7567 /* NIP cannot be restored if the memory exception comes from an helper */ \
7568 gen_update_nip(ctx, ctx->nip - 4); \
7569 opc = tcg_const_i32(ctx->opcode); \
7570 gen_helper_##name(cpu_env, opc); \
7571 tcg_temp_free_i32(opc); \
7572 }
7573
7574 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7575 static void gen_##name(DisasContext * ctx) \
7576 { \
7577 if (unlikely(!ctx->vsx_enabled)) { \
7578 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7579 return; \
7580 } \
7581 /* NIP cannot be restored if the exception comes */ \
7582 /* from a helper. */ \
7583 gen_update_nip(ctx, ctx->nip - 4); \
7584 \
7585 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7586 cpu_vsrh(xB(ctx->opcode))); \
7587 }
7588
7589 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7590 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7591 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7592 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7593 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7594 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7595 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7596 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7597 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7598 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7599 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7600 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7601 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7602 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7603 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7604 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7605 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7606 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7607 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7608 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7609 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7610 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7611 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7612 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7613 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7614 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7615 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7616 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7617 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7618 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7619 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7620 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7621 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7622 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7623 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7624 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7625 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7626
7627 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7628 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7629 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7630 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7631 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7632 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7633 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7634 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7635 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7636 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7637 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7638 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7639 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7640 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7641 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7642 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7643 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7644
7645 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7646 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7647 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7648 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7649 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7650 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7651 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7652 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7653 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7654 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7655 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7656 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7657 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7658 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7659 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7660 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7661 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7662 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7663 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7664 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7665 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7666 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7667 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7668 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7669 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7670 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7671 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7672 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7673 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7674 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7675 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7676 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7677 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7678 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7679 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7680 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7681
7682 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7683 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7684 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7685 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
7686 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
7687 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
7688 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
7689 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
7690 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
7691 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
7692 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
7693 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
7694 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
7695 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
7696 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
7697 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
7698 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
7699 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
7700 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
7701 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
7702 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
7703 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
7704 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
7705 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
7706 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
7707 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
7708 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
7709 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
7710 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
7711 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
7712 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
7713 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
7714 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
7715 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
7716 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
7717 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
7718
7719 #define VSX_LOGICAL(name, tcg_op) \
7720 static void glue(gen_, name)(DisasContext * ctx) \
7721 { \
7722 if (unlikely(!ctx->vsx_enabled)) { \
7723 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7724 return; \
7725 } \
7726 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
7727 cpu_vsrh(xB(ctx->opcode))); \
7728 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
7729 cpu_vsrl(xB(ctx->opcode))); \
7730 }
7731
7732 VSX_LOGICAL(xxland, tcg_gen_and_i64)
7733 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
7734 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
7735 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
7736 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
7737 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
7738 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
7739 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
7740
7741 #define VSX_XXMRG(name, high) \
7742 static void glue(gen_, name)(DisasContext * ctx) \
7743 { \
7744 TCGv_i64 a0, a1, b0, b1; \
7745 if (unlikely(!ctx->vsx_enabled)) { \
7746 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7747 return; \
7748 } \
7749 a0 = tcg_temp_new_i64(); \
7750 a1 = tcg_temp_new_i64(); \
7751 b0 = tcg_temp_new_i64(); \
7752 b1 = tcg_temp_new_i64(); \
7753 if (high) { \
7754 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
7755 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
7756 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
7757 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
7758 } else { \
7759 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
7760 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
7761 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
7762 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
7763 } \
7764 tcg_gen_shri_i64(a0, a0, 32); \
7765 tcg_gen_shri_i64(b0, b0, 32); \
7766 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
7767 b0, a0, 32, 32); \
7768 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
7769 b1, a1, 32, 32); \
7770 tcg_temp_free_i64(a0); \
7771 tcg_temp_free_i64(a1); \
7772 tcg_temp_free_i64(b0); \
7773 tcg_temp_free_i64(b1); \
7774 }
7775
7776 VSX_XXMRG(xxmrghw, 1)
7777 VSX_XXMRG(xxmrglw, 0)
7778
7779 static void gen_xxsel(DisasContext * ctx)
7780 {
7781 TCGv_i64 a, b, c;
7782 if (unlikely(!ctx->vsx_enabled)) {
7783 gen_exception(ctx, POWERPC_EXCP_VSXU);
7784 return;
7785 }
7786 a = tcg_temp_new_i64();
7787 b = tcg_temp_new_i64();
7788 c = tcg_temp_new_i64();
7789
7790 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
7791 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
7792 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
7793
7794 tcg_gen_and_i64(b, b, c);
7795 tcg_gen_andc_i64(a, a, c);
7796 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
7797
7798 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
7799 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
7800 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
7801
7802 tcg_gen_and_i64(b, b, c);
7803 tcg_gen_andc_i64(a, a, c);
7804 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
7805
7806 tcg_temp_free_i64(a);
7807 tcg_temp_free_i64(b);
7808 tcg_temp_free_i64(c);
7809 }
7810
7811 static void gen_xxspltw(DisasContext *ctx)
7812 {
7813 TCGv_i64 b, b2;
7814 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
7815 cpu_vsrl(xB(ctx->opcode)) :
7816 cpu_vsrh(xB(ctx->opcode));
7817
7818 if (unlikely(!ctx->vsx_enabled)) {
7819 gen_exception(ctx, POWERPC_EXCP_VSXU);
7820 return;
7821 }
7822
7823 b = tcg_temp_new_i64();
7824 b2 = tcg_temp_new_i64();
7825
7826 if (UIM(ctx->opcode) & 1) {
7827 tcg_gen_ext32u_i64(b, vsr);
7828 } else {
7829 tcg_gen_shri_i64(b, vsr, 32);
7830 }
7831
7832 tcg_gen_shli_i64(b2, b, 32);
7833 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
7834 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7835
7836 tcg_temp_free_i64(b);
7837 tcg_temp_free_i64(b2);
7838 }
7839
7840 static void gen_xxsldwi(DisasContext *ctx)
7841 {
7842 TCGv_i64 xth, xtl;
7843 if (unlikely(!ctx->vsx_enabled)) {
7844 gen_exception(ctx, POWERPC_EXCP_VSXU);
7845 return;
7846 }
7847 xth = tcg_temp_new_i64();
7848 xtl = tcg_temp_new_i64();
7849
7850 switch (SHW(ctx->opcode)) {
7851 case 0: {
7852 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
7853 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
7854 break;
7855 }
7856 case 1: {
7857 TCGv_i64 t0 = tcg_temp_new_i64();
7858 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
7859 tcg_gen_shli_i64(xth, xth, 32);
7860 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
7861 tcg_gen_shri_i64(t0, t0, 32);
7862 tcg_gen_or_i64(xth, xth, t0);
7863 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
7864 tcg_gen_shli_i64(xtl, xtl, 32);
7865 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
7866 tcg_gen_shri_i64(t0, t0, 32);
7867 tcg_gen_or_i64(xtl, xtl, t0);
7868 tcg_temp_free_i64(t0);
7869 break;
7870 }
7871 case 2: {
7872 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
7873 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
7874 break;
7875 }
7876 case 3: {
7877 TCGv_i64 t0 = tcg_temp_new_i64();
7878 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
7879 tcg_gen_shli_i64(xth, xth, 32);
7880 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
7881 tcg_gen_shri_i64(t0, t0, 32);
7882 tcg_gen_or_i64(xth, xth, t0);
7883 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
7884 tcg_gen_shli_i64(xtl, xtl, 32);
7885 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
7886 tcg_gen_shri_i64(t0, t0, 32);
7887 tcg_gen_or_i64(xtl, xtl, t0);
7888 tcg_temp_free_i64(t0);
7889 break;
7890 }
7891 }
7892
7893 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
7894 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
7895
7896 tcg_temp_free_i64(xth);
7897 tcg_temp_free_i64(xtl);
7898 }
7899
7900
7901 /*** SPE extension ***/
7902 /* Register moves */
7903
7904 static inline void gen_evmra(DisasContext *ctx)
7905 {
7906
7907 if (unlikely(!ctx->spe_enabled)) {
7908 gen_exception(ctx, POWERPC_EXCP_SPEU);
7909 return;
7910 }
7911
7912 #if defined(TARGET_PPC64)
7913 /* rD := rA */
7914 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7915
7916 /* spe_acc := rA */
7917 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
7918 cpu_env,
7919 offsetof(CPUPPCState, spe_acc));
7920 #else
7921 TCGv_i64 tmp = tcg_temp_new_i64();
7922
7923 /* tmp := rA_lo + rA_hi << 32 */
7924 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7925
7926 /* spe_acc := tmp */
7927 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7928 tcg_temp_free_i64(tmp);
7929
7930 /* rD := rA */
7931 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7932 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7933 #endif
7934 }
7935
7936 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
7937 {
7938 #if defined(TARGET_PPC64)
7939 tcg_gen_mov_i64(t, cpu_gpr[reg]);
7940 #else
7941 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
7942 #endif
7943 }
7944
7945 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
7946 {
7947 #if defined(TARGET_PPC64)
7948 tcg_gen_mov_i64(cpu_gpr[reg], t);
7949 #else
7950 TCGv_i64 tmp = tcg_temp_new_i64();
7951 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
7952 tcg_gen_shri_i64(tmp, t, 32);
7953 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
7954 tcg_temp_free_i64(tmp);
7955 #endif
7956 }
7957
7958 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
7959 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7960 { \
7961 if (Rc(ctx->opcode)) \
7962 gen_##name1(ctx); \
7963 else \
7964 gen_##name0(ctx); \
7965 }
7966
7967 /* Handler for undefined SPE opcodes */
7968 static inline void gen_speundef(DisasContext *ctx)
7969 {
7970 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7971 }
7972
7973 /* SPE logic */
7974 #if defined(TARGET_PPC64)
7975 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7976 static inline void gen_##name(DisasContext *ctx) \
7977 { \
7978 if (unlikely(!ctx->spe_enabled)) { \
7979 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7980 return; \
7981 } \
7982 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7983 cpu_gpr[rB(ctx->opcode)]); \
7984 }
7985 #else
7986 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7987 static inline void gen_##name(DisasContext *ctx) \
7988 { \
7989 if (unlikely(!ctx->spe_enabled)) { \
7990 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7991 return; \
7992 } \
7993 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7994 cpu_gpr[rB(ctx->opcode)]); \
7995 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7996 cpu_gprh[rB(ctx->opcode)]); \
7997 }
7998 #endif
7999
8000 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8001 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8002 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8003 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8004 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8005 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8006 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8007 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8008
8009 /* SPE logic immediate */
8010 #if defined(TARGET_PPC64)
8011 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8012 static inline void gen_##name(DisasContext *ctx) \
8013 { \
8014 if (unlikely(!ctx->spe_enabled)) { \
8015 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8016 return; \
8017 } \
8018 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8019 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8020 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8021 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8022 tcg_opi(t0, t0, rB(ctx->opcode)); \
8023 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8024 tcg_gen_trunc_i64_i32(t1, t2); \
8025 tcg_temp_free_i64(t2); \
8026 tcg_opi(t1, t1, rB(ctx->opcode)); \
8027 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8028 tcg_temp_free_i32(t0); \
8029 tcg_temp_free_i32(t1); \
8030 }
8031 #else
8032 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8033 static inline void gen_##name(DisasContext *ctx) \
8034 { \
8035 if (unlikely(!ctx->spe_enabled)) { \
8036 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8037 return; \
8038 } \
8039 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8040 rB(ctx->opcode)); \
8041 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8042 rB(ctx->opcode)); \
8043 }
8044 #endif
8045 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8046 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8047 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8048 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8049
8050 /* SPE arithmetic */
8051 #if defined(TARGET_PPC64)
8052 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8053 static inline void gen_##name(DisasContext *ctx) \
8054 { \
8055 if (unlikely(!ctx->spe_enabled)) { \
8056 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8057 return; \
8058 } \
8059 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8060 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8061 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8062 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8063 tcg_op(t0, t0); \
8064 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8065 tcg_gen_trunc_i64_i32(t1, t2); \
8066 tcg_temp_free_i64(t2); \
8067 tcg_op(t1, t1); \
8068 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8069 tcg_temp_free_i32(t0); \
8070 tcg_temp_free_i32(t1); \
8071 }
8072 #else
8073 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8074 static inline void gen_##name(DisasContext *ctx) \
8075 { \
8076 if (unlikely(!ctx->spe_enabled)) { \
8077 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8078 return; \
8079 } \
8080 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8081 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8082 }
8083 #endif
8084
8085 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8086 {
8087 int l1 = gen_new_label();
8088 int l2 = gen_new_label();
8089
8090 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8091 tcg_gen_neg_i32(ret, arg1);
8092 tcg_gen_br(l2);
8093 gen_set_label(l1);
8094 tcg_gen_mov_i32(ret, arg1);
8095 gen_set_label(l2);
8096 }
8097 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8098 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8099 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8100 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8101 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8102 {
8103 tcg_gen_addi_i32(ret, arg1, 0x8000);
8104 tcg_gen_ext16u_i32(ret, ret);
8105 }
8106 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8107 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8108 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8109
8110 #if defined(TARGET_PPC64)
8111 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8112 static inline void gen_##name(DisasContext *ctx) \
8113 { \
8114 if (unlikely(!ctx->spe_enabled)) { \
8115 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8116 return; \
8117 } \
8118 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8119 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8120 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
8121 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
8122 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8123 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
8124 tcg_op(t0, t0, t2); \
8125 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
8126 tcg_gen_trunc_i64_i32(t1, t3); \
8127 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
8128 tcg_gen_trunc_i64_i32(t2, t3); \
8129 tcg_temp_free_i64(t3); \
8130 tcg_op(t1, t1, t2); \
8131 tcg_temp_free_i32(t2); \
8132 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8133 tcg_temp_free_i32(t0); \
8134 tcg_temp_free_i32(t1); \
8135 }
8136 #else
8137 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8138 static inline void gen_##name(DisasContext *ctx) \
8139 { \
8140 if (unlikely(!ctx->spe_enabled)) { \
8141 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8142 return; \
8143 } \
8144 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8145 cpu_gpr[rB(ctx->opcode)]); \
8146 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8147 cpu_gprh[rB(ctx->opcode)]); \
8148 }
8149 #endif
8150
8151 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8152 {
8153 TCGv_i32 t0;
8154 int l1, l2;
8155
8156 l1 = gen_new_label();
8157 l2 = gen_new_label();
8158 t0 = tcg_temp_local_new_i32();
8159 /* No error here: 6 bits are used */
8160 tcg_gen_andi_i32(t0, arg2, 0x3F);
8161 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8162 tcg_gen_shr_i32(ret, arg1, t0);
8163 tcg_gen_br(l2);
8164 gen_set_label(l1);
8165 tcg_gen_movi_i32(ret, 0);
8166 gen_set_label(l2);
8167 tcg_temp_free_i32(t0);
8168 }
8169 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8170 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8171 {
8172 TCGv_i32 t0;
8173 int l1, l2;
8174
8175 l1 = gen_new_label();
8176 l2 = gen_new_label();
8177 t0 = tcg_temp_local_new_i32();
8178 /* No error here: 6 bits are used */
8179 tcg_gen_andi_i32(t0, arg2, 0x3F);
8180 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8181 tcg_gen_sar_i32(ret, arg1, t0);
8182 tcg_gen_br(l2);
8183 gen_set_label(l1);
8184 tcg_gen_movi_i32(ret, 0);
8185 gen_set_label(l2);
8186 tcg_temp_free_i32(t0);
8187 }
8188 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8189 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8190 {
8191 TCGv_i32 t0;
8192 int l1, l2;
8193
8194 l1 = gen_new_label();
8195 l2 = gen_new_label();
8196 t0 = tcg_temp_local_new_i32();
8197 /* No error here: 6 bits are used */
8198 tcg_gen_andi_i32(t0, arg2, 0x3F);
8199 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8200 tcg_gen_shl_i32(ret, arg1, t0);
8201 tcg_gen_br(l2);
8202 gen_set_label(l1);
8203 tcg_gen_movi_i32(ret, 0);
8204 gen_set_label(l2);
8205 tcg_temp_free_i32(t0);
8206 }
8207 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8208 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8209 {
8210 TCGv_i32 t0 = tcg_temp_new_i32();
8211 tcg_gen_andi_i32(t0, arg2, 0x1F);
8212 tcg_gen_rotl_i32(ret, arg1, t0);
8213 tcg_temp_free_i32(t0);
8214 }
8215 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8216 static inline void gen_evmergehi(DisasContext *ctx)
8217 {
8218 if (unlikely(!ctx->spe_enabled)) {
8219 gen_exception(ctx, POWERPC_EXCP_SPEU);
8220 return;
8221 }
8222 #if defined(TARGET_PPC64)
8223 TCGv t0 = tcg_temp_new();
8224 TCGv t1 = tcg_temp_new();
8225 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8226 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8227 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8228 tcg_temp_free(t0);
8229 tcg_temp_free(t1);
8230 #else
8231 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8232 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8233 #endif
8234 }
8235 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8236 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8237 {
8238 tcg_gen_sub_i32(ret, arg2, arg1);
8239 }
8240 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8241
8242 /* SPE arithmetic immediate */
8243 #if defined(TARGET_PPC64)
8244 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8245 static inline void gen_##name(DisasContext *ctx) \
8246 { \
8247 if (unlikely(!ctx->spe_enabled)) { \
8248 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8249 return; \
8250 } \
8251 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8252 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8253 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8254 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8255 tcg_op(t0, t0, rA(ctx->opcode)); \
8256 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8257 tcg_gen_trunc_i64_i32(t1, t2); \
8258 tcg_temp_free_i64(t2); \
8259 tcg_op(t1, t1, rA(ctx->opcode)); \
8260 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8261 tcg_temp_free_i32(t0); \
8262 tcg_temp_free_i32(t1); \
8263 }
8264 #else
8265 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8266 static inline void gen_##name(DisasContext *ctx) \
8267 { \
8268 if (unlikely(!ctx->spe_enabled)) { \
8269 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8270 return; \
8271 } \
8272 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
8273 rA(ctx->opcode)); \
8274 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
8275 rA(ctx->opcode)); \
8276 }
8277 #endif
8278 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8279 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8280
8281 /* SPE comparison */
8282 #if defined(TARGET_PPC64)
8283 #define GEN_SPEOP_COMP(name, tcg_cond) \
8284 static inline void gen_##name(DisasContext *ctx) \
8285 { \
8286 if (unlikely(!ctx->spe_enabled)) { \
8287 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8288 return; \
8289 } \
8290 int l1 = gen_new_label(); \
8291 int l2 = gen_new_label(); \
8292 int l3 = gen_new_label(); \
8293 int l4 = gen_new_label(); \
8294 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8295 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8296 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8297 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8298 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8299 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
8300 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8301 tcg_gen_br(l2); \
8302 gen_set_label(l1); \
8303 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8304 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8305 gen_set_label(l2); \
8306 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8307 tcg_gen_trunc_i64_i32(t0, t2); \
8308 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8309 tcg_gen_trunc_i64_i32(t1, t2); \
8310 tcg_temp_free_i64(t2); \
8311 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
8312 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8313 ~(CRF_CH | CRF_CH_AND_CL)); \
8314 tcg_gen_br(l4); \
8315 gen_set_label(l3); \
8316 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8317 CRF_CH | CRF_CH_OR_CL); \
8318 gen_set_label(l4); \
8319 tcg_temp_free_i32(t0); \
8320 tcg_temp_free_i32(t1); \
8321 }
8322 #else
8323 #define GEN_SPEOP_COMP(name, tcg_cond) \
8324 static inline void gen_##name(DisasContext *ctx) \
8325 { \
8326 if (unlikely(!ctx->spe_enabled)) { \
8327 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8328 return; \
8329 } \
8330 int l1 = gen_new_label(); \
8331 int l2 = gen_new_label(); \
8332 int l3 = gen_new_label(); \
8333 int l4 = gen_new_label(); \
8334 \
8335 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8336 cpu_gpr[rB(ctx->opcode)], l1); \
8337 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
8338 tcg_gen_br(l2); \
8339 gen_set_label(l1); \
8340 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8341 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8342 gen_set_label(l2); \
8343 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8344 cpu_gprh[rB(ctx->opcode)], l3); \
8345 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8346 ~(CRF_CH | CRF_CH_AND_CL)); \
8347 tcg_gen_br(l4); \
8348 gen_set_label(l3); \
8349 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8350 CRF_CH | CRF_CH_OR_CL); \
8351 gen_set_label(l4); \
8352 }
8353 #endif
8354 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8355 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8356 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8357 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8358 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8359
8360 /* SPE misc */
8361 static inline void gen_brinc(DisasContext *ctx)
8362 {
8363 /* Note: brinc is usable even if SPE is disabled */
8364 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8365 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8366 }
8367 static inline void gen_evmergelo(DisasContext *ctx)
8368 {
8369 if (unlikely(!ctx->spe_enabled)) {
8370 gen_exception(ctx, POWERPC_EXCP_SPEU);
8371 return;
8372 }
8373 #if defined(TARGET_PPC64)
8374 TCGv t0 = tcg_temp_new();
8375 TCGv t1 = tcg_temp_new();
8376 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8377 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8378 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8379 tcg_temp_free(t0);
8380 tcg_temp_free(t1);
8381 #else
8382 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8383 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8384 #endif
8385 }
8386 static inline void gen_evmergehilo(DisasContext *ctx)
8387 {
8388 if (unlikely(!ctx->spe_enabled)) {
8389 gen_exception(ctx, POWERPC_EXCP_SPEU);
8390 return;
8391 }
8392 #if defined(TARGET_PPC64)
8393 TCGv t0 = tcg_temp_new();
8394 TCGv t1 = tcg_temp_new();
8395 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8396 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8397 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8398 tcg_temp_free(t0);
8399 tcg_temp_free(t1);
8400 #else
8401 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8402 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8403 #endif
8404 }
8405 static inline void gen_evmergelohi(DisasContext *ctx)
8406 {
8407 if (unlikely(!ctx->spe_enabled)) {
8408 gen_exception(ctx, POWERPC_EXCP_SPEU);
8409 return;
8410 }
8411 #if defined(TARGET_PPC64)
8412 TCGv t0 = tcg_temp_new();
8413 TCGv t1 = tcg_temp_new();
8414 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8415 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8416 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8417 tcg_temp_free(t0);
8418 tcg_temp_free(t1);
8419 #else
8420 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8421 TCGv_i32 tmp = tcg_temp_new_i32();
8422 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
8423 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8424 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
8425 tcg_temp_free_i32(tmp);
8426 } else {
8427 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8428 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8429 }
8430 #endif
8431 }
8432 static inline void gen_evsplati(DisasContext *ctx)
8433 {
8434 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8435
8436 #if defined(TARGET_PPC64)
8437 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8438 #else
8439 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8440 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8441 #endif
8442 }
8443 static inline void gen_evsplatfi(DisasContext *ctx)
8444 {
8445 uint64_t imm = rA(ctx->opcode) << 27;
8446
8447 #if defined(TARGET_PPC64)
8448 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8449 #else
8450 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8451 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8452 #endif
8453 }
8454
8455 static inline void gen_evsel(DisasContext *ctx)
8456 {
8457 int l1 = gen_new_label();
8458 int l2 = gen_new_label();
8459 int l3 = gen_new_label();
8460 int l4 = gen_new_label();
8461 TCGv_i32 t0 = tcg_temp_local_new_i32();
8462 #if defined(TARGET_PPC64)
8463 TCGv t1 = tcg_temp_local_new();
8464 TCGv t2 = tcg_temp_local_new();
8465 #endif
8466 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8467 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8468 #if defined(TARGET_PPC64)
8469 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8470 #else
8471 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8472 #endif
8473 tcg_gen_br(l2);
8474 gen_set_label(l1);
8475 #if defined(TARGET_PPC64)
8476 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8477 #else
8478 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8479 #endif
8480 gen_set_label(l2);
8481 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8482 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8483 #if defined(TARGET_PPC64)
8484 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
8485 #else
8486 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8487 #endif
8488 tcg_gen_br(l4);
8489 gen_set_label(l3);
8490 #if defined(TARGET_PPC64)
8491 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
8492 #else
8493 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8494 #endif
8495 gen_set_label(l4);
8496 tcg_temp_free_i32(t0);
8497 #if defined(TARGET_PPC64)
8498 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
8499 tcg_temp_free(t1);
8500 tcg_temp_free(t2);
8501 #endif
8502 }
8503
8504 static void gen_evsel0(DisasContext *ctx)
8505 {
8506 gen_evsel(ctx);
8507 }
8508
8509 static void gen_evsel1(DisasContext *ctx)
8510 {
8511 gen_evsel(ctx);
8512 }
8513
8514 static void gen_evsel2(DisasContext *ctx)
8515 {
8516 gen_evsel(ctx);
8517 }
8518
8519 static void gen_evsel3(DisasContext *ctx)
8520 {
8521 gen_evsel(ctx);
8522 }
8523
8524 /* Multiply */
8525
8526 static inline void gen_evmwumi(DisasContext *ctx)
8527 {
8528 TCGv_i64 t0, t1;
8529
8530 if (unlikely(!ctx->spe_enabled)) {
8531 gen_exception(ctx, POWERPC_EXCP_SPEU);
8532 return;
8533 }
8534
8535 t0 = tcg_temp_new_i64();
8536 t1 = tcg_temp_new_i64();
8537
8538 /* t0 := rA; t1 := rB */
8539 #if defined(TARGET_PPC64)
8540 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8541 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8542 #else
8543 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8544 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8545 #endif
8546
8547 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8548
8549 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8550
8551 tcg_temp_free_i64(t0);
8552 tcg_temp_free_i64(t1);
8553 }
8554
8555 static inline void gen_evmwumia(DisasContext *ctx)
8556 {
8557 TCGv_i64 tmp;
8558
8559 if (unlikely(!ctx->spe_enabled)) {
8560 gen_exception(ctx, POWERPC_EXCP_SPEU);
8561 return;
8562 }
8563
8564 gen_evmwumi(ctx); /* rD := rA * rB */
8565
8566 tmp = tcg_temp_new_i64();
8567
8568 /* acc := rD */
8569 gen_load_gpr64(tmp, rD(ctx->opcode));
8570 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8571 tcg_temp_free_i64(tmp);
8572 }
8573
8574 static inline void gen_evmwumiaa(DisasContext *ctx)
8575 {
8576 TCGv_i64 acc;
8577 TCGv_i64 tmp;
8578
8579 if (unlikely(!ctx->spe_enabled)) {
8580 gen_exception(ctx, POWERPC_EXCP_SPEU);
8581 return;
8582 }
8583
8584 gen_evmwumi(ctx); /* rD := rA * rB */
8585
8586 acc = tcg_temp_new_i64();
8587 tmp = tcg_temp_new_i64();
8588
8589 /* tmp := rD */
8590 gen_load_gpr64(tmp, rD(ctx->opcode));
8591
8592 /* Load acc */
8593 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8594
8595 /* acc := tmp + acc */
8596 tcg_gen_add_i64(acc, acc, tmp);
8597
8598 /* Store acc */
8599 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8600
8601 /* rD := acc */
8602 gen_store_gpr64(rD(ctx->opcode), acc);
8603
8604 tcg_temp_free_i64(acc);
8605 tcg_temp_free_i64(tmp);
8606 }
8607
8608 static inline void gen_evmwsmi(DisasContext *ctx)
8609 {
8610 TCGv_i64 t0, t1;
8611
8612 if (unlikely(!ctx->spe_enabled)) {
8613 gen_exception(ctx, POWERPC_EXCP_SPEU);
8614 return;
8615 }
8616
8617 t0 = tcg_temp_new_i64();
8618 t1 = tcg_temp_new_i64();
8619
8620 /* t0 := rA; t1 := rB */
8621 #if defined(TARGET_PPC64)
8622 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8623 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8624 #else
8625 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8626 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8627 #endif
8628
8629 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8630
8631 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8632
8633 tcg_temp_free_i64(t0);
8634 tcg_temp_free_i64(t1);
8635 }
8636
8637 static inline void gen_evmwsmia(DisasContext *ctx)
8638 {
8639 TCGv_i64 tmp;
8640
8641 gen_evmwsmi(ctx); /* rD := rA * rB */
8642
8643 tmp = tcg_temp_new_i64();
8644
8645 /* acc := rD */
8646 gen_load_gpr64(tmp, rD(ctx->opcode));
8647 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8648
8649 tcg_temp_free_i64(tmp);
8650 }
8651
8652 static inline void gen_evmwsmiaa(DisasContext *ctx)
8653 {
8654 TCGv_i64 acc = tcg_temp_new_i64();
8655 TCGv_i64 tmp = tcg_temp_new_i64();
8656
8657 gen_evmwsmi(ctx); /* rD := rA * rB */
8658
8659 acc = tcg_temp_new_i64();
8660 tmp = tcg_temp_new_i64();
8661
8662 /* tmp := rD */
8663 gen_load_gpr64(tmp, rD(ctx->opcode));
8664
8665 /* Load acc */
8666 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8667
8668 /* acc := tmp + acc */
8669 tcg_gen_add_i64(acc, acc, tmp);
8670
8671 /* Store acc */
8672 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8673
8674 /* rD := acc */
8675 gen_store_gpr64(rD(ctx->opcode), acc);
8676
8677 tcg_temp_free_i64(acc);
8678 tcg_temp_free_i64(tmp);
8679 }
8680
8681 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8682 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8683 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8684 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8685 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8686 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8687 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8688 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
8689 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
8690 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8691 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8692 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8693 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8694 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8695 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8696 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8697 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8698 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8699 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8700 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
8701 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8702 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8703 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
8704 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
8705 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8706 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8707 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8708 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8709 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
8710
8711 /* SPE load and stores */
8712 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
8713 {
8714 target_ulong uimm = rB(ctx->opcode);
8715
8716 if (rA(ctx->opcode) == 0) {
8717 tcg_gen_movi_tl(EA, uimm << sh);
8718 } else {
8719 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
8720 if (NARROW_MODE(ctx)) {
8721 tcg_gen_ext32u_tl(EA, EA);
8722 }
8723 }
8724 }
8725
8726 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
8727 {
8728 #if defined(TARGET_PPC64)
8729 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8730 #else
8731 TCGv_i64 t0 = tcg_temp_new_i64();
8732 gen_qemu_ld64(ctx, t0, addr);
8733 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
8734 tcg_gen_shri_i64(t0, t0, 32);
8735 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
8736 tcg_temp_free_i64(t0);
8737 #endif
8738 }
8739
8740 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
8741 {
8742 #if defined(TARGET_PPC64)
8743 TCGv t0 = tcg_temp_new();
8744 gen_qemu_ld32u(ctx, t0, addr);
8745 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8746 gen_addr_add(ctx, addr, addr, 4);
8747 gen_qemu_ld32u(ctx, t0, addr);
8748 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8749 tcg_temp_free(t0);
8750 #else
8751 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8752 gen_addr_add(ctx, addr, addr, 4);
8753 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8754 #endif
8755 }
8756
8757 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
8758 {
8759 TCGv t0 = tcg_temp_new();
8760 #if defined(TARGET_PPC64)
8761 gen_qemu_ld16u(ctx, t0, addr);
8762 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8763 gen_addr_add(ctx, addr, addr, 2);
8764 gen_qemu_ld16u(ctx, t0, addr);
8765 tcg_gen_shli_tl(t0, t0, 32);
8766 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8767 gen_addr_add(ctx, addr, addr, 2);
8768 gen_qemu_ld16u(ctx, t0, addr);
8769 tcg_gen_shli_tl(t0, t0, 16);
8770 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8771 gen_addr_add(ctx, addr, addr, 2);
8772 gen_qemu_ld16u(ctx, t0, addr);
8773 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8774 #else
8775 gen_qemu_ld16u(ctx, t0, addr);
8776 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8777 gen_addr_add(ctx, addr, addr, 2);
8778 gen_qemu_ld16u(ctx, t0, addr);
8779 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8780 gen_addr_add(ctx, addr, addr, 2);
8781 gen_qemu_ld16u(ctx, t0, addr);
8782 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8783 gen_addr_add(ctx, addr, addr, 2);
8784 gen_qemu_ld16u(ctx, t0, addr);
8785 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8786 #endif
8787 tcg_temp_free(t0);
8788 }
8789
8790 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
8791 {
8792 TCGv t0 = tcg_temp_new();
8793 gen_qemu_ld16u(ctx, t0, addr);
8794 #if defined(TARGET_PPC64)
8795 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8796 tcg_gen_shli_tl(t0, t0, 16);
8797 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8798 #else
8799 tcg_gen_shli_tl(t0, t0, 16);
8800 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8801 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8802 #endif
8803 tcg_temp_free(t0);
8804 }
8805
8806 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
8807 {
8808 TCGv t0 = tcg_temp_new();
8809 gen_qemu_ld16u(ctx, t0, addr);
8810 #if defined(TARGET_PPC64)
8811 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8812 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8813 #else
8814 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8815 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8816 #endif
8817 tcg_temp_free(t0);
8818 }
8819
8820 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
8821 {
8822 TCGv t0 = tcg_temp_new();
8823 gen_qemu_ld16s(ctx, t0, addr);
8824 #if defined(TARGET_PPC64)
8825 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8826 tcg_gen_ext32u_tl(t0, t0);
8827 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8828 #else
8829 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8830 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8831 #endif
8832 tcg_temp_free(t0);
8833 }
8834
8835 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
8836 {
8837 TCGv t0 = tcg_temp_new();
8838 #if defined(TARGET_PPC64)
8839 gen_qemu_ld16u(ctx, t0, addr);
8840 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8841 gen_addr_add(ctx, addr, addr, 2);
8842 gen_qemu_ld16u(ctx, t0, addr);
8843 tcg_gen_shli_tl(t0, t0, 16);
8844 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8845 #else
8846 gen_qemu_ld16u(ctx, t0, addr);
8847 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8848 gen_addr_add(ctx, addr, addr, 2);
8849 gen_qemu_ld16u(ctx, t0, addr);
8850 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
8851 #endif
8852 tcg_temp_free(t0);
8853 }
8854
8855 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
8856 {
8857 #if defined(TARGET_PPC64)
8858 TCGv t0 = tcg_temp_new();
8859 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8860 gen_addr_add(ctx, addr, addr, 2);
8861 gen_qemu_ld16u(ctx, t0, addr);
8862 tcg_gen_shli_tl(t0, t0, 32);
8863 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8864 tcg_temp_free(t0);
8865 #else
8866 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8867 gen_addr_add(ctx, addr, addr, 2);
8868 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8869 #endif
8870 }
8871
8872 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
8873 {
8874 #if defined(TARGET_PPC64)
8875 TCGv t0 = tcg_temp_new();
8876 gen_qemu_ld16s(ctx, t0, addr);
8877 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
8878 gen_addr_add(ctx, addr, addr, 2);
8879 gen_qemu_ld16s(ctx, t0, addr);
8880 tcg_gen_shli_tl(t0, t0, 32);
8881 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8882 tcg_temp_free(t0);
8883 #else
8884 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8885 gen_addr_add(ctx, addr, addr, 2);
8886 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8887 #endif
8888 }
8889
8890 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
8891 {
8892 TCGv t0 = tcg_temp_new();
8893 gen_qemu_ld32u(ctx, t0, addr);
8894 #if defined(TARGET_PPC64)
8895 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8896 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8897 #else
8898 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8899 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8900 #endif
8901 tcg_temp_free(t0);
8902 }
8903
8904 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
8905 {
8906 TCGv t0 = tcg_temp_new();
8907 #if defined(TARGET_PPC64)
8908 gen_qemu_ld16u(ctx, t0, addr);
8909 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8910 tcg_gen_shli_tl(t0, t0, 32);
8911 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8912 gen_addr_add(ctx, addr, addr, 2);
8913 gen_qemu_ld16u(ctx, t0, addr);
8914 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8915 tcg_gen_shli_tl(t0, t0, 16);
8916 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8917 #else
8918 gen_qemu_ld16u(ctx, t0, addr);
8919 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8920 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8921 gen_addr_add(ctx, addr, addr, 2);
8922 gen_qemu_ld16u(ctx, t0, addr);
8923 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
8924 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8925 #endif
8926 tcg_temp_free(t0);
8927 }
8928
8929 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
8930 {
8931 #if defined(TARGET_PPC64)
8932 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8933 #else
8934 TCGv_i64 t0 = tcg_temp_new_i64();
8935 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
8936 gen_qemu_st64(ctx, t0, addr);
8937 tcg_temp_free_i64(t0);
8938 #endif
8939 }
8940
8941 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
8942 {
8943 #if defined(TARGET_PPC64)
8944 TCGv t0 = tcg_temp_new();
8945 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8946 gen_qemu_st32(ctx, t0, addr);
8947 tcg_temp_free(t0);
8948 #else
8949 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8950 #endif
8951 gen_addr_add(ctx, addr, addr, 4);
8952 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8953 }
8954
8955 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
8956 {
8957 TCGv t0 = tcg_temp_new();
8958 #if defined(TARGET_PPC64)
8959 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8960 #else
8961 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8962 #endif
8963 gen_qemu_st16(ctx, t0, addr);
8964 gen_addr_add(ctx, addr, addr, 2);
8965 #if defined(TARGET_PPC64)
8966 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8967 gen_qemu_st16(ctx, t0, addr);
8968 #else
8969 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8970 #endif
8971 gen_addr_add(ctx, addr, addr, 2);
8972 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8973 gen_qemu_st16(ctx, t0, addr);
8974 tcg_temp_free(t0);
8975 gen_addr_add(ctx, addr, addr, 2);
8976 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8977 }
8978
8979 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
8980 {
8981 TCGv t0 = tcg_temp_new();
8982 #if defined(TARGET_PPC64)
8983 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8984 #else
8985 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8986 #endif
8987 gen_qemu_st16(ctx, t0, addr);
8988 gen_addr_add(ctx, addr, addr, 2);
8989 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8990 gen_qemu_st16(ctx, t0, addr);
8991 tcg_temp_free(t0);
8992 }
8993
8994 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
8995 {
8996 #if defined(TARGET_PPC64)
8997 TCGv t0 = tcg_temp_new();
8998 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8999 gen_qemu_st16(ctx, t0, addr);
9000 tcg_temp_free(t0);
9001 #else
9002 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9003 #endif
9004 gen_addr_add(ctx, addr, addr, 2);
9005 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9006 }
9007
9008 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9009 {
9010 #if defined(TARGET_PPC64)
9011 TCGv t0 = tcg_temp_new();
9012 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
9013 gen_qemu_st32(ctx, t0, addr);
9014 tcg_temp_free(t0);
9015 #else
9016 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9017 #endif
9018 }
9019
9020 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9021 {
9022 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9023 }
9024
9025 #define GEN_SPEOP_LDST(name, opc2, sh) \
9026 static void glue(gen_, name)(DisasContext *ctx) \
9027 { \
9028 TCGv t0; \
9029 if (unlikely(!ctx->spe_enabled)) { \
9030 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9031 return; \
9032 } \
9033 gen_set_access_type(ctx, ACCESS_INT); \
9034 t0 = tcg_temp_new(); \
9035 if (Rc(ctx->opcode)) { \
9036 gen_addr_spe_imm_index(ctx, t0, sh); \
9037 } else { \
9038 gen_addr_reg_index(ctx, t0); \
9039 } \
9040 gen_op_##name(ctx, t0); \
9041 tcg_temp_free(t0); \
9042 }
9043
9044 GEN_SPEOP_LDST(evldd, 0x00, 3);
9045 GEN_SPEOP_LDST(evldw, 0x01, 3);
9046 GEN_SPEOP_LDST(evldh, 0x02, 3);
9047 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9048 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9049 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9050 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9051 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9052 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9053 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9054 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9055
9056 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9057 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9058 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9059 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9060 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9061 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9062 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9063
9064 /* Multiply and add - TODO */
9065 #if 0
9066 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9067 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9068 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9069 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9070 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9071 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9072 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9073 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9074 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9075 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9076 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9077 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9078
9079 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9080 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9081 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9082 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9083 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9084 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9085 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9086 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9087 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9088 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9089 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9090 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9091
9092 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9093 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9094 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9095 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9096 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9097
9098 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9099 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9100 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9101 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9102 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9103 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9104 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9105 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9106 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9107 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9108 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9109 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9110
9111 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9112 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9113 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9114 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9115
9116 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9117 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9118 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9119 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9120 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9121 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9122 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9123 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9124 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9125 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9126 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9127 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9128
9129 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9130 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9131 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9132 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9133 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9134 #endif
9135
9136 /*** SPE floating-point extension ***/
9137 #if defined(TARGET_PPC64)
9138 #define GEN_SPEFPUOP_CONV_32_32(name) \
9139 static inline void gen_##name(DisasContext *ctx) \
9140 { \
9141 TCGv_i32 t0; \
9142 TCGv t1; \
9143 t0 = tcg_temp_new_i32(); \
9144 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9145 gen_helper_##name(t0, cpu_env, t0); \
9146 t1 = tcg_temp_new(); \
9147 tcg_gen_extu_i32_tl(t1, t0); \
9148 tcg_temp_free_i32(t0); \
9149 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9150 0xFFFFFFFF00000000ULL); \
9151 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9152 tcg_temp_free(t1); \
9153 }
9154 #define GEN_SPEFPUOP_CONV_32_64(name) \
9155 static inline void gen_##name(DisasContext *ctx) \
9156 { \
9157 TCGv_i32 t0; \
9158 TCGv t1; \
9159 t0 = tcg_temp_new_i32(); \
9160 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9161 t1 = tcg_temp_new(); \
9162 tcg_gen_extu_i32_tl(t1, t0); \
9163 tcg_temp_free_i32(t0); \
9164 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9165 0xFFFFFFFF00000000ULL); \
9166 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9167 tcg_temp_free(t1); \
9168 }
9169 #define GEN_SPEFPUOP_CONV_64_32(name) \
9170 static inline void gen_##name(DisasContext *ctx) \
9171 { \
9172 TCGv_i32 t0 = tcg_temp_new_i32(); \
9173 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9174 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9175 tcg_temp_free_i32(t0); \
9176 }
9177 #define GEN_SPEFPUOP_CONV_64_64(name) \
9178 static inline void gen_##name(DisasContext *ctx) \
9179 { \
9180 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9181 cpu_gpr[rB(ctx->opcode)]); \
9182 }
9183 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9184 static inline void gen_##name(DisasContext *ctx) \
9185 { \
9186 TCGv_i32 t0, t1; \
9187 TCGv_i64 t2; \
9188 if (unlikely(!ctx->spe_enabled)) { \
9189 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9190 return; \
9191 } \
9192 t0 = tcg_temp_new_i32(); \
9193 t1 = tcg_temp_new_i32(); \
9194 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9195 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9196 gen_helper_##name(t0, cpu_env, t0, t1); \
9197 tcg_temp_free_i32(t1); \
9198 t2 = tcg_temp_new(); \
9199 tcg_gen_extu_i32_tl(t2, t0); \
9200 tcg_temp_free_i32(t0); \
9201 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9202 0xFFFFFFFF00000000ULL); \
9203 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
9204 tcg_temp_free(t2); \
9205 }
9206 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9207 static inline void gen_##name(DisasContext *ctx) \
9208 { \
9209 if (unlikely(!ctx->spe_enabled)) { \
9210 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9211 return; \
9212 } \
9213 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9214 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9215 }
9216 #define GEN_SPEFPUOP_COMP_32(name) \
9217 static inline void gen_##name(DisasContext *ctx) \
9218 { \
9219 TCGv_i32 t0, t1; \
9220 if (unlikely(!ctx->spe_enabled)) { \
9221 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9222 return; \
9223 } \
9224 t0 = tcg_temp_new_i32(); \
9225 t1 = tcg_temp_new_i32(); \
9226 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9227 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9228 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9229 tcg_temp_free_i32(t0); \
9230 tcg_temp_free_i32(t1); \
9231 }
9232 #define GEN_SPEFPUOP_COMP_64(name) \
9233 static inline void gen_##name(DisasContext *ctx) \
9234 { \
9235 if (unlikely(!ctx->spe_enabled)) { \
9236 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9237 return; \
9238 } \
9239 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9240 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9241 }
9242 #else
9243 #define GEN_SPEFPUOP_CONV_32_32(name) \
9244 static inline void gen_##name(DisasContext *ctx) \
9245 { \
9246 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9247 cpu_gpr[rB(ctx->opcode)]); \
9248 }
9249 #define GEN_SPEFPUOP_CONV_32_64(name) \
9250 static inline void gen_##name(DisasContext *ctx) \
9251 { \
9252 TCGv_i64 t0 = tcg_temp_new_i64(); \
9253 gen_load_gpr64(t0, rB(ctx->opcode)); \
9254 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9255 tcg_temp_free_i64(t0); \
9256 }
9257 #define GEN_SPEFPUOP_CONV_64_32(name) \
9258 static inline void gen_##name(DisasContext *ctx) \
9259 { \
9260 TCGv_i64 t0 = tcg_temp_new_i64(); \
9261 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9262 gen_store_gpr64(rD(ctx->opcode), t0); \
9263 tcg_temp_free_i64(t0); \
9264 }
9265 #define GEN_SPEFPUOP_CONV_64_64(name) \
9266 static inline void gen_##name(DisasContext *ctx) \
9267 { \
9268 TCGv_i64 t0 = tcg_temp_new_i64(); \
9269 gen_load_gpr64(t0, rB(ctx->opcode)); \
9270 gen_helper_##name(t0, cpu_env, t0); \
9271 gen_store_gpr64(rD(ctx->opcode), t0); \
9272 tcg_temp_free_i64(t0); \
9273 }
9274 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9275 static inline void gen_##name(DisasContext *ctx) \
9276 { \
9277 if (unlikely(!ctx->spe_enabled)) { \
9278 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9279 return; \
9280 } \
9281 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9282 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9283 }
9284 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9285 static inline void gen_##name(DisasContext *ctx) \
9286 { \
9287 TCGv_i64 t0, t1; \
9288 if (unlikely(!ctx->spe_enabled)) { \
9289 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9290 return; \
9291 } \
9292 t0 = tcg_temp_new_i64(); \
9293 t1 = tcg_temp_new_i64(); \
9294 gen_load_gpr64(t0, rA(ctx->opcode)); \
9295 gen_load_gpr64(t1, rB(ctx->opcode)); \
9296 gen_helper_##name(t0, cpu_env, t0, t1); \
9297 gen_store_gpr64(rD(ctx->opcode), t0); \
9298 tcg_temp_free_i64(t0); \
9299 tcg_temp_free_i64(t1); \
9300 }
9301 #define GEN_SPEFPUOP_COMP_32(name) \
9302 static inline void gen_##name(DisasContext *ctx) \
9303 { \
9304 if (unlikely(!ctx->spe_enabled)) { \
9305 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9306 return; \
9307 } \
9308 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9309 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9310 }
9311 #define GEN_SPEFPUOP_COMP_64(name) \
9312 static inline void gen_##name(DisasContext *ctx) \
9313 { \
9314 TCGv_i64 t0, t1; \
9315 if (unlikely(!ctx->spe_enabled)) { \
9316 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9317 return; \
9318 } \
9319 t0 = tcg_temp_new_i64(); \
9320 t1 = tcg_temp_new_i64(); \
9321 gen_load_gpr64(t0, rA(ctx->opcode)); \
9322 gen_load_gpr64(t1, rB(ctx->opcode)); \
9323 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9324 tcg_temp_free_i64(t0); \
9325 tcg_temp_free_i64(t1); \
9326 }
9327 #endif
9328
9329 /* Single precision floating-point vectors operations */
9330 /* Arithmetic */
9331 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9332 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9333 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9334 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9335 static inline void gen_evfsabs(DisasContext *ctx)
9336 {
9337 if (unlikely(!ctx->spe_enabled)) {
9338 gen_exception(ctx, POWERPC_EXCP_SPEU);
9339 return;
9340 }
9341 #if defined(TARGET_PPC64)
9342 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
9343 #else
9344 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
9345 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9346 #endif
9347 }
9348 static inline void gen_evfsnabs(DisasContext *ctx)
9349 {
9350 if (unlikely(!ctx->spe_enabled)) {
9351 gen_exception(ctx, POWERPC_EXCP_SPEU);
9352 return;
9353 }
9354 #if defined(TARGET_PPC64)
9355 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9356 #else
9357 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9358 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9359 #endif
9360 }
9361 static inline void gen_evfsneg(DisasContext *ctx)
9362 {
9363 if (unlikely(!ctx->spe_enabled)) {
9364 gen_exception(ctx, POWERPC_EXCP_SPEU);
9365 return;
9366 }
9367 #if defined(TARGET_PPC64)
9368 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9369 #else
9370 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9371 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9372 #endif
9373 }
9374
9375 /* Conversion */
9376 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9377 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9378 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9379 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9380 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9381 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9382 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9383 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9384 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9385 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9386
9387 /* Comparison */
9388 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9389 GEN_SPEFPUOP_COMP_64(evfscmplt);
9390 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9391 GEN_SPEFPUOP_COMP_64(evfststgt);
9392 GEN_SPEFPUOP_COMP_64(evfststlt);
9393 GEN_SPEFPUOP_COMP_64(evfststeq);
9394
9395 /* Opcodes definitions */
9396 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9397 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9398 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9399 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9400 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9401 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9402 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9403 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9404 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9405 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9406 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9407 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9408 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9409 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9410
9411 /* Single precision floating-point operations */
9412 /* Arithmetic */
9413 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9414 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9415 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9416 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9417 static inline void gen_efsabs(DisasContext *ctx)
9418 {
9419 if (unlikely(!ctx->spe_enabled)) {
9420 gen_exception(ctx, POWERPC_EXCP_SPEU);
9421 return;
9422 }
9423 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9424 }
9425 static inline void gen_efsnabs(DisasContext *ctx)
9426 {
9427 if (unlikely(!ctx->spe_enabled)) {
9428 gen_exception(ctx, POWERPC_EXCP_SPEU);
9429 return;
9430 }
9431 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9432 }
9433 static inline void gen_efsneg(DisasContext *ctx)
9434 {
9435 if (unlikely(!ctx->spe_enabled)) {
9436 gen_exception(ctx, POWERPC_EXCP_SPEU);
9437 return;
9438 }
9439 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9440 }
9441
9442 /* Conversion */
9443 GEN_SPEFPUOP_CONV_32_32(efscfui);
9444 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9445 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9446 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9447 GEN_SPEFPUOP_CONV_32_32(efsctui);
9448 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9449 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9450 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9451 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9452 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9453 GEN_SPEFPUOP_CONV_32_64(efscfd);
9454
9455 /* Comparison */
9456 GEN_SPEFPUOP_COMP_32(efscmpgt);
9457 GEN_SPEFPUOP_COMP_32(efscmplt);
9458 GEN_SPEFPUOP_COMP_32(efscmpeq);
9459 GEN_SPEFPUOP_COMP_32(efststgt);
9460 GEN_SPEFPUOP_COMP_32(efststlt);
9461 GEN_SPEFPUOP_COMP_32(efststeq);
9462
9463 /* Opcodes definitions */
9464 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9465 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9466 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9467 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9468 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9469 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9470 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9471 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9472 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9473 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9474 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9475 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9476 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9477 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9478
9479 /* Double precision floating-point operations */
9480 /* Arithmetic */
9481 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9482 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9483 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9484 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9485 static inline void gen_efdabs(DisasContext *ctx)
9486 {
9487 if (unlikely(!ctx->spe_enabled)) {
9488 gen_exception(ctx, POWERPC_EXCP_SPEU);
9489 return;
9490 }
9491 #if defined(TARGET_PPC64)
9492 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
9493 #else
9494 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9495 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9496 #endif
9497 }
9498 static inline void gen_efdnabs(DisasContext *ctx)
9499 {
9500 if (unlikely(!ctx->spe_enabled)) {
9501 gen_exception(ctx, POWERPC_EXCP_SPEU);
9502 return;
9503 }
9504 #if defined(TARGET_PPC64)
9505 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9506 #else
9507 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9508 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9509 #endif
9510 }
9511 static inline void gen_efdneg(DisasContext *ctx)
9512 {
9513 if (unlikely(!ctx->spe_enabled)) {
9514 gen_exception(ctx, POWERPC_EXCP_SPEU);
9515 return;
9516 }
9517 #if defined(TARGET_PPC64)
9518 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9519 #else
9520 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9521 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9522 #endif
9523 }
9524
9525 /* Conversion */
9526 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9527 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9528 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9529 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9530 GEN_SPEFPUOP_CONV_32_64(efdctui);
9531 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9532 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9533 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9534 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9535 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9536 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9537 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9538 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9539 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9540 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9541
9542 /* Comparison */
9543 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9544 GEN_SPEFPUOP_COMP_64(efdcmplt);
9545 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9546 GEN_SPEFPUOP_COMP_64(efdtstgt);
9547 GEN_SPEFPUOP_COMP_64(efdtstlt);
9548 GEN_SPEFPUOP_COMP_64(efdtsteq);
9549
9550 /* Opcodes definitions */
9551 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9552 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9553 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9554 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9555 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9556 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9557 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9558 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9559 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9560 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9561 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9562 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9563 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9564 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9565 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9566 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9567
9568 static opcode_t opcodes[] = {
9569 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9570 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9571 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9572 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9573 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9574 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9575 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9576 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9577 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9578 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9579 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9580 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9581 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9582 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9583 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9584 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9585 #if defined(TARGET_PPC64)
9586 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9587 #endif
9588 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9589 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9590 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9591 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9592 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9593 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9594 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9595 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9596 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9597 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9598 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9599 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9600 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
9601 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9602 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9603 #if defined(TARGET_PPC64)
9604 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9605 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9606 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9607 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9608 #endif
9609 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9610 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9611 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9612 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9613 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9614 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9615 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9616 #if defined(TARGET_PPC64)
9617 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9618 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9619 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9620 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9621 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9622 #endif
9623 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9624 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9625 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9626 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9627 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9628 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9629 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9630 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9631 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9632 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9633 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9634 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9635 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9636 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9637 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9638 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9639 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9640 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9641 #if defined(TARGET_PPC64)
9642 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9643 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9644 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9645 #endif
9646 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9647 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9648 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9649 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9650 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9651 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9652 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9653 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9654 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9655 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9656 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9657 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9658 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9659 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9660 #if defined(TARGET_PPC64)
9661 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9662 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9663 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9664 #endif
9665 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9666 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9667 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9668 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9669 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9670 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9671 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9672 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9673 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9674 #if defined(TARGET_PPC64)
9675 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9676 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9677 #endif
9678 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9679 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9680 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9681 #if defined(TARGET_PPC64)
9682 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9683 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9684 #endif
9685 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9686 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9687 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9688 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9689 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9690 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9691 #if defined(TARGET_PPC64)
9692 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9693 #endif
9694 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9695 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9696 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9697 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9698 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9699 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9700 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9701 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9702 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9703 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9704 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9705 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9706 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9707 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9708 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9709 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9710 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9711 #if defined(TARGET_PPC64)
9712 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9713 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9714 PPC_SEGMENT_64B),
9715 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9716 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9717 PPC_SEGMENT_64B),
9718 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9719 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9720 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9721 #endif
9722 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9723 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9724 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9725 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9726 #if defined(TARGET_PPC64)
9727 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9728 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9729 #endif
9730 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9731 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9732 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9733 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9734 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9735 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9736 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9737 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9738 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9739 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9740 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9741 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9742 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9743 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9744 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9745 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9746 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9747 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9748 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9749 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9750 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9751 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9752 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9753 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9754 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9755 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9756 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9757 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9758 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9759 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9760 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9761 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9762 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9763 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9764 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9765 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9766 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9767 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9768 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9769 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9770 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9771 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9772 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9773 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9774 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9775 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9776 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9777 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9778 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9779 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9780 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9781 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9782 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9783 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9784 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9785 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9786 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9787 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9788 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9789 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9790 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9791 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9792 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9793 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9794 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9795 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9796 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9797 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9798 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9799 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9800 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9801 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9802 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9803 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9804 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9805 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9806 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9807 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9808 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9809 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9810 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9811 PPC_NONE, PPC2_BOOKE206),
9812 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9813 PPC_NONE, PPC2_BOOKE206),
9814 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9815 PPC_NONE, PPC2_BOOKE206),
9816 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9817 PPC_NONE, PPC2_BOOKE206),
9818 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9819 PPC_NONE, PPC2_BOOKE206),
9820 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9821 PPC_NONE, PPC2_PRCNTL),
9822 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9823 PPC_NONE, PPC2_PRCNTL),
9824 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
9825 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
9826 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
9827 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9828 PPC_BOOKE, PPC2_BOOKE206),
9829 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
9830 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9831 PPC_BOOKE, PPC2_BOOKE206),
9832 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9833 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9834 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9835 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
9836 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
9837 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9838 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9839 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9840 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9841 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9842
9843 #undef GEN_INT_ARITH_ADD
9844 #undef GEN_INT_ARITH_ADD_CONST
9845 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9846 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9847 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9848 add_ca, compute_ca, compute_ov) \
9849 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9850 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9851 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9852 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9853 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9854 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9855 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9856 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
9857 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
9858 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
9859 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
9860
9861 #undef GEN_INT_ARITH_DIVW
9862 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9863 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9864 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
9865 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
9866 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
9867 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
9868 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9869 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9870 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9871 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9872
9873 #if defined(TARGET_PPC64)
9874 #undef GEN_INT_ARITH_DIVD
9875 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9876 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9877 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
9878 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
9879 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
9880 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
9881
9882 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9883 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9884 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9885 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9886
9887 #undef GEN_INT_ARITH_MUL_HELPER
9888 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
9889 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9890 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
9891 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
9892 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
9893 #endif
9894
9895 #undef GEN_INT_ARITH_SUBF
9896 #undef GEN_INT_ARITH_SUBF_CONST
9897 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
9898 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
9899 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
9900 add_ca, compute_ca, compute_ov) \
9901 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
9902 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
9903 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
9904 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
9905 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
9906 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
9907 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
9908 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
9909 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
9910 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
9911 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
9912
9913 #undef GEN_LOGICAL1
9914 #undef GEN_LOGICAL2
9915 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
9916 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
9917 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
9918 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
9919 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
9920 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
9921 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
9922 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
9923 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
9924 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
9925 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
9926 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
9927 #if defined(TARGET_PPC64)
9928 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
9929 #endif
9930
9931 #if defined(TARGET_PPC64)
9932 #undef GEN_PPC64_R2
9933 #undef GEN_PPC64_R4
9934 #define GEN_PPC64_R2(name, opc1, opc2) \
9935 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9936 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9937 PPC_64B)
9938 #define GEN_PPC64_R4(name, opc1, opc2) \
9939 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9940 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
9941 PPC_64B), \
9942 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9943 PPC_64B), \
9944 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
9945 PPC_64B)
9946 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
9947 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
9948 GEN_PPC64_R4(rldic, 0x1E, 0x04),
9949 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
9950 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
9951 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
9952 #endif
9953
9954 #undef _GEN_FLOAT_ACB
9955 #undef GEN_FLOAT_ACB
9956 #undef _GEN_FLOAT_AB
9957 #undef GEN_FLOAT_AB
9958 #undef _GEN_FLOAT_AC
9959 #undef GEN_FLOAT_AC
9960 #undef GEN_FLOAT_B
9961 #undef GEN_FLOAT_BS
9962 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
9963 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
9964 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
9965 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
9966 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
9967 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9968 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9969 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
9970 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9971 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9972 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9973 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9974 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
9975 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9976 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9977 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
9978 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
9979 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
9980 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
9981
9982 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
9983 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
9984 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
9985 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
9986 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
9987 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
9988 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
9989 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
9990 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
9991 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
9992 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
9993 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
9994 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
9995 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
9996 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
9997 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9998 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
9999 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10000 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10001 #if defined(TARGET_PPC64)
10002 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
10003 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10004 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10005 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10006 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
10007 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10008 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
10009 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10010 #endif
10011 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10012 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10013 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10014 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10015
10016 #undef GEN_LD
10017 #undef GEN_LDU
10018 #undef GEN_LDUX
10019 #undef GEN_LDX_E
10020 #undef GEN_LDS
10021 #define GEN_LD(name, ldop, opc, type) \
10022 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10023 #define GEN_LDU(name, ldop, opc, type) \
10024 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10025 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10026 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10027 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10028 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10029 #define GEN_LDS(name, ldop, op, type) \
10030 GEN_LD(name, ldop, op | 0x20, type) \
10031 GEN_LDU(name, ldop, op | 0x21, type) \
10032 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10033 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10034
10035 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10036 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10037 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10038 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10039 #if defined(TARGET_PPC64)
10040 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10041 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10042 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10043 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10044 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10045 #endif
10046 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10047 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10048
10049 #undef GEN_ST
10050 #undef GEN_STU
10051 #undef GEN_STUX
10052 #undef GEN_STX_E
10053 #undef GEN_STS
10054 #define GEN_ST(name, stop, opc, type) \
10055 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10056 #define GEN_STU(name, stop, opc, type) \
10057 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10058 #define GEN_STUX(name, stop, opc2, opc3, type) \
10059 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10060 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10061 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10062 #define GEN_STS(name, stop, op, type) \
10063 GEN_ST(name, stop, op | 0x20, type) \
10064 GEN_STU(name, stop, op | 0x21, type) \
10065 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10066 GEN_STX(name, stop, 0x17, op | 0x00, type)
10067
10068 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10069 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10070 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10071 #if defined(TARGET_PPC64)
10072 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10073 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10074 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10075 #endif
10076 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10077 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10078
10079 #undef GEN_LDF
10080 #undef GEN_LDUF
10081 #undef GEN_LDUXF
10082 #undef GEN_LDXF
10083 #undef GEN_LDFS
10084 #define GEN_LDF(name, ldop, opc, type) \
10085 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10086 #define GEN_LDUF(name, ldop, opc, type) \
10087 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10088 #define GEN_LDUXF(name, ldop, opc, type) \
10089 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10090 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10091 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10092 #define GEN_LDFS(name, ldop, op, type) \
10093 GEN_LDF(name, ldop, op | 0x20, type) \
10094 GEN_LDUF(name, ldop, op | 0x21, type) \
10095 GEN_LDUXF(name, ldop, op | 0x01, type) \
10096 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10097
10098 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10099 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10100 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10101 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10102 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10103 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10104
10105 #undef GEN_STF
10106 #undef GEN_STUF
10107 #undef GEN_STUXF
10108 #undef GEN_STXF
10109 #undef GEN_STFS
10110 #define GEN_STF(name, stop, opc, type) \
10111 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10112 #define GEN_STUF(name, stop, opc, type) \
10113 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10114 #define GEN_STUXF(name, stop, opc, type) \
10115 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10116 #define GEN_STXF(name, stop, opc2, opc3, type) \
10117 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10118 #define GEN_STFS(name, stop, op, type) \
10119 GEN_STF(name, stop, op | 0x20, type) \
10120 GEN_STUF(name, stop, op | 0x21, type) \
10121 GEN_STUXF(name, stop, op | 0x01, type) \
10122 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10123
10124 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10125 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10126 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10127 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10128 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10129
10130 #undef GEN_CRLOGIC
10131 #define GEN_CRLOGIC(name, tcg_op, opc) \
10132 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10133 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10134 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10135 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10136 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10137 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10138 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10139 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10140 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10141
10142 #undef GEN_MAC_HANDLER
10143 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10144 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10145 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10146 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10147 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10148 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10149 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10150 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10151 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10152 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10153 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10154 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10155 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10156 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10157 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10158 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10159 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10160 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10161 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10162 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10163 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10164 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10165 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10166 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10167 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10168 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10169 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10170 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10171 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10172 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10173 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10174 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10175 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10176 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10177 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10178 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10179 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10180 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10181 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10182 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10183 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10184 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10185 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10186 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10187
10188 #undef GEN_VR_LDX
10189 #undef GEN_VR_STX
10190 #undef GEN_VR_LVE
10191 #undef GEN_VR_STVE
10192 #define GEN_VR_LDX(name, opc2, opc3) \
10193 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10194 #define GEN_VR_STX(name, opc2, opc3) \
10195 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10196 #define GEN_VR_LVE(name, opc2, opc3) \
10197 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10198 #define GEN_VR_STVE(name, opc2, opc3) \
10199 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10200 GEN_VR_LDX(lvx, 0x07, 0x03),
10201 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10202 GEN_VR_LVE(bx, 0x07, 0x00),
10203 GEN_VR_LVE(hx, 0x07, 0x01),
10204 GEN_VR_LVE(wx, 0x07, 0x02),
10205 GEN_VR_STX(svx, 0x07, 0x07),
10206 GEN_VR_STX(svxl, 0x07, 0x0F),
10207 GEN_VR_STVE(bx, 0x07, 0x04),
10208 GEN_VR_STVE(hx, 0x07, 0x05),
10209 GEN_VR_STVE(wx, 0x07, 0x06),
10210
10211 #undef GEN_VX_LOGICAL
10212 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10213 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10214 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10215 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10216 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10217 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10218 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10219
10220 #undef GEN_VXFORM
10221 #define GEN_VXFORM(name, opc2, opc3) \
10222 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10223 GEN_VXFORM(vaddubm, 0, 0),
10224 GEN_VXFORM(vadduhm, 0, 1),
10225 GEN_VXFORM(vadduwm, 0, 2),
10226 GEN_VXFORM(vsububm, 0, 16),
10227 GEN_VXFORM(vsubuhm, 0, 17),
10228 GEN_VXFORM(vsubuwm, 0, 18),
10229 GEN_VXFORM(vmaxub, 1, 0),
10230 GEN_VXFORM(vmaxuh, 1, 1),
10231 GEN_VXFORM(vmaxuw, 1, 2),
10232 GEN_VXFORM(vmaxsb, 1, 4),
10233 GEN_VXFORM(vmaxsh, 1, 5),
10234 GEN_VXFORM(vmaxsw, 1, 6),
10235 GEN_VXFORM(vminub, 1, 8),
10236 GEN_VXFORM(vminuh, 1, 9),
10237 GEN_VXFORM(vminuw, 1, 10),
10238 GEN_VXFORM(vminsb, 1, 12),
10239 GEN_VXFORM(vminsh, 1, 13),
10240 GEN_VXFORM(vminsw, 1, 14),
10241 GEN_VXFORM(vavgub, 1, 16),
10242 GEN_VXFORM(vavguh, 1, 17),
10243 GEN_VXFORM(vavguw, 1, 18),
10244 GEN_VXFORM(vavgsb, 1, 20),
10245 GEN_VXFORM(vavgsh, 1, 21),
10246 GEN_VXFORM(vavgsw, 1, 22),
10247 GEN_VXFORM(vmrghb, 6, 0),
10248 GEN_VXFORM(vmrghh, 6, 1),
10249 GEN_VXFORM(vmrghw, 6, 2),
10250 GEN_VXFORM(vmrglb, 6, 4),
10251 GEN_VXFORM(vmrglh, 6, 5),
10252 GEN_VXFORM(vmrglw, 6, 6),
10253 GEN_VXFORM(vmuloub, 4, 0),
10254 GEN_VXFORM(vmulouh, 4, 1),
10255 GEN_VXFORM(vmulosb, 4, 4),
10256 GEN_VXFORM(vmulosh, 4, 5),
10257 GEN_VXFORM(vmuleub, 4, 8),
10258 GEN_VXFORM(vmuleuh, 4, 9),
10259 GEN_VXFORM(vmulesb, 4, 12),
10260 GEN_VXFORM(vmulesh, 4, 13),
10261 GEN_VXFORM(vslb, 2, 4),
10262 GEN_VXFORM(vslh, 2, 5),
10263 GEN_VXFORM(vslw, 2, 6),
10264 GEN_VXFORM(vsrb, 2, 8),
10265 GEN_VXFORM(vsrh, 2, 9),
10266 GEN_VXFORM(vsrw, 2, 10),
10267 GEN_VXFORM(vsrab, 2, 12),
10268 GEN_VXFORM(vsrah, 2, 13),
10269 GEN_VXFORM(vsraw, 2, 14),
10270 GEN_VXFORM(vslo, 6, 16),
10271 GEN_VXFORM(vsro, 6, 17),
10272 GEN_VXFORM(vaddcuw, 0, 6),
10273 GEN_VXFORM(vsubcuw, 0, 22),
10274 GEN_VXFORM(vaddubs, 0, 8),
10275 GEN_VXFORM(vadduhs, 0, 9),
10276 GEN_VXFORM(vadduws, 0, 10),
10277 GEN_VXFORM(vaddsbs, 0, 12),
10278 GEN_VXFORM(vaddshs, 0, 13),
10279 GEN_VXFORM(vaddsws, 0, 14),
10280 GEN_VXFORM(vsububs, 0, 24),
10281 GEN_VXFORM(vsubuhs, 0, 25),
10282 GEN_VXFORM(vsubuws, 0, 26),
10283 GEN_VXFORM(vsubsbs, 0, 28),
10284 GEN_VXFORM(vsubshs, 0, 29),
10285 GEN_VXFORM(vsubsws, 0, 30),
10286 GEN_VXFORM(vrlb, 2, 0),
10287 GEN_VXFORM(vrlh, 2, 1),
10288 GEN_VXFORM(vrlw, 2, 2),
10289 GEN_VXFORM(vsl, 2, 7),
10290 GEN_VXFORM(vsr, 2, 11),
10291 GEN_VXFORM(vpkuhum, 7, 0),
10292 GEN_VXFORM(vpkuwum, 7, 1),
10293 GEN_VXFORM(vpkuhus, 7, 2),
10294 GEN_VXFORM(vpkuwus, 7, 3),
10295 GEN_VXFORM(vpkshus, 7, 4),
10296 GEN_VXFORM(vpkswus, 7, 5),
10297 GEN_VXFORM(vpkshss, 7, 6),
10298 GEN_VXFORM(vpkswss, 7, 7),
10299 GEN_VXFORM(vpkpx, 7, 12),
10300 GEN_VXFORM(vsum4ubs, 4, 24),
10301 GEN_VXFORM(vsum4sbs, 4, 28),
10302 GEN_VXFORM(vsum4shs, 4, 25),
10303 GEN_VXFORM(vsum2sws, 4, 26),
10304 GEN_VXFORM(vsumsws, 4, 30),
10305 GEN_VXFORM(vaddfp, 5, 0),
10306 GEN_VXFORM(vsubfp, 5, 1),
10307 GEN_VXFORM(vmaxfp, 5, 16),
10308 GEN_VXFORM(vminfp, 5, 17),
10309
10310 #undef GEN_VXRFORM1
10311 #undef GEN_VXRFORM
10312 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10313 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10314 #define GEN_VXRFORM(name, opc2, opc3) \
10315 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10316 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10317 GEN_VXRFORM(vcmpequb, 3, 0)
10318 GEN_VXRFORM(vcmpequh, 3, 1)
10319 GEN_VXRFORM(vcmpequw, 3, 2)
10320 GEN_VXRFORM(vcmpgtsb, 3, 12)
10321 GEN_VXRFORM(vcmpgtsh, 3, 13)
10322 GEN_VXRFORM(vcmpgtsw, 3, 14)
10323 GEN_VXRFORM(vcmpgtub, 3, 8)
10324 GEN_VXRFORM(vcmpgtuh, 3, 9)
10325 GEN_VXRFORM(vcmpgtuw, 3, 10)
10326 GEN_VXRFORM(vcmpeqfp, 3, 3)
10327 GEN_VXRFORM(vcmpgefp, 3, 7)
10328 GEN_VXRFORM(vcmpgtfp, 3, 11)
10329 GEN_VXRFORM(vcmpbfp, 3, 15)
10330
10331 #undef GEN_VXFORM_SIMM
10332 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10333 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10334 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10335 GEN_VXFORM_SIMM(vspltish, 6, 13),
10336 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10337
10338 #undef GEN_VXFORM_NOA
10339 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10340 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10341 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10342 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10343 GEN_VXFORM_NOA(vupklsb, 7, 10),
10344 GEN_VXFORM_NOA(vupklsh, 7, 11),
10345 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10346 GEN_VXFORM_NOA(vupklpx, 7, 15),
10347 GEN_VXFORM_NOA(vrefp, 5, 4),
10348 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10349 GEN_VXFORM_NOA(vexptefp, 5, 6),
10350 GEN_VXFORM_NOA(vlogefp, 5, 7),
10351 GEN_VXFORM_NOA(vrfim, 5, 8),
10352 GEN_VXFORM_NOA(vrfin, 5, 9),
10353 GEN_VXFORM_NOA(vrfip, 5, 10),
10354 GEN_VXFORM_NOA(vrfiz, 5, 11),
10355
10356 #undef GEN_VXFORM_UIMM
10357 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10358 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10359 GEN_VXFORM_UIMM(vspltb, 6, 8),
10360 GEN_VXFORM_UIMM(vsplth, 6, 9),
10361 GEN_VXFORM_UIMM(vspltw, 6, 10),
10362 GEN_VXFORM_UIMM(vcfux, 5, 12),
10363 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10364 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10365 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10366
10367 #undef GEN_VAFORM_PAIRED
10368 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10369 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10370 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10371 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10372 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10373 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10374 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10375 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10376
10377 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10378 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10379 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10380 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10381 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10382 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10383 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10384
10385 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10386 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10387 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10388 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10389 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10390
10391 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10392 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10393 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10394 #if defined(TARGET_PPC64)
10395 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10396 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10397 #endif
10398
10399 #undef GEN_XX2FORM
10400 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10401 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10402 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10403
10404 #undef GEN_XX3FORM
10405 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10406 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10407 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10408 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10409 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10410
10411 #undef GEN_XX3_RC_FORM
10412 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10413 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10414 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10415 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10416 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10417 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10418 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10419 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10420 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10421
10422 #undef GEN_XX3FORM_DM
10423 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10424 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10425 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10426 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10427 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10428 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10429 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10430 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10431 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10432 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10433 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10434 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10435 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10436 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10437 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10438 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10439 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10440
10441 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10442 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10443 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10444 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10445
10446 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10447 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10448 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10449 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10450 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10451 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10452 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10453 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10454
10455 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10456 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10457 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10458 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10459 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10460 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10461 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10462 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10463 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10464 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10465 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10466 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10467 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10468 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10469 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10470 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10471 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10472 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10473 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10474 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10475 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10476 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10477 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10478 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10479 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10480 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10481 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10482 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10483 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10484 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10485 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10486 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10487 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10488 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10489 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10490 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10491
10492 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10493 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10494 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10495 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10496 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10497 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10498 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10499 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10500 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10501 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10502 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10503 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10504 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10505 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10506 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10507 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10508 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10509 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10510
10511 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10512 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10513 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10514 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10515 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10516 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10517 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10518 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10519 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10520 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10521 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10522 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10523 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10524 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10525 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10526 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10527 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10528 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10529 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10530 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10531 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10532 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10533 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10534 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10535 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10536 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10537 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10538 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10539 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10540 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10541 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10542 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10543 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10544 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10545 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10546 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10547
10548 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10549 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10550 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10551 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10552 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10553 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10554 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10555 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10556 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10557 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10558 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10559 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10560 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10561 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10562 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10563 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10564 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10565 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10566 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10567 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10568 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10569 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10570 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10571 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10572 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10573 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10574 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10575 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10576 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10577 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10578 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10579 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10580 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10581 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10582 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10583 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10584
10585 #undef VSX_LOGICAL
10586 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10587 GEN_XX3FORM(name, opc2, opc3, fl2)
10588
10589 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10590 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10591 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10592 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10593 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10594 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10595 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10596 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10597 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10598 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10599 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10600 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10601
10602 #define GEN_XXSEL_ROW(opc3) \
10603 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10604 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10605 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10606 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10607 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10608 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10609 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10610 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10611
10612 GEN_XXSEL_ROW(0x00)
10613 GEN_XXSEL_ROW(0x01)
10614 GEN_XXSEL_ROW(0x02)
10615 GEN_XXSEL_ROW(0x03)
10616 GEN_XXSEL_ROW(0x04)
10617 GEN_XXSEL_ROW(0x05)
10618 GEN_XXSEL_ROW(0x06)
10619 GEN_XXSEL_ROW(0x07)
10620 GEN_XXSEL_ROW(0x08)
10621 GEN_XXSEL_ROW(0x09)
10622 GEN_XXSEL_ROW(0x0A)
10623 GEN_XXSEL_ROW(0x0B)
10624 GEN_XXSEL_ROW(0x0C)
10625 GEN_XXSEL_ROW(0x0D)
10626 GEN_XXSEL_ROW(0x0E)
10627 GEN_XXSEL_ROW(0x0F)
10628 GEN_XXSEL_ROW(0x10)
10629 GEN_XXSEL_ROW(0x11)
10630 GEN_XXSEL_ROW(0x12)
10631 GEN_XXSEL_ROW(0x13)
10632 GEN_XXSEL_ROW(0x14)
10633 GEN_XXSEL_ROW(0x15)
10634 GEN_XXSEL_ROW(0x16)
10635 GEN_XXSEL_ROW(0x17)
10636 GEN_XXSEL_ROW(0x18)
10637 GEN_XXSEL_ROW(0x19)
10638 GEN_XXSEL_ROW(0x1A)
10639 GEN_XXSEL_ROW(0x1B)
10640 GEN_XXSEL_ROW(0x1C)
10641 GEN_XXSEL_ROW(0x1D)
10642 GEN_XXSEL_ROW(0x1E)
10643 GEN_XXSEL_ROW(0x1F)
10644
10645 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10646
10647 #undef GEN_SPE
10648 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10649 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10650 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10651 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10652 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10653 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10654 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10655 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10656 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10657 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
10658 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
10659 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10660 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10661 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10662 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10663 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10664 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10665 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
10666 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10667 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10668 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10669 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10670 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10671 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10672 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10673 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10674 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10675 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10676 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10677 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10678 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
10679
10680 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10681 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10682 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10683 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10684 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10685 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10686 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10687 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10688 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10689 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10690 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10691 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10692 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10693 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10694
10695 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10696 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10697 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10698 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10699 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10700 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
10701 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10702 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10703 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10704 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10705 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10706 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10707 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10708 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10709
10710 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10711 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10712 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
10713 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10714 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10715 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10716 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10717 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
10718 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10719 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10720 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10721 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10722 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10723 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10724 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10725 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10726
10727 #undef GEN_SPEOP_LDST
10728 #define GEN_SPEOP_LDST(name, opc2, sh) \
10729 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
10730 GEN_SPEOP_LDST(evldd, 0x00, 3),
10731 GEN_SPEOP_LDST(evldw, 0x01, 3),
10732 GEN_SPEOP_LDST(evldh, 0x02, 3),
10733 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
10734 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
10735 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
10736 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
10737 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
10738 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
10739 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
10740 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
10741
10742 GEN_SPEOP_LDST(evstdd, 0x10, 3),
10743 GEN_SPEOP_LDST(evstdw, 0x11, 3),
10744 GEN_SPEOP_LDST(evstdh, 0x12, 3),
10745 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
10746 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
10747 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
10748 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
10749 };
10750
10751 #include "helper_regs.h"
10752 #include "translate_init.c"
10753
10754 /*****************************************************************************/
10755 /* Misc PowerPC helpers */
10756 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
10757 int flags)
10758 {
10759 #define RGPL 4
10760 #define RFPL 4
10761
10762 PowerPCCPU *cpu = POWERPC_CPU(cs);
10763 CPUPPCState *env = &cpu->env;
10764 int i;
10765
10766 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
10767 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
10768 env->nip, env->lr, env->ctr, cpu_read_xer(env));
10769 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
10770 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
10771 env->hflags, env->mmu_idx);
10772 #if !defined(NO_TIMER_DUMP)
10773 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
10774 #if !defined(CONFIG_USER_ONLY)
10775 " DECR %08" PRIu32
10776 #endif
10777 "\n",
10778 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
10779 #if !defined(CONFIG_USER_ONLY)
10780 , cpu_ppc_load_decr(env)
10781 #endif
10782 );
10783 #endif
10784 for (i = 0; i < 32; i++) {
10785 if ((i & (RGPL - 1)) == 0)
10786 cpu_fprintf(f, "GPR%02d", i);
10787 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
10788 if ((i & (RGPL - 1)) == (RGPL - 1))
10789 cpu_fprintf(f, "\n");
10790 }
10791 cpu_fprintf(f, "CR ");
10792 for (i = 0; i < 8; i++)
10793 cpu_fprintf(f, "%01x", env->crf[i]);
10794 cpu_fprintf(f, " [");
10795 for (i = 0; i < 8; i++) {
10796 char a = '-';
10797 if (env->crf[i] & 0x08)
10798 a = 'L';
10799 else if (env->crf[i] & 0x04)
10800 a = 'G';
10801 else if (env->crf[i] & 0x02)
10802 a = 'E';
10803 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
10804 }
10805 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
10806 env->reserve_addr);
10807 for (i = 0; i < 32; i++) {
10808 if ((i & (RFPL - 1)) == 0)
10809 cpu_fprintf(f, "FPR%02d", i);
10810 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
10811 if ((i & (RFPL - 1)) == (RFPL - 1))
10812 cpu_fprintf(f, "\n");
10813 }
10814 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
10815 #if !defined(CONFIG_USER_ONLY)
10816 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
10817 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
10818 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
10819 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
10820
10821 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
10822 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
10823 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
10824 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
10825
10826 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
10827 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
10828 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
10829 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
10830
10831 if (env->excp_model == POWERPC_EXCP_BOOKE) {
10832 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
10833 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
10834 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
10835 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
10836
10837 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
10838 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
10839 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
10840 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
10841
10842 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
10843 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
10844 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
10845 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
10846
10847 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
10848 " EPR " TARGET_FMT_lx "\n",
10849 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
10850 env->spr[SPR_BOOKE_EPR]);
10851
10852 /* FSL-specific */
10853 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
10854 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
10855 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
10856 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
10857
10858 /*
10859 * IVORs are left out as they are large and do not change often --
10860 * they can be read with "p $ivor0", "p $ivor1", etc.
10861 */
10862 }
10863
10864 #if defined(TARGET_PPC64)
10865 if (env->flags & POWERPC_FLAG_CFAR) {
10866 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
10867 }
10868 #endif
10869
10870 switch (env->mmu_model) {
10871 case POWERPC_MMU_32B:
10872 case POWERPC_MMU_601:
10873 case POWERPC_MMU_SOFT_6xx:
10874 case POWERPC_MMU_SOFT_74xx:
10875 #if defined(TARGET_PPC64)
10876 case POWERPC_MMU_64B:
10877 case POWERPC_MMU_2_06:
10878 case POWERPC_MMU_2_06a:
10879 case POWERPC_MMU_2_06d:
10880 #endif
10881 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
10882 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
10883 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
10884 break;
10885 case POWERPC_MMU_BOOKE206:
10886 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
10887 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
10888 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
10889 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
10890
10891 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
10892 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
10893 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
10894 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
10895
10896 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
10897 " TLB1CFG " TARGET_FMT_lx "\n",
10898 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
10899 env->spr[SPR_BOOKE_TLB1CFG]);
10900 break;
10901 default:
10902 break;
10903 }
10904 #endif
10905
10906 #undef RGPL
10907 #undef RFPL
10908 }
10909
10910 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
10911 fprintf_function cpu_fprintf, int flags)
10912 {
10913 #if defined(DO_PPC_STATISTICS)
10914 PowerPCCPU *cpu = POWERPC_CPU(cs);
10915 opc_handler_t **t1, **t2, **t3, *handler;
10916 int op1, op2, op3;
10917
10918 t1 = cpu->env.opcodes;
10919 for (op1 = 0; op1 < 64; op1++) {
10920 handler = t1[op1];
10921 if (is_indirect_opcode(handler)) {
10922 t2 = ind_table(handler);
10923 for (op2 = 0; op2 < 32; op2++) {
10924 handler = t2[op2];
10925 if (is_indirect_opcode(handler)) {
10926 t3 = ind_table(handler);
10927 for (op3 = 0; op3 < 32; op3++) {
10928 handler = t3[op3];
10929 if (handler->count == 0)
10930 continue;
10931 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
10932 "%016" PRIx64 " %" PRId64 "\n",
10933 op1, op2, op3, op1, (op3 << 5) | op2,
10934 handler->oname,
10935 handler->count, handler->count);
10936 }
10937 } else {
10938 if (handler->count == 0)
10939 continue;
10940 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
10941 "%016" PRIx64 " %" PRId64 "\n",
10942 op1, op2, op1, op2, handler->oname,
10943 handler->count, handler->count);
10944 }
10945 }
10946 } else {
10947 if (handler->count == 0)
10948 continue;
10949 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
10950 " %" PRId64 "\n",
10951 op1, op1, handler->oname,
10952 handler->count, handler->count);
10953 }
10954 }
10955 #endif
10956 }
10957
10958 /*****************************************************************************/
10959 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
10960 TranslationBlock *tb,
10961 bool search_pc)
10962 {
10963 CPUState *cs = CPU(cpu);
10964 CPUPPCState *env = &cpu->env;
10965 DisasContext ctx, *ctxp = &ctx;
10966 opc_handler_t **table, *handler;
10967 target_ulong pc_start;
10968 uint16_t *gen_opc_end;
10969 CPUBreakpoint *bp;
10970 int j, lj = -1;
10971 int num_insns;
10972 int max_insns;
10973
10974 pc_start = tb->pc;
10975 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
10976 ctx.nip = pc_start;
10977 ctx.tb = tb;
10978 ctx.exception = POWERPC_EXCP_NONE;
10979 ctx.spr_cb = env->spr_cb;
10980 ctx.mem_idx = env->mmu_idx;
10981 ctx.insns_flags = env->insns_flags;
10982 ctx.insns_flags2 = env->insns_flags2;
10983 ctx.access_type = -1;
10984 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
10985 #if defined(TARGET_PPC64)
10986 ctx.sf_mode = msr_is_64bit(env, env->msr);
10987 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
10988 #endif
10989 ctx.fpu_enabled = msr_fp;
10990 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
10991 ctx.spe_enabled = msr_spe;
10992 else
10993 ctx.spe_enabled = 0;
10994 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
10995 ctx.altivec_enabled = msr_vr;
10996 else
10997 ctx.altivec_enabled = 0;
10998 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
10999 ctx.vsx_enabled = msr_vsx;
11000 } else {
11001 ctx.vsx_enabled = 0;
11002 }
11003 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11004 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11005 else
11006 ctx.singlestep_enabled = 0;
11007 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11008 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11009 if (unlikely(cs->singlestep_enabled)) {
11010 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11011 }
11012 #if defined (DO_SINGLE_STEP) && 0
11013 /* Single step trace mode */
11014 msr_se = 1;
11015 #endif
11016 num_insns = 0;
11017 max_insns = tb->cflags & CF_COUNT_MASK;
11018 if (max_insns == 0)
11019 max_insns = CF_COUNT_MASK;
11020
11021 gen_tb_start();
11022 /* Set env in case of segfault during code fetch */
11023 while (ctx.exception == POWERPC_EXCP_NONE
11024 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
11025 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
11026 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
11027 if (bp->pc == ctx.nip) {
11028 gen_debug_exception(ctxp);
11029 break;
11030 }
11031 }
11032 }
11033 if (unlikely(search_pc)) {
11034 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11035 if (lj < j) {
11036 lj++;
11037 while (lj < j)
11038 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11039 }
11040 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
11041 tcg_ctx.gen_opc_instr_start[lj] = 1;
11042 tcg_ctx.gen_opc_icount[lj] = num_insns;
11043 }
11044 LOG_DISAS("----------------\n");
11045 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11046 ctx.nip, ctx.mem_idx, (int)msr_ir);
11047 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11048 gen_io_start();
11049 if (unlikely(ctx.le_mode)) {
11050 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11051 } else {
11052 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11053 }
11054 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11055 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11056 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11057 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
11058 tcg_gen_debug_insn_start(ctx.nip);
11059 }
11060 ctx.nip += 4;
11061 table = env->opcodes;
11062 num_insns++;
11063 handler = table[opc1(ctx.opcode)];
11064 if (is_indirect_opcode(handler)) {
11065 table = ind_table(handler);
11066 handler = table[opc2(ctx.opcode)];
11067 if (is_indirect_opcode(handler)) {
11068 table = ind_table(handler);
11069 handler = table[opc3(ctx.opcode)];
11070 }
11071 }
11072 /* Is opcode *REALLY* valid ? */
11073 if (unlikely(handler->handler == &gen_invalid)) {
11074 if (qemu_log_enabled()) {
11075 qemu_log("invalid/unsupported opcode: "
11076 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11077 opc1(ctx.opcode), opc2(ctx.opcode),
11078 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11079 }
11080 } else {
11081 uint32_t inval;
11082
11083 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11084 inval = handler->inval2;
11085 } else {
11086 inval = handler->inval1;
11087 }
11088
11089 if (unlikely((ctx.opcode & inval) != 0)) {
11090 if (qemu_log_enabled()) {
11091 qemu_log("invalid bits: %08x for opcode: "
11092 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11093 ctx.opcode & inval, opc1(ctx.opcode),
11094 opc2(ctx.opcode), opc3(ctx.opcode),
11095 ctx.opcode, ctx.nip - 4);
11096 }
11097 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11098 break;
11099 }
11100 }
11101 (*(handler->handler))(&ctx);
11102 #if defined(DO_PPC_STATISTICS)
11103 handler->count++;
11104 #endif
11105 /* Check trace mode exceptions */
11106 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11107 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11108 ctx.exception != POWERPC_SYSCALL &&
11109 ctx.exception != POWERPC_EXCP_TRAP &&
11110 ctx.exception != POWERPC_EXCP_BRANCH)) {
11111 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11112 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11113 (cs->singlestep_enabled) ||
11114 singlestep ||
11115 num_insns >= max_insns)) {
11116 /* if we reach a page boundary or are single stepping, stop
11117 * generation
11118 */
11119 break;
11120 }
11121 }
11122 if (tb->cflags & CF_LAST_IO)
11123 gen_io_end();
11124 if (ctx.exception == POWERPC_EXCP_NONE) {
11125 gen_goto_tb(&ctx, 0, ctx.nip);
11126 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11127 if (unlikely(cs->singlestep_enabled)) {
11128 gen_debug_exception(ctxp);
11129 }
11130 /* Generate the return instruction */
11131 tcg_gen_exit_tb(0);
11132 }
11133 gen_tb_end(tb, num_insns);
11134 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11135 if (unlikely(search_pc)) {
11136 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11137 lj++;
11138 while (lj <= j)
11139 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11140 } else {
11141 tb->size = ctx.nip - pc_start;
11142 tb->icount = num_insns;
11143 }
11144 #if defined(DEBUG_DISAS)
11145 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11146 int flags;
11147 flags = env->bfd_mach;
11148 flags |= ctx.le_mode << 16;
11149 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11150 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11151 qemu_log("\n");
11152 }
11153 #endif
11154 }
11155
11156 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11157 {
11158 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11159 }
11160
11161 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11162 {
11163 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11164 }
11165
11166 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11167 {
11168 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11169 }
AR7 emulation for QEMU