2 * RISC-V GDB Server Stub
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu-common.h"
21 #include "exec/gdbstub.h"
25 * The GDB CSR xml files list them in documentation order, not numerical order,
26 * and are missing entries for unnamed CSRs. So we need to map the gdb numbers
27 * to the hardware numbers.
30 static int csr_register_map
[] = {
273 int riscv_cpu_gdb_read_register(CPUState
*cs
, uint8_t *mem_buf
, int n
)
275 RISCVCPU
*cpu
= RISCV_CPU(cs
);
276 CPURISCVState
*env
= &cpu
->env
;
279 return gdb_get_regl(mem_buf
, env
->gpr
[n
]);
280 } else if (n
== 32) {
281 return gdb_get_regl(mem_buf
, env
->pc
);
286 int riscv_cpu_gdb_write_register(CPUState
*cs
, uint8_t *mem_buf
, int n
)
288 RISCVCPU
*cpu
= RISCV_CPU(cs
);
289 CPURISCVState
*env
= &cpu
->env
;
292 /* discard writes to x0 */
293 return sizeof(target_ulong
);
295 env
->gpr
[n
] = ldtul_p(mem_buf
);
296 return sizeof(target_ulong
);
297 } else if (n
== 32) {
298 env
->pc
= ldtul_p(mem_buf
);
299 return sizeof(target_ulong
);
304 static int riscv_gdb_get_fpu(CPURISCVState
*env
, uint8_t *mem_buf
, int n
)
307 return gdb_get_reg64(mem_buf
, env
->fpr
[n
]);
308 /* there is hole between ft11 and fflags in fpu.xml */
309 } else if (n
< 36 && n
> 32) {
310 target_ulong val
= 0;
313 * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
314 * register 33, so we recalculate the map index.
315 * This also works for CSR_FRM and CSR_FCSR.
317 result
= riscv_csrrw_debug(env
, n
- 33 + 8, &val
, 0, 0);
319 return gdb_get_regl(mem_buf
, val
);
325 static int riscv_gdb_set_fpu(CPURISCVState
*env
, uint8_t *mem_buf
, int n
)
328 env
->fpr
[n
] = ldq_p(mem_buf
); /* always 64-bit */
329 return sizeof(uint64_t);
330 /* there is hole between ft11 and fflags in fpu.xml */
331 } else if (n
< 36 && n
> 32) {
332 target_ulong val
= ldtul_p(mem_buf
);
335 * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
336 * register 33, so we recalculate the map index.
337 * This also works for CSR_FRM and CSR_FCSR.
339 result
= riscv_csrrw_debug(env
, n
- 33 + 8, NULL
, val
, -1);
341 return sizeof(target_ulong
);
347 static int riscv_gdb_get_csr(CPURISCVState
*env
, uint8_t *mem_buf
, int n
)
349 if (n
< ARRAY_SIZE(csr_register_map
)) {
350 target_ulong val
= 0;
353 result
= riscv_csrrw_debug(env
, csr_register_map
[n
], &val
, 0, 0);
355 return gdb_get_regl(mem_buf
, val
);
361 static int riscv_gdb_set_csr(CPURISCVState
*env
, uint8_t *mem_buf
, int n
)
363 if (n
< ARRAY_SIZE(csr_register_map
)) {
364 target_ulong val
= ldtul_p(mem_buf
);
367 result
= riscv_csrrw_debug(env
, csr_register_map
[n
], NULL
, val
, -1);
369 return sizeof(target_ulong
);
375 void riscv_cpu_register_gdb_regs_for_features(CPUState
*cs
)
377 RISCVCPU
*cpu
= RISCV_CPU(cs
);
378 CPURISCVState
*env
= &cpu
->env
;
379 #if defined(TARGET_RISCV32)
380 if (env
->misa
& RVF
) {
381 gdb_register_coprocessor(cs
, riscv_gdb_get_fpu
, riscv_gdb_set_fpu
,
382 36, "riscv-32bit-fpu.xml", 0);
385 gdb_register_coprocessor(cs
, riscv_gdb_get_csr
, riscv_gdb_set_csr
,
386 4096, "riscv-32bit-csr.xml", 0);
387 #elif defined(TARGET_RISCV64)
388 if (env
->misa
& RVF
) {
389 gdb_register_coprocessor(cs
, riscv_gdb_get_fpu
, riscv_gdb_set_fpu
,
390 36, "riscv-64bit-fpu.xml", 0);
393 gdb_register_coprocessor(cs
, riscv_gdb_get_csr
, riscv_gdb_set_csr
,
394 4096, "riscv-64bit-csr.xml", 0);