2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu-common.h"
23 #include "disas/disas.h"
25 #include "qemu/host-utils.h"
26 #include "exec/cpu_ldst.h"
28 #include "exec/helper-proto.h"
29 #include "exec/helper-gen.h"
31 #include "trace-tcg.h"
34 #define CPU_SINGLE_STEP 0x1
35 #define CPU_BRANCH_STEP 0x2
36 #define GDBSTUB_SINGLE_STEP 0x4
38 /* Include definitions for instructions classes and implementations flags */
39 //#define PPC_DEBUG_DISAS
40 //#define DO_PPC_STATISTICS
42 #ifdef PPC_DEBUG_DISAS
43 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
45 # define LOG_DISAS(...) do { } while (0)
47 /*****************************************************************************/
48 /* Code translation helpers */
50 /* global register indexes */
51 static TCGv_ptr cpu_env
;
52 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
53 + 10*4 + 22*5 /* SPE GPRh */
54 + 10*4 + 22*5 /* FPR */
55 + 2*(10*6 + 22*7) /* AVRh, AVRl */
56 + 10*5 + 22*6 /* VSR */
58 static TCGv cpu_gpr
[32];
59 static TCGv cpu_gprh
[32];
60 static TCGv_i64 cpu_fpr
[32];
61 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
62 static TCGv_i64 cpu_vsr
[32];
63 static TCGv_i32 cpu_crf
[8];
68 #if defined(TARGET_PPC64)
71 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
;
72 static TCGv cpu_reserve
;
73 static TCGv cpu_fpscr
;
74 static TCGv_i32 cpu_access_type
;
76 #include "exec/gen-icount.h"
78 void ppc_translate_init(void)
82 size_t cpu_reg_names_size
;
83 static int done_init
= 0;
88 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
91 cpu_reg_names_size
= sizeof(cpu_reg_names
);
93 for (i
= 0; i
< 8; i
++) {
94 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
95 cpu_crf
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
96 offsetof(CPUPPCState
, crf
[i
]), p
);
98 cpu_reg_names_size
-= 5;
101 for (i
= 0; i
< 32; i
++) {
102 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
103 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
104 offsetof(CPUPPCState
, gpr
[i
]), p
);
105 p
+= (i
< 10) ? 3 : 4;
106 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
107 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
108 cpu_gprh
[i
] = tcg_global_mem_new(TCG_AREG0
,
109 offsetof(CPUPPCState
, gprh
[i
]), p
);
110 p
+= (i
< 10) ? 4 : 5;
111 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
113 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
114 cpu_fpr
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
115 offsetof(CPUPPCState
, fpr
[i
]), p
);
116 p
+= (i
< 10) ? 4 : 5;
117 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
119 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
122 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
124 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
125 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
127 p
+= (i
< 10) ? 6 : 7;
128 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
130 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
133 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
135 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
136 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
138 p
+= (i
< 10) ? 6 : 7;
139 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
140 snprintf(p
, cpu_reg_names_size
, "vsr%d", i
);
141 cpu_vsr
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
142 offsetof(CPUPPCState
, vsr
[i
]), p
);
143 p
+= (i
< 10) ? 5 : 6;
144 cpu_reg_names_size
-= (i
< 10) ? 5 : 6;
147 cpu_nip
= tcg_global_mem_new(TCG_AREG0
,
148 offsetof(CPUPPCState
, nip
), "nip");
150 cpu_msr
= tcg_global_mem_new(TCG_AREG0
,
151 offsetof(CPUPPCState
, msr
), "msr");
153 cpu_ctr
= tcg_global_mem_new(TCG_AREG0
,
154 offsetof(CPUPPCState
, ctr
), "ctr");
156 cpu_lr
= tcg_global_mem_new(TCG_AREG0
,
157 offsetof(CPUPPCState
, lr
), "lr");
159 #if defined(TARGET_PPC64)
160 cpu_cfar
= tcg_global_mem_new(TCG_AREG0
,
161 offsetof(CPUPPCState
, cfar
), "cfar");
164 cpu_xer
= tcg_global_mem_new(TCG_AREG0
,
165 offsetof(CPUPPCState
, xer
), "xer");
166 cpu_so
= tcg_global_mem_new(TCG_AREG0
,
167 offsetof(CPUPPCState
, so
), "SO");
168 cpu_ov
= tcg_global_mem_new(TCG_AREG0
,
169 offsetof(CPUPPCState
, ov
), "OV");
170 cpu_ca
= tcg_global_mem_new(TCG_AREG0
,
171 offsetof(CPUPPCState
, ca
), "CA");
173 cpu_reserve
= tcg_global_mem_new(TCG_AREG0
,
174 offsetof(CPUPPCState
, reserve_addr
),
177 cpu_fpscr
= tcg_global_mem_new(TCG_AREG0
,
178 offsetof(CPUPPCState
, fpscr
), "fpscr");
180 cpu_access_type
= tcg_global_mem_new_i32(TCG_AREG0
,
181 offsetof(CPUPPCState
, access_type
), "access_type");
186 /* internal defines */
187 struct DisasContext
{
188 struct TranslationBlock
*tb
;
192 /* Routine used to access memory */
196 /* Translation flags */
198 TCGMemOp default_tcg_memop_mask
;
199 #if defined(TARGET_PPC64)
208 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
209 int singlestep_enabled
;
210 uint64_t insns_flags
;
211 uint64_t insns_flags2
;
214 /* Return true iff byteswap is needed in a scalar memop */
215 static inline bool need_byteswap(const DisasContext
*ctx
)
217 #if defined(TARGET_WORDS_BIGENDIAN)
220 return !ctx
->le_mode
;
224 /* True when active word size < size of target_long. */
226 # define NARROW_MODE(C) (!(C)->sf_mode)
228 # define NARROW_MODE(C) 0
231 struct opc_handler_t
{
232 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
234 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
236 /* instruction type */
238 /* extended instruction type */
241 void (*handler
)(DisasContext
*ctx
);
242 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
245 #if defined(DO_PPC_STATISTICS)
250 static inline void gen_reset_fpstatus(void)
252 gen_helper_reset_fpstatus(cpu_env
);
255 static inline void gen_compute_fprf(TCGv_i64 arg
)
257 gen_helper_compute_fprf(cpu_env
, arg
);
258 gen_helper_float_check_status(cpu_env
);
261 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
263 if (ctx
->access_type
!= access_type
) {
264 tcg_gen_movi_i32(cpu_access_type
, access_type
);
265 ctx
->access_type
= access_type
;
269 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
271 if (NARROW_MODE(ctx
)) {
274 tcg_gen_movi_tl(cpu_nip
, nip
);
277 void gen_update_current_nip(void *opaque
)
279 DisasContext
*ctx
= opaque
;
281 tcg_gen_movi_tl(cpu_nip
, ctx
->nip
);
284 static inline void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
287 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
288 gen_update_nip(ctx
, ctx
->nip
);
290 t0
= tcg_const_i32(excp
);
291 t1
= tcg_const_i32(error
);
292 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
293 tcg_temp_free_i32(t0
);
294 tcg_temp_free_i32(t1
);
295 ctx
->exception
= (excp
);
298 static inline void gen_exception(DisasContext
*ctx
, uint32_t excp
)
301 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
302 gen_update_nip(ctx
, ctx
->nip
);
304 t0
= tcg_const_i32(excp
);
305 gen_helper_raise_exception(cpu_env
, t0
);
306 tcg_temp_free_i32(t0
);
307 ctx
->exception
= (excp
);
310 static inline void gen_debug_exception(DisasContext
*ctx
)
314 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
315 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
316 gen_update_nip(ctx
, ctx
->nip
);
318 t0
= tcg_const_i32(EXCP_DEBUG
);
319 gen_helper_raise_exception(cpu_env
, t0
);
320 tcg_temp_free_i32(t0
);
323 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
325 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_INVAL
| error
);
328 /* Stop translation */
329 static inline void gen_stop_exception(DisasContext
*ctx
)
331 gen_update_nip(ctx
, ctx
->nip
);
332 ctx
->exception
= POWERPC_EXCP_STOP
;
335 #ifndef CONFIG_USER_ONLY
336 /* No need to update nip here, as execution flow will change */
337 static inline void gen_sync_exception(DisasContext
*ctx
)
339 ctx
->exception
= POWERPC_EXCP_SYNC
;
343 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
344 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
346 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
347 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
349 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
350 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
352 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
353 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
355 typedef struct opcode_t
{
356 unsigned char opc1
, opc2
, opc3
;
357 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
358 unsigned char pad
[5];
360 unsigned char pad
[1];
362 opc_handler_t handler
;
366 /*****************************************************************************/
367 /*** Instruction decoding ***/
368 #define EXTRACT_HELPER(name, shift, nb) \
369 static inline uint32_t name(uint32_t opcode) \
371 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
374 #define EXTRACT_SHELPER(name, shift, nb) \
375 static inline int32_t name(uint32_t opcode) \
377 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
380 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
381 static inline uint32_t name(uint32_t opcode) \
383 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
384 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
387 EXTRACT_HELPER(opc1
, 26, 6);
389 EXTRACT_HELPER(opc2
, 1, 5);
391 EXTRACT_HELPER(opc3
, 6, 5);
392 /* Update Cr0 flags */
393 EXTRACT_HELPER(Rc
, 0, 1);
394 /* Update Cr6 flags (Altivec) */
395 EXTRACT_HELPER(Rc21
, 10, 1);
397 EXTRACT_HELPER(rD
, 21, 5);
399 EXTRACT_HELPER(rS
, 21, 5);
401 EXTRACT_HELPER(rA
, 16, 5);
403 EXTRACT_HELPER(rB
, 11, 5);
405 EXTRACT_HELPER(rC
, 6, 5);
407 EXTRACT_HELPER(crfD
, 23, 3);
408 EXTRACT_HELPER(crfS
, 18, 3);
409 EXTRACT_HELPER(crbD
, 21, 5);
410 EXTRACT_HELPER(crbA
, 16, 5);
411 EXTRACT_HELPER(crbB
, 11, 5);
413 EXTRACT_HELPER(_SPR
, 11, 10);
414 static inline uint32_t SPR(uint32_t opcode
)
416 uint32_t sprn
= _SPR(opcode
);
418 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
420 /*** Get constants ***/
421 /* 16 bits signed immediate value */
422 EXTRACT_SHELPER(SIMM
, 0, 16);
423 /* 16 bits unsigned immediate value */
424 EXTRACT_HELPER(UIMM
, 0, 16);
425 /* 5 bits signed immediate value */
426 EXTRACT_HELPER(SIMM5
, 16, 5);
427 /* 5 bits signed immediate value */
428 EXTRACT_HELPER(UIMM5
, 16, 5);
430 EXTRACT_HELPER(NB
, 11, 5);
432 EXTRACT_HELPER(SH
, 11, 5);
433 /* Vector shift count */
434 EXTRACT_HELPER(VSH
, 6, 4);
436 EXTRACT_HELPER(MB
, 6, 5);
438 EXTRACT_HELPER(ME
, 1, 5);
440 EXTRACT_HELPER(TO
, 21, 5);
442 EXTRACT_HELPER(CRM
, 12, 8);
444 #ifndef CONFIG_USER_ONLY
445 EXTRACT_HELPER(SR
, 16, 4);
449 EXTRACT_HELPER(FPBF
, 23, 3);
450 EXTRACT_HELPER(FPIMM
, 12, 4);
451 EXTRACT_HELPER(FPL
, 25, 1);
452 EXTRACT_HELPER(FPFLM
, 17, 8);
453 EXTRACT_HELPER(FPW
, 16, 1);
455 /*** Jump target decoding ***/
456 /* Immediate address */
457 static inline target_ulong
LI(uint32_t opcode
)
459 return (opcode
>> 0) & 0x03FFFFFC;
462 static inline uint32_t BD(uint32_t opcode
)
464 return (opcode
>> 0) & 0xFFFC;
467 EXTRACT_HELPER(BO
, 21, 5);
468 EXTRACT_HELPER(BI
, 16, 5);
469 /* Absolute/relative address */
470 EXTRACT_HELPER(AA
, 1, 1);
472 EXTRACT_HELPER(LK
, 0, 1);
475 EXTRACT_HELPER(DCM
, 10, 6)
478 EXTRACT_HELPER(RMC
, 9, 2)
480 /* Create a mask between <start> and <end> bits */
481 static inline target_ulong
MASK(uint32_t start
, uint32_t end
)
485 #if defined(TARGET_PPC64)
486 if (likely(start
== 0)) {
487 ret
= UINT64_MAX
<< (63 - end
);
488 } else if (likely(end
== 63)) {
489 ret
= UINT64_MAX
>> start
;
492 if (likely(start
== 0)) {
493 ret
= UINT32_MAX
<< (31 - end
);
494 } else if (likely(end
== 31)) {
495 ret
= UINT32_MAX
>> start
;
499 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
500 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
501 if (unlikely(start
> end
))
508 EXTRACT_HELPER_SPLIT(xT
, 0, 1, 21, 5);
509 EXTRACT_HELPER_SPLIT(xS
, 0, 1, 21, 5);
510 EXTRACT_HELPER_SPLIT(xA
, 2, 1, 16, 5);
511 EXTRACT_HELPER_SPLIT(xB
, 1, 1, 11, 5);
512 EXTRACT_HELPER_SPLIT(xC
, 3, 1, 6, 5);
513 EXTRACT_HELPER(DM
, 8, 2);
514 EXTRACT_HELPER(UIM
, 16, 2);
515 EXTRACT_HELPER(SHW
, 8, 2);
516 EXTRACT_HELPER(SP
, 19, 2);
517 /*****************************************************************************/
518 /* PowerPC instructions table */
520 #if defined(DO_PPC_STATISTICS)
521 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
531 .handler = &gen_##name, \
532 .oname = stringify(name), \
534 .oname = stringify(name), \
536 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
547 .handler = &gen_##name, \
548 .oname = stringify(name), \
550 .oname = stringify(name), \
552 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
562 .handler = &gen_##name, \
568 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
578 .handler = &gen_##name, \
580 .oname = stringify(name), \
582 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
593 .handler = &gen_##name, \
595 .oname = stringify(name), \
597 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
607 .handler = &gen_##name, \
613 /* SPR load/store helpers */
614 static inline void gen_load_spr(TCGv t
, int reg
)
616 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
619 static inline void gen_store_spr(int reg
, TCGv t
)
621 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
624 /* Invalid instruction */
625 static void gen_invalid(DisasContext
*ctx
)
627 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
630 static opc_handler_t invalid_handler
= {
631 .inval1
= 0xFFFFFFFF,
632 .inval2
= 0xFFFFFFFF,
635 .handler
= gen_invalid
,
638 /*** Integer comparison ***/
640 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
642 TCGv t0
= tcg_temp_new();
643 TCGv_i32 t1
= tcg_temp_new_i32();
645 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
647 tcg_gen_setcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
), t0
, arg0
, arg1
);
648 tcg_gen_trunc_tl_i32(t1
, t0
);
649 tcg_gen_shli_i32(t1
, t1
, CRF_LT
);
650 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
652 tcg_gen_setcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
), t0
, arg0
, arg1
);
653 tcg_gen_trunc_tl_i32(t1
, t0
);
654 tcg_gen_shli_i32(t1
, t1
, CRF_GT
);
655 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
657 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, arg0
, arg1
);
658 tcg_gen_trunc_tl_i32(t1
, t0
);
659 tcg_gen_shli_i32(t1
, t1
, CRF_EQ
);
660 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
663 tcg_temp_free_i32(t1
);
666 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
668 TCGv t0
= tcg_const_tl(arg1
);
669 gen_op_cmp(arg0
, t0
, s
, crf
);
673 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
679 tcg_gen_ext32s_tl(t0
, arg0
);
680 tcg_gen_ext32s_tl(t1
, arg1
);
682 tcg_gen_ext32u_tl(t0
, arg0
);
683 tcg_gen_ext32u_tl(t1
, arg1
);
685 gen_op_cmp(t0
, t1
, s
, crf
);
690 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
692 TCGv t0
= tcg_const_tl(arg1
);
693 gen_op_cmp32(arg0
, t0
, s
, crf
);
697 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
699 if (NARROW_MODE(ctx
)) {
700 gen_op_cmpi32(reg
, 0, 1, 0);
702 gen_op_cmpi(reg
, 0, 1, 0);
707 static void gen_cmp(DisasContext
*ctx
)
709 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
710 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
711 1, crfD(ctx
->opcode
));
713 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
714 1, crfD(ctx
->opcode
));
719 static void gen_cmpi(DisasContext
*ctx
)
721 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
722 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
723 1, crfD(ctx
->opcode
));
725 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
726 1, crfD(ctx
->opcode
));
731 static void gen_cmpl(DisasContext
*ctx
)
733 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
734 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
735 0, crfD(ctx
->opcode
));
737 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
738 0, crfD(ctx
->opcode
));
743 static void gen_cmpli(DisasContext
*ctx
)
745 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
746 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
747 0, crfD(ctx
->opcode
));
749 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
750 0, crfD(ctx
->opcode
));
754 /* isel (PowerPC 2.03 specification) */
755 static void gen_isel(DisasContext
*ctx
)
758 uint32_t bi
= rC(ctx
->opcode
);
762 l1
= gen_new_label();
763 l2
= gen_new_label();
765 mask
= 0x08 >> (bi
& 0x03);
766 t0
= tcg_temp_new_i32();
767 tcg_gen_andi_i32(t0
, cpu_crf
[bi
>> 2], mask
);
768 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
769 if (rA(ctx
->opcode
) == 0)
770 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
772 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
775 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
777 tcg_temp_free_i32(t0
);
780 /* cmpb: PowerPC 2.05 specification */
781 static void gen_cmpb(DisasContext
*ctx
)
783 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
784 cpu_gpr
[rB(ctx
->opcode
)]);
787 /*** Integer arithmetic ***/
789 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
790 TCGv arg1
, TCGv arg2
, int sub
)
792 TCGv t0
= tcg_temp_new();
794 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
795 tcg_gen_xor_tl(t0
, arg1
, arg2
);
797 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
799 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
802 if (NARROW_MODE(ctx
)) {
803 tcg_gen_ext32s_tl(cpu_ov
, cpu_ov
);
805 tcg_gen_shri_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1);
806 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
809 /* Common add function */
810 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
811 TCGv arg2
, bool add_ca
, bool compute_ca
,
812 bool compute_ov
, bool compute_rc0
)
816 if (compute_ca
|| compute_ov
) {
821 if (NARROW_MODE(ctx
)) {
822 /* Caution: a non-obvious corner case of the spec is that we
823 must produce the *entire* 64-bit addition, but produce the
824 carry into bit 32. */
825 TCGv t1
= tcg_temp_new();
826 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
827 tcg_gen_add_tl(t0
, arg1
, arg2
);
829 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
831 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changed w/ carry */
833 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
834 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
836 TCGv zero
= tcg_const_tl(0);
838 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, cpu_ca
, zero
);
839 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, arg2
, zero
);
841 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, arg2
, zero
);
846 tcg_gen_add_tl(t0
, arg1
, arg2
);
848 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
853 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
855 if (unlikely(compute_rc0
)) {
856 gen_set_Rc0(ctx
, t0
);
859 if (!TCGV_EQUAL(t0
, ret
)) {
860 tcg_gen_mov_tl(ret
, t0
);
864 /* Add functions with two operands */
865 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
866 static void glue(gen_, name)(DisasContext *ctx) \
868 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
869 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
870 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
872 /* Add functions with one operand and one immediate */
873 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
874 add_ca, compute_ca, compute_ov) \
875 static void glue(gen_, name)(DisasContext *ctx) \
877 TCGv t0 = tcg_const_tl(const_val); \
878 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
879 cpu_gpr[rA(ctx->opcode)], t0, \
880 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
884 /* add add. addo addo. */
885 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
886 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
887 /* addc addc. addco addco. */
888 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
889 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
890 /* adde adde. addeo addeo. */
891 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
892 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
893 /* addme addme. addmeo addmeo. */
894 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
895 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
896 /* addze addze. addzeo addzeo.*/
897 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
898 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
900 static void gen_addi(DisasContext
*ctx
)
902 target_long simm
= SIMM(ctx
->opcode
);
904 if (rA(ctx
->opcode
) == 0) {
906 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
908 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
909 cpu_gpr
[rA(ctx
->opcode
)], simm
);
913 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
915 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
916 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
917 c
, 0, 1, 0, compute_rc0
);
921 static void gen_addic(DisasContext
*ctx
)
923 gen_op_addic(ctx
, 0);
926 static void gen_addic_(DisasContext
*ctx
)
928 gen_op_addic(ctx
, 1);
932 static void gen_addis(DisasContext
*ctx
)
934 target_long simm
= SIMM(ctx
->opcode
);
936 if (rA(ctx
->opcode
) == 0) {
938 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
940 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
941 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
945 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
946 TCGv arg2
, int sign
, int compute_ov
)
948 int l1
= gen_new_label();
949 int l2
= gen_new_label();
950 TCGv_i32 t0
= tcg_temp_local_new_i32();
951 TCGv_i32 t1
= tcg_temp_local_new_i32();
953 tcg_gen_trunc_tl_i32(t0
, arg1
);
954 tcg_gen_trunc_tl_i32(t1
, arg2
);
955 tcg_gen_brcondi_i32(TCG_COND_EQ
, t1
, 0, l1
);
957 int l3
= gen_new_label();
958 tcg_gen_brcondi_i32(TCG_COND_NE
, t1
, -1, l3
);
959 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
961 tcg_gen_div_i32(t0
, t0
, t1
);
963 tcg_gen_divu_i32(t0
, t0
, t1
);
966 tcg_gen_movi_tl(cpu_ov
, 0);
971 tcg_gen_sari_i32(t0
, t0
, 31);
973 tcg_gen_movi_i32(t0
, 0);
976 tcg_gen_movi_tl(cpu_ov
, 1);
977 tcg_gen_movi_tl(cpu_so
, 1);
980 tcg_gen_extu_i32_tl(ret
, t0
);
981 tcg_temp_free_i32(t0
);
982 tcg_temp_free_i32(t1
);
983 if (unlikely(Rc(ctx
->opcode
) != 0))
984 gen_set_Rc0(ctx
, ret
);
987 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
988 static void glue(gen_, name)(DisasContext *ctx) \
990 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
991 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
994 /* divwu divwu. divwuo divwuo. */
995 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
996 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
997 /* divw divw. divwo divwo. */
998 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
999 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1001 /* div[wd]eu[o][.] */
1002 #define GEN_DIVE(name, hlpr, compute_ov) \
1003 static void gen_##name(DisasContext *ctx) \
1005 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1006 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1007 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1008 tcg_temp_free_i32(t0); \
1009 if (unlikely(Rc(ctx->opcode) != 0)) { \
1010 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1014 GEN_DIVE(divweu
, divweu
, 0);
1015 GEN_DIVE(divweuo
, divweu
, 1);
1016 GEN_DIVE(divwe
, divwe
, 0);
1017 GEN_DIVE(divweo
, divwe
, 1);
1019 #if defined(TARGET_PPC64)
1020 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1021 TCGv arg2
, int sign
, int compute_ov
)
1023 int l1
= gen_new_label();
1024 int l2
= gen_new_label();
1026 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg2
, 0, l1
);
1028 int l3
= gen_new_label();
1029 tcg_gen_brcondi_i64(TCG_COND_NE
, arg2
, -1, l3
);
1030 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg1
, INT64_MIN
, l1
);
1032 tcg_gen_div_i64(ret
, arg1
, arg2
);
1034 tcg_gen_divu_i64(ret
, arg1
, arg2
);
1037 tcg_gen_movi_tl(cpu_ov
, 0);
1042 tcg_gen_sari_i64(ret
, arg1
, 63);
1044 tcg_gen_movi_i64(ret
, 0);
1047 tcg_gen_movi_tl(cpu_ov
, 1);
1048 tcg_gen_movi_tl(cpu_so
, 1);
1051 if (unlikely(Rc(ctx
->opcode
) != 0))
1052 gen_set_Rc0(ctx
, ret
);
1054 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1055 static void glue(gen_, name)(DisasContext *ctx) \
1057 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1058 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1059 sign, compute_ov); \
1061 /* divwu divwu. divwuo divwuo. */
1062 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1063 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1064 /* divw divw. divwo divwo. */
1065 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1066 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1068 GEN_DIVE(divdeu
, divdeu
, 0);
1069 GEN_DIVE(divdeuo
, divdeu
, 1);
1070 GEN_DIVE(divde
, divde
, 0);
1071 GEN_DIVE(divdeo
, divde
, 1);
1075 static void gen_mulhw(DisasContext
*ctx
)
1077 TCGv_i32 t0
= tcg_temp_new_i32();
1078 TCGv_i32 t1
= tcg_temp_new_i32();
1080 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1081 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1082 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1083 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1084 tcg_temp_free_i32(t0
);
1085 tcg_temp_free_i32(t1
);
1086 if (unlikely(Rc(ctx
->opcode
) != 0))
1087 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1090 /* mulhwu mulhwu. */
1091 static void gen_mulhwu(DisasContext
*ctx
)
1093 TCGv_i32 t0
= tcg_temp_new_i32();
1094 TCGv_i32 t1
= tcg_temp_new_i32();
1096 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1097 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1098 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1099 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1100 tcg_temp_free_i32(t0
);
1101 tcg_temp_free_i32(t1
);
1102 if (unlikely(Rc(ctx
->opcode
) != 0))
1103 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1107 static void gen_mullw(DisasContext
*ctx
)
1109 #if defined(TARGET_PPC64)
1111 t0
= tcg_temp_new_i64();
1112 t1
= tcg_temp_new_i64();
1113 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1114 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1115 tcg_gen_mul_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1119 tcg_gen_mul_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1120 cpu_gpr
[rB(ctx
->opcode
)]);
1122 if (unlikely(Rc(ctx
->opcode
) != 0))
1123 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1126 /* mullwo mullwo. */
1127 static void gen_mullwo(DisasContext
*ctx
)
1129 TCGv_i32 t0
= tcg_temp_new_i32();
1130 TCGv_i32 t1
= tcg_temp_new_i32();
1132 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1133 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1134 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1135 #if defined(TARGET_PPC64)
1136 tcg_gen_concat_i32_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1138 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1141 tcg_gen_sari_i32(t0
, t0
, 31);
1142 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1143 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1144 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1146 tcg_temp_free_i32(t0
);
1147 tcg_temp_free_i32(t1
);
1148 if (unlikely(Rc(ctx
->opcode
) != 0))
1149 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1153 static void gen_mulli(DisasContext
*ctx
)
1155 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1159 #if defined(TARGET_PPC64)
1161 static void gen_mulhd(DisasContext
*ctx
)
1163 TCGv lo
= tcg_temp_new();
1164 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1165 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1167 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1168 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1172 /* mulhdu mulhdu. */
1173 static void gen_mulhdu(DisasContext
*ctx
)
1175 TCGv lo
= tcg_temp_new();
1176 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1177 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1179 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1180 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1185 static void gen_mulld(DisasContext
*ctx
)
1187 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1188 cpu_gpr
[rB(ctx
->opcode
)]);
1189 if (unlikely(Rc(ctx
->opcode
) != 0))
1190 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1193 /* mulldo mulldo. */
1194 static void gen_mulldo(DisasContext
*ctx
)
1196 TCGv_i64 t0
= tcg_temp_new_i64();
1197 TCGv_i64 t1
= tcg_temp_new_i64();
1199 tcg_gen_muls2_i64(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)],
1200 cpu_gpr
[rB(ctx
->opcode
)]);
1201 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1203 tcg_gen_sari_i64(t0
, t0
, 63);
1204 tcg_gen_setcond_i64(TCG_COND_NE
, cpu_ov
, t0
, t1
);
1205 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1207 tcg_temp_free_i64(t0
);
1208 tcg_temp_free_i64(t1
);
1210 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1211 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1216 /* Common subf function */
1217 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1218 TCGv arg2
, bool add_ca
, bool compute_ca
,
1219 bool compute_ov
, bool compute_rc0
)
1223 if (compute_ca
|| compute_ov
) {
1224 t0
= tcg_temp_new();
1228 /* dest = ~arg1 + arg2 [+ ca]. */
1229 if (NARROW_MODE(ctx
)) {
1230 /* Caution: a non-obvious corner case of the spec is that we
1231 must produce the *entire* 64-bit addition, but produce the
1232 carry into bit 32. */
1233 TCGv inv1
= tcg_temp_new();
1234 TCGv t1
= tcg_temp_new();
1235 tcg_gen_not_tl(inv1
, arg1
);
1237 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
1239 tcg_gen_addi_tl(t0
, arg2
, 1);
1241 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
1242 tcg_gen_add_tl(t0
, t0
, inv1
);
1243 tcg_temp_free(inv1
);
1244 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
1246 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
1247 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
1248 } else if (add_ca
) {
1249 TCGv zero
, inv1
= tcg_temp_new();
1250 tcg_gen_not_tl(inv1
, arg1
);
1251 zero
= tcg_const_tl(0);
1252 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1253 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
1254 tcg_temp_free(zero
);
1255 tcg_temp_free(inv1
);
1257 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1258 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1260 } else if (add_ca
) {
1261 /* Since we're ignoring carry-out, we can simplify the
1262 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1263 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1264 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1265 tcg_gen_subi_tl(t0
, t0
, 1);
1267 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1271 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1273 if (unlikely(compute_rc0
)) {
1274 gen_set_Rc0(ctx
, t0
);
1277 if (!TCGV_EQUAL(t0
, ret
)) {
1278 tcg_gen_mov_tl(ret
, t0
);
1282 /* Sub functions with Two operands functions */
1283 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1284 static void glue(gen_, name)(DisasContext *ctx) \
1286 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1287 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1288 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1290 /* Sub functions with one operand and one immediate */
1291 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1292 add_ca, compute_ca, compute_ov) \
1293 static void glue(gen_, name)(DisasContext *ctx) \
1295 TCGv t0 = tcg_const_tl(const_val); \
1296 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1297 cpu_gpr[rA(ctx->opcode)], t0, \
1298 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1299 tcg_temp_free(t0); \
1301 /* subf subf. subfo subfo. */
1302 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1303 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1304 /* subfc subfc. subfco subfco. */
1305 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1306 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1307 /* subfe subfe. subfeo subfo. */
1308 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1309 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1310 /* subfme subfme. subfmeo subfmeo. */
1311 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1312 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1313 /* subfze subfze. subfzeo subfzeo.*/
1314 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1315 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1318 static void gen_subfic(DisasContext
*ctx
)
1320 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1321 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1326 /* neg neg. nego nego. */
1327 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1329 TCGv zero
= tcg_const_tl(0);
1330 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1331 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1332 tcg_temp_free(zero
);
1335 static void gen_neg(DisasContext
*ctx
)
1337 gen_op_arith_neg(ctx
, 0);
1340 static void gen_nego(DisasContext
*ctx
)
1342 gen_op_arith_neg(ctx
, 1);
1345 /*** Integer logical ***/
1346 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1347 static void glue(gen_, name)(DisasContext *ctx) \
1349 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1350 cpu_gpr[rB(ctx->opcode)]); \
1351 if (unlikely(Rc(ctx->opcode) != 0)) \
1352 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1355 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1356 static void glue(gen_, name)(DisasContext *ctx) \
1358 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1359 if (unlikely(Rc(ctx->opcode) != 0)) \
1360 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1364 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1366 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1369 static void gen_andi_(DisasContext
*ctx
)
1371 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1372 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1376 static void gen_andis_(DisasContext
*ctx
)
1378 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1379 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1383 static void gen_cntlzw(DisasContext
*ctx
)
1385 gen_helper_cntlzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1386 if (unlikely(Rc(ctx
->opcode
) != 0))
1387 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1390 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1391 /* extsb & extsb. */
1392 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1393 /* extsh & extsh. */
1394 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1396 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1398 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1401 static void gen_or(DisasContext
*ctx
)
1405 rs
= rS(ctx
->opcode
);
1406 ra
= rA(ctx
->opcode
);
1407 rb
= rB(ctx
->opcode
);
1408 /* Optimisation for mr. ri case */
1409 if (rs
!= ra
|| rs
!= rb
) {
1411 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1413 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1414 if (unlikely(Rc(ctx
->opcode
) != 0))
1415 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1416 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1417 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1418 #if defined(TARGET_PPC64)
1424 /* Set process priority to low */
1428 /* Set process priority to medium-low */
1432 /* Set process priority to normal */
1435 #if !defined(CONFIG_USER_ONLY)
1438 /* Set process priority to very low */
1444 /* Set process priority to medium-hight */
1450 /* Set process priority to high */
1456 /* Set process priority to very high */
1466 TCGv t0
= tcg_temp_new();
1467 gen_load_spr(t0
, SPR_PPR
);
1468 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1469 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1470 gen_store_spr(SPR_PPR
, t0
);
1477 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1480 static void gen_xor(DisasContext
*ctx
)
1482 /* Optimisation for "set to zero" case */
1483 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1484 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1486 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1487 if (unlikely(Rc(ctx
->opcode
) != 0))
1488 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1492 static void gen_ori(DisasContext
*ctx
)
1494 target_ulong uimm
= UIMM(ctx
->opcode
);
1496 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1498 /* XXX: should handle special NOPs for POWER series */
1501 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1505 static void gen_oris(DisasContext
*ctx
)
1507 target_ulong uimm
= UIMM(ctx
->opcode
);
1509 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1513 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1517 static void gen_xori(DisasContext
*ctx
)
1519 target_ulong uimm
= UIMM(ctx
->opcode
);
1521 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1525 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1529 static void gen_xoris(DisasContext
*ctx
)
1531 target_ulong uimm
= UIMM(ctx
->opcode
);
1533 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1537 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1540 /* popcntb : PowerPC 2.03 specification */
1541 static void gen_popcntb(DisasContext
*ctx
)
1543 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1546 static void gen_popcntw(DisasContext
*ctx
)
1548 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1551 #if defined(TARGET_PPC64)
1552 /* popcntd: PowerPC 2.06 specification */
1553 static void gen_popcntd(DisasContext
*ctx
)
1555 gen_helper_popcntd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1559 /* prtyw: PowerPC 2.05 specification */
1560 static void gen_prtyw(DisasContext
*ctx
)
1562 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1563 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1564 TCGv t0
= tcg_temp_new();
1565 tcg_gen_shri_tl(t0
, rs
, 16);
1566 tcg_gen_xor_tl(ra
, rs
, t0
);
1567 tcg_gen_shri_tl(t0
, ra
, 8);
1568 tcg_gen_xor_tl(ra
, ra
, t0
);
1569 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
1573 #if defined(TARGET_PPC64)
1574 /* prtyd: PowerPC 2.05 specification */
1575 static void gen_prtyd(DisasContext
*ctx
)
1577 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1578 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1579 TCGv t0
= tcg_temp_new();
1580 tcg_gen_shri_tl(t0
, rs
, 32);
1581 tcg_gen_xor_tl(ra
, rs
, t0
);
1582 tcg_gen_shri_tl(t0
, ra
, 16);
1583 tcg_gen_xor_tl(ra
, ra
, t0
);
1584 tcg_gen_shri_tl(t0
, ra
, 8);
1585 tcg_gen_xor_tl(ra
, ra
, t0
);
1586 tcg_gen_andi_tl(ra
, ra
, 1);
1591 #if defined(TARGET_PPC64)
1593 static void gen_bpermd(DisasContext
*ctx
)
1595 gen_helper_bpermd(cpu_gpr
[rA(ctx
->opcode
)],
1596 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1600 #if defined(TARGET_PPC64)
1601 /* extsw & extsw. */
1602 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1605 static void gen_cntlzd(DisasContext
*ctx
)
1607 gen_helper_cntlzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1608 if (unlikely(Rc(ctx
->opcode
) != 0))
1609 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1613 /*** Integer rotate ***/
1615 /* rlwimi & rlwimi. */
1616 static void gen_rlwimi(DisasContext
*ctx
)
1618 uint32_t mb
, me
, sh
;
1620 mb
= MB(ctx
->opcode
);
1621 me
= ME(ctx
->opcode
);
1622 sh
= SH(ctx
->opcode
);
1623 if (likely(sh
== (31-me
) && mb
<= me
)) {
1624 tcg_gen_deposit_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1625 cpu_gpr
[rS(ctx
->opcode
)], sh
, me
- mb
+ 1);
1629 TCGv t0
= tcg_temp_new();
1630 #if defined(TARGET_PPC64)
1631 tcg_gen_deposit_i64(t0
, cpu_gpr
[rS(ctx
->opcode
)],
1632 cpu_gpr
[rS(ctx
->opcode
)], 32, 32);
1633 tcg_gen_rotli_i64(t0
, t0
, sh
);
1635 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1637 #if defined(TARGET_PPC64)
1641 mask
= MASK(mb
, me
);
1642 t1
= tcg_temp_new();
1643 tcg_gen_andi_tl(t0
, t0
, mask
);
1644 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1645 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1649 if (unlikely(Rc(ctx
->opcode
) != 0))
1650 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1653 /* rlwinm & rlwinm. */
1654 static void gen_rlwinm(DisasContext
*ctx
)
1656 uint32_t mb
, me
, sh
;
1658 sh
= SH(ctx
->opcode
);
1659 mb
= MB(ctx
->opcode
);
1660 me
= ME(ctx
->opcode
);
1662 if (likely(mb
== 0 && me
== (31 - sh
))) {
1663 if (likely(sh
== 0)) {
1664 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1666 TCGv t0
= tcg_temp_new();
1667 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1668 tcg_gen_shli_tl(t0
, t0
, sh
);
1669 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1672 } else if (likely(sh
!= 0 && me
== 31 && sh
== (32 - mb
))) {
1673 TCGv t0
= tcg_temp_new();
1674 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1675 tcg_gen_shri_tl(t0
, t0
, mb
);
1676 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1678 } else if (likely(mb
== 0 && me
== 31)) {
1679 TCGv_i32 t0
= tcg_temp_new_i32();
1680 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1681 tcg_gen_rotli_i32(t0
, t0
, sh
);
1682 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1683 tcg_temp_free_i32(t0
);
1685 TCGv t0
= tcg_temp_new();
1686 #if defined(TARGET_PPC64)
1687 tcg_gen_deposit_i64(t0
, cpu_gpr
[rS(ctx
->opcode
)],
1688 cpu_gpr
[rS(ctx
->opcode
)], 32, 32);
1689 tcg_gen_rotli_i64(t0
, t0
, sh
);
1691 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1693 #if defined(TARGET_PPC64)
1697 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1700 if (unlikely(Rc(ctx
->opcode
) != 0))
1701 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1704 /* rlwnm & rlwnm. */
1705 static void gen_rlwnm(DisasContext
*ctx
)
1708 mb
= MB(ctx
->opcode
);
1709 me
= ME(ctx
->opcode
);
1711 if (likely(mb
== 0 && me
== 31)) {
1713 t0
= tcg_temp_new_i32();
1714 t1
= tcg_temp_new_i32();
1715 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
1716 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1717 tcg_gen_andi_i32(t0
, t0
, 0x1f);
1718 tcg_gen_rotl_i32(t1
, t1
, t0
);
1719 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
1720 tcg_temp_free_i32(t0
);
1721 tcg_temp_free_i32(t1
);
1724 #if defined(TARGET_PPC64)
1728 t0
= tcg_temp_new();
1729 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1730 #if defined(TARGET_PPC64)
1731 t1
= tcg_temp_new_i64();
1732 tcg_gen_deposit_i64(t1
, cpu_gpr
[rS(ctx
->opcode
)],
1733 cpu_gpr
[rS(ctx
->opcode
)], 32, 32);
1734 tcg_gen_rotl_i64(t0
, t1
, t0
);
1735 tcg_temp_free_i64(t1
);
1737 tcg_gen_rotl_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1739 if (unlikely(mb
!= 0 || me
!= 31)) {
1740 #if defined(TARGET_PPC64)
1744 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1746 tcg_gen_andi_tl(t0
, t0
, MASK(32, 63));
1747 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1751 if (unlikely(Rc(ctx
->opcode
) != 0))
1752 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1755 #if defined(TARGET_PPC64)
1756 #define GEN_PPC64_R2(name, opc1, opc2) \
1757 static void glue(gen_, name##0)(DisasContext *ctx) \
1759 gen_##name(ctx, 0); \
1762 static void glue(gen_, name##1)(DisasContext *ctx) \
1764 gen_##name(ctx, 1); \
1766 #define GEN_PPC64_R4(name, opc1, opc2) \
1767 static void glue(gen_, name##0)(DisasContext *ctx) \
1769 gen_##name(ctx, 0, 0); \
1772 static void glue(gen_, name##1)(DisasContext *ctx) \
1774 gen_##name(ctx, 0, 1); \
1777 static void glue(gen_, name##2)(DisasContext *ctx) \
1779 gen_##name(ctx, 1, 0); \
1782 static void glue(gen_, name##3)(DisasContext *ctx) \
1784 gen_##name(ctx, 1, 1); \
1787 static inline void gen_rldinm(DisasContext
*ctx
, uint32_t mb
, uint32_t me
,
1790 if (likely(sh
!= 0 && mb
== 0 && me
== (63 - sh
))) {
1791 tcg_gen_shli_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
1792 } else if (likely(sh
!= 0 && me
== 63 && sh
== (64 - mb
))) {
1793 tcg_gen_shri_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], mb
);
1795 TCGv t0
= tcg_temp_new();
1796 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1797 if (likely(mb
== 0 && me
== 63)) {
1798 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1800 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1804 if (unlikely(Rc(ctx
->opcode
) != 0))
1805 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1807 /* rldicl - rldicl. */
1808 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
1812 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1813 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1814 gen_rldinm(ctx
, mb
, 63, sh
);
1816 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1817 /* rldicr - rldicr. */
1818 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
1822 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1823 me
= MB(ctx
->opcode
) | (men
<< 5);
1824 gen_rldinm(ctx
, 0, me
, sh
);
1826 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1827 /* rldic - rldic. */
1828 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
1832 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1833 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1834 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1836 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1838 static inline void gen_rldnm(DisasContext
*ctx
, uint32_t mb
, uint32_t me
)
1842 t0
= tcg_temp_new();
1843 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1844 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1845 if (unlikely(mb
!= 0 || me
!= 63)) {
1846 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1848 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1851 if (unlikely(Rc(ctx
->opcode
) != 0))
1852 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1855 /* rldcl - rldcl. */
1856 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
1860 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1861 gen_rldnm(ctx
, mb
, 63);
1863 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1864 /* rldcr - rldcr. */
1865 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
1869 me
= MB(ctx
->opcode
) | (men
<< 5);
1870 gen_rldnm(ctx
, 0, me
);
1872 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1873 /* rldimi - rldimi. */
1874 static inline void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
1876 uint32_t sh
, mb
, me
;
1878 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1879 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1881 if (unlikely(sh
== 0 && mb
== 0)) {
1882 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1887 t0
= tcg_temp_new();
1888 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1889 t1
= tcg_temp_new();
1890 mask
= MASK(mb
, me
);
1891 tcg_gen_andi_tl(t0
, t0
, mask
);
1892 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1893 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1897 if (unlikely(Rc(ctx
->opcode
) != 0))
1898 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1900 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1903 /*** Integer shift ***/
1906 static void gen_slw(DisasContext
*ctx
)
1910 t0
= tcg_temp_new();
1911 /* AND rS with a mask that is 0 when rB >= 0x20 */
1912 #if defined(TARGET_PPC64)
1913 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1914 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1916 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1917 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1919 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1920 t1
= tcg_temp_new();
1921 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1922 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1925 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1926 if (unlikely(Rc(ctx
->opcode
) != 0))
1927 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1931 static void gen_sraw(DisasContext
*ctx
)
1933 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
1934 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1935 if (unlikely(Rc(ctx
->opcode
) != 0))
1936 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1939 /* srawi & srawi. */
1940 static void gen_srawi(DisasContext
*ctx
)
1942 int sh
= SH(ctx
->opcode
);
1943 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
1944 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
1946 tcg_gen_ext32s_tl(dst
, src
);
1947 tcg_gen_movi_tl(cpu_ca
, 0);
1950 tcg_gen_ext32s_tl(dst
, src
);
1951 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
1952 t0
= tcg_temp_new();
1953 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
1954 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
1956 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
1957 tcg_gen_sari_tl(dst
, dst
, sh
);
1959 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1960 gen_set_Rc0(ctx
, dst
);
1965 static void gen_srw(DisasContext
*ctx
)
1969 t0
= tcg_temp_new();
1970 /* AND rS with a mask that is 0 when rB >= 0x20 */
1971 #if defined(TARGET_PPC64)
1972 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1973 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1975 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1976 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1978 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1979 tcg_gen_ext32u_tl(t0
, t0
);
1980 t1
= tcg_temp_new();
1981 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1982 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1985 if (unlikely(Rc(ctx
->opcode
) != 0))
1986 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1989 #if defined(TARGET_PPC64)
1991 static void gen_sld(DisasContext
*ctx
)
1995 t0
= tcg_temp_new();
1996 /* AND rS with a mask that is 0 when rB >= 0x40 */
1997 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
1998 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1999 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2000 t1
= tcg_temp_new();
2001 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2002 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2005 if (unlikely(Rc(ctx
->opcode
) != 0))
2006 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2010 static void gen_srad(DisasContext
*ctx
)
2012 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2013 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2014 if (unlikely(Rc(ctx
->opcode
) != 0))
2015 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2017 /* sradi & sradi. */
2018 static inline void gen_sradi(DisasContext
*ctx
, int n
)
2020 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2021 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2022 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2024 tcg_gen_mov_tl(dst
, src
);
2025 tcg_gen_movi_tl(cpu_ca
, 0);
2028 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
2029 t0
= tcg_temp_new();
2030 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
2031 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2033 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2034 tcg_gen_sari_tl(dst
, src
, sh
);
2036 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2037 gen_set_Rc0(ctx
, dst
);
2041 static void gen_sradi0(DisasContext
*ctx
)
2046 static void gen_sradi1(DisasContext
*ctx
)
2052 static void gen_srd(DisasContext
*ctx
)
2056 t0
= tcg_temp_new();
2057 /* AND rS with a mask that is 0 when rB >= 0x40 */
2058 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2059 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2060 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2061 t1
= tcg_temp_new();
2062 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2063 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2066 if (unlikely(Rc(ctx
->opcode
) != 0))
2067 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2071 #if defined(TARGET_PPC64)
2072 static void gen_set_cr1_from_fpscr(DisasContext
*ctx
)
2074 TCGv_i32 tmp
= tcg_temp_new_i32();
2075 tcg_gen_trunc_tl_i32(tmp
, cpu_fpscr
);
2076 tcg_gen_shri_i32(cpu_crf
[1], tmp
, 28);
2077 tcg_temp_free_i32(tmp
);
2080 static void gen_set_cr1_from_fpscr(DisasContext
*ctx
)
2082 tcg_gen_shri_tl(cpu_crf
[1], cpu_fpscr
, 28);
2086 /*** Floating-Point arithmetic ***/
2087 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2088 static void gen_f##name(DisasContext *ctx) \
2090 if (unlikely(!ctx->fpu_enabled)) { \
2091 gen_exception(ctx, POWERPC_EXCP_FPU); \
2094 /* NIP cannot be restored if the memory exception comes from an helper */ \
2095 gen_update_nip(ctx, ctx->nip - 4); \
2096 gen_reset_fpstatus(); \
2097 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2098 cpu_fpr[rA(ctx->opcode)], \
2099 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2101 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2102 cpu_fpr[rD(ctx->opcode)]); \
2105 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2107 if (unlikely(Rc(ctx->opcode) != 0)) { \
2108 gen_set_cr1_from_fpscr(ctx); \
2112 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2113 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2114 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2116 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2117 static void gen_f##name(DisasContext *ctx) \
2119 if (unlikely(!ctx->fpu_enabled)) { \
2120 gen_exception(ctx, POWERPC_EXCP_FPU); \
2123 /* NIP cannot be restored if the memory exception comes from an helper */ \
2124 gen_update_nip(ctx, ctx->nip - 4); \
2125 gen_reset_fpstatus(); \
2126 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2127 cpu_fpr[rA(ctx->opcode)], \
2128 cpu_fpr[rB(ctx->opcode)]); \
2130 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2131 cpu_fpr[rD(ctx->opcode)]); \
2134 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2136 if (unlikely(Rc(ctx->opcode) != 0)) { \
2137 gen_set_cr1_from_fpscr(ctx); \
2140 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2141 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2142 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2144 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2145 static void gen_f##name(DisasContext *ctx) \
2147 if (unlikely(!ctx->fpu_enabled)) { \
2148 gen_exception(ctx, POWERPC_EXCP_FPU); \
2151 /* NIP cannot be restored if the memory exception comes from an helper */ \
2152 gen_update_nip(ctx, ctx->nip - 4); \
2153 gen_reset_fpstatus(); \
2154 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2155 cpu_fpr[rA(ctx->opcode)], \
2156 cpu_fpr[rC(ctx->opcode)]); \
2158 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2159 cpu_fpr[rD(ctx->opcode)]); \
2162 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2164 if (unlikely(Rc(ctx->opcode) != 0)) { \
2165 gen_set_cr1_from_fpscr(ctx); \
2168 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2169 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2170 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2172 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2173 static void gen_f##name(DisasContext *ctx) \
2175 if (unlikely(!ctx->fpu_enabled)) { \
2176 gen_exception(ctx, POWERPC_EXCP_FPU); \
2179 /* NIP cannot be restored if the memory exception comes from an helper */ \
2180 gen_update_nip(ctx, ctx->nip - 4); \
2181 gen_reset_fpstatus(); \
2182 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2183 cpu_fpr[rB(ctx->opcode)]); \
2185 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2187 if (unlikely(Rc(ctx->opcode) != 0)) { \
2188 gen_set_cr1_from_fpscr(ctx); \
2192 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2193 static void gen_f##name(DisasContext *ctx) \
2195 if (unlikely(!ctx->fpu_enabled)) { \
2196 gen_exception(ctx, POWERPC_EXCP_FPU); \
2199 /* NIP cannot be restored if the memory exception comes from an helper */ \
2200 gen_update_nip(ctx, ctx->nip - 4); \
2201 gen_reset_fpstatus(); \
2202 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2203 cpu_fpr[rB(ctx->opcode)]); \
2205 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2207 if (unlikely(Rc(ctx->opcode) != 0)) { \
2208 gen_set_cr1_from_fpscr(ctx); \
2213 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
2215 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
2217 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
2220 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
2223 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
2226 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
2229 static void gen_frsqrtes(DisasContext
*ctx
)
2231 if (unlikely(!ctx
->fpu_enabled
)) {
2232 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2235 /* NIP cannot be restored if the memory exception comes from an helper */
2236 gen_update_nip(ctx
, ctx
->nip
- 4);
2237 gen_reset_fpstatus();
2238 gen_helper_frsqrte(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2239 cpu_fpr
[rB(ctx
->opcode
)]);
2240 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2241 cpu_fpr
[rD(ctx
->opcode
)]);
2242 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)]);
2243 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2244 gen_set_cr1_from_fpscr(ctx
);
2249 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
2251 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
2255 static void gen_fsqrt(DisasContext
*ctx
)
2257 if (unlikely(!ctx
->fpu_enabled
)) {
2258 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2261 /* NIP cannot be restored if the memory exception comes from an helper */
2262 gen_update_nip(ctx
, ctx
->nip
- 4);
2263 gen_reset_fpstatus();
2264 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2265 cpu_fpr
[rB(ctx
->opcode
)]);
2266 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)]);
2267 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2268 gen_set_cr1_from_fpscr(ctx
);
2272 static void gen_fsqrts(DisasContext
*ctx
)
2274 if (unlikely(!ctx
->fpu_enabled
)) {
2275 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2278 /* NIP cannot be restored if the memory exception comes from an helper */
2279 gen_update_nip(ctx
, ctx
->nip
- 4);
2280 gen_reset_fpstatus();
2281 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2282 cpu_fpr
[rB(ctx
->opcode
)]);
2283 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2284 cpu_fpr
[rD(ctx
->opcode
)]);
2285 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)]);
2286 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2287 gen_set_cr1_from_fpscr(ctx
);
2291 /*** Floating-Point multiply-and-add ***/
2292 /* fmadd - fmadds */
2293 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
2294 /* fmsub - fmsubs */
2295 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
2296 /* fnmadd - fnmadds */
2297 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
2298 /* fnmsub - fnmsubs */
2299 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
2301 /*** Floating-Point round & convert ***/
2303 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
2305 GEN_FLOAT_B(ctiwu
, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206
);
2307 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
2309 GEN_FLOAT_B(ctiwuz
, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206
);
2311 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
2313 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64
);
2315 GEN_FLOAT_B(cfids
, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206
);
2317 GEN_FLOAT_B(cfidu
, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206
);
2319 GEN_FLOAT_B(cfidus
, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206
);
2321 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC2_FP_CVT_S64
);
2323 GEN_FLOAT_B(ctidu
, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206
);
2325 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC2_FP_CVT_S64
);
2327 GEN_FLOAT_B(ctiduz
, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206
);
2330 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
2332 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
2334 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
2336 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
2338 static void gen_ftdiv(DisasContext
*ctx
)
2340 if (unlikely(!ctx
->fpu_enabled
)) {
2341 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2344 gen_helper_ftdiv(cpu_crf
[crfD(ctx
->opcode
)], cpu_fpr
[rA(ctx
->opcode
)],
2345 cpu_fpr
[rB(ctx
->opcode
)]);
2348 static void gen_ftsqrt(DisasContext
*ctx
)
2350 if (unlikely(!ctx
->fpu_enabled
)) {
2351 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2354 gen_helper_ftsqrt(cpu_crf
[crfD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2359 /*** Floating-Point compare ***/
2362 static void gen_fcmpo(DisasContext
*ctx
)
2365 if (unlikely(!ctx
->fpu_enabled
)) {
2366 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2369 /* NIP cannot be restored if the memory exception comes from an helper */
2370 gen_update_nip(ctx
, ctx
->nip
- 4);
2371 gen_reset_fpstatus();
2372 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2373 gen_helper_fcmpo(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2374 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2375 tcg_temp_free_i32(crf
);
2376 gen_helper_float_check_status(cpu_env
);
2380 static void gen_fcmpu(DisasContext
*ctx
)
2383 if (unlikely(!ctx
->fpu_enabled
)) {
2384 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2387 /* NIP cannot be restored if the memory exception comes from an helper */
2388 gen_update_nip(ctx
, ctx
->nip
- 4);
2389 gen_reset_fpstatus();
2390 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2391 gen_helper_fcmpu(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2392 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2393 tcg_temp_free_i32(crf
);
2394 gen_helper_float_check_status(cpu_env
);
2397 /*** Floating-point move ***/
2399 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2400 static void gen_fabs(DisasContext
*ctx
)
2402 if (unlikely(!ctx
->fpu_enabled
)) {
2403 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2406 tcg_gen_andi_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2408 if (unlikely(Rc(ctx
->opcode
))) {
2409 gen_set_cr1_from_fpscr(ctx
);
2414 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2415 static void gen_fmr(DisasContext
*ctx
)
2417 if (unlikely(!ctx
->fpu_enabled
)) {
2418 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2421 tcg_gen_mov_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2422 if (unlikely(Rc(ctx
->opcode
))) {
2423 gen_set_cr1_from_fpscr(ctx
);
2428 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2429 static void gen_fnabs(DisasContext
*ctx
)
2431 if (unlikely(!ctx
->fpu_enabled
)) {
2432 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2435 tcg_gen_ori_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2437 if (unlikely(Rc(ctx
->opcode
))) {
2438 gen_set_cr1_from_fpscr(ctx
);
2443 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2444 static void gen_fneg(DisasContext
*ctx
)
2446 if (unlikely(!ctx
->fpu_enabled
)) {
2447 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2450 tcg_gen_xori_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2452 if (unlikely(Rc(ctx
->opcode
))) {
2453 gen_set_cr1_from_fpscr(ctx
);
2457 /* fcpsgn: PowerPC 2.05 specification */
2458 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2459 static void gen_fcpsgn(DisasContext
*ctx
)
2461 if (unlikely(!ctx
->fpu_enabled
)) {
2462 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2465 tcg_gen_deposit_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rA(ctx
->opcode
)],
2466 cpu_fpr
[rB(ctx
->opcode
)], 0, 63);
2467 if (unlikely(Rc(ctx
->opcode
))) {
2468 gen_set_cr1_from_fpscr(ctx
);
2472 static void gen_fmrgew(DisasContext
*ctx
)
2475 if (unlikely(!ctx
->fpu_enabled
)) {
2476 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2479 b0
= tcg_temp_new_i64();
2480 tcg_gen_shri_i64(b0
, cpu_fpr
[rB(ctx
->opcode
)], 32);
2481 tcg_gen_deposit_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rA(ctx
->opcode
)],
2483 tcg_temp_free_i64(b0
);
2486 static void gen_fmrgow(DisasContext
*ctx
)
2488 if (unlikely(!ctx
->fpu_enabled
)) {
2489 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2492 tcg_gen_deposit_i64(cpu_fpr
[rD(ctx
->opcode
)],
2493 cpu_fpr
[rB(ctx
->opcode
)],
2494 cpu_fpr
[rA(ctx
->opcode
)],
2498 /*** Floating-Point status & ctrl register ***/
2501 static void gen_mcrfs(DisasContext
*ctx
)
2503 TCGv tmp
= tcg_temp_new();
2506 if (unlikely(!ctx
->fpu_enabled
)) {
2507 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2510 bfa
= 4 * (7 - crfS(ctx
->opcode
));
2511 tcg_gen_shri_tl(tmp
, cpu_fpscr
, bfa
);
2512 tcg_gen_trunc_tl_i32(cpu_crf
[crfD(ctx
->opcode
)], tmp
);
2514 tcg_gen_andi_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], 0xf);
2515 tcg_gen_andi_tl(cpu_fpscr
, cpu_fpscr
, ~(0xF << bfa
));
2519 static void gen_mffs(DisasContext
*ctx
)
2521 if (unlikely(!ctx
->fpu_enabled
)) {
2522 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2525 gen_reset_fpstatus();
2526 tcg_gen_extu_tl_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpscr
);
2527 if (unlikely(Rc(ctx
->opcode
))) {
2528 gen_set_cr1_from_fpscr(ctx
);
2533 static void gen_mtfsb0(DisasContext
*ctx
)
2537 if (unlikely(!ctx
->fpu_enabled
)) {
2538 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2541 crb
= 31 - crbD(ctx
->opcode
);
2542 gen_reset_fpstatus();
2543 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
)) {
2545 /* NIP cannot be restored if the memory exception comes from an helper */
2546 gen_update_nip(ctx
, ctx
->nip
- 4);
2547 t0
= tcg_const_i32(crb
);
2548 gen_helper_fpscr_clrbit(cpu_env
, t0
);
2549 tcg_temp_free_i32(t0
);
2551 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2552 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2553 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2558 static void gen_mtfsb1(DisasContext
*ctx
)
2562 if (unlikely(!ctx
->fpu_enabled
)) {
2563 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2566 crb
= 31 - crbD(ctx
->opcode
);
2567 gen_reset_fpstatus();
2568 /* XXX: we pretend we can only do IEEE floating-point computations */
2569 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
)) {
2571 /* NIP cannot be restored if the memory exception comes from an helper */
2572 gen_update_nip(ctx
, ctx
->nip
- 4);
2573 t0
= tcg_const_i32(crb
);
2574 gen_helper_fpscr_setbit(cpu_env
, t0
);
2575 tcg_temp_free_i32(t0
);
2577 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2578 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2579 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2581 /* We can raise a differed exception */
2582 gen_helper_float_check_status(cpu_env
);
2586 static void gen_mtfsf(DisasContext
*ctx
)
2591 if (unlikely(!ctx
->fpu_enabled
)) {
2592 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2595 flm
= FPFLM(ctx
->opcode
);
2596 l
= FPL(ctx
->opcode
);
2597 w
= FPW(ctx
->opcode
);
2598 if (unlikely(w
& !(ctx
->insns_flags2
& PPC2_ISA205
))) {
2599 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2602 /* NIP cannot be restored if the memory exception comes from an helper */
2603 gen_update_nip(ctx
, ctx
->nip
- 4);
2604 gen_reset_fpstatus();
2606 t0
= tcg_const_i32((ctx
->insns_flags2
& PPC2_ISA205
) ? 0xffff : 0xff);
2608 t0
= tcg_const_i32(flm
<< (w
* 8));
2610 gen_helper_store_fpscr(cpu_env
, cpu_fpr
[rB(ctx
->opcode
)], t0
);
2611 tcg_temp_free_i32(t0
);
2612 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2613 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2614 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2616 /* We can raise a differed exception */
2617 gen_helper_float_check_status(cpu_env
);
2621 static void gen_mtfsfi(DisasContext
*ctx
)
2627 if (unlikely(!ctx
->fpu_enabled
)) {
2628 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2631 w
= FPW(ctx
->opcode
);
2632 bf
= FPBF(ctx
->opcode
);
2633 if (unlikely(w
& !(ctx
->insns_flags2
& PPC2_ISA205
))) {
2634 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2637 sh
= (8 * w
) + 7 - bf
;
2638 /* NIP cannot be restored if the memory exception comes from an helper */
2639 gen_update_nip(ctx
, ctx
->nip
- 4);
2640 gen_reset_fpstatus();
2641 t0
= tcg_const_i64(((uint64_t)FPIMM(ctx
->opcode
)) << (4 * sh
));
2642 t1
= tcg_const_i32(1 << sh
);
2643 gen_helper_store_fpscr(cpu_env
, t0
, t1
);
2644 tcg_temp_free_i64(t0
);
2645 tcg_temp_free_i32(t1
);
2646 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2647 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2648 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2650 /* We can raise a differed exception */
2651 gen_helper_float_check_status(cpu_env
);
2654 /*** Addressing modes ***/
2655 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2656 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2659 target_long simm
= SIMM(ctx
->opcode
);
2662 if (rA(ctx
->opcode
) == 0) {
2663 if (NARROW_MODE(ctx
)) {
2664 simm
= (uint32_t)simm
;
2666 tcg_gen_movi_tl(EA
, simm
);
2667 } else if (likely(simm
!= 0)) {
2668 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2669 if (NARROW_MODE(ctx
)) {
2670 tcg_gen_ext32u_tl(EA
, EA
);
2673 if (NARROW_MODE(ctx
)) {
2674 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2676 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2681 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2683 if (rA(ctx
->opcode
) == 0) {
2684 if (NARROW_MODE(ctx
)) {
2685 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2687 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2690 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2691 if (NARROW_MODE(ctx
)) {
2692 tcg_gen_ext32u_tl(EA
, EA
);
2697 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2699 if (rA(ctx
->opcode
) == 0) {
2700 tcg_gen_movi_tl(EA
, 0);
2701 } else if (NARROW_MODE(ctx
)) {
2702 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2704 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2708 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2711 tcg_gen_addi_tl(ret
, arg1
, val
);
2712 if (NARROW_MODE(ctx
)) {
2713 tcg_gen_ext32u_tl(ret
, ret
);
2717 static inline void gen_check_align(DisasContext
*ctx
, TCGv EA
, int mask
)
2719 int l1
= gen_new_label();
2720 TCGv t0
= tcg_temp_new();
2722 /* NIP cannot be restored if the memory exception comes from an helper */
2723 gen_update_nip(ctx
, ctx
->nip
- 4);
2724 tcg_gen_andi_tl(t0
, EA
, mask
);
2725 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2726 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2727 t2
= tcg_const_i32(0);
2728 gen_helper_raise_exception_err(cpu_env
, t1
, t2
);
2729 tcg_temp_free_i32(t1
);
2730 tcg_temp_free_i32(t2
);
2735 /*** Integer load ***/
2736 static inline void gen_qemu_ld8u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2738 tcg_gen_qemu_ld8u(arg1
, arg2
, ctx
->mem_idx
);
2741 static inline void gen_qemu_ld16u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2743 TCGMemOp op
= MO_UW
| ctx
->default_tcg_memop_mask
;
2744 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2747 static inline void gen_qemu_ld16s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2749 TCGMemOp op
= MO_SW
| ctx
->default_tcg_memop_mask
;
2750 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2753 static inline void gen_qemu_ld32u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2755 TCGMemOp op
= MO_UL
| ctx
->default_tcg_memop_mask
;
2756 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2759 static void gen_qemu_ld32u_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2761 TCGv tmp
= tcg_temp_new();
2762 gen_qemu_ld32u(ctx
, tmp
, addr
);
2763 tcg_gen_extu_tl_i64(val
, tmp
);
2767 static inline void gen_qemu_ld32s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2769 TCGMemOp op
= MO_SL
| ctx
->default_tcg_memop_mask
;
2770 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2773 static void gen_qemu_ld32s_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2775 TCGv tmp
= tcg_temp_new();
2776 gen_qemu_ld32s(ctx
, tmp
, addr
);
2777 tcg_gen_ext_tl_i64(val
, tmp
);
2781 static inline void gen_qemu_ld64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2783 TCGMemOp op
= MO_Q
| ctx
->default_tcg_memop_mask
;
2784 tcg_gen_qemu_ld_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2787 static inline void gen_qemu_st8(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2789 tcg_gen_qemu_st8(arg1
, arg2
, ctx
->mem_idx
);
2792 static inline void gen_qemu_st16(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2794 TCGMemOp op
= MO_UW
| ctx
->default_tcg_memop_mask
;
2795 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2798 static inline void gen_qemu_st32(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2800 TCGMemOp op
= MO_UL
| ctx
->default_tcg_memop_mask
;
2801 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2804 static void gen_qemu_st32_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2806 TCGv tmp
= tcg_temp_new();
2807 tcg_gen_trunc_i64_tl(tmp
, val
);
2808 gen_qemu_st32(ctx
, tmp
, addr
);
2812 static inline void gen_qemu_st64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2814 TCGMemOp op
= MO_Q
| ctx
->default_tcg_memop_mask
;
2815 tcg_gen_qemu_st_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2818 #define GEN_LD(name, ldop, opc, type) \
2819 static void glue(gen_, name)(DisasContext *ctx) \
2822 gen_set_access_type(ctx, ACCESS_INT); \
2823 EA = tcg_temp_new(); \
2824 gen_addr_imm_index(ctx, EA, 0); \
2825 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2826 tcg_temp_free(EA); \
2829 #define GEN_LDU(name, ldop, opc, type) \
2830 static void glue(gen_, name##u)(DisasContext *ctx) \
2833 if (unlikely(rA(ctx->opcode) == 0 || \
2834 rA(ctx->opcode) == rD(ctx->opcode))) { \
2835 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2838 gen_set_access_type(ctx, ACCESS_INT); \
2839 EA = tcg_temp_new(); \
2840 if (type == PPC_64B) \
2841 gen_addr_imm_index(ctx, EA, 0x03); \
2843 gen_addr_imm_index(ctx, EA, 0); \
2844 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2845 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2846 tcg_temp_free(EA); \
2849 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2850 static void glue(gen_, name##ux)(DisasContext *ctx) \
2853 if (unlikely(rA(ctx->opcode) == 0 || \
2854 rA(ctx->opcode) == rD(ctx->opcode))) { \
2855 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2858 gen_set_access_type(ctx, ACCESS_INT); \
2859 EA = tcg_temp_new(); \
2860 gen_addr_reg_index(ctx, EA); \
2861 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2862 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2863 tcg_temp_free(EA); \
2866 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2867 static void glue(gen_, name##x)(DisasContext *ctx) \
2870 gen_set_access_type(ctx, ACCESS_INT); \
2871 EA = tcg_temp_new(); \
2872 gen_addr_reg_index(ctx, EA); \
2873 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2874 tcg_temp_free(EA); \
2876 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2877 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2879 #define GEN_LDS(name, ldop, op, type) \
2880 GEN_LD(name, ldop, op | 0x20, type); \
2881 GEN_LDU(name, ldop, op | 0x21, type); \
2882 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2883 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2885 /* lbz lbzu lbzux lbzx */
2886 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2887 /* lha lhau lhaux lhax */
2888 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2889 /* lhz lhzu lhzux lhzx */
2890 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2891 /* lwz lwzu lwzux lwzx */
2892 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2893 #if defined(TARGET_PPC64)
2895 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2897 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2899 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
);
2901 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
);
2903 static void gen_ld(DisasContext
*ctx
)
2906 if (Rc(ctx
->opcode
)) {
2907 if (unlikely(rA(ctx
->opcode
) == 0 ||
2908 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2909 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2913 gen_set_access_type(ctx
, ACCESS_INT
);
2914 EA
= tcg_temp_new();
2915 gen_addr_imm_index(ctx
, EA
, 0x03);
2916 if (ctx
->opcode
& 0x02) {
2917 /* lwa (lwau is undefined) */
2918 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2921 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2923 if (Rc(ctx
->opcode
))
2924 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2929 static void gen_lq(DisasContext
*ctx
)
2934 /* lq is a legal user mode instruction starting in ISA 2.07 */
2935 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2936 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2938 if (!legal_in_user_mode
&& ctx
->pr
) {
2939 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2943 if (!le_is_supported
&& ctx
->le_mode
) {
2944 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2948 ra
= rA(ctx
->opcode
);
2949 rd
= rD(ctx
->opcode
);
2950 if (unlikely((rd
& 1) || rd
== ra
)) {
2951 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2955 gen_set_access_type(ctx
, ACCESS_INT
);
2956 EA
= tcg_temp_new();
2957 gen_addr_imm_index(ctx
, EA
, 0x0F);
2959 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2960 64-bit byteswap already. */
2961 if (unlikely(ctx
->le_mode
)) {
2962 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2963 gen_addr_add(ctx
, EA
, EA
, 8);
2964 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2966 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2967 gen_addr_add(ctx
, EA
, EA
, 8);
2968 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2974 /*** Integer store ***/
2975 #define GEN_ST(name, stop, opc, type) \
2976 static void glue(gen_, name)(DisasContext *ctx) \
2979 gen_set_access_type(ctx, ACCESS_INT); \
2980 EA = tcg_temp_new(); \
2981 gen_addr_imm_index(ctx, EA, 0); \
2982 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2983 tcg_temp_free(EA); \
2986 #define GEN_STU(name, stop, opc, type) \
2987 static void glue(gen_, stop##u)(DisasContext *ctx) \
2990 if (unlikely(rA(ctx->opcode) == 0)) { \
2991 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2994 gen_set_access_type(ctx, ACCESS_INT); \
2995 EA = tcg_temp_new(); \
2996 if (type == PPC_64B) \
2997 gen_addr_imm_index(ctx, EA, 0x03); \
2999 gen_addr_imm_index(ctx, EA, 0); \
3000 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3001 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3002 tcg_temp_free(EA); \
3005 #define GEN_STUX(name, stop, opc2, opc3, type) \
3006 static void glue(gen_, name##ux)(DisasContext *ctx) \
3009 if (unlikely(rA(ctx->opcode) == 0)) { \
3010 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3013 gen_set_access_type(ctx, ACCESS_INT); \
3014 EA = tcg_temp_new(); \
3015 gen_addr_reg_index(ctx, EA); \
3016 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3017 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3018 tcg_temp_free(EA); \
3021 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3022 static void glue(gen_, name##x)(DisasContext *ctx) \
3025 gen_set_access_type(ctx, ACCESS_INT); \
3026 EA = tcg_temp_new(); \
3027 gen_addr_reg_index(ctx, EA); \
3028 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3029 tcg_temp_free(EA); \
3031 #define GEN_STX(name, stop, opc2, opc3, type) \
3032 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3034 #define GEN_STS(name, stop, op, type) \
3035 GEN_ST(name, stop, op | 0x20, type); \
3036 GEN_STU(name, stop, op | 0x21, type); \
3037 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3038 GEN_STX(name, stop, 0x17, op | 0x00, type)
3040 /* stb stbu stbux stbx */
3041 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
3042 /* sth sthu sthux sthx */
3043 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
3044 /* stw stwu stwux stwx */
3045 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
3046 #if defined(TARGET_PPC64)
3047 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
);
3048 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
);
3050 static void gen_std(DisasContext
*ctx
)
3055 rs
= rS(ctx
->opcode
);
3056 if ((ctx
->opcode
& 0x3) == 0x2) { /* stq */
3058 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3059 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3061 if (!legal_in_user_mode
&& ctx
->pr
) {
3062 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3066 if (!le_is_supported
&& ctx
->le_mode
) {
3067 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
3071 if (unlikely(rs
& 1)) {
3072 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3075 gen_set_access_type(ctx
, ACCESS_INT
);
3076 EA
= tcg_temp_new();
3077 gen_addr_imm_index(ctx
, EA
, 0x03);
3079 /* We only need to swap high and low halves. gen_qemu_st64 does
3080 necessary 64-bit byteswap already. */
3081 if (unlikely(ctx
->le_mode
)) {
3082 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
3083 gen_addr_add(ctx
, EA
, EA
, 8);
3084 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
3086 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
3087 gen_addr_add(ctx
, EA
, EA
, 8);
3088 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
3093 if (Rc(ctx
->opcode
)) {
3094 if (unlikely(rA(ctx
->opcode
) == 0)) {
3095 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3099 gen_set_access_type(ctx
, ACCESS_INT
);
3100 EA
= tcg_temp_new();
3101 gen_addr_imm_index(ctx
, EA
, 0x03);
3102 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
3103 if (Rc(ctx
->opcode
))
3104 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
3109 /*** Integer load and store with byte reverse ***/
3112 static inline void gen_qemu_ld16ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3114 TCGMemOp op
= MO_UW
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3115 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3117 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
3120 static inline void gen_qemu_ld32ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3122 TCGMemOp op
= MO_UL
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3123 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3125 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
3127 #if defined(TARGET_PPC64)
3129 static inline void gen_qemu_ld64ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3131 TCGMemOp op
= MO_Q
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3132 tcg_gen_qemu_ld_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
3134 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
);
3135 #endif /* TARGET_PPC64 */
3138 static inline void gen_qemu_st16r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3140 TCGMemOp op
= MO_UW
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3141 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3143 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
3146 static inline void gen_qemu_st32r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3148 TCGMemOp op
= MO_UL
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3149 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3151 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
3153 #if defined(TARGET_PPC64)
3155 static inline void gen_qemu_st64r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3157 TCGMemOp op
= MO_Q
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3158 tcg_gen_qemu_st_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
3160 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
);
3161 #endif /* TARGET_PPC64 */
3163 /*** Integer load and store multiple ***/
3166 static void gen_lmw(DisasContext
*ctx
)
3170 gen_set_access_type(ctx
, ACCESS_INT
);
3171 /* NIP cannot be restored if the memory exception comes from an helper */
3172 gen_update_nip(ctx
, ctx
->nip
- 4);
3173 t0
= tcg_temp_new();
3174 t1
= tcg_const_i32(rD(ctx
->opcode
));
3175 gen_addr_imm_index(ctx
, t0
, 0);
3176 gen_helper_lmw(cpu_env
, t0
, t1
);
3178 tcg_temp_free_i32(t1
);
3182 static void gen_stmw(DisasContext
*ctx
)
3186 gen_set_access_type(ctx
, ACCESS_INT
);
3187 /* NIP cannot be restored if the memory exception comes from an helper */
3188 gen_update_nip(ctx
, ctx
->nip
- 4);
3189 t0
= tcg_temp_new();
3190 t1
= tcg_const_i32(rS(ctx
->opcode
));
3191 gen_addr_imm_index(ctx
, t0
, 0);
3192 gen_helper_stmw(cpu_env
, t0
, t1
);
3194 tcg_temp_free_i32(t1
);
3197 /*** Integer load and store strings ***/
3200 /* PowerPC32 specification says we must generate an exception if
3201 * rA is in the range of registers to be loaded.
3202 * In an other hand, IBM says this is valid, but rA won't be loaded.
3203 * For now, I'll follow the spec...
3205 static void gen_lswi(DisasContext
*ctx
)
3209 int nb
= NB(ctx
->opcode
);
3210 int start
= rD(ctx
->opcode
);
3211 int ra
= rA(ctx
->opcode
);
3217 if (unlikely(((start
+ nr
) > 32 &&
3218 start
<= ra
&& (start
+ nr
- 32) > ra
) ||
3219 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
))) {
3220 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
3223 gen_set_access_type(ctx
, ACCESS_INT
);
3224 /* NIP cannot be restored if the memory exception comes from an helper */
3225 gen_update_nip(ctx
, ctx
->nip
- 4);
3226 t0
= tcg_temp_new();
3227 gen_addr_register(ctx
, t0
);
3228 t1
= tcg_const_i32(nb
);
3229 t2
= tcg_const_i32(start
);
3230 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
3232 tcg_temp_free_i32(t1
);
3233 tcg_temp_free_i32(t2
);
3237 static void gen_lswx(DisasContext
*ctx
)
3240 TCGv_i32 t1
, t2
, t3
;
3241 gen_set_access_type(ctx
, ACCESS_INT
);
3242 /* NIP cannot be restored if the memory exception comes from an helper */
3243 gen_update_nip(ctx
, ctx
->nip
- 4);
3244 t0
= tcg_temp_new();
3245 gen_addr_reg_index(ctx
, t0
);
3246 t1
= tcg_const_i32(rD(ctx
->opcode
));
3247 t2
= tcg_const_i32(rA(ctx
->opcode
));
3248 t3
= tcg_const_i32(rB(ctx
->opcode
));
3249 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
3251 tcg_temp_free_i32(t1
);
3252 tcg_temp_free_i32(t2
);
3253 tcg_temp_free_i32(t3
);
3257 static void gen_stswi(DisasContext
*ctx
)
3261 int nb
= NB(ctx
->opcode
);
3262 gen_set_access_type(ctx
, ACCESS_INT
);
3263 /* NIP cannot be restored if the memory exception comes from an helper */
3264 gen_update_nip(ctx
, ctx
->nip
- 4);
3265 t0
= tcg_temp_new();
3266 gen_addr_register(ctx
, t0
);
3269 t1
= tcg_const_i32(nb
);
3270 t2
= tcg_const_i32(rS(ctx
->opcode
));
3271 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3273 tcg_temp_free_i32(t1
);
3274 tcg_temp_free_i32(t2
);
3278 static void gen_stswx(DisasContext
*ctx
)
3282 gen_set_access_type(ctx
, ACCESS_INT
);
3283 /* NIP cannot be restored if the memory exception comes from an helper */
3284 gen_update_nip(ctx
, ctx
->nip
- 4);
3285 t0
= tcg_temp_new();
3286 gen_addr_reg_index(ctx
, t0
);
3287 t1
= tcg_temp_new_i32();
3288 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3289 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3290 t2
= tcg_const_i32(rS(ctx
->opcode
));
3291 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3293 tcg_temp_free_i32(t1
);
3294 tcg_temp_free_i32(t2
);
3297 /*** Memory synchronisation ***/
3299 static void gen_eieio(DisasContext
*ctx
)
3304 static void gen_isync(DisasContext
*ctx
)
3306 gen_stop_exception(ctx
);
3309 #define LARX(name, len, loadop) \
3310 static void gen_##name(DisasContext *ctx) \
3313 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3314 gen_set_access_type(ctx, ACCESS_RES); \
3315 t0 = tcg_temp_local_new(); \
3316 gen_addr_reg_index(ctx, t0); \
3318 gen_check_align(ctx, t0, (len)-1); \
3320 gen_qemu_##loadop(ctx, gpr, t0); \
3321 tcg_gen_mov_tl(cpu_reserve, t0); \
3322 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3323 tcg_temp_free(t0); \
3327 LARX(lbarx
, 1, ld8u
);
3328 LARX(lharx
, 2, ld16u
);
3329 LARX(lwarx
, 4, ld32u
);
3332 #if defined(CONFIG_USER_ONLY)
3333 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3336 TCGv t0
= tcg_temp_new();
3337 uint32_t save_exception
= ctx
->exception
;
3339 tcg_gen_st_tl(EA
, cpu_env
, offsetof(CPUPPCState
, reserve_ea
));
3340 tcg_gen_movi_tl(t0
, (size
<< 5) | reg
);
3341 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, reserve_info
));
3343 gen_update_nip(ctx
, ctx
->nip
-4);
3344 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3345 gen_exception(ctx
, POWERPC_EXCP_STCX
);
3346 ctx
->exception
= save_exception
;
3349 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3354 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3355 l1
= gen_new_label();
3356 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, l1
);
3357 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3358 #if defined(TARGET_PPC64)
3360 gen_qemu_st64(ctx
, cpu_gpr
[reg
], EA
);
3364 gen_qemu_st32(ctx
, cpu_gpr
[reg
], EA
);
3365 } else if (size
== 2) {
3366 gen_qemu_st16(ctx
, cpu_gpr
[reg
], EA
);
3367 #if defined(TARGET_PPC64)
3368 } else if (size
== 16) {
3369 TCGv gpr1
, gpr2
, EA8
;
3370 if (unlikely(ctx
->le_mode
)) {
3371 gpr1
= cpu_gpr
[reg
+1];
3372 gpr2
= cpu_gpr
[reg
];
3374 gpr1
= cpu_gpr
[reg
];
3375 gpr2
= cpu_gpr
[reg
+1];
3377 gen_qemu_st64(ctx
, gpr1
, EA
);
3378 EA8
= tcg_temp_local_new();
3379 gen_addr_add(ctx
, EA8
, EA
, 8);
3380 gen_qemu_st64(ctx
, gpr2
, EA8
);
3384 gen_qemu_st8(ctx
, cpu_gpr
[reg
], EA
);
3387 tcg_gen_movi_tl(cpu_reserve
, -1);
3391 #define STCX(name, len) \
3392 static void gen_##name(DisasContext *ctx) \
3395 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3396 gen_inval_exception(ctx, \
3397 POWERPC_EXCP_INVAL_INVAL); \
3400 gen_set_access_type(ctx, ACCESS_RES); \
3401 t0 = tcg_temp_local_new(); \
3402 gen_addr_reg_index(ctx, t0); \
3404 gen_check_align(ctx, t0, (len)-1); \
3406 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3407 tcg_temp_free(t0); \
3414 #if defined(TARGET_PPC64)
3416 LARX(ldarx
, 8, ld64
);
3419 static void gen_lqarx(DisasContext
*ctx
)
3422 int rd
= rD(ctx
->opcode
);
3425 if (unlikely((rd
& 1) || (rd
== rA(ctx
->opcode
)) ||
3426 (rd
== rB(ctx
->opcode
)))) {
3427 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3431 gen_set_access_type(ctx
, ACCESS_RES
);
3432 EA
= tcg_temp_local_new();
3433 gen_addr_reg_index(ctx
, EA
);
3434 gen_check_align(ctx
, EA
, 15);
3435 if (unlikely(ctx
->le_mode
)) {
3436 gpr1
= cpu_gpr
[rd
+1];
3440 gpr2
= cpu_gpr
[rd
+1];
3442 gen_qemu_ld64(ctx
, gpr1
, EA
);
3443 tcg_gen_mov_tl(cpu_reserve
, EA
);
3445 gen_addr_add(ctx
, EA
, EA
, 8);
3446 gen_qemu_ld64(ctx
, gpr2
, EA
);
3448 tcg_gen_st_tl(gpr1
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3449 tcg_gen_st_tl(gpr2
, cpu_env
, offsetof(CPUPPCState
, reserve_val2
));
3457 #endif /* defined(TARGET_PPC64) */
3460 static void gen_sync(DisasContext
*ctx
)
3465 static void gen_wait(DisasContext
*ctx
)
3467 TCGv_i32 t0
= tcg_temp_new_i32();
3468 tcg_gen_st_i32(t0
, cpu_env
,
3469 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
3470 tcg_temp_free_i32(t0
);
3471 /* Stop translation, as the CPU is supposed to sleep from now */
3472 gen_exception_err(ctx
, EXCP_HLT
, 1);
3475 /*** Floating-point load ***/
3476 #define GEN_LDF(name, ldop, opc, type) \
3477 static void glue(gen_, name)(DisasContext *ctx) \
3480 if (unlikely(!ctx->fpu_enabled)) { \
3481 gen_exception(ctx, POWERPC_EXCP_FPU); \
3484 gen_set_access_type(ctx, ACCESS_FLOAT); \
3485 EA = tcg_temp_new(); \
3486 gen_addr_imm_index(ctx, EA, 0); \
3487 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3488 tcg_temp_free(EA); \
3491 #define GEN_LDUF(name, ldop, opc, type) \
3492 static void glue(gen_, name##u)(DisasContext *ctx) \
3495 if (unlikely(!ctx->fpu_enabled)) { \
3496 gen_exception(ctx, POWERPC_EXCP_FPU); \
3499 if (unlikely(rA(ctx->opcode) == 0)) { \
3500 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3503 gen_set_access_type(ctx, ACCESS_FLOAT); \
3504 EA = tcg_temp_new(); \
3505 gen_addr_imm_index(ctx, EA, 0); \
3506 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3507 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3508 tcg_temp_free(EA); \
3511 #define GEN_LDUXF(name, ldop, opc, type) \
3512 static void glue(gen_, name##ux)(DisasContext *ctx) \
3515 if (unlikely(!ctx->fpu_enabled)) { \
3516 gen_exception(ctx, POWERPC_EXCP_FPU); \
3519 if (unlikely(rA(ctx->opcode) == 0)) { \
3520 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3523 gen_set_access_type(ctx, ACCESS_FLOAT); \
3524 EA = tcg_temp_new(); \
3525 gen_addr_reg_index(ctx, EA); \
3526 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3527 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3528 tcg_temp_free(EA); \
3531 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3532 static void glue(gen_, name##x)(DisasContext *ctx) \
3535 if (unlikely(!ctx->fpu_enabled)) { \
3536 gen_exception(ctx, POWERPC_EXCP_FPU); \
3539 gen_set_access_type(ctx, ACCESS_FLOAT); \
3540 EA = tcg_temp_new(); \
3541 gen_addr_reg_index(ctx, EA); \
3542 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3543 tcg_temp_free(EA); \
3546 #define GEN_LDFS(name, ldop, op, type) \
3547 GEN_LDF(name, ldop, op | 0x20, type); \
3548 GEN_LDUF(name, ldop, op | 0x21, type); \
3549 GEN_LDUXF(name, ldop, op | 0x01, type); \
3550 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3552 static inline void gen_qemu_ld32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3554 TCGv t0
= tcg_temp_new();
3555 TCGv_i32 t1
= tcg_temp_new_i32();
3556 gen_qemu_ld32u(ctx
, t0
, arg2
);
3557 tcg_gen_trunc_tl_i32(t1
, t0
);
3559 gen_helper_float32_to_float64(arg1
, cpu_env
, t1
);
3560 tcg_temp_free_i32(t1
);
3563 /* lfd lfdu lfdux lfdx */
3564 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
);
3565 /* lfs lfsu lfsux lfsx */
3566 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
);
3569 static void gen_lfdp(DisasContext
*ctx
)
3572 if (unlikely(!ctx
->fpu_enabled
)) {
3573 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3576 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3577 EA
= tcg_temp_new();
3578 gen_addr_imm_index(ctx
, EA
, 0);
3579 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3580 64-bit byteswap already. */
3581 if (unlikely(ctx
->le_mode
)) {
3582 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3583 tcg_gen_addi_tl(EA
, EA
, 8);
3584 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3586 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3587 tcg_gen_addi_tl(EA
, EA
, 8);
3588 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3594 static void gen_lfdpx(DisasContext
*ctx
)
3597 if (unlikely(!ctx
->fpu_enabled
)) {
3598 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3601 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3602 EA
= tcg_temp_new();
3603 gen_addr_reg_index(ctx
, EA
);
3604 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3605 64-bit byteswap already. */
3606 if (unlikely(ctx
->le_mode
)) {
3607 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3608 tcg_gen_addi_tl(EA
, EA
, 8);
3609 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3611 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3612 tcg_gen_addi_tl(EA
, EA
, 8);
3613 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3619 static void gen_lfiwax(DisasContext
*ctx
)
3623 if (unlikely(!ctx
->fpu_enabled
)) {
3624 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3627 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3628 EA
= tcg_temp_new();
3629 t0
= tcg_temp_new();
3630 gen_addr_reg_index(ctx
, EA
);
3631 gen_qemu_ld32s(ctx
, t0
, EA
);
3632 tcg_gen_ext_tl_i64(cpu_fpr
[rD(ctx
->opcode
)], t0
);
3638 static void gen_lfiwzx(DisasContext
*ctx
)
3641 if (unlikely(!ctx
->fpu_enabled
)) {
3642 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3645 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3646 EA
= tcg_temp_new();
3647 gen_addr_reg_index(ctx
, EA
);
3648 gen_qemu_ld32u_i64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3651 /*** Floating-point store ***/
3652 #define GEN_STF(name, stop, opc, type) \
3653 static void glue(gen_, name)(DisasContext *ctx) \
3656 if (unlikely(!ctx->fpu_enabled)) { \
3657 gen_exception(ctx, POWERPC_EXCP_FPU); \
3660 gen_set_access_type(ctx, ACCESS_FLOAT); \
3661 EA = tcg_temp_new(); \
3662 gen_addr_imm_index(ctx, EA, 0); \
3663 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3664 tcg_temp_free(EA); \
3667 #define GEN_STUF(name, stop, opc, type) \
3668 static void glue(gen_, name##u)(DisasContext *ctx) \
3671 if (unlikely(!ctx->fpu_enabled)) { \
3672 gen_exception(ctx, POWERPC_EXCP_FPU); \
3675 if (unlikely(rA(ctx->opcode) == 0)) { \
3676 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3679 gen_set_access_type(ctx, ACCESS_FLOAT); \
3680 EA = tcg_temp_new(); \
3681 gen_addr_imm_index(ctx, EA, 0); \
3682 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3683 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3684 tcg_temp_free(EA); \
3687 #define GEN_STUXF(name, stop, opc, type) \
3688 static void glue(gen_, name##ux)(DisasContext *ctx) \
3691 if (unlikely(!ctx->fpu_enabled)) { \
3692 gen_exception(ctx, POWERPC_EXCP_FPU); \
3695 if (unlikely(rA(ctx->opcode) == 0)) { \
3696 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3699 gen_set_access_type(ctx, ACCESS_FLOAT); \
3700 EA = tcg_temp_new(); \
3701 gen_addr_reg_index(ctx, EA); \
3702 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3703 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3704 tcg_temp_free(EA); \
3707 #define GEN_STXF(name, stop, opc2, opc3, type) \
3708 static void glue(gen_, name##x)(DisasContext *ctx) \
3711 if (unlikely(!ctx->fpu_enabled)) { \
3712 gen_exception(ctx, POWERPC_EXCP_FPU); \
3715 gen_set_access_type(ctx, ACCESS_FLOAT); \
3716 EA = tcg_temp_new(); \
3717 gen_addr_reg_index(ctx, EA); \
3718 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3719 tcg_temp_free(EA); \
3722 #define GEN_STFS(name, stop, op, type) \
3723 GEN_STF(name, stop, op | 0x20, type); \
3724 GEN_STUF(name, stop, op | 0x21, type); \
3725 GEN_STUXF(name, stop, op | 0x01, type); \
3726 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3728 static inline void gen_qemu_st32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3730 TCGv_i32 t0
= tcg_temp_new_i32();
3731 TCGv t1
= tcg_temp_new();
3732 gen_helper_float64_to_float32(t0
, cpu_env
, arg1
);
3733 tcg_gen_extu_i32_tl(t1
, t0
);
3734 tcg_temp_free_i32(t0
);
3735 gen_qemu_st32(ctx
, t1
, arg2
);
3739 /* stfd stfdu stfdux stfdx */
3740 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
);
3741 /* stfs stfsu stfsux stfsx */
3742 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
);
3745 static void gen_stfdp(DisasContext
*ctx
)
3748 if (unlikely(!ctx
->fpu_enabled
)) {
3749 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3752 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3753 EA
= tcg_temp_new();
3754 gen_addr_imm_index(ctx
, EA
, 0);
3755 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3756 64-bit byteswap already. */
3757 if (unlikely(ctx
->le_mode
)) {
3758 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3759 tcg_gen_addi_tl(EA
, EA
, 8);
3760 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3762 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3763 tcg_gen_addi_tl(EA
, EA
, 8);
3764 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3770 static void gen_stfdpx(DisasContext
*ctx
)
3773 if (unlikely(!ctx
->fpu_enabled
)) {
3774 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3777 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3778 EA
= tcg_temp_new();
3779 gen_addr_reg_index(ctx
, EA
);
3780 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3781 64-bit byteswap already. */
3782 if (unlikely(ctx
->le_mode
)) {
3783 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3784 tcg_gen_addi_tl(EA
, EA
, 8);
3785 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3787 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3788 tcg_gen_addi_tl(EA
, EA
, 8);
3789 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3795 static inline void gen_qemu_st32fiw(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3797 TCGv t0
= tcg_temp_new();
3798 tcg_gen_trunc_i64_tl(t0
, arg1
),
3799 gen_qemu_st32(ctx
, t0
, arg2
);
3803 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
3805 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3807 #if defined(TARGET_PPC64)
3809 tcg_gen_movi_tl(cpu_cfar
, nip
);
3814 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3816 TranslationBlock
*tb
;
3818 if (NARROW_MODE(ctx
)) {
3819 dest
= (uint32_t) dest
;
3821 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
3822 likely(!ctx
->singlestep_enabled
)) {
3824 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3825 tcg_gen_exit_tb((uintptr_t)tb
+ n
);
3827 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3828 if (unlikely(ctx
->singlestep_enabled
)) {
3829 if ((ctx
->singlestep_enabled
&
3830 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3831 (ctx
->exception
== POWERPC_EXCP_BRANCH
||
3832 ctx
->exception
== POWERPC_EXCP_TRACE
)) {
3833 target_ulong tmp
= ctx
->nip
;
3835 gen_exception(ctx
, POWERPC_EXCP_TRACE
);
3838 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3839 gen_debug_exception(ctx
);
3846 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3848 if (NARROW_MODE(ctx
)) {
3849 nip
= (uint32_t)nip
;
3851 tcg_gen_movi_tl(cpu_lr
, nip
);
3855 static void gen_b(DisasContext
*ctx
)
3857 target_ulong li
, target
;
3859 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3860 /* sign extend LI */
3861 li
= LI(ctx
->opcode
);
3862 li
= (li
^ 0x02000000) - 0x02000000;
3863 if (likely(AA(ctx
->opcode
) == 0)) {
3864 target
= ctx
->nip
+ li
- 4;
3868 if (LK(ctx
->opcode
)) {
3869 gen_setlr(ctx
, ctx
->nip
);
3871 gen_update_cfar(ctx
, ctx
->nip
);
3872 gen_goto_tb(ctx
, 0, target
);
3880 static inline void gen_bcond(DisasContext
*ctx
, int type
)
3882 uint32_t bo
= BO(ctx
->opcode
);
3886 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3887 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3888 target
= tcg_temp_local_new();
3889 if (type
== BCOND_CTR
)
3890 tcg_gen_mov_tl(target
, cpu_ctr
);
3891 else if (type
== BCOND_TAR
)
3892 gen_load_spr(target
, SPR_TAR
);
3894 tcg_gen_mov_tl(target
, cpu_lr
);
3896 TCGV_UNUSED(target
);
3898 if (LK(ctx
->opcode
))
3899 gen_setlr(ctx
, ctx
->nip
);
3900 l1
= gen_new_label();
3901 if ((bo
& 0x4) == 0) {
3902 /* Decrement and test CTR */
3903 TCGv temp
= tcg_temp_new();
3904 if (unlikely(type
== BCOND_CTR
)) {
3905 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3908 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3909 if (NARROW_MODE(ctx
)) {
3910 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3912 tcg_gen_mov_tl(temp
, cpu_ctr
);
3915 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3917 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3919 tcg_temp_free(temp
);
3921 if ((bo
& 0x10) == 0) {
3923 uint32_t bi
= BI(ctx
->opcode
);
3924 uint32_t mask
= 0x08 >> (bi
& 0x03);
3925 TCGv_i32 temp
= tcg_temp_new_i32();
3928 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3929 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3931 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3932 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3934 tcg_temp_free_i32(temp
);
3936 gen_update_cfar(ctx
, ctx
->nip
);
3937 if (type
== BCOND_IM
) {
3938 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3939 if (likely(AA(ctx
->opcode
) == 0)) {
3940 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
3942 gen_goto_tb(ctx
, 0, li
);
3945 gen_goto_tb(ctx
, 1, ctx
->nip
);
3947 if (NARROW_MODE(ctx
)) {
3948 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3950 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3954 gen_update_nip(ctx
, ctx
->nip
);
3957 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3958 tcg_temp_free(target
);
3962 static void gen_bc(DisasContext
*ctx
)
3964 gen_bcond(ctx
, BCOND_IM
);
3967 static void gen_bcctr(DisasContext
*ctx
)
3969 gen_bcond(ctx
, BCOND_CTR
);
3972 static void gen_bclr(DisasContext
*ctx
)
3974 gen_bcond(ctx
, BCOND_LR
);
3977 static void gen_bctar(DisasContext
*ctx
)
3979 gen_bcond(ctx
, BCOND_TAR
);
3982 /*** Condition register logical ***/
3983 #define GEN_CRLOGIC(name, tcg_op, opc) \
3984 static void glue(gen_, name)(DisasContext *ctx) \
3989 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3990 t0 = tcg_temp_new_i32(); \
3992 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3994 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3996 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3997 t1 = tcg_temp_new_i32(); \
3998 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4000 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4002 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4004 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4005 tcg_op(t0, t0, t1); \
4006 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4007 tcg_gen_andi_i32(t0, t0, bitmask); \
4008 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4009 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4010 tcg_temp_free_i32(t0); \
4011 tcg_temp_free_i32(t1); \
4015 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
4017 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
4019 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
4021 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
4023 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
4025 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
4027 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
4029 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
4032 static void gen_mcrf(DisasContext
*ctx
)
4034 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
4037 /*** System linkage ***/
4039 /* rfi (supervisor only) */
4040 static void gen_rfi(DisasContext
*ctx
)
4042 #if defined(CONFIG_USER_ONLY)
4043 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4045 /* Restore CPU state */
4046 if (unlikely(ctx
->pr
)) {
4047 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4050 gen_update_cfar(ctx
, ctx
->nip
);
4051 gen_helper_rfi(cpu_env
);
4052 gen_sync_exception(ctx
);
4056 #if defined(TARGET_PPC64)
4057 static void gen_rfid(DisasContext
*ctx
)
4059 #if defined(CONFIG_USER_ONLY)
4060 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4062 /* Restore CPU state */
4063 if (unlikely(ctx
->pr
)) {
4064 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4067 gen_update_cfar(ctx
, ctx
->nip
);
4068 gen_helper_rfid(cpu_env
);
4069 gen_sync_exception(ctx
);
4073 static void gen_hrfid(DisasContext
*ctx
)
4075 #if defined(CONFIG_USER_ONLY)
4076 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4078 /* Restore CPU state */
4079 if (unlikely(!ctx
->hv
)) {
4080 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4083 gen_helper_hrfid(cpu_env
);
4084 gen_sync_exception(ctx
);
4090 #if defined(CONFIG_USER_ONLY)
4091 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4093 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4095 static void gen_sc(DisasContext
*ctx
)
4099 lev
= (ctx
->opcode
>> 5) & 0x7F;
4100 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
4106 static void gen_tw(DisasContext
*ctx
)
4108 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
4109 /* Update the nip since this might generate a trap exception */
4110 gen_update_nip(ctx
, ctx
->nip
);
4111 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4113 tcg_temp_free_i32(t0
);
4117 static void gen_twi(DisasContext
*ctx
)
4119 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4120 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
4121 /* Update the nip since this might generate a trap exception */
4122 gen_update_nip(ctx
, ctx
->nip
);
4123 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4125 tcg_temp_free_i32(t1
);
4128 #if defined(TARGET_PPC64)
4130 static void gen_td(DisasContext
*ctx
)
4132 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
4133 /* Update the nip since this might generate a trap exception */
4134 gen_update_nip(ctx
, ctx
->nip
);
4135 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4137 tcg_temp_free_i32(t0
);
4141 static void gen_tdi(DisasContext
*ctx
)
4143 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4144 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
4145 /* Update the nip since this might generate a trap exception */
4146 gen_update_nip(ctx
, ctx
->nip
);
4147 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4149 tcg_temp_free_i32(t1
);
4153 /*** Processor control ***/
4155 static void gen_read_xer(TCGv dst
)
4157 TCGv t0
= tcg_temp_new();
4158 TCGv t1
= tcg_temp_new();
4159 TCGv t2
= tcg_temp_new();
4160 tcg_gen_mov_tl(dst
, cpu_xer
);
4161 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
4162 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
4163 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
4164 tcg_gen_or_tl(t0
, t0
, t1
);
4165 tcg_gen_or_tl(dst
, dst
, t2
);
4166 tcg_gen_or_tl(dst
, dst
, t0
);
4172 static void gen_write_xer(TCGv src
)
4174 tcg_gen_andi_tl(cpu_xer
, src
,
4175 ~((1u << XER_SO
) | (1u << XER_OV
) | (1u << XER_CA
)));
4176 tcg_gen_shri_tl(cpu_so
, src
, XER_SO
);
4177 tcg_gen_shri_tl(cpu_ov
, src
, XER_OV
);
4178 tcg_gen_shri_tl(cpu_ca
, src
, XER_CA
);
4179 tcg_gen_andi_tl(cpu_so
, cpu_so
, 1);
4180 tcg_gen_andi_tl(cpu_ov
, cpu_ov
, 1);
4181 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
4185 static void gen_mcrxr(DisasContext
*ctx
)
4187 TCGv_i32 t0
= tcg_temp_new_i32();
4188 TCGv_i32 t1
= tcg_temp_new_i32();
4189 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
4191 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
4192 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
4193 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
4194 tcg_gen_shli_i32(t0
, t0
, 3);
4195 tcg_gen_shli_i32(t1
, t1
, 2);
4196 tcg_gen_shli_i32(dst
, dst
, 1);
4197 tcg_gen_or_i32(dst
, dst
, t0
);
4198 tcg_gen_or_i32(dst
, dst
, t1
);
4199 tcg_temp_free_i32(t0
);
4200 tcg_temp_free_i32(t1
);
4202 tcg_gen_movi_tl(cpu_so
, 0);
4203 tcg_gen_movi_tl(cpu_ov
, 0);
4204 tcg_gen_movi_tl(cpu_ca
, 0);
4208 static void gen_mfcr(DisasContext
*ctx
)
4212 if (likely(ctx
->opcode
& 0x00100000)) {
4213 crm
= CRM(ctx
->opcode
);
4214 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
4216 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
4217 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
4218 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
4221 TCGv_i32 t0
= tcg_temp_new_i32();
4222 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
4223 tcg_gen_shli_i32(t0
, t0
, 4);
4224 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
4225 tcg_gen_shli_i32(t0
, t0
, 4);
4226 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
4227 tcg_gen_shli_i32(t0
, t0
, 4);
4228 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
4229 tcg_gen_shli_i32(t0
, t0
, 4);
4230 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
4231 tcg_gen_shli_i32(t0
, t0
, 4);
4232 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
4233 tcg_gen_shli_i32(t0
, t0
, 4);
4234 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
4235 tcg_gen_shli_i32(t0
, t0
, 4);
4236 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
4237 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4238 tcg_temp_free_i32(t0
);
4243 static void gen_mfmsr(DisasContext
*ctx
)
4245 #if defined(CONFIG_USER_ONLY)
4246 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4248 if (unlikely(ctx
->pr
)) {
4249 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4252 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
4256 static void spr_noaccess(DisasContext
*ctx
, int gprn
, int sprn
)
4259 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
4260 printf("ERROR: try to access SPR %d !\n", sprn
);
4263 #define SPR_NOACCESS (&spr_noaccess)
4266 static inline void gen_op_mfspr(DisasContext
*ctx
)
4268 void (*read_cb
)(DisasContext
*ctx
, int gprn
, int sprn
);
4269 uint32_t sprn
= SPR(ctx
->opcode
);
4271 #if !defined(CONFIG_USER_ONLY)
4273 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
4275 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
4278 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4279 if (likely(read_cb
!= NULL
)) {
4280 if (likely(read_cb
!= SPR_NOACCESS
)) {
4281 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
4283 /* Privilege exception */
4284 /* This is a hack to avoid warnings when running Linux:
4285 * this OS breaks the PowerPC virtualisation model,
4286 * allowing userland application to read the PVR
4288 if (sprn
!= SPR_PVR
) {
4289 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4290 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4291 printf("Trying to read privileged spr %d (0x%03x) at "
4292 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4294 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4298 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4299 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4300 printf("Trying to read invalid spr %d (0x%03x) at "
4301 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4302 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4306 static void gen_mfspr(DisasContext
*ctx
)
4312 static void gen_mftb(DisasContext
*ctx
)
4318 static void gen_mtcrf(DisasContext
*ctx
)
4322 crm
= CRM(ctx
->opcode
);
4323 if (likely((ctx
->opcode
& 0x00100000))) {
4324 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
4325 TCGv_i32 temp
= tcg_temp_new_i32();
4327 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4328 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
4329 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
4330 tcg_temp_free_i32(temp
);
4333 TCGv_i32 temp
= tcg_temp_new_i32();
4334 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4335 for (crn
= 0 ; crn
< 8 ; crn
++) {
4336 if (crm
& (1 << crn
)) {
4337 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
4338 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
4341 tcg_temp_free_i32(temp
);
4346 #if defined(TARGET_PPC64)
4347 static void gen_mtmsrd(DisasContext
*ctx
)
4349 #if defined(CONFIG_USER_ONLY)
4350 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4352 if (unlikely(ctx
->pr
)) {
4353 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4356 if (ctx
->opcode
& 0x00010000) {
4357 /* Special form that does not need any synchronisation */
4358 TCGv t0
= tcg_temp_new();
4359 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4360 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
4361 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4364 /* XXX: we need to update nip before the store
4365 * if we enter power saving mode, we will exit the loop
4366 * directly from ppc_store_msr
4368 gen_update_nip(ctx
, ctx
->nip
);
4369 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
4370 /* Must stop the translation as machine state (may have) changed */
4371 /* Note that mtmsr is not always defined as context-synchronizing */
4372 gen_stop_exception(ctx
);
4378 static void gen_mtmsr(DisasContext
*ctx
)
4380 #if defined(CONFIG_USER_ONLY)
4381 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4383 if (unlikely(ctx
->pr
)) {
4384 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4387 if (ctx
->opcode
& 0x00010000) {
4388 /* Special form that does not need any synchronisation */
4389 TCGv t0
= tcg_temp_new();
4390 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4391 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
4392 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4395 TCGv msr
= tcg_temp_new();
4397 /* XXX: we need to update nip before the store
4398 * if we enter power saving mode, we will exit the loop
4399 * directly from ppc_store_msr
4401 gen_update_nip(ctx
, ctx
->nip
);
4402 #if defined(TARGET_PPC64)
4403 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
4405 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
4407 gen_helper_store_msr(cpu_env
, msr
);
4409 /* Must stop the translation as machine state (may have) changed */
4410 /* Note that mtmsr is not always defined as context-synchronizing */
4411 gen_stop_exception(ctx
);
4417 static void gen_mtspr(DisasContext
*ctx
)
4419 void (*write_cb
)(DisasContext
*ctx
, int sprn
, int gprn
);
4420 uint32_t sprn
= SPR(ctx
->opcode
);
4422 #if !defined(CONFIG_USER_ONLY)
4424 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4426 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4429 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4430 if (likely(write_cb
!= NULL
)) {
4431 if (likely(write_cb
!= SPR_NOACCESS
)) {
4432 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4434 /* Privilege exception */
4435 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4436 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4437 printf("Trying to write privileged spr %d (0x%03x) at "
4438 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4439 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4443 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4444 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4445 printf("Trying to write invalid spr %d (0x%03x) at "
4446 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4447 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4451 /*** Cache management ***/
4454 static void gen_dcbf(DisasContext
*ctx
)
4456 /* XXX: specification says this is treated as a load by the MMU */
4458 gen_set_access_type(ctx
, ACCESS_CACHE
);
4459 t0
= tcg_temp_new();
4460 gen_addr_reg_index(ctx
, t0
);
4461 gen_qemu_ld8u(ctx
, t0
, t0
);
4465 /* dcbi (Supervisor only) */
4466 static void gen_dcbi(DisasContext
*ctx
)
4468 #if defined(CONFIG_USER_ONLY)
4469 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4472 if (unlikely(ctx
->pr
)) {
4473 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4476 EA
= tcg_temp_new();
4477 gen_set_access_type(ctx
, ACCESS_CACHE
);
4478 gen_addr_reg_index(ctx
, EA
);
4479 val
= tcg_temp_new();
4480 /* XXX: specification says this should be treated as a store by the MMU */
4481 gen_qemu_ld8u(ctx
, val
, EA
);
4482 gen_qemu_st8(ctx
, val
, EA
);
4489 static void gen_dcbst(DisasContext
*ctx
)
4491 /* XXX: specification say this is treated as a load by the MMU */
4493 gen_set_access_type(ctx
, ACCESS_CACHE
);
4494 t0
= tcg_temp_new();
4495 gen_addr_reg_index(ctx
, t0
);
4496 gen_qemu_ld8u(ctx
, t0
, t0
);
4501 static void gen_dcbt(DisasContext
*ctx
)
4503 /* interpreted as no-op */
4504 /* XXX: specification say this is treated as a load by the MMU
4505 * but does not generate any exception
4510 static void gen_dcbtst(DisasContext
*ctx
)
4512 /* interpreted as no-op */
4513 /* XXX: specification say this is treated as a load by the MMU
4514 * but does not generate any exception
4519 static void gen_dcbtls(DisasContext
*ctx
)
4521 /* Always fails locking the cache */
4522 TCGv t0
= tcg_temp_new();
4523 gen_load_spr(t0
, SPR_Exxx_L1CSR0
);
4524 tcg_gen_ori_tl(t0
, t0
, L1CSR0_CUL
);
4525 gen_store_spr(SPR_Exxx_L1CSR0
, t0
);
4530 static void gen_dcbz(DisasContext
*ctx
)
4533 TCGv_i32 tcgv_is_dcbzl
;
4534 int is_dcbzl
= ctx
->opcode
& 0x00200000 ? 1 : 0;
4536 gen_set_access_type(ctx
, ACCESS_CACHE
);
4537 /* NIP cannot be restored if the memory exception comes from an helper */
4538 gen_update_nip(ctx
, ctx
->nip
- 4);
4539 tcgv_addr
= tcg_temp_new();
4540 tcgv_is_dcbzl
= tcg_const_i32(is_dcbzl
);
4542 gen_addr_reg_index(ctx
, tcgv_addr
);
4543 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_is_dcbzl
);
4545 tcg_temp_free(tcgv_addr
);
4546 tcg_temp_free_i32(tcgv_is_dcbzl
);
4550 static void gen_dst(DisasContext
*ctx
)
4552 if (rA(ctx
->opcode
) == 0) {
4553 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4555 /* interpreted as no-op */
4560 static void gen_dstst(DisasContext
*ctx
)
4562 if (rA(ctx
->opcode
) == 0) {
4563 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4565 /* interpreted as no-op */
4571 static void gen_dss(DisasContext
*ctx
)
4573 /* interpreted as no-op */
4577 static void gen_icbi(DisasContext
*ctx
)
4580 gen_set_access_type(ctx
, ACCESS_CACHE
);
4581 /* NIP cannot be restored if the memory exception comes from an helper */
4582 gen_update_nip(ctx
, ctx
->nip
- 4);
4583 t0
= tcg_temp_new();
4584 gen_addr_reg_index(ctx
, t0
);
4585 gen_helper_icbi(cpu_env
, t0
);
4591 static void gen_dcba(DisasContext
*ctx
)
4593 /* interpreted as no-op */
4594 /* XXX: specification say this is treated as a store by the MMU
4595 * but does not generate any exception
4599 /*** Segment register manipulation ***/
4600 /* Supervisor only: */
4603 static void gen_mfsr(DisasContext
*ctx
)
4605 #if defined(CONFIG_USER_ONLY)
4606 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4609 if (unlikely(ctx
->pr
)) {
4610 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4613 t0
= tcg_const_tl(SR(ctx
->opcode
));
4614 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4620 static void gen_mfsrin(DisasContext
*ctx
)
4622 #if defined(CONFIG_USER_ONLY)
4623 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4626 if (unlikely(ctx
->pr
)) {
4627 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4630 t0
= tcg_temp_new();
4631 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4632 tcg_gen_andi_tl(t0
, t0
, 0xF);
4633 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4639 static void gen_mtsr(DisasContext
*ctx
)
4641 #if defined(CONFIG_USER_ONLY)
4642 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4645 if (unlikely(ctx
->pr
)) {
4646 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4649 t0
= tcg_const_tl(SR(ctx
->opcode
));
4650 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4656 static void gen_mtsrin(DisasContext
*ctx
)
4658 #if defined(CONFIG_USER_ONLY)
4659 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4662 if (unlikely(ctx
->pr
)) {
4663 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4666 t0
= tcg_temp_new();
4667 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4668 tcg_gen_andi_tl(t0
, t0
, 0xF);
4669 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4674 #if defined(TARGET_PPC64)
4675 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4678 static void gen_mfsr_64b(DisasContext
*ctx
)
4680 #if defined(CONFIG_USER_ONLY)
4681 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4684 if (unlikely(ctx
->pr
)) {
4685 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4688 t0
= tcg_const_tl(SR(ctx
->opcode
));
4689 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4695 static void gen_mfsrin_64b(DisasContext
*ctx
)
4697 #if defined(CONFIG_USER_ONLY)
4698 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4701 if (unlikely(ctx
->pr
)) {
4702 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4705 t0
= tcg_temp_new();
4706 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4707 tcg_gen_andi_tl(t0
, t0
, 0xF);
4708 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4714 static void gen_mtsr_64b(DisasContext
*ctx
)
4716 #if defined(CONFIG_USER_ONLY)
4717 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4720 if (unlikely(ctx
->pr
)) {
4721 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4724 t0
= tcg_const_tl(SR(ctx
->opcode
));
4725 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4731 static void gen_mtsrin_64b(DisasContext
*ctx
)
4733 #if defined(CONFIG_USER_ONLY)
4734 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4737 if (unlikely(ctx
->pr
)) {
4738 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4741 t0
= tcg_temp_new();
4742 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4743 tcg_gen_andi_tl(t0
, t0
, 0xF);
4744 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4750 static void gen_slbmte(DisasContext
*ctx
)
4752 #if defined(CONFIG_USER_ONLY)
4753 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4755 if (unlikely(ctx
->pr
)) {
4756 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4759 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4760 cpu_gpr
[rS(ctx
->opcode
)]);
4764 static void gen_slbmfee(DisasContext
*ctx
)
4766 #if defined(CONFIG_USER_ONLY)
4767 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4769 if (unlikely(ctx
->pr
)) {
4770 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4773 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4774 cpu_gpr
[rB(ctx
->opcode
)]);
4778 static void gen_slbmfev(DisasContext
*ctx
)
4780 #if defined(CONFIG_USER_ONLY)
4781 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4783 if (unlikely(ctx
->pr
)) {
4784 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4787 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4788 cpu_gpr
[rB(ctx
->opcode
)]);
4791 #endif /* defined(TARGET_PPC64) */
4793 /*** Lookaside buffer management ***/
4794 /* Optional & supervisor only: */
4797 static void gen_tlbia(DisasContext
*ctx
)
4799 #if defined(CONFIG_USER_ONLY)
4800 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4802 if (unlikely(ctx
->pr
)) {
4803 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4806 gen_helper_tlbia(cpu_env
);
4811 static void gen_tlbiel(DisasContext
*ctx
)
4813 #if defined(CONFIG_USER_ONLY)
4814 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4816 if (unlikely(ctx
->pr
)) {
4817 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4820 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4825 static void gen_tlbie(DisasContext
*ctx
)
4827 #if defined(CONFIG_USER_ONLY)
4828 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4830 if (unlikely(ctx
->pr
)) {
4831 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4834 if (NARROW_MODE(ctx
)) {
4835 TCGv t0
= tcg_temp_new();
4836 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4837 gen_helper_tlbie(cpu_env
, t0
);
4840 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4846 static void gen_tlbsync(DisasContext
*ctx
)
4848 #if defined(CONFIG_USER_ONLY)
4849 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4851 if (unlikely(ctx
->pr
)) {
4852 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4855 /* This has no effect: it should ensure that all previous
4856 * tlbie have completed
4858 gen_stop_exception(ctx
);
4862 #if defined(TARGET_PPC64)
4864 static void gen_slbia(DisasContext
*ctx
)
4866 #if defined(CONFIG_USER_ONLY)
4867 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4869 if (unlikely(ctx
->pr
)) {
4870 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4873 gen_helper_slbia(cpu_env
);
4878 static void gen_slbie(DisasContext
*ctx
)
4880 #if defined(CONFIG_USER_ONLY)
4881 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4883 if (unlikely(ctx
->pr
)) {
4884 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4887 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4892 /*** External control ***/
4896 static void gen_eciwx(DisasContext
*ctx
)
4899 /* Should check EAR[E] ! */
4900 gen_set_access_type(ctx
, ACCESS_EXT
);
4901 t0
= tcg_temp_new();
4902 gen_addr_reg_index(ctx
, t0
);
4903 gen_check_align(ctx
, t0
, 0x03);
4904 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4909 static void gen_ecowx(DisasContext
*ctx
)
4912 /* Should check EAR[E] ! */
4913 gen_set_access_type(ctx
, ACCESS_EXT
);
4914 t0
= tcg_temp_new();
4915 gen_addr_reg_index(ctx
, t0
);
4916 gen_check_align(ctx
, t0
, 0x03);
4917 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4921 /* PowerPC 601 specific instructions */
4924 static void gen_abs(DisasContext
*ctx
)
4926 int l1
= gen_new_label();
4927 int l2
= gen_new_label();
4928 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4929 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4932 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4934 if (unlikely(Rc(ctx
->opcode
) != 0))
4935 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4939 static void gen_abso(DisasContext
*ctx
)
4941 int l1
= gen_new_label();
4942 int l2
= gen_new_label();
4943 int l3
= gen_new_label();
4944 /* Start with XER OV disabled, the most likely case */
4945 tcg_gen_movi_tl(cpu_ov
, 0);
4946 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4947 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4948 tcg_gen_movi_tl(cpu_ov
, 1);
4949 tcg_gen_movi_tl(cpu_so
, 1);
4952 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4955 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4957 if (unlikely(Rc(ctx
->opcode
) != 0))
4958 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4962 static void gen_clcs(DisasContext
*ctx
)
4964 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4965 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4966 tcg_temp_free_i32(t0
);
4967 /* Rc=1 sets CR0 to an undefined state */
4971 static void gen_div(DisasContext
*ctx
)
4973 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4974 cpu_gpr
[rB(ctx
->opcode
)]);
4975 if (unlikely(Rc(ctx
->opcode
) != 0))
4976 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4980 static void gen_divo(DisasContext
*ctx
)
4982 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4983 cpu_gpr
[rB(ctx
->opcode
)]);
4984 if (unlikely(Rc(ctx
->opcode
) != 0))
4985 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4989 static void gen_divs(DisasContext
*ctx
)
4991 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4992 cpu_gpr
[rB(ctx
->opcode
)]);
4993 if (unlikely(Rc(ctx
->opcode
) != 0))
4994 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4997 /* divso - divso. */
4998 static void gen_divso(DisasContext
*ctx
)
5000 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5001 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5002 if (unlikely(Rc(ctx
->opcode
) != 0))
5003 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5007 static void gen_doz(DisasContext
*ctx
)
5009 int l1
= gen_new_label();
5010 int l2
= gen_new_label();
5011 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
5012 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5015 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5017 if (unlikely(Rc(ctx
->opcode
) != 0))
5018 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5022 static void gen_dozo(DisasContext
*ctx
)
5024 int l1
= gen_new_label();
5025 int l2
= gen_new_label();
5026 TCGv t0
= tcg_temp_new();
5027 TCGv t1
= tcg_temp_new();
5028 TCGv t2
= tcg_temp_new();
5029 /* Start with XER OV disabled, the most likely case */
5030 tcg_gen_movi_tl(cpu_ov
, 0);
5031 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
5032 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5033 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5034 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
5035 tcg_gen_andc_tl(t1
, t1
, t2
);
5036 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5037 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5038 tcg_gen_movi_tl(cpu_ov
, 1);
5039 tcg_gen_movi_tl(cpu_so
, 1);
5042 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5047 if (unlikely(Rc(ctx
->opcode
) != 0))
5048 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5052 static void gen_dozi(DisasContext
*ctx
)
5054 target_long simm
= SIMM(ctx
->opcode
);
5055 int l1
= gen_new_label();
5056 int l2
= gen_new_label();
5057 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
5058 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
5061 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5063 if (unlikely(Rc(ctx
->opcode
) != 0))
5064 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5067 /* lscbx - lscbx. */
5068 static void gen_lscbx(DisasContext
*ctx
)
5070 TCGv t0
= tcg_temp_new();
5071 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
5072 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
5073 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
5075 gen_addr_reg_index(ctx
, t0
);
5076 /* NIP cannot be restored if the memory exception comes from an helper */
5077 gen_update_nip(ctx
, ctx
->nip
- 4);
5078 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
5079 tcg_temp_free_i32(t1
);
5080 tcg_temp_free_i32(t2
);
5081 tcg_temp_free_i32(t3
);
5082 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
5083 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
5084 if (unlikely(Rc(ctx
->opcode
) != 0))
5085 gen_set_Rc0(ctx
, t0
);
5089 /* maskg - maskg. */
5090 static void gen_maskg(DisasContext
*ctx
)
5092 int l1
= gen_new_label();
5093 TCGv t0
= tcg_temp_new();
5094 TCGv t1
= tcg_temp_new();
5095 TCGv t2
= tcg_temp_new();
5096 TCGv t3
= tcg_temp_new();
5097 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
5098 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5099 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
5100 tcg_gen_addi_tl(t2
, t0
, 1);
5101 tcg_gen_shr_tl(t2
, t3
, t2
);
5102 tcg_gen_shr_tl(t3
, t3
, t1
);
5103 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
5104 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
5105 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5111 if (unlikely(Rc(ctx
->opcode
) != 0))
5112 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5115 /* maskir - maskir. */
5116 static void gen_maskir(DisasContext
*ctx
)
5118 TCGv t0
= tcg_temp_new();
5119 TCGv t1
= tcg_temp_new();
5120 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5121 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5122 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5125 if (unlikely(Rc(ctx
->opcode
) != 0))
5126 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5130 static void gen_mul(DisasContext
*ctx
)
5132 TCGv_i64 t0
= tcg_temp_new_i64();
5133 TCGv_i64 t1
= tcg_temp_new_i64();
5134 TCGv t2
= tcg_temp_new();
5135 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5136 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5137 tcg_gen_mul_i64(t0
, t0
, t1
);
5138 tcg_gen_trunc_i64_tl(t2
, t0
);
5139 gen_store_spr(SPR_MQ
, t2
);
5140 tcg_gen_shri_i64(t1
, t0
, 32);
5141 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5142 tcg_temp_free_i64(t0
);
5143 tcg_temp_free_i64(t1
);
5145 if (unlikely(Rc(ctx
->opcode
) != 0))
5146 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5150 static void gen_mulo(DisasContext
*ctx
)
5152 int l1
= gen_new_label();
5153 TCGv_i64 t0
= tcg_temp_new_i64();
5154 TCGv_i64 t1
= tcg_temp_new_i64();
5155 TCGv t2
= tcg_temp_new();
5156 /* Start with XER OV disabled, the most likely case */
5157 tcg_gen_movi_tl(cpu_ov
, 0);
5158 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5159 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5160 tcg_gen_mul_i64(t0
, t0
, t1
);
5161 tcg_gen_trunc_i64_tl(t2
, t0
);
5162 gen_store_spr(SPR_MQ
, t2
);
5163 tcg_gen_shri_i64(t1
, t0
, 32);
5164 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5165 tcg_gen_ext32s_i64(t1
, t0
);
5166 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
5167 tcg_gen_movi_tl(cpu_ov
, 1);
5168 tcg_gen_movi_tl(cpu_so
, 1);
5170 tcg_temp_free_i64(t0
);
5171 tcg_temp_free_i64(t1
);
5173 if (unlikely(Rc(ctx
->opcode
) != 0))
5174 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5178 static void gen_nabs(DisasContext
*ctx
)
5180 int l1
= gen_new_label();
5181 int l2
= gen_new_label();
5182 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5183 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5186 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5188 if (unlikely(Rc(ctx
->opcode
) != 0))
5189 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5192 /* nabso - nabso. */
5193 static void gen_nabso(DisasContext
*ctx
)
5195 int l1
= gen_new_label();
5196 int l2
= gen_new_label();
5197 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5198 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5201 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5203 /* nabs never overflows */
5204 tcg_gen_movi_tl(cpu_ov
, 0);
5205 if (unlikely(Rc(ctx
->opcode
) != 0))
5206 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5210 static void gen_rlmi(DisasContext
*ctx
)
5212 uint32_t mb
= MB(ctx
->opcode
);
5213 uint32_t me
= ME(ctx
->opcode
);
5214 TCGv t0
= tcg_temp_new();
5215 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5216 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5217 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
5218 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
5219 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
5221 if (unlikely(Rc(ctx
->opcode
) != 0))
5222 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5226 static void gen_rrib(DisasContext
*ctx
)
5228 TCGv t0
= tcg_temp_new();
5229 TCGv t1
= tcg_temp_new();
5230 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5231 tcg_gen_movi_tl(t1
, 0x80000000);
5232 tcg_gen_shr_tl(t1
, t1
, t0
);
5233 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5234 tcg_gen_and_tl(t0
, t0
, t1
);
5235 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
5236 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5239 if (unlikely(Rc(ctx
->opcode
) != 0))
5240 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5244 static void gen_sle(DisasContext
*ctx
)
5246 TCGv t0
= tcg_temp_new();
5247 TCGv t1
= tcg_temp_new();
5248 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5249 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5250 tcg_gen_subfi_tl(t1
, 32, t1
);
5251 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5252 tcg_gen_or_tl(t1
, t0
, t1
);
5253 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5254 gen_store_spr(SPR_MQ
, t1
);
5257 if (unlikely(Rc(ctx
->opcode
) != 0))
5258 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5262 static void gen_sleq(DisasContext
*ctx
)
5264 TCGv t0
= tcg_temp_new();
5265 TCGv t1
= tcg_temp_new();
5266 TCGv t2
= tcg_temp_new();
5267 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5268 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
5269 tcg_gen_shl_tl(t2
, t2
, t0
);
5270 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5271 gen_load_spr(t1
, SPR_MQ
);
5272 gen_store_spr(SPR_MQ
, t0
);
5273 tcg_gen_and_tl(t0
, t0
, t2
);
5274 tcg_gen_andc_tl(t1
, t1
, t2
);
5275 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5279 if (unlikely(Rc(ctx
->opcode
) != 0))
5280 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5284 static void gen_sliq(DisasContext
*ctx
)
5286 int sh
= SH(ctx
->opcode
);
5287 TCGv t0
= tcg_temp_new();
5288 TCGv t1
= tcg_temp_new();
5289 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5290 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5291 tcg_gen_or_tl(t1
, t0
, t1
);
5292 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5293 gen_store_spr(SPR_MQ
, t1
);
5296 if (unlikely(Rc(ctx
->opcode
) != 0))
5297 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5300 /* slliq - slliq. */
5301 static void gen_slliq(DisasContext
*ctx
)
5303 int sh
= SH(ctx
->opcode
);
5304 TCGv t0
= tcg_temp_new();
5305 TCGv t1
= tcg_temp_new();
5306 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5307 gen_load_spr(t1
, SPR_MQ
);
5308 gen_store_spr(SPR_MQ
, t0
);
5309 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
5310 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
5311 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5314 if (unlikely(Rc(ctx
->opcode
) != 0))
5315 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5319 static void gen_sllq(DisasContext
*ctx
)
5321 int l1
= gen_new_label();
5322 int l2
= gen_new_label();
5323 TCGv t0
= tcg_temp_local_new();
5324 TCGv t1
= tcg_temp_local_new();
5325 TCGv t2
= tcg_temp_local_new();
5326 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5327 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5328 tcg_gen_shl_tl(t1
, t1
, t2
);
5329 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5330 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5331 gen_load_spr(t0
, SPR_MQ
);
5332 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5335 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5336 gen_load_spr(t2
, SPR_MQ
);
5337 tcg_gen_andc_tl(t1
, t2
, t1
);
5338 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5343 if (unlikely(Rc(ctx
->opcode
) != 0))
5344 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5348 static void gen_slq(DisasContext
*ctx
)
5350 int l1
= gen_new_label();
5351 TCGv t0
= tcg_temp_new();
5352 TCGv t1
= tcg_temp_new();
5353 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5354 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5355 tcg_gen_subfi_tl(t1
, 32, t1
);
5356 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5357 tcg_gen_or_tl(t1
, t0
, t1
);
5358 gen_store_spr(SPR_MQ
, t1
);
5359 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5360 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5361 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5362 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5366 if (unlikely(Rc(ctx
->opcode
) != 0))
5367 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5370 /* sraiq - sraiq. */
5371 static void gen_sraiq(DisasContext
*ctx
)
5373 int sh
= SH(ctx
->opcode
);
5374 int l1
= gen_new_label();
5375 TCGv t0
= tcg_temp_new();
5376 TCGv t1
= tcg_temp_new();
5377 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5378 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5379 tcg_gen_or_tl(t0
, t0
, t1
);
5380 gen_store_spr(SPR_MQ
, t0
);
5381 tcg_gen_movi_tl(cpu_ca
, 0);
5382 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5383 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
5384 tcg_gen_movi_tl(cpu_ca
, 1);
5386 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
5389 if (unlikely(Rc(ctx
->opcode
) != 0))
5390 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5394 static void gen_sraq(DisasContext
*ctx
)
5396 int l1
= gen_new_label();
5397 int l2
= gen_new_label();
5398 TCGv t0
= tcg_temp_new();
5399 TCGv t1
= tcg_temp_local_new();
5400 TCGv t2
= tcg_temp_local_new();
5401 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5402 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5403 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5404 tcg_gen_subfi_tl(t2
, 32, t2
);
5405 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5406 tcg_gen_or_tl(t0
, t0
, t2
);
5407 gen_store_spr(SPR_MQ
, t0
);
5408 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5409 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
5410 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
5411 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5414 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5415 tcg_gen_movi_tl(cpu_ca
, 0);
5416 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5417 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5418 tcg_gen_movi_tl(cpu_ca
, 1);
5422 if (unlikely(Rc(ctx
->opcode
) != 0))
5423 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5427 static void gen_sre(DisasContext
*ctx
)
5429 TCGv t0
= tcg_temp_new();
5430 TCGv t1
= tcg_temp_new();
5431 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5432 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5433 tcg_gen_subfi_tl(t1
, 32, t1
);
5434 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5435 tcg_gen_or_tl(t1
, t0
, t1
);
5436 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5437 gen_store_spr(SPR_MQ
, t1
);
5440 if (unlikely(Rc(ctx
->opcode
) != 0))
5441 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5445 static void gen_srea(DisasContext
*ctx
)
5447 TCGv t0
= tcg_temp_new();
5448 TCGv t1
= tcg_temp_new();
5449 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5450 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5451 gen_store_spr(SPR_MQ
, t0
);
5452 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5455 if (unlikely(Rc(ctx
->opcode
) != 0))
5456 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5460 static void gen_sreq(DisasContext
*ctx
)
5462 TCGv t0
= tcg_temp_new();
5463 TCGv t1
= tcg_temp_new();
5464 TCGv t2
= tcg_temp_new();
5465 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5466 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5467 tcg_gen_shr_tl(t1
, t1
, t0
);
5468 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5469 gen_load_spr(t2
, SPR_MQ
);
5470 gen_store_spr(SPR_MQ
, t0
);
5471 tcg_gen_and_tl(t0
, t0
, t1
);
5472 tcg_gen_andc_tl(t2
, t2
, t1
);
5473 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5477 if (unlikely(Rc(ctx
->opcode
) != 0))
5478 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5482 static void gen_sriq(DisasContext
*ctx
)
5484 int sh
= SH(ctx
->opcode
);
5485 TCGv t0
= tcg_temp_new();
5486 TCGv t1
= tcg_temp_new();
5487 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5488 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5489 tcg_gen_or_tl(t1
, t0
, t1
);
5490 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5491 gen_store_spr(SPR_MQ
, t1
);
5494 if (unlikely(Rc(ctx
->opcode
) != 0))
5495 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5499 static void gen_srliq(DisasContext
*ctx
)
5501 int sh
= SH(ctx
->opcode
);
5502 TCGv t0
= tcg_temp_new();
5503 TCGv t1
= tcg_temp_new();
5504 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5505 gen_load_spr(t1
, SPR_MQ
);
5506 gen_store_spr(SPR_MQ
, t0
);
5507 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5508 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5509 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5512 if (unlikely(Rc(ctx
->opcode
) != 0))
5513 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5517 static void gen_srlq(DisasContext
*ctx
)
5519 int l1
= gen_new_label();
5520 int l2
= gen_new_label();
5521 TCGv t0
= tcg_temp_local_new();
5522 TCGv t1
= tcg_temp_local_new();
5523 TCGv t2
= tcg_temp_local_new();
5524 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5525 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5526 tcg_gen_shr_tl(t2
, t1
, t2
);
5527 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5528 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5529 gen_load_spr(t0
, SPR_MQ
);
5530 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5533 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5534 tcg_gen_and_tl(t0
, t0
, t2
);
5535 gen_load_spr(t1
, SPR_MQ
);
5536 tcg_gen_andc_tl(t1
, t1
, t2
);
5537 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5542 if (unlikely(Rc(ctx
->opcode
) != 0))
5543 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5547 static void gen_srq(DisasContext
*ctx
)
5549 int l1
= gen_new_label();
5550 TCGv t0
= tcg_temp_new();
5551 TCGv t1
= tcg_temp_new();
5552 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5553 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5554 tcg_gen_subfi_tl(t1
, 32, t1
);
5555 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5556 tcg_gen_or_tl(t1
, t0
, t1
);
5557 gen_store_spr(SPR_MQ
, t1
);
5558 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5559 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5560 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5561 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5565 if (unlikely(Rc(ctx
->opcode
) != 0))
5566 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5569 /* PowerPC 602 specific instructions */
5572 static void gen_dsa(DisasContext
*ctx
)
5575 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5579 static void gen_esa(DisasContext
*ctx
)
5582 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5586 static void gen_mfrom(DisasContext
*ctx
)
5588 #if defined(CONFIG_USER_ONLY)
5589 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5591 if (unlikely(ctx
->pr
)) {
5592 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5595 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5599 /* 602 - 603 - G2 TLB management */
5602 static void gen_tlbld_6xx(DisasContext
*ctx
)
5604 #if defined(CONFIG_USER_ONLY)
5605 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5607 if (unlikely(ctx
->pr
)) {
5608 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5611 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5616 static void gen_tlbli_6xx(DisasContext
*ctx
)
5618 #if defined(CONFIG_USER_ONLY)
5619 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5621 if (unlikely(ctx
->pr
)) {
5622 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5625 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5629 /* 74xx TLB management */
5632 static void gen_tlbld_74xx(DisasContext
*ctx
)
5634 #if defined(CONFIG_USER_ONLY)
5635 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5637 if (unlikely(ctx
->pr
)) {
5638 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5641 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5646 static void gen_tlbli_74xx(DisasContext
*ctx
)
5648 #if defined(CONFIG_USER_ONLY)
5649 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5651 if (unlikely(ctx
->pr
)) {
5652 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5655 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5659 /* POWER instructions not in PowerPC 601 */
5662 static void gen_clf(DisasContext
*ctx
)
5664 /* Cache line flush: implemented as no-op */
5668 static void gen_cli(DisasContext
*ctx
)
5670 /* Cache line invalidate: privileged and treated as no-op */
5671 #if defined(CONFIG_USER_ONLY)
5672 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5674 if (unlikely(ctx
->pr
)) {
5675 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5682 static void gen_dclst(DisasContext
*ctx
)
5684 /* Data cache line store: treated as no-op */
5687 static void gen_mfsri(DisasContext
*ctx
)
5689 #if defined(CONFIG_USER_ONLY)
5690 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5692 int ra
= rA(ctx
->opcode
);
5693 int rd
= rD(ctx
->opcode
);
5695 if (unlikely(ctx
->pr
)) {
5696 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5699 t0
= tcg_temp_new();
5700 gen_addr_reg_index(ctx
, t0
);
5701 tcg_gen_shri_tl(t0
, t0
, 28);
5702 tcg_gen_andi_tl(t0
, t0
, 0xF);
5703 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5705 if (ra
!= 0 && ra
!= rd
)
5706 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5710 static void gen_rac(DisasContext
*ctx
)
5712 #if defined(CONFIG_USER_ONLY)
5713 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5716 if (unlikely(ctx
->pr
)) {
5717 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5720 t0
= tcg_temp_new();
5721 gen_addr_reg_index(ctx
, t0
);
5722 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5727 static void gen_rfsvc(DisasContext
*ctx
)
5729 #if defined(CONFIG_USER_ONLY)
5730 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5732 if (unlikely(ctx
->pr
)) {
5733 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5736 gen_helper_rfsvc(cpu_env
);
5737 gen_sync_exception(ctx
);
5741 /* svc is not implemented for now */
5743 /* POWER2 specific instructions */
5744 /* Quad manipulation (load/store two floats at a time) */
5747 static void gen_lfq(DisasContext
*ctx
)
5749 int rd
= rD(ctx
->opcode
);
5751 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5752 t0
= tcg_temp_new();
5753 gen_addr_imm_index(ctx
, t0
, 0);
5754 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5755 gen_addr_add(ctx
, t0
, t0
, 8);
5756 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5761 static void gen_lfqu(DisasContext
*ctx
)
5763 int ra
= rA(ctx
->opcode
);
5764 int rd
= rD(ctx
->opcode
);
5766 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5767 t0
= tcg_temp_new();
5768 t1
= tcg_temp_new();
5769 gen_addr_imm_index(ctx
, t0
, 0);
5770 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5771 gen_addr_add(ctx
, t1
, t0
, 8);
5772 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5774 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5780 static void gen_lfqux(DisasContext
*ctx
)
5782 int ra
= rA(ctx
->opcode
);
5783 int rd
= rD(ctx
->opcode
);
5784 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5786 t0
= tcg_temp_new();
5787 gen_addr_reg_index(ctx
, t0
);
5788 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5789 t1
= tcg_temp_new();
5790 gen_addr_add(ctx
, t1
, t0
, 8);
5791 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5794 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5799 static void gen_lfqx(DisasContext
*ctx
)
5801 int rd
= rD(ctx
->opcode
);
5803 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5804 t0
= tcg_temp_new();
5805 gen_addr_reg_index(ctx
, t0
);
5806 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5807 gen_addr_add(ctx
, t0
, t0
, 8);
5808 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5813 static void gen_stfq(DisasContext
*ctx
)
5815 int rd
= rD(ctx
->opcode
);
5817 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5818 t0
= tcg_temp_new();
5819 gen_addr_imm_index(ctx
, t0
, 0);
5820 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5821 gen_addr_add(ctx
, t0
, t0
, 8);
5822 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5827 static void gen_stfqu(DisasContext
*ctx
)
5829 int ra
= rA(ctx
->opcode
);
5830 int rd
= rD(ctx
->opcode
);
5832 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5833 t0
= tcg_temp_new();
5834 gen_addr_imm_index(ctx
, t0
, 0);
5835 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5836 t1
= tcg_temp_new();
5837 gen_addr_add(ctx
, t1
, t0
, 8);
5838 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5841 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5846 static void gen_stfqux(DisasContext
*ctx
)
5848 int ra
= rA(ctx
->opcode
);
5849 int rd
= rD(ctx
->opcode
);
5851 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5852 t0
= tcg_temp_new();
5853 gen_addr_reg_index(ctx
, t0
);
5854 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5855 t1
= tcg_temp_new();
5856 gen_addr_add(ctx
, t1
, t0
, 8);
5857 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5860 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5865 static void gen_stfqx(DisasContext
*ctx
)
5867 int rd
= rD(ctx
->opcode
);
5869 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5870 t0
= tcg_temp_new();
5871 gen_addr_reg_index(ctx
, t0
);
5872 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5873 gen_addr_add(ctx
, t0
, t0
, 8);
5874 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5878 /* BookE specific instructions */
5880 /* XXX: not implemented on 440 ? */
5881 static void gen_mfapidi(DisasContext
*ctx
)
5884 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5887 /* XXX: not implemented on 440 ? */
5888 static void gen_tlbiva(DisasContext
*ctx
)
5890 #if defined(CONFIG_USER_ONLY)
5891 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5894 if (unlikely(ctx
->pr
)) {
5895 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5898 t0
= tcg_temp_new();
5899 gen_addr_reg_index(ctx
, t0
);
5900 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5905 /* All 405 MAC instructions are translated here */
5906 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5907 int ra
, int rb
, int rt
, int Rc
)
5911 t0
= tcg_temp_local_new();
5912 t1
= tcg_temp_local_new();
5914 switch (opc3
& 0x0D) {
5916 /* macchw - macchw. - macchwo - macchwo. */
5917 /* macchws - macchws. - macchwso - macchwso. */
5918 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5919 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5920 /* mulchw - mulchw. */
5921 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5922 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5923 tcg_gen_ext16s_tl(t1
, t1
);
5926 /* macchwu - macchwu. - macchwuo - macchwuo. */
5927 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5928 /* mulchwu - mulchwu. */
5929 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5930 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5931 tcg_gen_ext16u_tl(t1
, t1
);
5934 /* machhw - machhw. - machhwo - machhwo. */
5935 /* machhws - machhws. - machhwso - machhwso. */
5936 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5937 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5938 /* mulhhw - mulhhw. */
5939 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5940 tcg_gen_ext16s_tl(t0
, t0
);
5941 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5942 tcg_gen_ext16s_tl(t1
, t1
);
5945 /* machhwu - machhwu. - machhwuo - machhwuo. */
5946 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5947 /* mulhhwu - mulhhwu. */
5948 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5949 tcg_gen_ext16u_tl(t0
, t0
);
5950 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5951 tcg_gen_ext16u_tl(t1
, t1
);
5954 /* maclhw - maclhw. - maclhwo - maclhwo. */
5955 /* maclhws - maclhws. - maclhwso - maclhwso. */
5956 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5957 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5958 /* mullhw - mullhw. */
5959 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5960 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5963 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5964 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5965 /* mullhwu - mullhwu. */
5966 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5967 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5971 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5972 tcg_gen_mul_tl(t1
, t0
, t1
);
5974 /* nmultiply-and-accumulate (0x0E) */
5975 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5977 /* multiply-and-accumulate (0x0C) */
5978 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5982 /* Check overflow and/or saturate */
5983 int l1
= gen_new_label();
5986 /* Start with XER OV disabled, the most likely case */
5987 tcg_gen_movi_tl(cpu_ov
, 0);
5991 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5992 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5993 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5994 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5997 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5998 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
6002 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
6005 tcg_gen_movi_tl(t0
, UINT32_MAX
);
6009 /* Check overflow */
6010 tcg_gen_movi_tl(cpu_ov
, 1);
6011 tcg_gen_movi_tl(cpu_so
, 1);
6014 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
6017 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
6021 if (unlikely(Rc
) != 0) {
6023 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
6027 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6028 static void glue(gen_, name)(DisasContext *ctx) \
6030 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6031 rD(ctx->opcode), Rc(ctx->opcode)); \
6034 /* macchw - macchw. */
6035 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
6036 /* macchwo - macchwo. */
6037 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
6038 /* macchws - macchws. */
6039 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
6040 /* macchwso - macchwso. */
6041 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
6042 /* macchwsu - macchwsu. */
6043 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
6044 /* macchwsuo - macchwsuo. */
6045 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
6046 /* macchwu - macchwu. */
6047 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
6048 /* macchwuo - macchwuo. */
6049 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
6050 /* machhw - machhw. */
6051 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
6052 /* machhwo - machhwo. */
6053 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
6054 /* machhws - machhws. */
6055 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
6056 /* machhwso - machhwso. */
6057 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
6058 /* machhwsu - machhwsu. */
6059 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
6060 /* machhwsuo - machhwsuo. */
6061 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
6062 /* machhwu - machhwu. */
6063 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
6064 /* machhwuo - machhwuo. */
6065 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
6066 /* maclhw - maclhw. */
6067 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
6068 /* maclhwo - maclhwo. */
6069 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
6070 /* maclhws - maclhws. */
6071 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
6072 /* maclhwso - maclhwso. */
6073 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
6074 /* maclhwu - maclhwu. */
6075 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
6076 /* maclhwuo - maclhwuo. */
6077 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
6078 /* maclhwsu - maclhwsu. */
6079 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
6080 /* maclhwsuo - maclhwsuo. */
6081 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
6082 /* nmacchw - nmacchw. */
6083 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
6084 /* nmacchwo - nmacchwo. */
6085 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
6086 /* nmacchws - nmacchws. */
6087 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
6088 /* nmacchwso - nmacchwso. */
6089 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
6090 /* nmachhw - nmachhw. */
6091 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
6092 /* nmachhwo - nmachhwo. */
6093 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
6094 /* nmachhws - nmachhws. */
6095 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
6096 /* nmachhwso - nmachhwso. */
6097 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
6098 /* nmaclhw - nmaclhw. */
6099 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
6100 /* nmaclhwo - nmaclhwo. */
6101 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
6102 /* nmaclhws - nmaclhws. */
6103 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
6104 /* nmaclhwso - nmaclhwso. */
6105 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
6107 /* mulchw - mulchw. */
6108 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
6109 /* mulchwu - mulchwu. */
6110 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
6111 /* mulhhw - mulhhw. */
6112 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
6113 /* mulhhwu - mulhhwu. */
6114 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
6115 /* mullhw - mullhw. */
6116 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
6117 /* mullhwu - mullhwu. */
6118 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
6121 static void gen_mfdcr(DisasContext
*ctx
)
6123 #if defined(CONFIG_USER_ONLY)
6124 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6127 if (unlikely(ctx
->pr
)) {
6128 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6131 /* NIP cannot be restored if the memory exception comes from an helper */
6132 gen_update_nip(ctx
, ctx
->nip
- 4);
6133 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6134 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
6135 tcg_temp_free(dcrn
);
6140 static void gen_mtdcr(DisasContext
*ctx
)
6142 #if defined(CONFIG_USER_ONLY)
6143 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6146 if (unlikely(ctx
->pr
)) {
6147 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6150 /* NIP cannot be restored if the memory exception comes from an helper */
6151 gen_update_nip(ctx
, ctx
->nip
- 4);
6152 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6153 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
6154 tcg_temp_free(dcrn
);
6159 /* XXX: not implemented on 440 ? */
6160 static void gen_mfdcrx(DisasContext
*ctx
)
6162 #if defined(CONFIG_USER_ONLY)
6163 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6165 if (unlikely(ctx
->pr
)) {
6166 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6169 /* NIP cannot be restored if the memory exception comes from an helper */
6170 gen_update_nip(ctx
, ctx
->nip
- 4);
6171 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6172 cpu_gpr
[rA(ctx
->opcode
)]);
6173 /* Note: Rc update flag set leads to undefined state of Rc0 */
6178 /* XXX: not implemented on 440 ? */
6179 static void gen_mtdcrx(DisasContext
*ctx
)
6181 #if defined(CONFIG_USER_ONLY)
6182 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6184 if (unlikely(ctx
->pr
)) {
6185 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6188 /* NIP cannot be restored if the memory exception comes from an helper */
6189 gen_update_nip(ctx
, ctx
->nip
- 4);
6190 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6191 cpu_gpr
[rS(ctx
->opcode
)]);
6192 /* Note: Rc update flag set leads to undefined state of Rc0 */
6196 /* mfdcrux (PPC 460) : user-mode access to DCR */
6197 static void gen_mfdcrux(DisasContext
*ctx
)
6199 /* NIP cannot be restored if the memory exception comes from an helper */
6200 gen_update_nip(ctx
, ctx
->nip
- 4);
6201 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6202 cpu_gpr
[rA(ctx
->opcode
)]);
6203 /* Note: Rc update flag set leads to undefined state of Rc0 */
6206 /* mtdcrux (PPC 460) : user-mode access to DCR */
6207 static void gen_mtdcrux(DisasContext
*ctx
)
6209 /* NIP cannot be restored if the memory exception comes from an helper */
6210 gen_update_nip(ctx
, ctx
->nip
- 4);
6211 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6212 cpu_gpr
[rS(ctx
->opcode
)]);
6213 /* Note: Rc update flag set leads to undefined state of Rc0 */
6217 static void gen_dccci(DisasContext
*ctx
)
6219 #if defined(CONFIG_USER_ONLY)
6220 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6222 if (unlikely(ctx
->pr
)) {
6223 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6226 /* interpreted as no-op */
6231 static void gen_dcread(DisasContext
*ctx
)
6233 #if defined(CONFIG_USER_ONLY)
6234 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6237 if (unlikely(ctx
->pr
)) {
6238 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6241 gen_set_access_type(ctx
, ACCESS_CACHE
);
6242 EA
= tcg_temp_new();
6243 gen_addr_reg_index(ctx
, EA
);
6244 val
= tcg_temp_new();
6245 gen_qemu_ld32u(ctx
, val
, EA
);
6247 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
6253 static void gen_icbt_40x(DisasContext
*ctx
)
6255 /* interpreted as no-op */
6256 /* XXX: specification say this is treated as a load by the MMU
6257 * but does not generate any exception
6262 static void gen_iccci(DisasContext
*ctx
)
6264 #if defined(CONFIG_USER_ONLY)
6265 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6267 if (unlikely(ctx
->pr
)) {
6268 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6271 /* interpreted as no-op */
6276 static void gen_icread(DisasContext
*ctx
)
6278 #if defined(CONFIG_USER_ONLY)
6279 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6281 if (unlikely(ctx
->pr
)) {
6282 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6285 /* interpreted as no-op */
6289 /* rfci (supervisor only) */
6290 static void gen_rfci_40x(DisasContext
*ctx
)
6292 #if defined(CONFIG_USER_ONLY)
6293 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6295 if (unlikely(ctx
->pr
)) {
6296 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6299 /* Restore CPU state */
6300 gen_helper_40x_rfci(cpu_env
);
6301 gen_sync_exception(ctx
);
6305 static void gen_rfci(DisasContext
*ctx
)
6307 #if defined(CONFIG_USER_ONLY)
6308 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6310 if (unlikely(ctx
->pr
)) {
6311 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6314 /* Restore CPU state */
6315 gen_helper_rfci(cpu_env
);
6316 gen_sync_exception(ctx
);
6320 /* BookE specific */
6322 /* XXX: not implemented on 440 ? */
6323 static void gen_rfdi(DisasContext
*ctx
)
6325 #if defined(CONFIG_USER_ONLY)
6326 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6328 if (unlikely(ctx
->pr
)) {
6329 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6332 /* Restore CPU state */
6333 gen_helper_rfdi(cpu_env
);
6334 gen_sync_exception(ctx
);
6338 /* XXX: not implemented on 440 ? */
6339 static void gen_rfmci(DisasContext
*ctx
)
6341 #if defined(CONFIG_USER_ONLY)
6342 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6344 if (unlikely(ctx
->pr
)) {
6345 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6348 /* Restore CPU state */
6349 gen_helper_rfmci(cpu_env
);
6350 gen_sync_exception(ctx
);
6354 /* TLB management - PowerPC 405 implementation */
6357 static void gen_tlbre_40x(DisasContext
*ctx
)
6359 #if defined(CONFIG_USER_ONLY)
6360 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6362 if (unlikely(ctx
->pr
)) {
6363 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6366 switch (rB(ctx
->opcode
)) {
6368 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6369 cpu_gpr
[rA(ctx
->opcode
)]);
6372 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6373 cpu_gpr
[rA(ctx
->opcode
)]);
6376 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6382 /* tlbsx - tlbsx. */
6383 static void gen_tlbsx_40x(DisasContext
*ctx
)
6385 #if defined(CONFIG_USER_ONLY)
6386 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6389 if (unlikely(ctx
->pr
)) {
6390 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6393 t0
= tcg_temp_new();
6394 gen_addr_reg_index(ctx
, t0
);
6395 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6397 if (Rc(ctx
->opcode
)) {
6398 int l1
= gen_new_label();
6399 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6400 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6401 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6408 static void gen_tlbwe_40x(DisasContext
*ctx
)
6410 #if defined(CONFIG_USER_ONLY)
6411 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6413 if (unlikely(ctx
->pr
)) {
6414 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6417 switch (rB(ctx
->opcode
)) {
6419 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6420 cpu_gpr
[rS(ctx
->opcode
)]);
6423 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6424 cpu_gpr
[rS(ctx
->opcode
)]);
6427 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6433 /* TLB management - PowerPC 440 implementation */
6436 static void gen_tlbre_440(DisasContext
*ctx
)
6438 #if defined(CONFIG_USER_ONLY)
6439 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6441 if (unlikely(ctx
->pr
)) {
6442 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6445 switch (rB(ctx
->opcode
)) {
6450 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6451 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6452 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
6453 tcg_temp_free_i32(t0
);
6457 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6463 /* tlbsx - tlbsx. */
6464 static void gen_tlbsx_440(DisasContext
*ctx
)
6466 #if defined(CONFIG_USER_ONLY)
6467 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6470 if (unlikely(ctx
->pr
)) {
6471 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6474 t0
= tcg_temp_new();
6475 gen_addr_reg_index(ctx
, t0
);
6476 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6478 if (Rc(ctx
->opcode
)) {
6479 int l1
= gen_new_label();
6480 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6481 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6482 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6489 static void gen_tlbwe_440(DisasContext
*ctx
)
6491 #if defined(CONFIG_USER_ONLY)
6492 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6494 if (unlikely(ctx
->pr
)) {
6495 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6498 switch (rB(ctx
->opcode
)) {
6503 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6504 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
6505 cpu_gpr
[rS(ctx
->opcode
)]);
6506 tcg_temp_free_i32(t0
);
6510 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6516 /* TLB management - PowerPC BookE 2.06 implementation */
6519 static void gen_tlbre_booke206(DisasContext
*ctx
)
6521 #if defined(CONFIG_USER_ONLY)
6522 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6524 if (unlikely(ctx
->pr
)) {
6525 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6529 gen_helper_booke206_tlbre(cpu_env
);
6533 /* tlbsx - tlbsx. */
6534 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6536 #if defined(CONFIG_USER_ONLY)
6537 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6540 if (unlikely(ctx
->pr
)) {
6541 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6545 if (rA(ctx
->opcode
)) {
6546 t0
= tcg_temp_new();
6547 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6549 t0
= tcg_const_tl(0);
6552 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6553 gen_helper_booke206_tlbsx(cpu_env
, t0
);
6559 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6561 #if defined(CONFIG_USER_ONLY)
6562 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6564 if (unlikely(ctx
->pr
)) {
6565 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6568 gen_update_nip(ctx
, ctx
->nip
- 4);
6569 gen_helper_booke206_tlbwe(cpu_env
);
6573 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6575 #if defined(CONFIG_USER_ONLY)
6576 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6579 if (unlikely(ctx
->pr
)) {
6580 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6584 t0
= tcg_temp_new();
6585 gen_addr_reg_index(ctx
, t0
);
6587 gen_helper_booke206_tlbivax(cpu_env
, t0
);
6592 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6594 #if defined(CONFIG_USER_ONLY)
6595 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6598 if (unlikely(ctx
->pr
)) {
6599 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6603 t0
= tcg_temp_new();
6604 gen_addr_reg_index(ctx
, t0
);
6606 switch((ctx
->opcode
>> 21) & 0x3) {
6608 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
6611 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
6614 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
6617 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6627 static void gen_wrtee(DisasContext
*ctx
)
6629 #if defined(CONFIG_USER_ONLY)
6630 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6633 if (unlikely(ctx
->pr
)) {
6634 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6637 t0
= tcg_temp_new();
6638 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6639 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6640 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6642 /* Stop translation to have a chance to raise an exception
6643 * if we just set msr_ee to 1
6645 gen_stop_exception(ctx
);
6650 static void gen_wrteei(DisasContext
*ctx
)
6652 #if defined(CONFIG_USER_ONLY)
6653 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6655 if (unlikely(ctx
->pr
)) {
6656 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6659 if (ctx
->opcode
& 0x00008000) {
6660 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6661 /* Stop translation to have a chance to raise an exception */
6662 gen_stop_exception(ctx
);
6664 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6669 /* PowerPC 440 specific instructions */
6672 static void gen_dlmzb(DisasContext
*ctx
)
6674 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6675 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6676 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6677 tcg_temp_free_i32(t0
);
6680 /* mbar replaces eieio on 440 */
6681 static void gen_mbar(DisasContext
*ctx
)
6683 /* interpreted as no-op */
6686 /* msync replaces sync on 440 */
6687 static void gen_msync_4xx(DisasContext
*ctx
)
6689 /* interpreted as no-op */
6693 static void gen_icbt_440(DisasContext
*ctx
)
6695 /* interpreted as no-op */
6696 /* XXX: specification say this is treated as a load by the MMU
6697 * but does not generate any exception
6701 /* Embedded.Processor Control */
6703 static void gen_msgclr(DisasContext
*ctx
)
6705 #if defined(CONFIG_USER_ONLY)
6706 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6708 if (unlikely(ctx
->pr
)) {
6709 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6713 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6717 static void gen_msgsnd(DisasContext
*ctx
)
6719 #if defined(CONFIG_USER_ONLY)
6720 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6722 if (unlikely(ctx
->pr
)) {
6723 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6727 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6731 /*** Altivec vector extension ***/
6732 /* Altivec registers moves */
6734 static inline TCGv_ptr
gen_avr_ptr(int reg
)
6736 TCGv_ptr r
= tcg_temp_new_ptr();
6737 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, avr
[reg
]));
6741 #define GEN_VR_LDX(name, opc2, opc3) \
6742 static void glue(gen_, name)(DisasContext *ctx) \
6745 if (unlikely(!ctx->altivec_enabled)) { \
6746 gen_exception(ctx, POWERPC_EXCP_VPU); \
6749 gen_set_access_type(ctx, ACCESS_INT); \
6750 EA = tcg_temp_new(); \
6751 gen_addr_reg_index(ctx, EA); \
6752 tcg_gen_andi_tl(EA, EA, ~0xf); \
6753 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6754 64-bit byteswap already. */ \
6755 if (ctx->le_mode) { \
6756 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6757 tcg_gen_addi_tl(EA, EA, 8); \
6758 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6760 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6761 tcg_gen_addi_tl(EA, EA, 8); \
6762 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6764 tcg_temp_free(EA); \
6767 #define GEN_VR_STX(name, opc2, opc3) \
6768 static void gen_st##name(DisasContext *ctx) \
6771 if (unlikely(!ctx->altivec_enabled)) { \
6772 gen_exception(ctx, POWERPC_EXCP_VPU); \
6775 gen_set_access_type(ctx, ACCESS_INT); \
6776 EA = tcg_temp_new(); \
6777 gen_addr_reg_index(ctx, EA); \
6778 tcg_gen_andi_tl(EA, EA, ~0xf); \
6779 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6780 64-bit byteswap already. */ \
6781 if (ctx->le_mode) { \
6782 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6783 tcg_gen_addi_tl(EA, EA, 8); \
6784 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6786 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6787 tcg_gen_addi_tl(EA, EA, 8); \
6788 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6790 tcg_temp_free(EA); \
6793 #define GEN_VR_LVE(name, opc2, opc3, size) \
6794 static void gen_lve##name(DisasContext *ctx) \
6798 if (unlikely(!ctx->altivec_enabled)) { \
6799 gen_exception(ctx, POWERPC_EXCP_VPU); \
6802 gen_set_access_type(ctx, ACCESS_INT); \
6803 EA = tcg_temp_new(); \
6804 gen_addr_reg_index(ctx, EA); \
6806 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6808 rs = gen_avr_ptr(rS(ctx->opcode)); \
6809 gen_helper_lve##name(cpu_env, rs, EA); \
6810 tcg_temp_free(EA); \
6811 tcg_temp_free_ptr(rs); \
6814 #define GEN_VR_STVE(name, opc2, opc3, size) \
6815 static void gen_stve##name(DisasContext *ctx) \
6819 if (unlikely(!ctx->altivec_enabled)) { \
6820 gen_exception(ctx, POWERPC_EXCP_VPU); \
6823 gen_set_access_type(ctx, ACCESS_INT); \
6824 EA = tcg_temp_new(); \
6825 gen_addr_reg_index(ctx, EA); \
6827 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6829 rs = gen_avr_ptr(rS(ctx->opcode)); \
6830 gen_helper_stve##name(cpu_env, rs, EA); \
6831 tcg_temp_free(EA); \
6832 tcg_temp_free_ptr(rs); \
6835 GEN_VR_LDX(lvx
, 0x07, 0x03);
6836 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6837 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
6839 GEN_VR_LVE(bx
, 0x07, 0x00, 1);
6840 GEN_VR_LVE(hx
, 0x07, 0x01, 2);
6841 GEN_VR_LVE(wx
, 0x07, 0x02, 4);
6843 GEN_VR_STX(svx
, 0x07, 0x07);
6844 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6845 GEN_VR_STX(svxl
, 0x07, 0x0F);
6847 GEN_VR_STVE(bx
, 0x07, 0x04, 1);
6848 GEN_VR_STVE(hx
, 0x07, 0x05, 2);
6849 GEN_VR_STVE(wx
, 0x07, 0x06, 4);
6851 static void gen_lvsl(DisasContext
*ctx
)
6855 if (unlikely(!ctx
->altivec_enabled
)) {
6856 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6859 EA
= tcg_temp_new();
6860 gen_addr_reg_index(ctx
, EA
);
6861 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6862 gen_helper_lvsl(rd
, EA
);
6864 tcg_temp_free_ptr(rd
);
6867 static void gen_lvsr(DisasContext
*ctx
)
6871 if (unlikely(!ctx
->altivec_enabled
)) {
6872 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6875 EA
= tcg_temp_new();
6876 gen_addr_reg_index(ctx
, EA
);
6877 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6878 gen_helper_lvsr(rd
, EA
);
6880 tcg_temp_free_ptr(rd
);
6883 static void gen_mfvscr(DisasContext
*ctx
)
6886 if (unlikely(!ctx
->altivec_enabled
)) {
6887 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6890 tcg_gen_movi_i64(cpu_avrh
[rD(ctx
->opcode
)], 0);
6891 t
= tcg_temp_new_i32();
6892 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, vscr
));
6893 tcg_gen_extu_i32_i64(cpu_avrl
[rD(ctx
->opcode
)], t
);
6894 tcg_temp_free_i32(t
);
6897 static void gen_mtvscr(DisasContext
*ctx
)
6900 if (unlikely(!ctx
->altivec_enabled
)) {
6901 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6904 p
= gen_avr_ptr(rB(ctx
->opcode
));
6905 gen_helper_mtvscr(cpu_env
, p
);
6906 tcg_temp_free_ptr(p
);
6909 /* Logical operations */
6910 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6911 static void glue(gen_, name)(DisasContext *ctx) \
6913 if (unlikely(!ctx->altivec_enabled)) { \
6914 gen_exception(ctx, POWERPC_EXCP_VPU); \
6917 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6918 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6921 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16);
6922 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17);
6923 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18);
6924 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19);
6925 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20);
6926 GEN_VX_LOGICAL(veqv
, tcg_gen_eqv_i64
, 2, 26);
6927 GEN_VX_LOGICAL(vnand
, tcg_gen_nand_i64
, 2, 22);
6928 GEN_VX_LOGICAL(vorc
, tcg_gen_orc_i64
, 2, 21);
6930 #define GEN_VXFORM(name, opc2, opc3) \
6931 static void glue(gen_, name)(DisasContext *ctx) \
6933 TCGv_ptr ra, rb, rd; \
6934 if (unlikely(!ctx->altivec_enabled)) { \
6935 gen_exception(ctx, POWERPC_EXCP_VPU); \
6938 ra = gen_avr_ptr(rA(ctx->opcode)); \
6939 rb = gen_avr_ptr(rB(ctx->opcode)); \
6940 rd = gen_avr_ptr(rD(ctx->opcode)); \
6941 gen_helper_##name (rd, ra, rb); \
6942 tcg_temp_free_ptr(ra); \
6943 tcg_temp_free_ptr(rb); \
6944 tcg_temp_free_ptr(rd); \
6947 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6948 static void glue(gen_, name)(DisasContext *ctx) \
6950 TCGv_ptr ra, rb, rd; \
6951 if (unlikely(!ctx->altivec_enabled)) { \
6952 gen_exception(ctx, POWERPC_EXCP_VPU); \
6955 ra = gen_avr_ptr(rA(ctx->opcode)); \
6956 rb = gen_avr_ptr(rB(ctx->opcode)); \
6957 rd = gen_avr_ptr(rD(ctx->opcode)); \
6958 gen_helper_##name(cpu_env, rd, ra, rb); \
6959 tcg_temp_free_ptr(ra); \
6960 tcg_temp_free_ptr(rb); \
6961 tcg_temp_free_ptr(rd); \
6964 #define GEN_VXFORM3(name, opc2, opc3) \
6965 static void glue(gen_, name)(DisasContext *ctx) \
6967 TCGv_ptr ra, rb, rc, rd; \
6968 if (unlikely(!ctx->altivec_enabled)) { \
6969 gen_exception(ctx, POWERPC_EXCP_VPU); \
6972 ra = gen_avr_ptr(rA(ctx->opcode)); \
6973 rb = gen_avr_ptr(rB(ctx->opcode)); \
6974 rc = gen_avr_ptr(rC(ctx->opcode)); \
6975 rd = gen_avr_ptr(rD(ctx->opcode)); \
6976 gen_helper_##name(rd, ra, rb, rc); \
6977 tcg_temp_free_ptr(ra); \
6978 tcg_temp_free_ptr(rb); \
6979 tcg_temp_free_ptr(rc); \
6980 tcg_temp_free_ptr(rd); \
6984 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6985 * an opcode bit. In general, these pairs come from different
6986 * versions of the ISA, so we must also support a pair of flags for
6989 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6990 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6992 if ((Rc(ctx->opcode) == 0) && \
6993 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6995 } else if ((Rc(ctx->opcode) == 1) && \
6996 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6999 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7003 GEN_VXFORM(vaddubm
, 0, 0);
7004 GEN_VXFORM(vadduhm
, 0, 1);
7005 GEN_VXFORM(vadduwm
, 0, 2);
7006 GEN_VXFORM(vaddudm
, 0, 3);
7007 GEN_VXFORM(vsububm
, 0, 16);
7008 GEN_VXFORM(vsubuhm
, 0, 17);
7009 GEN_VXFORM(vsubuwm
, 0, 18);
7010 GEN_VXFORM(vsubudm
, 0, 19);
7011 GEN_VXFORM(vmaxub
, 1, 0);
7012 GEN_VXFORM(vmaxuh
, 1, 1);
7013 GEN_VXFORM(vmaxuw
, 1, 2);
7014 GEN_VXFORM(vmaxud
, 1, 3);
7015 GEN_VXFORM(vmaxsb
, 1, 4);
7016 GEN_VXFORM(vmaxsh
, 1, 5);
7017 GEN_VXFORM(vmaxsw
, 1, 6);
7018 GEN_VXFORM(vmaxsd
, 1, 7);
7019 GEN_VXFORM(vminub
, 1, 8);
7020 GEN_VXFORM(vminuh
, 1, 9);
7021 GEN_VXFORM(vminuw
, 1, 10);
7022 GEN_VXFORM(vminud
, 1, 11);
7023 GEN_VXFORM(vminsb
, 1, 12);
7024 GEN_VXFORM(vminsh
, 1, 13);
7025 GEN_VXFORM(vminsw
, 1, 14);
7026 GEN_VXFORM(vminsd
, 1, 15);
7027 GEN_VXFORM(vavgub
, 1, 16);
7028 GEN_VXFORM(vavguh
, 1, 17);
7029 GEN_VXFORM(vavguw
, 1, 18);
7030 GEN_VXFORM(vavgsb
, 1, 20);
7031 GEN_VXFORM(vavgsh
, 1, 21);
7032 GEN_VXFORM(vavgsw
, 1, 22);
7033 GEN_VXFORM(vmrghb
, 6, 0);
7034 GEN_VXFORM(vmrghh
, 6, 1);
7035 GEN_VXFORM(vmrghw
, 6, 2);
7036 GEN_VXFORM(vmrglb
, 6, 4);
7037 GEN_VXFORM(vmrglh
, 6, 5);
7038 GEN_VXFORM(vmrglw
, 6, 6);
7040 static void gen_vmrgew(DisasContext
*ctx
)
7044 if (unlikely(!ctx
->altivec_enabled
)) {
7045 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7048 VT
= rD(ctx
->opcode
);
7049 VA
= rA(ctx
->opcode
);
7050 VB
= rB(ctx
->opcode
);
7051 tmp
= tcg_temp_new_i64();
7052 tcg_gen_shri_i64(tmp
, cpu_avrh
[VB
], 32);
7053 tcg_gen_deposit_i64(cpu_avrh
[VT
], cpu_avrh
[VA
], tmp
, 0, 32);
7054 tcg_gen_shri_i64(tmp
, cpu_avrl
[VB
], 32);
7055 tcg_gen_deposit_i64(cpu_avrl
[VT
], cpu_avrl
[VA
], tmp
, 0, 32);
7056 tcg_temp_free_i64(tmp
);
7059 static void gen_vmrgow(DisasContext
*ctx
)
7062 if (unlikely(!ctx
->altivec_enabled
)) {
7063 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7066 VT
= rD(ctx
->opcode
);
7067 VA
= rA(ctx
->opcode
);
7068 VB
= rB(ctx
->opcode
);
7070 tcg_gen_deposit_i64(cpu_avrh
[VT
], cpu_avrh
[VB
], cpu_avrh
[VA
], 32, 32);
7071 tcg_gen_deposit_i64(cpu_avrl
[VT
], cpu_avrl
[VB
], cpu_avrl
[VA
], 32, 32);
7074 GEN_VXFORM(vmuloub
, 4, 0);
7075 GEN_VXFORM(vmulouh
, 4, 1);
7076 GEN_VXFORM(vmulouw
, 4, 2);
7077 GEN_VXFORM(vmuluwm
, 4, 2);
7078 GEN_VXFORM_DUAL(vmulouw
, PPC_ALTIVEC
, PPC_NONE
,
7079 vmuluwm
, PPC_NONE
, PPC2_ALTIVEC_207
)
7080 GEN_VXFORM(vmulosb
, 4, 4);
7081 GEN_VXFORM(vmulosh
, 4, 5);
7082 GEN_VXFORM(vmulosw
, 4, 6);
7083 GEN_VXFORM(vmuleub
, 4, 8);
7084 GEN_VXFORM(vmuleuh
, 4, 9);
7085 GEN_VXFORM(vmuleuw
, 4, 10);
7086 GEN_VXFORM(vmulesb
, 4, 12);
7087 GEN_VXFORM(vmulesh
, 4, 13);
7088 GEN_VXFORM(vmulesw
, 4, 14);
7089 GEN_VXFORM(vslb
, 2, 4);
7090 GEN_VXFORM(vslh
, 2, 5);
7091 GEN_VXFORM(vslw
, 2, 6);
7092 GEN_VXFORM(vsld
, 2, 23);
7093 GEN_VXFORM(vsrb
, 2, 8);
7094 GEN_VXFORM(vsrh
, 2, 9);
7095 GEN_VXFORM(vsrw
, 2, 10);
7096 GEN_VXFORM(vsrd
, 2, 27);
7097 GEN_VXFORM(vsrab
, 2, 12);
7098 GEN_VXFORM(vsrah
, 2, 13);
7099 GEN_VXFORM(vsraw
, 2, 14);
7100 GEN_VXFORM(vsrad
, 2, 15);
7101 GEN_VXFORM(vslo
, 6, 16);
7102 GEN_VXFORM(vsro
, 6, 17);
7103 GEN_VXFORM(vaddcuw
, 0, 6);
7104 GEN_VXFORM(vsubcuw
, 0, 22);
7105 GEN_VXFORM_ENV(vaddubs
, 0, 8);
7106 GEN_VXFORM_ENV(vadduhs
, 0, 9);
7107 GEN_VXFORM_ENV(vadduws
, 0, 10);
7108 GEN_VXFORM_ENV(vaddsbs
, 0, 12);
7109 GEN_VXFORM_ENV(vaddshs
, 0, 13);
7110 GEN_VXFORM_ENV(vaddsws
, 0, 14);
7111 GEN_VXFORM_ENV(vsububs
, 0, 24);
7112 GEN_VXFORM_ENV(vsubuhs
, 0, 25);
7113 GEN_VXFORM_ENV(vsubuws
, 0, 26);
7114 GEN_VXFORM_ENV(vsubsbs
, 0, 28);
7115 GEN_VXFORM_ENV(vsubshs
, 0, 29);
7116 GEN_VXFORM_ENV(vsubsws
, 0, 30);
7117 GEN_VXFORM(vadduqm
, 0, 4);
7118 GEN_VXFORM(vaddcuq
, 0, 5);
7119 GEN_VXFORM3(vaddeuqm
, 30, 0);
7120 GEN_VXFORM3(vaddecuq
, 30, 0);
7121 GEN_VXFORM_DUAL(vaddeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7122 vaddecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
7123 GEN_VXFORM(vsubuqm
, 0, 20);
7124 GEN_VXFORM(vsubcuq
, 0, 21);
7125 GEN_VXFORM3(vsubeuqm
, 31, 0);
7126 GEN_VXFORM3(vsubecuq
, 31, 0);
7127 GEN_VXFORM_DUAL(vsubeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7128 vsubecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
7129 GEN_VXFORM(vrlb
, 2, 0);
7130 GEN_VXFORM(vrlh
, 2, 1);
7131 GEN_VXFORM(vrlw
, 2, 2);
7132 GEN_VXFORM(vrld
, 2, 3);
7133 GEN_VXFORM(vsl
, 2, 7);
7134 GEN_VXFORM(vsr
, 2, 11);
7135 GEN_VXFORM_ENV(vpkuhum
, 7, 0);
7136 GEN_VXFORM_ENV(vpkuwum
, 7, 1);
7137 GEN_VXFORM_ENV(vpkudum
, 7, 17);
7138 GEN_VXFORM_ENV(vpkuhus
, 7, 2);
7139 GEN_VXFORM_ENV(vpkuwus
, 7, 3);
7140 GEN_VXFORM_ENV(vpkudus
, 7, 19);
7141 GEN_VXFORM_ENV(vpkshus
, 7, 4);
7142 GEN_VXFORM_ENV(vpkswus
, 7, 5);
7143 GEN_VXFORM_ENV(vpksdus
, 7, 21);
7144 GEN_VXFORM_ENV(vpkshss
, 7, 6);
7145 GEN_VXFORM_ENV(vpkswss
, 7, 7);
7146 GEN_VXFORM_ENV(vpksdss
, 7, 23);
7147 GEN_VXFORM(vpkpx
, 7, 12);
7148 GEN_VXFORM_ENV(vsum4ubs
, 4, 24);
7149 GEN_VXFORM_ENV(vsum4sbs
, 4, 28);
7150 GEN_VXFORM_ENV(vsum4shs
, 4, 25);
7151 GEN_VXFORM_ENV(vsum2sws
, 4, 26);
7152 GEN_VXFORM_ENV(vsumsws
, 4, 30);
7153 GEN_VXFORM_ENV(vaddfp
, 5, 0);
7154 GEN_VXFORM_ENV(vsubfp
, 5, 1);
7155 GEN_VXFORM_ENV(vmaxfp
, 5, 16);
7156 GEN_VXFORM_ENV(vminfp
, 5, 17);
7158 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7159 static void glue(gen_, name)(DisasContext *ctx) \
7161 TCGv_ptr ra, rb, rd; \
7162 if (unlikely(!ctx->altivec_enabled)) { \
7163 gen_exception(ctx, POWERPC_EXCP_VPU); \
7166 ra = gen_avr_ptr(rA(ctx->opcode)); \
7167 rb = gen_avr_ptr(rB(ctx->opcode)); \
7168 rd = gen_avr_ptr(rD(ctx->opcode)); \
7169 gen_helper_##opname(cpu_env, rd, ra, rb); \
7170 tcg_temp_free_ptr(ra); \
7171 tcg_temp_free_ptr(rb); \
7172 tcg_temp_free_ptr(rd); \
7175 #define GEN_VXRFORM(name, opc2, opc3) \
7176 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7177 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7180 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7181 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7182 * come from different versions of the ISA, so we must also support a
7183 * pair of flags for each instruction.
7185 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7186 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7188 if ((Rc(ctx->opcode) == 0) && \
7189 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7190 if (Rc21(ctx->opcode) == 0) { \
7193 gen_##name0##_(ctx); \
7195 } else if ((Rc(ctx->opcode) == 1) && \
7196 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7197 if (Rc21(ctx->opcode) == 0) { \
7200 gen_##name1##_(ctx); \
7203 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7207 GEN_VXRFORM(vcmpequb
, 3, 0)
7208 GEN_VXRFORM(vcmpequh
, 3, 1)
7209 GEN_VXRFORM(vcmpequw
, 3, 2)
7210 GEN_VXRFORM(vcmpequd
, 3, 3)
7211 GEN_VXRFORM(vcmpgtsb
, 3, 12)
7212 GEN_VXRFORM(vcmpgtsh
, 3, 13)
7213 GEN_VXRFORM(vcmpgtsw
, 3, 14)
7214 GEN_VXRFORM(vcmpgtsd
, 3, 15)
7215 GEN_VXRFORM(vcmpgtub
, 3, 8)
7216 GEN_VXRFORM(vcmpgtuh
, 3, 9)
7217 GEN_VXRFORM(vcmpgtuw
, 3, 10)
7218 GEN_VXRFORM(vcmpgtud
, 3, 11)
7219 GEN_VXRFORM(vcmpeqfp
, 3, 3)
7220 GEN_VXRFORM(vcmpgefp
, 3, 7)
7221 GEN_VXRFORM(vcmpgtfp
, 3, 11)
7222 GEN_VXRFORM(vcmpbfp
, 3, 15)
7224 GEN_VXRFORM_DUAL(vcmpeqfp
, PPC_ALTIVEC
, PPC_NONE
, \
7225 vcmpequd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7226 GEN_VXRFORM_DUAL(vcmpbfp
, PPC_ALTIVEC
, PPC_NONE
, \
7227 vcmpgtsd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7228 GEN_VXRFORM_DUAL(vcmpgtfp
, PPC_ALTIVEC
, PPC_NONE
, \
7229 vcmpgtud
, PPC_NONE
, PPC2_ALTIVEC_207
)
7231 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7232 static void glue(gen_, name)(DisasContext *ctx) \
7236 if (unlikely(!ctx->altivec_enabled)) { \
7237 gen_exception(ctx, POWERPC_EXCP_VPU); \
7240 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7241 rd = gen_avr_ptr(rD(ctx->opcode)); \
7242 gen_helper_##name (rd, simm); \
7243 tcg_temp_free_i32(simm); \
7244 tcg_temp_free_ptr(rd); \
7247 GEN_VXFORM_SIMM(vspltisb
, 6, 12);
7248 GEN_VXFORM_SIMM(vspltish
, 6, 13);
7249 GEN_VXFORM_SIMM(vspltisw
, 6, 14);
7251 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7252 static void glue(gen_, name)(DisasContext *ctx) \
7255 if (unlikely(!ctx->altivec_enabled)) { \
7256 gen_exception(ctx, POWERPC_EXCP_VPU); \
7259 rb = gen_avr_ptr(rB(ctx->opcode)); \
7260 rd = gen_avr_ptr(rD(ctx->opcode)); \
7261 gen_helper_##name (rd, rb); \
7262 tcg_temp_free_ptr(rb); \
7263 tcg_temp_free_ptr(rd); \
7266 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7267 static void glue(gen_, name)(DisasContext *ctx) \
7271 if (unlikely(!ctx->altivec_enabled)) { \
7272 gen_exception(ctx, POWERPC_EXCP_VPU); \
7275 rb = gen_avr_ptr(rB(ctx->opcode)); \
7276 rd = gen_avr_ptr(rD(ctx->opcode)); \
7277 gen_helper_##name(cpu_env, rd, rb); \
7278 tcg_temp_free_ptr(rb); \
7279 tcg_temp_free_ptr(rd); \
7282 GEN_VXFORM_NOA(vupkhsb
, 7, 8);
7283 GEN_VXFORM_NOA(vupkhsh
, 7, 9);
7284 GEN_VXFORM_NOA(vupkhsw
, 7, 25);
7285 GEN_VXFORM_NOA(vupklsb
, 7, 10);
7286 GEN_VXFORM_NOA(vupklsh
, 7, 11);
7287 GEN_VXFORM_NOA(vupklsw
, 7, 27);
7288 GEN_VXFORM_NOA(vupkhpx
, 7, 13);
7289 GEN_VXFORM_NOA(vupklpx
, 7, 15);
7290 GEN_VXFORM_NOA_ENV(vrefp
, 5, 4);
7291 GEN_VXFORM_NOA_ENV(vrsqrtefp
, 5, 5);
7292 GEN_VXFORM_NOA_ENV(vexptefp
, 5, 6);
7293 GEN_VXFORM_NOA_ENV(vlogefp
, 5, 7);
7294 GEN_VXFORM_NOA_ENV(vrfim
, 5, 11);
7295 GEN_VXFORM_NOA_ENV(vrfin
, 5, 8);
7296 GEN_VXFORM_NOA_ENV(vrfip
, 5, 10);
7297 GEN_VXFORM_NOA_ENV(vrfiz
, 5, 9);
7299 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7300 static void glue(gen_, name)(DisasContext *ctx) \
7304 if (unlikely(!ctx->altivec_enabled)) { \
7305 gen_exception(ctx, POWERPC_EXCP_VPU); \
7308 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7309 rd = gen_avr_ptr(rD(ctx->opcode)); \
7310 gen_helper_##name (rd, simm); \
7311 tcg_temp_free_i32(simm); \
7312 tcg_temp_free_ptr(rd); \
7315 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7316 static void glue(gen_, name)(DisasContext *ctx) \
7320 if (unlikely(!ctx->altivec_enabled)) { \
7321 gen_exception(ctx, POWERPC_EXCP_VPU); \
7324 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7325 rb = gen_avr_ptr(rB(ctx->opcode)); \
7326 rd = gen_avr_ptr(rD(ctx->opcode)); \
7327 gen_helper_##name (rd, rb, uimm); \
7328 tcg_temp_free_i32(uimm); \
7329 tcg_temp_free_ptr(rb); \
7330 tcg_temp_free_ptr(rd); \
7333 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7334 static void glue(gen_, name)(DisasContext *ctx) \
7339 if (unlikely(!ctx->altivec_enabled)) { \
7340 gen_exception(ctx, POWERPC_EXCP_VPU); \
7343 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7344 rb = gen_avr_ptr(rB(ctx->opcode)); \
7345 rd = gen_avr_ptr(rD(ctx->opcode)); \
7346 gen_helper_##name(cpu_env, rd, rb, uimm); \
7347 tcg_temp_free_i32(uimm); \
7348 tcg_temp_free_ptr(rb); \
7349 tcg_temp_free_ptr(rd); \
7352 GEN_VXFORM_UIMM(vspltb
, 6, 8);
7353 GEN_VXFORM_UIMM(vsplth
, 6, 9);
7354 GEN_VXFORM_UIMM(vspltw
, 6, 10);
7355 GEN_VXFORM_UIMM_ENV(vcfux
, 5, 12);
7356 GEN_VXFORM_UIMM_ENV(vcfsx
, 5, 13);
7357 GEN_VXFORM_UIMM_ENV(vctuxs
, 5, 14);
7358 GEN_VXFORM_UIMM_ENV(vctsxs
, 5, 15);
7360 static void gen_vsldoi(DisasContext
*ctx
)
7362 TCGv_ptr ra
, rb
, rd
;
7364 if (unlikely(!ctx
->altivec_enabled
)) {
7365 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7368 ra
= gen_avr_ptr(rA(ctx
->opcode
));
7369 rb
= gen_avr_ptr(rB(ctx
->opcode
));
7370 rd
= gen_avr_ptr(rD(ctx
->opcode
));
7371 sh
= tcg_const_i32(VSH(ctx
->opcode
));
7372 gen_helper_vsldoi (rd
, ra
, rb
, sh
);
7373 tcg_temp_free_ptr(ra
);
7374 tcg_temp_free_ptr(rb
);
7375 tcg_temp_free_ptr(rd
);
7376 tcg_temp_free_i32(sh
);
7379 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7380 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7382 TCGv_ptr ra, rb, rc, rd; \
7383 if (unlikely(!ctx->altivec_enabled)) { \
7384 gen_exception(ctx, POWERPC_EXCP_VPU); \
7387 ra = gen_avr_ptr(rA(ctx->opcode)); \
7388 rb = gen_avr_ptr(rB(ctx->opcode)); \
7389 rc = gen_avr_ptr(rC(ctx->opcode)); \
7390 rd = gen_avr_ptr(rD(ctx->opcode)); \
7391 if (Rc(ctx->opcode)) { \
7392 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7394 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7396 tcg_temp_free_ptr(ra); \
7397 tcg_temp_free_ptr(rb); \
7398 tcg_temp_free_ptr(rc); \
7399 tcg_temp_free_ptr(rd); \
7402 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16)
7404 static void gen_vmladduhm(DisasContext
*ctx
)
7406 TCGv_ptr ra
, rb
, rc
, rd
;
7407 if (unlikely(!ctx
->altivec_enabled
)) {
7408 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7411 ra
= gen_avr_ptr(rA(ctx
->opcode
));
7412 rb
= gen_avr_ptr(rB(ctx
->opcode
));
7413 rc
= gen_avr_ptr(rC(ctx
->opcode
));
7414 rd
= gen_avr_ptr(rD(ctx
->opcode
));
7415 gen_helper_vmladduhm(rd
, ra
, rb
, rc
);
7416 tcg_temp_free_ptr(ra
);
7417 tcg_temp_free_ptr(rb
);
7418 tcg_temp_free_ptr(rc
);
7419 tcg_temp_free_ptr(rd
);
7422 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18)
7423 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19)
7424 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20)
7425 GEN_VAFORM_PAIRED(vsel
, vperm
, 21)
7426 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23)
7428 GEN_VXFORM_NOA(vclzb
, 1, 28)
7429 GEN_VXFORM_NOA(vclzh
, 1, 29)
7430 GEN_VXFORM_NOA(vclzw
, 1, 30)
7431 GEN_VXFORM_NOA(vclzd
, 1, 31)
7432 GEN_VXFORM_NOA(vpopcntb
, 1, 28)
7433 GEN_VXFORM_NOA(vpopcnth
, 1, 29)
7434 GEN_VXFORM_NOA(vpopcntw
, 1, 30)
7435 GEN_VXFORM_NOA(vpopcntd
, 1, 31)
7436 GEN_VXFORM_DUAL(vclzb
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7437 vpopcntb
, PPC_NONE
, PPC2_ALTIVEC_207
)
7438 GEN_VXFORM_DUAL(vclzh
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7439 vpopcnth
, PPC_NONE
, PPC2_ALTIVEC_207
)
7440 GEN_VXFORM_DUAL(vclzw
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7441 vpopcntw
, PPC_NONE
, PPC2_ALTIVEC_207
)
7442 GEN_VXFORM_DUAL(vclzd
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7443 vpopcntd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7444 GEN_VXFORM(vbpermq
, 6, 21);
7445 GEN_VXFORM_NOA(vgbbd
, 6, 20);
7446 GEN_VXFORM(vpmsumb
, 4, 16)
7447 GEN_VXFORM(vpmsumh
, 4, 17)
7448 GEN_VXFORM(vpmsumw
, 4, 18)
7449 GEN_VXFORM(vpmsumd
, 4, 19)
7451 #define GEN_BCD(op) \
7452 static void gen_##op(DisasContext *ctx) \
7454 TCGv_ptr ra, rb, rd; \
7457 if (unlikely(!ctx->altivec_enabled)) { \
7458 gen_exception(ctx, POWERPC_EXCP_VPU); \
7462 ra = gen_avr_ptr(rA(ctx->opcode)); \
7463 rb = gen_avr_ptr(rB(ctx->opcode)); \
7464 rd = gen_avr_ptr(rD(ctx->opcode)); \
7466 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7468 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7470 tcg_temp_free_ptr(ra); \
7471 tcg_temp_free_ptr(rb); \
7472 tcg_temp_free_ptr(rd); \
7473 tcg_temp_free_i32(ps); \
7479 GEN_VXFORM_DUAL(vsububm
, PPC_ALTIVEC
, PPC_NONE
, \
7480 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7481 GEN_VXFORM_DUAL(vsububs
, PPC_ALTIVEC
, PPC_NONE
, \
7482 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7483 GEN_VXFORM_DUAL(vsubuhm
, PPC_ALTIVEC
, PPC_NONE
, \
7484 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
7485 GEN_VXFORM_DUAL(vsubuhs
, PPC_ALTIVEC
, PPC_NONE
, \
7486 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
7488 static void gen_vsbox(DisasContext
*ctx
)
7491 if (unlikely(!ctx
->altivec_enabled
)) {
7492 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7495 ra
= gen_avr_ptr(rA(ctx
->opcode
));
7496 rd
= gen_avr_ptr(rD(ctx
->opcode
));
7497 gen_helper_vsbox(rd
, ra
);
7498 tcg_temp_free_ptr(ra
);
7499 tcg_temp_free_ptr(rd
);
7502 GEN_VXFORM(vcipher
, 4, 20)
7503 GEN_VXFORM(vcipherlast
, 4, 20)
7504 GEN_VXFORM(vncipher
, 4, 21)
7505 GEN_VXFORM(vncipherlast
, 4, 21)
7507 GEN_VXFORM_DUAL(vcipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
7508 vcipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
7509 GEN_VXFORM_DUAL(vncipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
7510 vncipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
7512 #define VSHASIGMA(op) \
7513 static void gen_##op(DisasContext *ctx) \
7517 if (unlikely(!ctx->altivec_enabled)) { \
7518 gen_exception(ctx, POWERPC_EXCP_VPU); \
7521 ra = gen_avr_ptr(rA(ctx->opcode)); \
7522 rd = gen_avr_ptr(rD(ctx->opcode)); \
7523 st_six = tcg_const_i32(rB(ctx->opcode)); \
7524 gen_helper_##op(rd, ra, st_six); \
7525 tcg_temp_free_ptr(ra); \
7526 tcg_temp_free_ptr(rd); \
7527 tcg_temp_free_i32(st_six); \
7530 VSHASIGMA(vshasigmaw
)
7531 VSHASIGMA(vshasigmad
)
7533 GEN_VXFORM3(vpermxor
, 22, 0xFF)
7534 GEN_VXFORM_DUAL(vsldoi
, PPC_ALTIVEC
, PPC_NONE
,
7535 vpermxor
, PPC_NONE
, PPC2_ALTIVEC_207
)
7537 /*** VSX extension ***/
7539 static inline TCGv_i64
cpu_vsrh(int n
)
7544 return cpu_avrh
[n
-32];
7548 static inline TCGv_i64
cpu_vsrl(int n
)
7553 return cpu_avrl
[n
-32];
7557 #define VSX_LOAD_SCALAR(name, operation) \
7558 static void gen_##name(DisasContext *ctx) \
7561 if (unlikely(!ctx->vsx_enabled)) { \
7562 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7565 gen_set_access_type(ctx, ACCESS_INT); \
7566 EA = tcg_temp_new(); \
7567 gen_addr_reg_index(ctx, EA); \
7568 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7569 /* NOTE: cpu_vsrl is undefined */ \
7570 tcg_temp_free(EA); \
7573 VSX_LOAD_SCALAR(lxsdx
, ld64
)
7574 VSX_LOAD_SCALAR(lxsiwax
, ld32s_i64
)
7575 VSX_LOAD_SCALAR(lxsiwzx
, ld32u_i64
)
7576 VSX_LOAD_SCALAR(lxsspx
, ld32fs
)
7578 static void gen_lxvd2x(DisasContext
*ctx
)
7581 if (unlikely(!ctx
->vsx_enabled
)) {
7582 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7585 gen_set_access_type(ctx
, ACCESS_INT
);
7586 EA
= tcg_temp_new();
7587 gen_addr_reg_index(ctx
, EA
);
7588 gen_qemu_ld64(ctx
, cpu_vsrh(xT(ctx
->opcode
)), EA
);
7589 tcg_gen_addi_tl(EA
, EA
, 8);
7590 gen_qemu_ld64(ctx
, cpu_vsrl(xT(ctx
->opcode
)), EA
);
7594 static void gen_lxvdsx(DisasContext
*ctx
)
7597 if (unlikely(!ctx
->vsx_enabled
)) {
7598 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7601 gen_set_access_type(ctx
, ACCESS_INT
);
7602 EA
= tcg_temp_new();
7603 gen_addr_reg_index(ctx
, EA
);
7604 gen_qemu_ld64(ctx
, cpu_vsrh(xT(ctx
->opcode
)), EA
);
7605 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xT(ctx
->opcode
)));
7609 static void gen_lxvw4x(DisasContext
*ctx
)
7613 TCGv_i64 xth
= cpu_vsrh(xT(ctx
->opcode
));
7614 TCGv_i64 xtl
= cpu_vsrl(xT(ctx
->opcode
));
7615 if (unlikely(!ctx
->vsx_enabled
)) {
7616 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7619 gen_set_access_type(ctx
, ACCESS_INT
);
7620 EA
= tcg_temp_new();
7621 tmp
= tcg_temp_new_i64();
7623 gen_addr_reg_index(ctx
, EA
);
7624 gen_qemu_ld32u_i64(ctx
, tmp
, EA
);
7625 tcg_gen_addi_tl(EA
, EA
, 4);
7626 gen_qemu_ld32u_i64(ctx
, xth
, EA
);
7627 tcg_gen_deposit_i64(xth
, xth
, tmp
, 32, 32);
7629 tcg_gen_addi_tl(EA
, EA
, 4);
7630 gen_qemu_ld32u_i64(ctx
, tmp
, EA
);
7631 tcg_gen_addi_tl(EA
, EA
, 4);
7632 gen_qemu_ld32u_i64(ctx
, xtl
, EA
);
7633 tcg_gen_deposit_i64(xtl
, xtl
, tmp
, 32, 32);
7636 tcg_temp_free_i64(tmp
);
7639 #define VSX_STORE_SCALAR(name, operation) \
7640 static void gen_##name(DisasContext *ctx) \
7643 if (unlikely(!ctx->vsx_enabled)) { \
7644 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7647 gen_set_access_type(ctx, ACCESS_INT); \
7648 EA = tcg_temp_new(); \
7649 gen_addr_reg_index(ctx, EA); \
7650 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7651 tcg_temp_free(EA); \
7654 VSX_STORE_SCALAR(stxsdx
, st64
)
7655 VSX_STORE_SCALAR(stxsiwx
, st32_i64
)
7656 VSX_STORE_SCALAR(stxsspx
, st32fs
)
7658 static void gen_stxvd2x(DisasContext
*ctx
)
7661 if (unlikely(!ctx
->vsx_enabled
)) {
7662 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7665 gen_set_access_type(ctx
, ACCESS_INT
);
7666 EA
= tcg_temp_new();
7667 gen_addr_reg_index(ctx
, EA
);
7668 gen_qemu_st64(ctx
, cpu_vsrh(xS(ctx
->opcode
)), EA
);
7669 tcg_gen_addi_tl(EA
, EA
, 8);
7670 gen_qemu_st64(ctx
, cpu_vsrl(xS(ctx
->opcode
)), EA
);
7674 static void gen_stxvw4x(DisasContext
*ctx
)
7678 if (unlikely(!ctx
->vsx_enabled
)) {
7679 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7682 gen_set_access_type(ctx
, ACCESS_INT
);
7683 EA
= tcg_temp_new();
7684 gen_addr_reg_index(ctx
, EA
);
7685 tmp
= tcg_temp_new_i64();
7687 tcg_gen_shri_i64(tmp
, cpu_vsrh(xS(ctx
->opcode
)), 32);
7688 gen_qemu_st32_i64(ctx
, tmp
, EA
);
7689 tcg_gen_addi_tl(EA
, EA
, 4);
7690 gen_qemu_st32_i64(ctx
, cpu_vsrh(xS(ctx
->opcode
)), EA
);
7692 tcg_gen_shri_i64(tmp
, cpu_vsrl(xS(ctx
->opcode
)), 32);
7693 tcg_gen_addi_tl(EA
, EA
, 4);
7694 gen_qemu_st32_i64(ctx
, tmp
, EA
);
7695 tcg_gen_addi_tl(EA
, EA
, 4);
7696 gen_qemu_st32_i64(ctx
, cpu_vsrl(xS(ctx
->opcode
)), EA
);
7699 tcg_temp_free_i64(tmp
);
7702 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7703 static void gen_##name(DisasContext *ctx) \
7705 if (xS(ctx->opcode) < 32) { \
7706 if (unlikely(!ctx->fpu_enabled)) { \
7707 gen_exception(ctx, POWERPC_EXCP_FPU); \
7711 if (unlikely(!ctx->altivec_enabled)) { \
7712 gen_exception(ctx, POWERPC_EXCP_VPU); \
7716 TCGv_i64 tmp = tcg_temp_new_i64(); \
7717 tcg_gen_##tcgop1(tmp, source); \
7718 tcg_gen_##tcgop2(target, tmp); \
7719 tcg_temp_free_i64(tmp); \
7723 MV_VSRW(mfvsrwz
, ext32u_i64
, trunc_i64_tl
, cpu_gpr
[rA(ctx
->opcode
)], \
7724 cpu_vsrh(xS(ctx
->opcode
)))
7725 MV_VSRW(mtvsrwa
, extu_tl_i64
, ext32s_i64
, cpu_vsrh(xT(ctx
->opcode
)), \
7726 cpu_gpr
[rA(ctx
->opcode
)])
7727 MV_VSRW(mtvsrwz
, extu_tl_i64
, ext32u_i64
, cpu_vsrh(xT(ctx
->opcode
)), \
7728 cpu_gpr
[rA(ctx
->opcode
)])
7730 #if defined(TARGET_PPC64)
7731 #define MV_VSRD(name, target, source) \
7732 static void gen_##name(DisasContext *ctx) \
7734 if (xS(ctx->opcode) < 32) { \
7735 if (unlikely(!ctx->fpu_enabled)) { \
7736 gen_exception(ctx, POWERPC_EXCP_FPU); \
7740 if (unlikely(!ctx->altivec_enabled)) { \
7741 gen_exception(ctx, POWERPC_EXCP_VPU); \
7745 tcg_gen_mov_i64(target, source); \
7748 MV_VSRD(mfvsrd
, cpu_gpr
[rA(ctx
->opcode
)], cpu_vsrh(xS(ctx
->opcode
)))
7749 MV_VSRD(mtvsrd
, cpu_vsrh(xT(ctx
->opcode
)), cpu_gpr
[rA(ctx
->opcode
)])
7753 static void gen_xxpermdi(DisasContext
*ctx
)
7755 if (unlikely(!ctx
->vsx_enabled
)) {
7756 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7760 if (unlikely((xT(ctx
->opcode
) == xA(ctx
->opcode
)) ||
7761 (xT(ctx
->opcode
) == xB(ctx
->opcode
)))) {
7764 xh
= tcg_temp_new_i64();
7765 xl
= tcg_temp_new_i64();
7767 if ((DM(ctx
->opcode
) & 2) == 0) {
7768 tcg_gen_mov_i64(xh
, cpu_vsrh(xA(ctx
->opcode
)));
7770 tcg_gen_mov_i64(xh
, cpu_vsrl(xA(ctx
->opcode
)));
7772 if ((DM(ctx
->opcode
) & 1) == 0) {
7773 tcg_gen_mov_i64(xl
, cpu_vsrh(xB(ctx
->opcode
)));
7775 tcg_gen_mov_i64(xl
, cpu_vsrl(xB(ctx
->opcode
)));
7778 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), xh
);
7779 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), xl
);
7781 tcg_temp_free_i64(xh
);
7782 tcg_temp_free_i64(xl
);
7784 if ((DM(ctx
->opcode
) & 2) == 0) {
7785 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), cpu_vsrh(xA(ctx
->opcode
)));
7787 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), cpu_vsrl(xA(ctx
->opcode
)));
7789 if ((DM(ctx
->opcode
) & 1) == 0) {
7790 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xB(ctx
->opcode
)));
7792 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrl(xB(ctx
->opcode
)));
7801 #define SGN_MASK_DP 0x8000000000000000ull
7802 #define SGN_MASK_SP 0x8000000080000000ull
7804 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7805 static void glue(gen_, name)(DisasContext * ctx) \
7808 if (unlikely(!ctx->vsx_enabled)) { \
7809 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7812 xb = tcg_temp_new_i64(); \
7813 sgm = tcg_temp_new_i64(); \
7814 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7815 tcg_gen_movi_i64(sgm, sgn_mask); \
7818 tcg_gen_andc_i64(xb, xb, sgm); \
7822 tcg_gen_or_i64(xb, xb, sgm); \
7826 tcg_gen_xor_i64(xb, xb, sgm); \
7830 TCGv_i64 xa = tcg_temp_new_i64(); \
7831 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7832 tcg_gen_and_i64(xa, xa, sgm); \
7833 tcg_gen_andc_i64(xb, xb, sgm); \
7834 tcg_gen_or_i64(xb, xb, xa); \
7835 tcg_temp_free_i64(xa); \
7839 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7840 tcg_temp_free_i64(xb); \
7841 tcg_temp_free_i64(sgm); \
7844 VSX_SCALAR_MOVE(xsabsdp
, OP_ABS
, SGN_MASK_DP
)
7845 VSX_SCALAR_MOVE(xsnabsdp
, OP_NABS
, SGN_MASK_DP
)
7846 VSX_SCALAR_MOVE(xsnegdp
, OP_NEG
, SGN_MASK_DP
)
7847 VSX_SCALAR_MOVE(xscpsgndp
, OP_CPSGN
, SGN_MASK_DP
)
7849 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7850 static void glue(gen_, name)(DisasContext * ctx) \
7852 TCGv_i64 xbh, xbl, sgm; \
7853 if (unlikely(!ctx->vsx_enabled)) { \
7854 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7857 xbh = tcg_temp_new_i64(); \
7858 xbl = tcg_temp_new_i64(); \
7859 sgm = tcg_temp_new_i64(); \
7860 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7861 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7862 tcg_gen_movi_i64(sgm, sgn_mask); \
7865 tcg_gen_andc_i64(xbh, xbh, sgm); \
7866 tcg_gen_andc_i64(xbl, xbl, sgm); \
7870 tcg_gen_or_i64(xbh, xbh, sgm); \
7871 tcg_gen_or_i64(xbl, xbl, sgm); \
7875 tcg_gen_xor_i64(xbh, xbh, sgm); \
7876 tcg_gen_xor_i64(xbl, xbl, sgm); \
7880 TCGv_i64 xah = tcg_temp_new_i64(); \
7881 TCGv_i64 xal = tcg_temp_new_i64(); \
7882 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7883 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7884 tcg_gen_and_i64(xah, xah, sgm); \
7885 tcg_gen_and_i64(xal, xal, sgm); \
7886 tcg_gen_andc_i64(xbh, xbh, sgm); \
7887 tcg_gen_andc_i64(xbl, xbl, sgm); \
7888 tcg_gen_or_i64(xbh, xbh, xah); \
7889 tcg_gen_or_i64(xbl, xbl, xal); \
7890 tcg_temp_free_i64(xah); \
7891 tcg_temp_free_i64(xal); \
7895 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7896 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7897 tcg_temp_free_i64(xbh); \
7898 tcg_temp_free_i64(xbl); \
7899 tcg_temp_free_i64(sgm); \
7902 VSX_VECTOR_MOVE(xvabsdp
, OP_ABS
, SGN_MASK_DP
)
7903 VSX_VECTOR_MOVE(xvnabsdp
, OP_NABS
, SGN_MASK_DP
)
7904 VSX_VECTOR_MOVE(xvnegdp
, OP_NEG
, SGN_MASK_DP
)
7905 VSX_VECTOR_MOVE(xvcpsgndp
, OP_CPSGN
, SGN_MASK_DP
)
7906 VSX_VECTOR_MOVE(xvabssp
, OP_ABS
, SGN_MASK_SP
)
7907 VSX_VECTOR_MOVE(xvnabssp
, OP_NABS
, SGN_MASK_SP
)
7908 VSX_VECTOR_MOVE(xvnegsp
, OP_NEG
, SGN_MASK_SP
)
7909 VSX_VECTOR_MOVE(xvcpsgnsp
, OP_CPSGN
, SGN_MASK_SP
)
7911 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7912 static void gen_##name(DisasContext * ctx) \
7915 if (unlikely(!ctx->vsx_enabled)) { \
7916 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7919 /* NIP cannot be restored if the memory exception comes from an helper */ \
7920 gen_update_nip(ctx, ctx->nip - 4); \
7921 opc = tcg_const_i32(ctx->opcode); \
7922 gen_helper_##name(cpu_env, opc); \
7923 tcg_temp_free_i32(opc); \
7926 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7927 static void gen_##name(DisasContext * ctx) \
7929 if (unlikely(!ctx->vsx_enabled)) { \
7930 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7933 /* NIP cannot be restored if the exception comes */ \
7934 /* from a helper. */ \
7935 gen_update_nip(ctx, ctx->nip - 4); \
7937 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7938 cpu_vsrh(xB(ctx->opcode))); \
7941 GEN_VSX_HELPER_2(xsadddp
, 0x00, 0x04, 0, PPC2_VSX
)
7942 GEN_VSX_HELPER_2(xssubdp
, 0x00, 0x05, 0, PPC2_VSX
)
7943 GEN_VSX_HELPER_2(xsmuldp
, 0x00, 0x06, 0, PPC2_VSX
)
7944 GEN_VSX_HELPER_2(xsdivdp
, 0x00, 0x07, 0, PPC2_VSX
)
7945 GEN_VSX_HELPER_2(xsredp
, 0x14, 0x05, 0, PPC2_VSX
)
7946 GEN_VSX_HELPER_2(xssqrtdp
, 0x16, 0x04, 0, PPC2_VSX
)
7947 GEN_VSX_HELPER_2(xsrsqrtedp
, 0x14, 0x04, 0, PPC2_VSX
)
7948 GEN_VSX_HELPER_2(xstdivdp
, 0x14, 0x07, 0, PPC2_VSX
)
7949 GEN_VSX_HELPER_2(xstsqrtdp
, 0x14, 0x06, 0, PPC2_VSX
)
7950 GEN_VSX_HELPER_2(xsmaddadp
, 0x04, 0x04, 0, PPC2_VSX
)
7951 GEN_VSX_HELPER_2(xsmaddmdp
, 0x04, 0x05, 0, PPC2_VSX
)
7952 GEN_VSX_HELPER_2(xsmsubadp
, 0x04, 0x06, 0, PPC2_VSX
)
7953 GEN_VSX_HELPER_2(xsmsubmdp
, 0x04, 0x07, 0, PPC2_VSX
)
7954 GEN_VSX_HELPER_2(xsnmaddadp
, 0x04, 0x14, 0, PPC2_VSX
)
7955 GEN_VSX_HELPER_2(xsnmaddmdp
, 0x04, 0x15, 0, PPC2_VSX
)
7956 GEN_VSX_HELPER_2(xsnmsubadp
, 0x04, 0x16, 0, PPC2_VSX
)
7957 GEN_VSX_HELPER_2(xsnmsubmdp
, 0x04, 0x17, 0, PPC2_VSX
)
7958 GEN_VSX_HELPER_2(xscmpodp
, 0x0C, 0x05, 0, PPC2_VSX
)
7959 GEN_VSX_HELPER_2(xscmpudp
, 0x0C, 0x04, 0, PPC2_VSX
)
7960 GEN_VSX_HELPER_2(xsmaxdp
, 0x00, 0x14, 0, PPC2_VSX
)
7961 GEN_VSX_HELPER_2(xsmindp
, 0x00, 0x15, 0, PPC2_VSX
)
7962 GEN_VSX_HELPER_2(xscvdpsp
, 0x12, 0x10, 0, PPC2_VSX
)
7963 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn
, 0x16, 0x10, 0, PPC2_VSX207
)
7964 GEN_VSX_HELPER_2(xscvspdp
, 0x12, 0x14, 0, PPC2_VSX
)
7965 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn
, 0x16, 0x14, 0, PPC2_VSX207
)
7966 GEN_VSX_HELPER_2(xscvdpsxds
, 0x10, 0x15, 0, PPC2_VSX
)
7967 GEN_VSX_HELPER_2(xscvdpsxws
, 0x10, 0x05, 0, PPC2_VSX
)
7968 GEN_VSX_HELPER_2(xscvdpuxds
, 0x10, 0x14, 0, PPC2_VSX
)
7969 GEN_VSX_HELPER_2(xscvdpuxws
, 0x10, 0x04, 0, PPC2_VSX
)
7970 GEN_VSX_HELPER_2(xscvsxddp
, 0x10, 0x17, 0, PPC2_VSX
)
7971 GEN_VSX_HELPER_2(xscvuxddp
, 0x10, 0x16, 0, PPC2_VSX
)
7972 GEN_VSX_HELPER_2(xsrdpi
, 0x12, 0x04, 0, PPC2_VSX
)
7973 GEN_VSX_HELPER_2(xsrdpic
, 0x16, 0x06, 0, PPC2_VSX
)
7974 GEN_VSX_HELPER_2(xsrdpim
, 0x12, 0x07, 0, PPC2_VSX
)
7975 GEN_VSX_HELPER_2(xsrdpip
, 0x12, 0x06, 0, PPC2_VSX
)
7976 GEN_VSX_HELPER_2(xsrdpiz
, 0x12, 0x05, 0, PPC2_VSX
)
7977 GEN_VSX_HELPER_XT_XB_ENV(xsrsp
, 0x12, 0x11, 0, PPC2_VSX207
)
7979 GEN_VSX_HELPER_2(xsaddsp
, 0x00, 0x00, 0, PPC2_VSX207
)
7980 GEN_VSX_HELPER_2(xssubsp
, 0x00, 0x01, 0, PPC2_VSX207
)
7981 GEN_VSX_HELPER_2(xsmulsp
, 0x00, 0x02, 0, PPC2_VSX207
)
7982 GEN_VSX_HELPER_2(xsdivsp
, 0x00, 0x03, 0, PPC2_VSX207
)
7983 GEN_VSX_HELPER_2(xsresp
, 0x14, 0x01, 0, PPC2_VSX207
)
7984 GEN_VSX_HELPER_2(xssqrtsp
, 0x16, 0x00, 0, PPC2_VSX207
)
7985 GEN_VSX_HELPER_2(xsrsqrtesp
, 0x14, 0x00, 0, PPC2_VSX207
)
7986 GEN_VSX_HELPER_2(xsmaddasp
, 0x04, 0x00, 0, PPC2_VSX207
)
7987 GEN_VSX_HELPER_2(xsmaddmsp
, 0x04, 0x01, 0, PPC2_VSX207
)
7988 GEN_VSX_HELPER_2(xsmsubasp
, 0x04, 0x02, 0, PPC2_VSX207
)
7989 GEN_VSX_HELPER_2(xsmsubmsp
, 0x04, 0x03, 0, PPC2_VSX207
)
7990 GEN_VSX_HELPER_2(xsnmaddasp
, 0x04, 0x10, 0, PPC2_VSX207
)
7991 GEN_VSX_HELPER_2(xsnmaddmsp
, 0x04, 0x11, 0, PPC2_VSX207
)
7992 GEN_VSX_HELPER_2(xsnmsubasp
, 0x04, 0x12, 0, PPC2_VSX207
)
7993 GEN_VSX_HELPER_2(xsnmsubmsp
, 0x04, 0x13, 0, PPC2_VSX207
)
7994 GEN_VSX_HELPER_2(xscvsxdsp
, 0x10, 0x13, 0, PPC2_VSX207
)
7995 GEN_VSX_HELPER_2(xscvuxdsp
, 0x10, 0x12, 0, PPC2_VSX207
)
7997 GEN_VSX_HELPER_2(xvadddp
, 0x00, 0x0C, 0, PPC2_VSX
)
7998 GEN_VSX_HELPER_2(xvsubdp
, 0x00, 0x0D, 0, PPC2_VSX
)
7999 GEN_VSX_HELPER_2(xvmuldp
, 0x00, 0x0E, 0, PPC2_VSX
)
8000 GEN_VSX_HELPER_2(xvdivdp
, 0x00, 0x0F, 0, PPC2_VSX
)
8001 GEN_VSX_HELPER_2(xvredp
, 0x14, 0x0D, 0, PPC2_VSX
)
8002 GEN_VSX_HELPER_2(xvsqrtdp
, 0x16, 0x0C, 0, PPC2_VSX
)
8003 GEN_VSX_HELPER_2(xvrsqrtedp
, 0x14, 0x0C, 0, PPC2_VSX
)
8004 GEN_VSX_HELPER_2(xvtdivdp
, 0x14, 0x0F, 0, PPC2_VSX
)
8005 GEN_VSX_HELPER_2(xvtsqrtdp
, 0x14, 0x0E, 0, PPC2_VSX
)
8006 GEN_VSX_HELPER_2(xvmaddadp
, 0x04, 0x0C, 0, PPC2_VSX
)
8007 GEN_VSX_HELPER_2(xvmaddmdp
, 0x04, 0x0D, 0, PPC2_VSX
)
8008 GEN_VSX_HELPER_2(xvmsubadp
, 0x04, 0x0E, 0, PPC2_VSX
)
8009 GEN_VSX_HELPER_2(xvmsubmdp
, 0x04, 0x0F, 0, PPC2_VSX
)
8010 GEN_VSX_HELPER_2(xvnmaddadp
, 0x04, 0x1C, 0, PPC2_VSX
)
8011 GEN_VSX_HELPER_2(xvnmaddmdp
, 0x04, 0x1D, 0, PPC2_VSX
)
8012 GEN_VSX_HELPER_2(xvnmsubadp
, 0x04, 0x1E, 0, PPC2_VSX
)
8013 GEN_VSX_HELPER_2(xvnmsubmdp
, 0x04, 0x1F, 0, PPC2_VSX
)
8014 GEN_VSX_HELPER_2(xvmaxdp
, 0x00, 0x1C, 0, PPC2_VSX
)
8015 GEN_VSX_HELPER_2(xvmindp
, 0x00, 0x1D, 0, PPC2_VSX
)
8016 GEN_VSX_HELPER_2(xvcmpeqdp
, 0x0C, 0x0C, 0, PPC2_VSX
)
8017 GEN_VSX_HELPER_2(xvcmpgtdp
, 0x0C, 0x0D, 0, PPC2_VSX
)
8018 GEN_VSX_HELPER_2(xvcmpgedp
, 0x0C, 0x0E, 0, PPC2_VSX
)
8019 GEN_VSX_HELPER_2(xvcvdpsp
, 0x12, 0x18, 0, PPC2_VSX
)
8020 GEN_VSX_HELPER_2(xvcvdpsxds
, 0x10, 0x1D, 0, PPC2_VSX
)
8021 GEN_VSX_HELPER_2(xvcvdpsxws
, 0x10, 0x0D, 0, PPC2_VSX
)
8022 GEN_VSX_HELPER_2(xvcvdpuxds
, 0x10, 0x1C, 0, PPC2_VSX
)
8023 GEN_VSX_HELPER_2(xvcvdpuxws
, 0x10, 0x0C, 0, PPC2_VSX
)
8024 GEN_VSX_HELPER_2(xvcvsxddp
, 0x10, 0x1F, 0, PPC2_VSX
)
8025 GEN_VSX_HELPER_2(xvcvuxddp
, 0x10, 0x1E, 0, PPC2_VSX
)
8026 GEN_VSX_HELPER_2(xvcvsxwdp
, 0x10, 0x0F, 0, PPC2_VSX
)
8027 GEN_VSX_HELPER_2(xvcvuxwdp
, 0x10, 0x0E, 0, PPC2_VSX
)
8028 GEN_VSX_HELPER_2(xvrdpi
, 0x12, 0x0C, 0, PPC2_VSX
)
8029 GEN_VSX_HELPER_2(xvrdpic
, 0x16, 0x0E, 0, PPC2_VSX
)
8030 GEN_VSX_HELPER_2(xvrdpim
, 0x12, 0x0F, 0, PPC2_VSX
)
8031 GEN_VSX_HELPER_2(xvrdpip
, 0x12, 0x0E, 0, PPC2_VSX
)
8032 GEN_VSX_HELPER_2(xvrdpiz
, 0x12, 0x0D, 0, PPC2_VSX
)
8034 GEN_VSX_HELPER_2(xvaddsp
, 0x00, 0x08, 0, PPC2_VSX
)
8035 GEN_VSX_HELPER_2(xvsubsp
, 0x00, 0x09, 0, PPC2_VSX
)
8036 GEN_VSX_HELPER_2(xvmulsp
, 0x00, 0x0A, 0, PPC2_VSX
)
8037 GEN_VSX_HELPER_2(xvdivsp
, 0x00, 0x0B, 0, PPC2_VSX
)
8038 GEN_VSX_HELPER_2(xvresp
, 0x14, 0x09, 0, PPC2_VSX
)
8039 GEN_VSX_HELPER_2(xvsqrtsp
, 0x16, 0x08, 0, PPC2_VSX
)
8040 GEN_VSX_HELPER_2(xvrsqrtesp
, 0x14, 0x08, 0, PPC2_VSX
)
8041 GEN_VSX_HELPER_2(xvtdivsp
, 0x14, 0x0B, 0, PPC2_VSX
)
8042 GEN_VSX_HELPER_2(xvtsqrtsp
, 0x14, 0x0A, 0, PPC2_VSX
)
8043 GEN_VSX_HELPER_2(xvmaddasp
, 0x04, 0x08, 0, PPC2_VSX
)
8044 GEN_VSX_HELPER_2(xvmaddmsp
, 0x04, 0x09, 0, PPC2_VSX
)
8045 GEN_VSX_HELPER_2(xvmsubasp
, 0x04, 0x0A, 0, PPC2_VSX
)
8046 GEN_VSX_HELPER_2(xvmsubmsp
, 0x04, 0x0B, 0, PPC2_VSX
)
8047 GEN_VSX_HELPER_2(xvnmaddasp
, 0x04, 0x18, 0, PPC2_VSX
)
8048 GEN_VSX_HELPER_2(xvnmaddmsp
, 0x04, 0x19, 0, PPC2_VSX
)
8049 GEN_VSX_HELPER_2(xvnmsubasp
, 0x04, 0x1A, 0, PPC2_VSX
)
8050 GEN_VSX_HELPER_2(xvnmsubmsp
, 0x04, 0x1B, 0, PPC2_VSX
)
8051 GEN_VSX_HELPER_2(xvmaxsp
, 0x00, 0x18, 0, PPC2_VSX
)
8052 GEN_VSX_HELPER_2(xvminsp
, 0x00, 0x19, 0, PPC2_VSX
)
8053 GEN_VSX_HELPER_2(xvcmpeqsp
, 0x0C, 0x08, 0, PPC2_VSX
)
8054 GEN_VSX_HELPER_2(xvcmpgtsp
, 0x0C, 0x09, 0, PPC2_VSX
)
8055 GEN_VSX_HELPER_2(xvcmpgesp
, 0x0C, 0x0A, 0, PPC2_VSX
)
8056 GEN_VSX_HELPER_2(xvcvspdp
, 0x12, 0x1C, 0, PPC2_VSX
)
8057 GEN_VSX_HELPER_2(xvcvspsxds
, 0x10, 0x19, 0, PPC2_VSX
)
8058 GEN_VSX_HELPER_2(xvcvspsxws
, 0x10, 0x09, 0, PPC2_VSX
)
8059 GEN_VSX_HELPER_2(xvcvspuxds
, 0x10, 0x18, 0, PPC2_VSX
)
8060 GEN_VSX_HELPER_2(xvcvspuxws
, 0x10, 0x08, 0, PPC2_VSX
)
8061 GEN_VSX_HELPER_2(xvcvsxdsp
, 0x10, 0x1B, 0, PPC2_VSX
)
8062 GEN_VSX_HELPER_2(xvcvuxdsp
, 0x10, 0x1A, 0, PPC2_VSX
)
8063 GEN_VSX_HELPER_2(xvcvsxwsp
, 0x10, 0x0B, 0, PPC2_VSX
)
8064 GEN_VSX_HELPER_2(xvcvuxwsp
, 0x10, 0x0A, 0, PPC2_VSX
)
8065 GEN_VSX_HELPER_2(xvrspi
, 0x12, 0x08, 0, PPC2_VSX
)
8066 GEN_VSX_HELPER_2(xvrspic
, 0x16, 0x0A, 0, PPC2_VSX
)
8067 GEN_VSX_HELPER_2(xvrspim
, 0x12, 0x0B, 0, PPC2_VSX
)
8068 GEN_VSX_HELPER_2(xvrspip
, 0x12, 0x0A, 0, PPC2_VSX
)
8069 GEN_VSX_HELPER_2(xvrspiz
, 0x12, 0x09, 0, PPC2_VSX
)
8071 #define VSX_LOGICAL(name, tcg_op) \
8072 static void glue(gen_, name)(DisasContext * ctx) \
8074 if (unlikely(!ctx->vsx_enabled)) { \
8075 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8078 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8079 cpu_vsrh(xB(ctx->opcode))); \
8080 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8081 cpu_vsrl(xB(ctx->opcode))); \
8084 VSX_LOGICAL(xxland
, tcg_gen_and_i64
)
8085 VSX_LOGICAL(xxlandc
, tcg_gen_andc_i64
)
8086 VSX_LOGICAL(xxlor
, tcg_gen_or_i64
)
8087 VSX_LOGICAL(xxlxor
, tcg_gen_xor_i64
)
8088 VSX_LOGICAL(xxlnor
, tcg_gen_nor_i64
)
8089 VSX_LOGICAL(xxleqv
, tcg_gen_eqv_i64
)
8090 VSX_LOGICAL(xxlnand
, tcg_gen_nand_i64
)
8091 VSX_LOGICAL(xxlorc
, tcg_gen_orc_i64
)
8093 #define VSX_XXMRG(name, high) \
8094 static void glue(gen_, name)(DisasContext * ctx) \
8096 TCGv_i64 a0, a1, b0, b1; \
8097 if (unlikely(!ctx->vsx_enabled)) { \
8098 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8101 a0 = tcg_temp_new_i64(); \
8102 a1 = tcg_temp_new_i64(); \
8103 b0 = tcg_temp_new_i64(); \
8104 b1 = tcg_temp_new_i64(); \
8106 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8107 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8108 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8109 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8111 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8112 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8113 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8114 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8116 tcg_gen_shri_i64(a0, a0, 32); \
8117 tcg_gen_shri_i64(b0, b0, 32); \
8118 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8120 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8122 tcg_temp_free_i64(a0); \
8123 tcg_temp_free_i64(a1); \
8124 tcg_temp_free_i64(b0); \
8125 tcg_temp_free_i64(b1); \
8128 VSX_XXMRG(xxmrghw
, 1)
8129 VSX_XXMRG(xxmrglw
, 0)
8131 static void gen_xxsel(DisasContext
* ctx
)
8134 if (unlikely(!ctx
->vsx_enabled
)) {
8135 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
8138 a
= tcg_temp_new_i64();
8139 b
= tcg_temp_new_i64();
8140 c
= tcg_temp_new_i64();
8142 tcg_gen_mov_i64(a
, cpu_vsrh(xA(ctx
->opcode
)));
8143 tcg_gen_mov_i64(b
, cpu_vsrh(xB(ctx
->opcode
)));
8144 tcg_gen_mov_i64(c
, cpu_vsrh(xC(ctx
->opcode
)));
8146 tcg_gen_and_i64(b
, b
, c
);
8147 tcg_gen_andc_i64(a
, a
, c
);
8148 tcg_gen_or_i64(cpu_vsrh(xT(ctx
->opcode
)), a
, b
);
8150 tcg_gen_mov_i64(a
, cpu_vsrl(xA(ctx
->opcode
)));
8151 tcg_gen_mov_i64(b
, cpu_vsrl(xB(ctx
->opcode
)));
8152 tcg_gen_mov_i64(c
, cpu_vsrl(xC(ctx
->opcode
)));
8154 tcg_gen_and_i64(b
, b
, c
);
8155 tcg_gen_andc_i64(a
, a
, c
);
8156 tcg_gen_or_i64(cpu_vsrl(xT(ctx
->opcode
)), a
, b
);
8158 tcg_temp_free_i64(a
);
8159 tcg_temp_free_i64(b
);
8160 tcg_temp_free_i64(c
);
8163 static void gen_xxspltw(DisasContext
*ctx
)
8166 TCGv_i64 vsr
= (UIM(ctx
->opcode
) & 2) ?
8167 cpu_vsrl(xB(ctx
->opcode
)) :
8168 cpu_vsrh(xB(ctx
->opcode
));
8170 if (unlikely(!ctx
->vsx_enabled
)) {
8171 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
8175 b
= tcg_temp_new_i64();
8176 b2
= tcg_temp_new_i64();
8178 if (UIM(ctx
->opcode
) & 1) {
8179 tcg_gen_ext32u_i64(b
, vsr
);
8181 tcg_gen_shri_i64(b
, vsr
, 32);
8184 tcg_gen_shli_i64(b2
, b
, 32);
8185 tcg_gen_or_i64(cpu_vsrh(xT(ctx
->opcode
)), b
, b2
);
8186 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xT(ctx
->opcode
)));
8188 tcg_temp_free_i64(b
);
8189 tcg_temp_free_i64(b2
);
8192 static void gen_xxsldwi(DisasContext
*ctx
)
8195 if (unlikely(!ctx
->vsx_enabled
)) {
8196 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
8199 xth
= tcg_temp_new_i64();
8200 xtl
= tcg_temp_new_i64();
8202 switch (SHW(ctx
->opcode
)) {
8204 tcg_gen_mov_i64(xth
, cpu_vsrh(xA(ctx
->opcode
)));
8205 tcg_gen_mov_i64(xtl
, cpu_vsrl(xA(ctx
->opcode
)));
8209 TCGv_i64 t0
= tcg_temp_new_i64();
8210 tcg_gen_mov_i64(xth
, cpu_vsrh(xA(ctx
->opcode
)));
8211 tcg_gen_shli_i64(xth
, xth
, 32);
8212 tcg_gen_mov_i64(t0
, cpu_vsrl(xA(ctx
->opcode
)));
8213 tcg_gen_shri_i64(t0
, t0
, 32);
8214 tcg_gen_or_i64(xth
, xth
, t0
);
8215 tcg_gen_mov_i64(xtl
, cpu_vsrl(xA(ctx
->opcode
)));
8216 tcg_gen_shli_i64(xtl
, xtl
, 32);
8217 tcg_gen_mov_i64(t0
, cpu_vsrh(xB(ctx
->opcode
)));
8218 tcg_gen_shri_i64(t0
, t0
, 32);
8219 tcg_gen_or_i64(xtl
, xtl
, t0
);
8220 tcg_temp_free_i64(t0
);
8224 tcg_gen_mov_i64(xth
, cpu_vsrl(xA(ctx
->opcode
)));
8225 tcg_gen_mov_i64(xtl
, cpu_vsrh(xB(ctx
->opcode
)));
8229 TCGv_i64 t0
= tcg_temp_new_i64();
8230 tcg_gen_mov_i64(xth
, cpu_vsrl(xA(ctx
->opcode
)));
8231 tcg_gen_shli_i64(xth
, xth
, 32);
8232 tcg_gen_mov_i64(t0
, cpu_vsrh(xB(ctx
->opcode
)));
8233 tcg_gen_shri_i64(t0
, t0
, 32);
8234 tcg_gen_or_i64(xth
, xth
, t0
);
8235 tcg_gen_mov_i64(xtl
, cpu_vsrh(xB(ctx
->opcode
)));
8236 tcg_gen_shli_i64(xtl
, xtl
, 32);
8237 tcg_gen_mov_i64(t0
, cpu_vsrl(xB(ctx
->opcode
)));
8238 tcg_gen_shri_i64(t0
, t0
, 32);
8239 tcg_gen_or_i64(xtl
, xtl
, t0
);
8240 tcg_temp_free_i64(t0
);
8245 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), xth
);
8246 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), xtl
);
8248 tcg_temp_free_i64(xth
);
8249 tcg_temp_free_i64(xtl
);
8252 /*** Decimal Floating Point ***/
8254 static inline TCGv_ptr
gen_fprp_ptr(int reg
)
8256 TCGv_ptr r
= tcg_temp_new_ptr();
8257 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, fpr
[reg
]));
8261 #define GEN_DFP_T_A_B_Rc(name) \
8262 static void gen_##name(DisasContext *ctx) \
8264 TCGv_ptr rd, ra, rb; \
8265 if (unlikely(!ctx->fpu_enabled)) { \
8266 gen_exception(ctx, POWERPC_EXCP_FPU); \
8269 gen_update_nip(ctx, ctx->nip - 4); \
8270 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8271 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8272 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8273 gen_helper_##name(cpu_env, rd, ra, rb); \
8274 if (unlikely(Rc(ctx->opcode) != 0)) { \
8275 gen_set_cr1_from_fpscr(ctx); \
8277 tcg_temp_free_ptr(rd); \
8278 tcg_temp_free_ptr(ra); \
8279 tcg_temp_free_ptr(rb); \
8282 #define GEN_DFP_BF_A_B(name) \
8283 static void gen_##name(DisasContext *ctx) \
8286 if (unlikely(!ctx->fpu_enabled)) { \
8287 gen_exception(ctx, POWERPC_EXCP_FPU); \
8290 gen_update_nip(ctx, ctx->nip - 4); \
8291 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8292 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8293 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8295 tcg_temp_free_ptr(ra); \
8296 tcg_temp_free_ptr(rb); \
8299 #define GEN_DFP_BF_A_DCM(name) \
8300 static void gen_##name(DisasContext *ctx) \
8304 if (unlikely(!ctx->fpu_enabled)) { \
8305 gen_exception(ctx, POWERPC_EXCP_FPU); \
8308 gen_update_nip(ctx, ctx->nip - 4); \
8309 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8310 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8311 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8312 cpu_env, ra, dcm); \
8313 tcg_temp_free_ptr(ra); \
8314 tcg_temp_free_i32(dcm); \
8317 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8318 static void gen_##name(DisasContext *ctx) \
8321 TCGv_i32 u32_1, u32_2; \
8322 if (unlikely(!ctx->fpu_enabled)) { \
8323 gen_exception(ctx, POWERPC_EXCP_FPU); \
8326 gen_update_nip(ctx, ctx->nip - 4); \
8327 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8328 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8329 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8330 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8331 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8332 if (unlikely(Rc(ctx->opcode) != 0)) { \
8333 gen_set_cr1_from_fpscr(ctx); \
8335 tcg_temp_free_ptr(rt); \
8336 tcg_temp_free_ptr(rb); \
8337 tcg_temp_free_i32(u32_1); \
8338 tcg_temp_free_i32(u32_2); \
8341 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8342 static void gen_##name(DisasContext *ctx) \
8344 TCGv_ptr rt, ra, rb; \
8346 if (unlikely(!ctx->fpu_enabled)) { \
8347 gen_exception(ctx, POWERPC_EXCP_FPU); \
8350 gen_update_nip(ctx, ctx->nip - 4); \
8351 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8352 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8353 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8354 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8355 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8356 if (unlikely(Rc(ctx->opcode) != 0)) { \
8357 gen_set_cr1_from_fpscr(ctx); \
8359 tcg_temp_free_ptr(rt); \
8360 tcg_temp_free_ptr(rb); \
8361 tcg_temp_free_ptr(ra); \
8362 tcg_temp_free_i32(i32); \
8365 #define GEN_DFP_T_B_Rc(name) \
8366 static void gen_##name(DisasContext *ctx) \
8369 if (unlikely(!ctx->fpu_enabled)) { \
8370 gen_exception(ctx, POWERPC_EXCP_FPU); \
8373 gen_update_nip(ctx, ctx->nip - 4); \
8374 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8375 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8376 gen_helper_##name(cpu_env, rt, rb); \
8377 if (unlikely(Rc(ctx->opcode) != 0)) { \
8378 gen_set_cr1_from_fpscr(ctx); \
8380 tcg_temp_free_ptr(rt); \
8381 tcg_temp_free_ptr(rb); \
8384 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8385 static void gen_##name(DisasContext *ctx) \
8389 if (unlikely(!ctx->fpu_enabled)) { \
8390 gen_exception(ctx, POWERPC_EXCP_FPU); \
8393 gen_update_nip(ctx, ctx->nip - 4); \
8394 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8395 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8396 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8397 gen_helper_##name(cpu_env, rt, rs, i32); \
8398 if (unlikely(Rc(ctx->opcode) != 0)) { \
8399 gen_set_cr1_from_fpscr(ctx); \
8401 tcg_temp_free_ptr(rt); \
8402 tcg_temp_free_ptr(rs); \
8403 tcg_temp_free_i32(i32); \
8406 GEN_DFP_T_A_B_Rc(dadd
)
8407 GEN_DFP_T_A_B_Rc(daddq
)
8408 GEN_DFP_T_A_B_Rc(dsub
)
8409 GEN_DFP_T_A_B_Rc(dsubq
)
8410 GEN_DFP_T_A_B_Rc(dmul
)
8411 GEN_DFP_T_A_B_Rc(dmulq
)
8412 GEN_DFP_T_A_B_Rc(ddiv
)
8413 GEN_DFP_T_A_B_Rc(ddivq
)
8414 GEN_DFP_BF_A_B(dcmpu
)
8415 GEN_DFP_BF_A_B(dcmpuq
)
8416 GEN_DFP_BF_A_B(dcmpo
)
8417 GEN_DFP_BF_A_B(dcmpoq
)
8418 GEN_DFP_BF_A_DCM(dtstdc
)
8419 GEN_DFP_BF_A_DCM(dtstdcq
)
8420 GEN_DFP_BF_A_DCM(dtstdg
)
8421 GEN_DFP_BF_A_DCM(dtstdgq
)
8422 GEN_DFP_BF_A_B(dtstex
)
8423 GEN_DFP_BF_A_B(dtstexq
)
8424 GEN_DFP_BF_A_B(dtstsf
)
8425 GEN_DFP_BF_A_B(dtstsfq
)
8426 GEN_DFP_T_B_U32_U32_Rc(dquai
, SIMM5
, RMC
)
8427 GEN_DFP_T_B_U32_U32_Rc(dquaiq
, SIMM5
, RMC
)
8428 GEN_DFP_T_A_B_I32_Rc(dqua
, RMC
)
8429 GEN_DFP_T_A_B_I32_Rc(dquaq
, RMC
)
8430 GEN_DFP_T_A_B_I32_Rc(drrnd
, RMC
)
8431 GEN_DFP_T_A_B_I32_Rc(drrndq
, RMC
)
8432 GEN_DFP_T_B_U32_U32_Rc(drintx
, FPW
, RMC
)
8433 GEN_DFP_T_B_U32_U32_Rc(drintxq
, FPW
, RMC
)
8434 GEN_DFP_T_B_U32_U32_Rc(drintn
, FPW
, RMC
)
8435 GEN_DFP_T_B_U32_U32_Rc(drintnq
, FPW
, RMC
)
8436 GEN_DFP_T_B_Rc(dctdp
)
8437 GEN_DFP_T_B_Rc(dctqpq
)
8438 GEN_DFP_T_B_Rc(drsp
)
8439 GEN_DFP_T_B_Rc(drdpq
)
8440 GEN_DFP_T_B_Rc(dcffix
)
8441 GEN_DFP_T_B_Rc(dcffixq
)
8442 GEN_DFP_T_B_Rc(dctfix
)
8443 GEN_DFP_T_B_Rc(dctfixq
)
8444 GEN_DFP_T_FPR_I32_Rc(ddedpd
, rB
, SP
)
8445 GEN_DFP_T_FPR_I32_Rc(ddedpdq
, rB
, SP
)
8446 GEN_DFP_T_FPR_I32_Rc(denbcd
, rB
, SP
)
8447 GEN_DFP_T_FPR_I32_Rc(denbcdq
, rB
, SP
)
8448 GEN_DFP_T_B_Rc(dxex
)
8449 GEN_DFP_T_B_Rc(dxexq
)
8450 GEN_DFP_T_A_B_Rc(diex
)
8451 GEN_DFP_T_A_B_Rc(diexq
)
8452 GEN_DFP_T_FPR_I32_Rc(dscli
, rA
, DCM
)
8453 GEN_DFP_T_FPR_I32_Rc(dscliq
, rA
, DCM
)
8454 GEN_DFP_T_FPR_I32_Rc(dscri
, rA
, DCM
)
8455 GEN_DFP_T_FPR_I32_Rc(dscriq
, rA
, DCM
)
8457 /*** SPE extension ***/
8458 /* Register moves */
8460 static inline void gen_evmra(DisasContext
*ctx
)
8463 if (unlikely(!ctx
->spe_enabled
)) {
8464 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8468 TCGv_i64 tmp
= tcg_temp_new_i64();
8470 /* tmp := rA_lo + rA_hi << 32 */
8471 tcg_gen_concat_tl_i64(tmp
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8473 /* spe_acc := tmp */
8474 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8475 tcg_temp_free_i64(tmp
);
8478 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8479 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8482 static inline void gen_load_gpr64(TCGv_i64 t
, int reg
)
8484 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg
], cpu_gprh
[reg
]);
8487 static inline void gen_store_gpr64(int reg
, TCGv_i64 t
)
8489 tcg_gen_extr_i64_tl(cpu_gpr
[reg
], cpu_gprh
[reg
], t
);
8492 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8493 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8495 if (Rc(ctx->opcode)) \
8501 /* Handler for undefined SPE opcodes */
8502 static inline void gen_speundef(DisasContext
*ctx
)
8504 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
8508 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8509 static inline void gen_##name(DisasContext *ctx) \
8511 if (unlikely(!ctx->spe_enabled)) { \
8512 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8515 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8516 cpu_gpr[rB(ctx->opcode)]); \
8517 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8518 cpu_gprh[rB(ctx->opcode)]); \
8521 GEN_SPEOP_LOGIC2(evand
, tcg_gen_and_tl
);
8522 GEN_SPEOP_LOGIC2(evandc
, tcg_gen_andc_tl
);
8523 GEN_SPEOP_LOGIC2(evxor
, tcg_gen_xor_tl
);
8524 GEN_SPEOP_LOGIC2(evor
, tcg_gen_or_tl
);
8525 GEN_SPEOP_LOGIC2(evnor
, tcg_gen_nor_tl
);
8526 GEN_SPEOP_LOGIC2(eveqv
, tcg_gen_eqv_tl
);
8527 GEN_SPEOP_LOGIC2(evorc
, tcg_gen_orc_tl
);
8528 GEN_SPEOP_LOGIC2(evnand
, tcg_gen_nand_tl
);
8530 /* SPE logic immediate */
8531 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8532 static inline void gen_##name(DisasContext *ctx) \
8535 if (unlikely(!ctx->spe_enabled)) { \
8536 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8539 t0 = tcg_temp_new_i32(); \
8541 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8542 tcg_opi(t0, t0, rB(ctx->opcode)); \
8543 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8545 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8546 tcg_opi(t0, t0, rB(ctx->opcode)); \
8547 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8549 tcg_temp_free_i32(t0); \
8551 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi
, tcg_gen_shli_i32
);
8552 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu
, tcg_gen_shri_i32
);
8553 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis
, tcg_gen_sari_i32
);
8554 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi
, tcg_gen_rotli_i32
);
8556 /* SPE arithmetic */
8557 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8558 static inline void gen_##name(DisasContext *ctx) \
8561 if (unlikely(!ctx->spe_enabled)) { \
8562 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8565 t0 = tcg_temp_new_i32(); \
8567 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8569 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8571 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8573 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8575 tcg_temp_free_i32(t0); \
8578 static inline void gen_op_evabs(TCGv_i32 ret
, TCGv_i32 arg1
)
8580 int l1
= gen_new_label();
8581 int l2
= gen_new_label();
8583 tcg_gen_brcondi_i32(TCG_COND_GE
, arg1
, 0, l1
);
8584 tcg_gen_neg_i32(ret
, arg1
);
8587 tcg_gen_mov_i32(ret
, arg1
);
8590 GEN_SPEOP_ARITH1(evabs
, gen_op_evabs
);
8591 GEN_SPEOP_ARITH1(evneg
, tcg_gen_neg_i32
);
8592 GEN_SPEOP_ARITH1(evextsb
, tcg_gen_ext8s_i32
);
8593 GEN_SPEOP_ARITH1(evextsh
, tcg_gen_ext16s_i32
);
8594 static inline void gen_op_evrndw(TCGv_i32 ret
, TCGv_i32 arg1
)
8596 tcg_gen_addi_i32(ret
, arg1
, 0x8000);
8597 tcg_gen_ext16u_i32(ret
, ret
);
8599 GEN_SPEOP_ARITH1(evrndw
, gen_op_evrndw
);
8600 GEN_SPEOP_ARITH1(evcntlsw
, gen_helper_cntlsw32
);
8601 GEN_SPEOP_ARITH1(evcntlzw
, gen_helper_cntlzw32
);
8603 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8604 static inline void gen_##name(DisasContext *ctx) \
8607 if (unlikely(!ctx->spe_enabled)) { \
8608 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8611 t0 = tcg_temp_new_i32(); \
8612 t1 = tcg_temp_new_i32(); \
8614 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8615 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8616 tcg_op(t0, t0, t1); \
8617 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8619 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8620 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8621 tcg_op(t0, t0, t1); \
8622 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8624 tcg_temp_free_i32(t0); \
8625 tcg_temp_free_i32(t1); \
8628 static inline void gen_op_evsrwu(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8633 l1
= gen_new_label();
8634 l2
= gen_new_label();
8635 t0
= tcg_temp_local_new_i32();
8636 /* No error here: 6 bits are used */
8637 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
8638 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
8639 tcg_gen_shr_i32(ret
, arg1
, t0
);
8642 tcg_gen_movi_i32(ret
, 0);
8644 tcg_temp_free_i32(t0
);
8646 GEN_SPEOP_ARITH2(evsrwu
, gen_op_evsrwu
);
8647 static inline void gen_op_evsrws(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8652 l1
= gen_new_label();
8653 l2
= gen_new_label();
8654 t0
= tcg_temp_local_new_i32();
8655 /* No error here: 6 bits are used */
8656 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
8657 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
8658 tcg_gen_sar_i32(ret
, arg1
, t0
);
8661 tcg_gen_movi_i32(ret
, 0);
8663 tcg_temp_free_i32(t0
);
8665 GEN_SPEOP_ARITH2(evsrws
, gen_op_evsrws
);
8666 static inline void gen_op_evslw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8671 l1
= gen_new_label();
8672 l2
= gen_new_label();
8673 t0
= tcg_temp_local_new_i32();
8674 /* No error here: 6 bits are used */
8675 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
8676 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
8677 tcg_gen_shl_i32(ret
, arg1
, t0
);
8680 tcg_gen_movi_i32(ret
, 0);
8682 tcg_temp_free_i32(t0
);
8684 GEN_SPEOP_ARITH2(evslw
, gen_op_evslw
);
8685 static inline void gen_op_evrlw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8687 TCGv_i32 t0
= tcg_temp_new_i32();
8688 tcg_gen_andi_i32(t0
, arg2
, 0x1F);
8689 tcg_gen_rotl_i32(ret
, arg1
, t0
);
8690 tcg_temp_free_i32(t0
);
8692 GEN_SPEOP_ARITH2(evrlw
, gen_op_evrlw
);
8693 static inline void gen_evmergehi(DisasContext
*ctx
)
8695 if (unlikely(!ctx
->spe_enabled
)) {
8696 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8699 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8700 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8702 GEN_SPEOP_ARITH2(evaddw
, tcg_gen_add_i32
);
8703 static inline void gen_op_evsubf(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8705 tcg_gen_sub_i32(ret
, arg2
, arg1
);
8707 GEN_SPEOP_ARITH2(evsubfw
, gen_op_evsubf
);
8709 /* SPE arithmetic immediate */
8710 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8711 static inline void gen_##name(DisasContext *ctx) \
8714 if (unlikely(!ctx->spe_enabled)) { \
8715 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8718 t0 = tcg_temp_new_i32(); \
8720 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8721 tcg_op(t0, t0, rA(ctx->opcode)); \
8722 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8724 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8725 tcg_op(t0, t0, rA(ctx->opcode)); \
8726 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8728 tcg_temp_free_i32(t0); \
8730 GEN_SPEOP_ARITH_IMM2(evaddiw
, tcg_gen_addi_i32
);
8731 GEN_SPEOP_ARITH_IMM2(evsubifw
, tcg_gen_subi_i32
);
8733 /* SPE comparison */
8734 #define GEN_SPEOP_COMP(name, tcg_cond) \
8735 static inline void gen_##name(DisasContext *ctx) \
8737 if (unlikely(!ctx->spe_enabled)) { \
8738 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8741 int l1 = gen_new_label(); \
8742 int l2 = gen_new_label(); \
8743 int l3 = gen_new_label(); \
8744 int l4 = gen_new_label(); \
8746 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8747 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8748 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8749 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8751 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8752 cpu_gpr[rB(ctx->opcode)], l1); \
8753 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8755 gen_set_label(l1); \
8756 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8757 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8758 gen_set_label(l2); \
8759 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8760 cpu_gprh[rB(ctx->opcode)], l3); \
8761 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8762 ~(CRF_CH | CRF_CH_AND_CL)); \
8764 gen_set_label(l3); \
8765 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8766 CRF_CH | CRF_CH_OR_CL); \
8767 gen_set_label(l4); \
8769 GEN_SPEOP_COMP(evcmpgtu
, TCG_COND_GTU
);
8770 GEN_SPEOP_COMP(evcmpgts
, TCG_COND_GT
);
8771 GEN_SPEOP_COMP(evcmpltu
, TCG_COND_LTU
);
8772 GEN_SPEOP_COMP(evcmplts
, TCG_COND_LT
);
8773 GEN_SPEOP_COMP(evcmpeq
, TCG_COND_EQ
);
8776 static inline void gen_brinc(DisasContext
*ctx
)
8778 /* Note: brinc is usable even if SPE is disabled */
8779 gen_helper_brinc(cpu_gpr
[rD(ctx
->opcode
)],
8780 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8782 static inline void gen_evmergelo(DisasContext
*ctx
)
8784 if (unlikely(!ctx
->spe_enabled
)) {
8785 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8788 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8789 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8791 static inline void gen_evmergehilo(DisasContext
*ctx
)
8793 if (unlikely(!ctx
->spe_enabled
)) {
8794 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8797 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8798 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8800 static inline void gen_evmergelohi(DisasContext
*ctx
)
8802 if (unlikely(!ctx
->spe_enabled
)) {
8803 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8806 if (rD(ctx
->opcode
) == rA(ctx
->opcode
)) {
8807 TCGv tmp
= tcg_temp_new();
8808 tcg_gen_mov_tl(tmp
, cpu_gpr
[rA(ctx
->opcode
)]);
8809 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8810 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], tmp
);
8813 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8814 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8817 static inline void gen_evsplati(DisasContext
*ctx
)
8819 uint64_t imm
= ((int32_t)(rA(ctx
->opcode
) << 27)) >> 27;
8821 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], imm
);
8822 tcg_gen_movi_tl(cpu_gprh
[rD(ctx
->opcode
)], imm
);
8824 static inline void gen_evsplatfi(DisasContext
*ctx
)
8826 uint64_t imm
= rA(ctx
->opcode
) << 27;
8828 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], imm
);
8829 tcg_gen_movi_tl(cpu_gprh
[rD(ctx
->opcode
)], imm
);
8832 static inline void gen_evsel(DisasContext
*ctx
)
8834 int l1
= gen_new_label();
8835 int l2
= gen_new_label();
8836 int l3
= gen_new_label();
8837 int l4
= gen_new_label();
8838 TCGv_i32 t0
= tcg_temp_local_new_i32();
8839 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 3);
8840 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
8841 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8844 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8846 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 2);
8847 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l3
);
8848 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8851 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8853 tcg_temp_free_i32(t0
);
8856 static void gen_evsel0(DisasContext
*ctx
)
8861 static void gen_evsel1(DisasContext
*ctx
)
8866 static void gen_evsel2(DisasContext
*ctx
)
8871 static void gen_evsel3(DisasContext
*ctx
)
8878 static inline void gen_evmwumi(DisasContext
*ctx
)
8882 if (unlikely(!ctx
->spe_enabled
)) {
8883 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8887 t0
= tcg_temp_new_i64();
8888 t1
= tcg_temp_new_i64();
8890 /* t0 := rA; t1 := rB */
8891 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
8892 tcg_gen_ext32u_i64(t0
, t0
);
8893 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
8894 tcg_gen_ext32u_i64(t1
, t1
);
8896 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
8898 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
8900 tcg_temp_free_i64(t0
);
8901 tcg_temp_free_i64(t1
);
8904 static inline void gen_evmwumia(DisasContext
*ctx
)
8908 if (unlikely(!ctx
->spe_enabled
)) {
8909 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8913 gen_evmwumi(ctx
); /* rD := rA * rB */
8915 tmp
= tcg_temp_new_i64();
8918 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
8919 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8920 tcg_temp_free_i64(tmp
);
8923 static inline void gen_evmwumiaa(DisasContext
*ctx
)
8928 if (unlikely(!ctx
->spe_enabled
)) {
8929 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8933 gen_evmwumi(ctx
); /* rD := rA * rB */
8935 acc
= tcg_temp_new_i64();
8936 tmp
= tcg_temp_new_i64();
8939 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
8942 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8944 /* acc := tmp + acc */
8945 tcg_gen_add_i64(acc
, acc
, tmp
);
8948 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8951 gen_store_gpr64(rD(ctx
->opcode
), acc
);
8953 tcg_temp_free_i64(acc
);
8954 tcg_temp_free_i64(tmp
);
8957 static inline void gen_evmwsmi(DisasContext
*ctx
)
8961 if (unlikely(!ctx
->spe_enabled
)) {
8962 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8966 t0
= tcg_temp_new_i64();
8967 t1
= tcg_temp_new_i64();
8969 /* t0 := rA; t1 := rB */
8970 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
8971 tcg_gen_ext32s_i64(t0
, t0
);
8972 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
8973 tcg_gen_ext32s_i64(t1
, t1
);
8975 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
8977 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
8979 tcg_temp_free_i64(t0
);
8980 tcg_temp_free_i64(t1
);
8983 static inline void gen_evmwsmia(DisasContext
*ctx
)
8987 gen_evmwsmi(ctx
); /* rD := rA * rB */
8989 tmp
= tcg_temp_new_i64();
8992 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
8993 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8995 tcg_temp_free_i64(tmp
);
8998 static inline void gen_evmwsmiaa(DisasContext
*ctx
)
9000 TCGv_i64 acc
= tcg_temp_new_i64();
9001 TCGv_i64 tmp
= tcg_temp_new_i64();
9003 gen_evmwsmi(ctx
); /* rD := rA * rB */
9005 acc
= tcg_temp_new_i64();
9006 tmp
= tcg_temp_new_i64();
9009 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
9012 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9014 /* acc := tmp + acc */
9015 tcg_gen_add_i64(acc
, acc
, tmp
);
9018 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9021 gen_store_gpr64(rD(ctx
->opcode
), acc
);
9023 tcg_temp_free_i64(acc
);
9024 tcg_temp_free_i64(tmp
);
9027 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9028 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9029 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9030 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9031 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
9032 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
9033 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
9034 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
); //
9035 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
);
9036 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
9037 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9038 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9039 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9040 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9041 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9042 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
9043 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
9044 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9045 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9046 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
);
9047 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9048 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9049 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
); //
9050 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
);
9051 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9052 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9053 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
9054 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
9055 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
); ////
9057 /* SPE load and stores */
9058 static inline void gen_addr_spe_imm_index(DisasContext
*ctx
, TCGv EA
, int sh
)
9060 target_ulong uimm
= rB(ctx
->opcode
);
9062 if (rA(ctx
->opcode
) == 0) {
9063 tcg_gen_movi_tl(EA
, uimm
<< sh
);
9065 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], uimm
<< sh
);
9066 if (NARROW_MODE(ctx
)) {
9067 tcg_gen_ext32u_tl(EA
, EA
);
9072 static inline void gen_op_evldd(DisasContext
*ctx
, TCGv addr
)
9074 TCGv_i64 t0
= tcg_temp_new_i64();
9075 gen_qemu_ld64(ctx
, t0
, addr
);
9076 gen_store_gpr64(rD(ctx
->opcode
), t0
);
9077 tcg_temp_free_i64(t0
);
9080 static inline void gen_op_evldw(DisasContext
*ctx
, TCGv addr
)
9082 gen_qemu_ld32u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
9083 gen_addr_add(ctx
, addr
, addr
, 4);
9084 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
9087 static inline void gen_op_evldh(DisasContext
*ctx
, TCGv addr
)
9089 TCGv t0
= tcg_temp_new();
9090 gen_qemu_ld16u(ctx
, t0
, addr
);
9091 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9092 gen_addr_add(ctx
, addr
, addr
, 2);
9093 gen_qemu_ld16u(ctx
, t0
, addr
);
9094 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
9095 gen_addr_add(ctx
, addr
, addr
, 2);
9096 gen_qemu_ld16u(ctx
, t0
, addr
);
9097 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9098 gen_addr_add(ctx
, addr
, addr
, 2);
9099 gen_qemu_ld16u(ctx
, t0
, addr
);
9100 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
9104 static inline void gen_op_evlhhesplat(DisasContext
*ctx
, TCGv addr
)
9106 TCGv t0
= tcg_temp_new();
9107 gen_qemu_ld16u(ctx
, t0
, addr
);
9108 tcg_gen_shli_tl(t0
, t0
, 16);
9109 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9110 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9114 static inline void gen_op_evlhhousplat(DisasContext
*ctx
, TCGv addr
)
9116 TCGv t0
= tcg_temp_new();
9117 gen_qemu_ld16u(ctx
, t0
, addr
);
9118 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9119 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9123 static inline void gen_op_evlhhossplat(DisasContext
*ctx
, TCGv addr
)
9125 TCGv t0
= tcg_temp_new();
9126 gen_qemu_ld16s(ctx
, t0
, addr
);
9127 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9128 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9132 static inline void gen_op_evlwhe(DisasContext
*ctx
, TCGv addr
)
9134 TCGv t0
= tcg_temp_new();
9135 gen_qemu_ld16u(ctx
, t0
, addr
);
9136 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9137 gen_addr_add(ctx
, addr
, addr
, 2);
9138 gen_qemu_ld16u(ctx
, t0
, addr
);
9139 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
9143 static inline void gen_op_evlwhou(DisasContext
*ctx
, TCGv addr
)
9145 gen_qemu_ld16u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
9146 gen_addr_add(ctx
, addr
, addr
, 2);
9147 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
9150 static inline void gen_op_evlwhos(DisasContext
*ctx
, TCGv addr
)
9152 gen_qemu_ld16s(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
9153 gen_addr_add(ctx
, addr
, addr
, 2);
9154 gen_qemu_ld16s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
9157 static inline void gen_op_evlwwsplat(DisasContext
*ctx
, TCGv addr
)
9159 TCGv t0
= tcg_temp_new();
9160 gen_qemu_ld32u(ctx
, t0
, addr
);
9161 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9162 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9166 static inline void gen_op_evlwhsplat(DisasContext
*ctx
, TCGv addr
)
9168 TCGv t0
= tcg_temp_new();
9169 gen_qemu_ld16u(ctx
, t0
, addr
);
9170 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9171 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
9172 gen_addr_add(ctx
, addr
, addr
, 2);
9173 gen_qemu_ld16u(ctx
, t0
, addr
);
9174 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
9175 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
9179 static inline void gen_op_evstdd(DisasContext
*ctx
, TCGv addr
)
9181 TCGv_i64 t0
= tcg_temp_new_i64();
9182 gen_load_gpr64(t0
, rS(ctx
->opcode
));
9183 gen_qemu_st64(ctx
, t0
, addr
);
9184 tcg_temp_free_i64(t0
);
9187 static inline void gen_op_evstdw(DisasContext
*ctx
, TCGv addr
)
9189 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9190 gen_addr_add(ctx
, addr
, addr
, 4);
9191 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9194 static inline void gen_op_evstdh(DisasContext
*ctx
, TCGv addr
)
9196 TCGv t0
= tcg_temp_new();
9197 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
9198 gen_qemu_st16(ctx
, t0
, addr
);
9199 gen_addr_add(ctx
, addr
, addr
, 2);
9200 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9201 gen_addr_add(ctx
, addr
, addr
, 2);
9202 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
9203 gen_qemu_st16(ctx
, t0
, addr
);
9205 gen_addr_add(ctx
, addr
, addr
, 2);
9206 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9209 static inline void gen_op_evstwhe(DisasContext
*ctx
, TCGv addr
)
9211 TCGv t0
= tcg_temp_new();
9212 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
9213 gen_qemu_st16(ctx
, t0
, addr
);
9214 gen_addr_add(ctx
, addr
, addr
, 2);
9215 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
9216 gen_qemu_st16(ctx
, t0
, addr
);
9220 static inline void gen_op_evstwho(DisasContext
*ctx
, TCGv addr
)
9222 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9223 gen_addr_add(ctx
, addr
, addr
, 2);
9224 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9227 static inline void gen_op_evstwwe(DisasContext
*ctx
, TCGv addr
)
9229 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9232 static inline void gen_op_evstwwo(DisasContext
*ctx
, TCGv addr
)
9234 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9237 #define GEN_SPEOP_LDST(name, opc2, sh) \
9238 static void glue(gen_, name)(DisasContext *ctx) \
9241 if (unlikely(!ctx->spe_enabled)) { \
9242 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9245 gen_set_access_type(ctx, ACCESS_INT); \
9246 t0 = tcg_temp_new(); \
9247 if (Rc(ctx->opcode)) { \
9248 gen_addr_spe_imm_index(ctx, t0, sh); \
9250 gen_addr_reg_index(ctx, t0); \
9252 gen_op_##name(ctx, t0); \
9253 tcg_temp_free(t0); \
9256 GEN_SPEOP_LDST(evldd
, 0x00, 3);
9257 GEN_SPEOP_LDST(evldw
, 0x01, 3);
9258 GEN_SPEOP_LDST(evldh
, 0x02, 3);
9259 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1);
9260 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1);
9261 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1);
9262 GEN_SPEOP_LDST(evlwhe
, 0x08, 2);
9263 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2);
9264 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2);
9265 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2);
9266 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2);
9268 GEN_SPEOP_LDST(evstdd
, 0x10, 3);
9269 GEN_SPEOP_LDST(evstdw
, 0x11, 3);
9270 GEN_SPEOP_LDST(evstdh
, 0x12, 3);
9271 GEN_SPEOP_LDST(evstwhe
, 0x18, 2);
9272 GEN_SPEOP_LDST(evstwho
, 0x1A, 2);
9273 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2);
9274 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2);
9276 /* Multiply and add - TODO */
9278 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);//
9279 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9280 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9281 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9282 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9283 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9284 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9285 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9286 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9287 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9288 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9289 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9291 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9292 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9293 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9294 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9295 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9296 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9297 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9298 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9299 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9300 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9301 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9302 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9304 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9305 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9306 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9307 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9308 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE
);
9310 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9311 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9312 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9313 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9314 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9315 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9316 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9317 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9318 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9319 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9320 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9321 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9323 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
9324 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
9325 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9326 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9328 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9329 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9330 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9331 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9332 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9333 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9334 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9335 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9336 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9337 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9338 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9339 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9341 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
9342 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
9343 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9344 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
9345 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9348 /*** SPE floating-point extension ***/
9349 #define GEN_SPEFPUOP_CONV_32_32(name) \
9350 static inline void gen_##name(DisasContext *ctx) \
9352 TCGv_i32 t0 = tcg_temp_new_i32(); \
9353 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9354 gen_helper_##name(t0, cpu_env, t0); \
9355 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9356 tcg_temp_free_i32(t0); \
9358 #define GEN_SPEFPUOP_CONV_32_64(name) \
9359 static inline void gen_##name(DisasContext *ctx) \
9361 TCGv_i64 t0 = tcg_temp_new_i64(); \
9362 TCGv_i32 t1 = tcg_temp_new_i32(); \
9363 gen_load_gpr64(t0, rB(ctx->opcode)); \
9364 gen_helper_##name(t1, cpu_env, t0); \
9365 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9366 tcg_temp_free_i64(t0); \
9367 tcg_temp_free_i32(t1); \
9369 #define GEN_SPEFPUOP_CONV_64_32(name) \
9370 static inline void gen_##name(DisasContext *ctx) \
9372 TCGv_i64 t0 = tcg_temp_new_i64(); \
9373 TCGv_i32 t1 = tcg_temp_new_i32(); \
9374 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9375 gen_helper_##name(t0, cpu_env, t1); \
9376 gen_store_gpr64(rD(ctx->opcode), t0); \
9377 tcg_temp_free_i64(t0); \
9378 tcg_temp_free_i32(t1); \
9380 #define GEN_SPEFPUOP_CONV_64_64(name) \
9381 static inline void gen_##name(DisasContext *ctx) \
9383 TCGv_i64 t0 = tcg_temp_new_i64(); \
9384 gen_load_gpr64(t0, rB(ctx->opcode)); \
9385 gen_helper_##name(t0, cpu_env, t0); \
9386 gen_store_gpr64(rD(ctx->opcode), t0); \
9387 tcg_temp_free_i64(t0); \
9389 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9390 static inline void gen_##name(DisasContext *ctx) \
9393 if (unlikely(!ctx->spe_enabled)) { \
9394 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9397 t0 = tcg_temp_new_i32(); \
9398 t1 = tcg_temp_new_i32(); \
9399 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9400 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9401 gen_helper_##name(t0, cpu_env, t0, t1); \
9402 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9404 tcg_temp_free_i32(t0); \
9405 tcg_temp_free_i32(t1); \
9407 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9408 static inline void gen_##name(DisasContext *ctx) \
9411 if (unlikely(!ctx->spe_enabled)) { \
9412 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9415 t0 = tcg_temp_new_i64(); \
9416 t1 = tcg_temp_new_i64(); \
9417 gen_load_gpr64(t0, rA(ctx->opcode)); \
9418 gen_load_gpr64(t1, rB(ctx->opcode)); \
9419 gen_helper_##name(t0, cpu_env, t0, t1); \
9420 gen_store_gpr64(rD(ctx->opcode), t0); \
9421 tcg_temp_free_i64(t0); \
9422 tcg_temp_free_i64(t1); \
9424 #define GEN_SPEFPUOP_COMP_32(name) \
9425 static inline void gen_##name(DisasContext *ctx) \
9428 if (unlikely(!ctx->spe_enabled)) { \
9429 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9432 t0 = tcg_temp_new_i32(); \
9433 t1 = tcg_temp_new_i32(); \
9435 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9436 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9437 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9439 tcg_temp_free_i32(t0); \
9440 tcg_temp_free_i32(t1); \
9442 #define GEN_SPEFPUOP_COMP_64(name) \
9443 static inline void gen_##name(DisasContext *ctx) \
9446 if (unlikely(!ctx->spe_enabled)) { \
9447 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9450 t0 = tcg_temp_new_i64(); \
9451 t1 = tcg_temp_new_i64(); \
9452 gen_load_gpr64(t0, rA(ctx->opcode)); \
9453 gen_load_gpr64(t1, rB(ctx->opcode)); \
9454 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9455 tcg_temp_free_i64(t0); \
9456 tcg_temp_free_i64(t1); \
9459 /* Single precision floating-point vectors operations */
9461 GEN_SPEFPUOP_ARITH2_64_64(evfsadd
);
9462 GEN_SPEFPUOP_ARITH2_64_64(evfssub
);
9463 GEN_SPEFPUOP_ARITH2_64_64(evfsmul
);
9464 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv
);
9465 static inline void gen_evfsabs(DisasContext
*ctx
)
9467 if (unlikely(!ctx
->spe_enabled
)) {
9468 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9471 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
9473 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9476 static inline void gen_evfsnabs(DisasContext
*ctx
)
9478 if (unlikely(!ctx
->spe_enabled
)) {
9479 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9482 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
9484 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9487 static inline void gen_evfsneg(DisasContext
*ctx
)
9489 if (unlikely(!ctx
->spe_enabled
)) {
9490 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9493 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
9495 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9500 GEN_SPEFPUOP_CONV_64_64(evfscfui
);
9501 GEN_SPEFPUOP_CONV_64_64(evfscfsi
);
9502 GEN_SPEFPUOP_CONV_64_64(evfscfuf
);
9503 GEN_SPEFPUOP_CONV_64_64(evfscfsf
);
9504 GEN_SPEFPUOP_CONV_64_64(evfsctui
);
9505 GEN_SPEFPUOP_CONV_64_64(evfsctsi
);
9506 GEN_SPEFPUOP_CONV_64_64(evfsctuf
);
9507 GEN_SPEFPUOP_CONV_64_64(evfsctsf
);
9508 GEN_SPEFPUOP_CONV_64_64(evfsctuiz
);
9509 GEN_SPEFPUOP_CONV_64_64(evfsctsiz
);
9512 GEN_SPEFPUOP_COMP_64(evfscmpgt
);
9513 GEN_SPEFPUOP_COMP_64(evfscmplt
);
9514 GEN_SPEFPUOP_COMP_64(evfscmpeq
);
9515 GEN_SPEFPUOP_COMP_64(evfststgt
);
9516 GEN_SPEFPUOP_COMP_64(evfststlt
);
9517 GEN_SPEFPUOP_COMP_64(evfststeq
);
9519 /* Opcodes definitions */
9520 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9521 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
9522 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9523 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9524 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9525 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9526 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9527 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9528 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9529 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9530 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9531 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9532 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9533 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9535 /* Single precision floating-point operations */
9537 GEN_SPEFPUOP_ARITH2_32_32(efsadd
);
9538 GEN_SPEFPUOP_ARITH2_32_32(efssub
);
9539 GEN_SPEFPUOP_ARITH2_32_32(efsmul
);
9540 GEN_SPEFPUOP_ARITH2_32_32(efsdiv
);
9541 static inline void gen_efsabs(DisasContext
*ctx
)
9543 if (unlikely(!ctx
->spe_enabled
)) {
9544 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9547 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], (target_long
)~0x80000000LL
);
9549 static inline void gen_efsnabs(DisasContext
*ctx
)
9551 if (unlikely(!ctx
->spe_enabled
)) {
9552 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9555 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
9557 static inline void gen_efsneg(DisasContext
*ctx
)
9559 if (unlikely(!ctx
->spe_enabled
)) {
9560 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9563 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
9567 GEN_SPEFPUOP_CONV_32_32(efscfui
);
9568 GEN_SPEFPUOP_CONV_32_32(efscfsi
);
9569 GEN_SPEFPUOP_CONV_32_32(efscfuf
);
9570 GEN_SPEFPUOP_CONV_32_32(efscfsf
);
9571 GEN_SPEFPUOP_CONV_32_32(efsctui
);
9572 GEN_SPEFPUOP_CONV_32_32(efsctsi
);
9573 GEN_SPEFPUOP_CONV_32_32(efsctuf
);
9574 GEN_SPEFPUOP_CONV_32_32(efsctsf
);
9575 GEN_SPEFPUOP_CONV_32_32(efsctuiz
);
9576 GEN_SPEFPUOP_CONV_32_32(efsctsiz
);
9577 GEN_SPEFPUOP_CONV_32_64(efscfd
);
9580 GEN_SPEFPUOP_COMP_32(efscmpgt
);
9581 GEN_SPEFPUOP_COMP_32(efscmplt
);
9582 GEN_SPEFPUOP_COMP_32(efscmpeq
);
9583 GEN_SPEFPUOP_COMP_32(efststgt
);
9584 GEN_SPEFPUOP_COMP_32(efststlt
);
9585 GEN_SPEFPUOP_COMP_32(efststeq
);
9587 /* Opcodes definitions */
9588 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9589 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
9590 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9591 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9592 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9593 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
); //
9594 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9595 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9596 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9597 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9598 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9599 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9600 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9601 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9603 /* Double precision floating-point operations */
9605 GEN_SPEFPUOP_ARITH2_64_64(efdadd
);
9606 GEN_SPEFPUOP_ARITH2_64_64(efdsub
);
9607 GEN_SPEFPUOP_ARITH2_64_64(efdmul
);
9608 GEN_SPEFPUOP_ARITH2_64_64(efddiv
);
9609 static inline void gen_efdabs(DisasContext
*ctx
)
9611 if (unlikely(!ctx
->spe_enabled
)) {
9612 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9615 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
9616 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9619 static inline void gen_efdnabs(DisasContext
*ctx
)
9621 if (unlikely(!ctx
->spe_enabled
)) {
9622 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9625 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
9626 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9629 static inline void gen_efdneg(DisasContext
*ctx
)
9631 if (unlikely(!ctx
->spe_enabled
)) {
9632 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9635 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
9636 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9641 GEN_SPEFPUOP_CONV_64_32(efdcfui
);
9642 GEN_SPEFPUOP_CONV_64_32(efdcfsi
);
9643 GEN_SPEFPUOP_CONV_64_32(efdcfuf
);
9644 GEN_SPEFPUOP_CONV_64_32(efdcfsf
);
9645 GEN_SPEFPUOP_CONV_32_64(efdctui
);
9646 GEN_SPEFPUOP_CONV_32_64(efdctsi
);
9647 GEN_SPEFPUOP_CONV_32_64(efdctuf
);
9648 GEN_SPEFPUOP_CONV_32_64(efdctsf
);
9649 GEN_SPEFPUOP_CONV_32_64(efdctuiz
);
9650 GEN_SPEFPUOP_CONV_32_64(efdctsiz
);
9651 GEN_SPEFPUOP_CONV_64_32(efdcfs
);
9652 GEN_SPEFPUOP_CONV_64_64(efdcfuid
);
9653 GEN_SPEFPUOP_CONV_64_64(efdcfsid
);
9654 GEN_SPEFPUOP_CONV_64_64(efdctuidz
);
9655 GEN_SPEFPUOP_CONV_64_64(efdctsidz
);
9658 GEN_SPEFPUOP_COMP_64(efdcmpgt
);
9659 GEN_SPEFPUOP_COMP_64(efdcmplt
);
9660 GEN_SPEFPUOP_COMP_64(efdcmpeq
);
9661 GEN_SPEFPUOP_COMP_64(efdtstgt
);
9662 GEN_SPEFPUOP_COMP_64(efdtstlt
);
9663 GEN_SPEFPUOP_COMP_64(efdtsteq
);
9665 /* Opcodes definitions */
9666 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
9667 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9668 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
); //
9669 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9670 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
9671 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9672 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
9673 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
); //
9674 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9675 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9676 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9677 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9678 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9679 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9680 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
9681 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9683 static void gen_tbegin(DisasContext
*ctx
)
9685 if (unlikely(!ctx
->tm_enabled
)) {
9686 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
9689 gen_helper_tbegin(cpu_env
);
9692 #define GEN_TM_NOOP(name) \
9693 static inline void gen_##name(DisasContext *ctx) \
9695 if (unlikely(!ctx->tm_enabled)) { \
9696 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9699 /* Because tbegin always fails in QEMU, these user \
9700 * space instructions all have a simple implementation: \
9702 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9703 * = 0b0 || 0b00 || 0b0 \
9705 tcg_gen_movi_i32(cpu_crf[0], 0); \
9709 GEN_TM_NOOP(tabort
);
9710 GEN_TM_NOOP(tabortwc
);
9711 GEN_TM_NOOP(tabortwci
);
9712 GEN_TM_NOOP(tabortdc
);
9713 GEN_TM_NOOP(tabortdci
);
9716 static void gen_tcheck(DisasContext
*ctx
)
9718 if (unlikely(!ctx
->tm_enabled
)) {
9719 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
9722 /* Because tbegin always fails, the tcheck implementation
9725 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9726 * = 0b1 || 0b00 || 0b0
9728 tcg_gen_movi_i32(cpu_crf
[crfD(ctx
->opcode
)], 0x8);
9731 #if defined(CONFIG_USER_ONLY)
9732 #define GEN_TM_PRIV_NOOP(name) \
9733 static inline void gen_##name(DisasContext *ctx) \
9735 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9740 #define GEN_TM_PRIV_NOOP(name) \
9741 static inline void gen_##name(DisasContext *ctx) \
9743 if (unlikely(ctx->pr)) { \
9744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9747 if (unlikely(!ctx->tm_enabled)) { \
9748 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9751 /* Because tbegin always fails, the implementation is \
9754 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9755 * = 0b0 || 0b00 | 0b0 \
9757 tcg_gen_movi_i32(cpu_crf[0], 0); \
9762 GEN_TM_PRIV_NOOP(treclaim
);
9763 GEN_TM_PRIV_NOOP(trechkpt
);
9765 static opcode_t opcodes
[] = {
9766 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
9767 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
9768 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
9769 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER
),
9770 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
9771 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
9772 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
9773 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9774 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9775 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9776 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9777 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
9778 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
9779 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
9780 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
9781 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9782 #if defined(TARGET_PPC64)
9783 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
9785 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
9786 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
9787 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9788 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9789 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9790 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
9791 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
9792 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
9793 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9794 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9795 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9796 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9797 GEN_HANDLER(popcntb
, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB
),
9798 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
9799 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
9800 #if defined(TARGET_PPC64)
9801 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
9802 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
9803 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
9804 GEN_HANDLER_E(bpermd
, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE
, PPC2_PERM_ISA206
),
9806 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9807 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9808 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9809 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
9810 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
9811 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
9812 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
9813 #if defined(TARGET_PPC64)
9814 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
9815 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
9816 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
9817 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
9818 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
9820 GEN_HANDLER(frsqrtes
, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES
),
9821 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
9822 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
9823 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
),
9824 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
),
9825 GEN_HANDLER(fabs
, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT
),
9826 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
),
9827 GEN_HANDLER(fnabs
, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT
),
9828 GEN_HANDLER(fneg
, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT
),
9829 GEN_HANDLER_E(fcpsgn
, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE
, PPC2_ISA205
),
9830 GEN_HANDLER_E(fmrgew
, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE
, PPC2_VSX207
),
9831 GEN_HANDLER_E(fmrgow
, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE
, PPC2_VSX207
),
9832 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
),
9833 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
),
9834 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
),
9835 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
),
9836 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT
),
9837 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT
),
9838 #if defined(TARGET_PPC64)
9839 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9840 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
9841 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9843 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9844 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9845 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
9846 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
9847 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
9848 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
9849 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
),
9850 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
9851 GEN_HANDLER_E(lbarx
, 0x1F, 0x14, 0x01, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9852 GEN_HANDLER_E(lharx
, 0x1F, 0x14, 0x03, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9853 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
9854 GEN_HANDLER_E(stbcx_
, 0x1F, 0x16, 0x15, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9855 GEN_HANDLER_E(sthcx_
, 0x1F, 0x16, 0x16, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9856 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
9857 #if defined(TARGET_PPC64)
9858 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
9859 GEN_HANDLER_E(lqarx
, 0x1F, 0x14, 0x08, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
9860 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
9861 GEN_HANDLER_E(stqcx_
, 0x1F, 0x16, 0x05, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
9863 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
9864 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
9865 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9866 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9867 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
9868 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
9869 GEN_HANDLER_E(bctar
, 0x13, 0x10, 0x11, 0, PPC_NONE
, PPC2_BCTAR_ISA207
),
9870 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
9871 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
9872 #if defined(TARGET_PPC64)
9873 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
9874 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
9876 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
9877 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
9878 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9879 #if defined(TARGET_PPC64)
9880 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
9881 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9883 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
9884 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
9885 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
9886 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
9887 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
9888 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
9889 #if defined(TARGET_PPC64)
9890 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
9892 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
),
9893 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC
),
9894 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
9895 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
9896 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
9897 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE
),
9898 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE
),
9899 GEN_HANDLER_E(dcbtls
, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE
, PPC2_BOOKE206
),
9900 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
9901 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
9902 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
),
9903 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
9904 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
9905 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
9906 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
9907 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
9908 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
9909 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
9910 #if defined(TARGET_PPC64)
9911 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
9912 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9914 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
9915 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9917 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
9918 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
9919 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
9921 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
9922 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE
),
9923 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE
),
9924 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
9925 #if defined(TARGET_PPC64)
9926 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI
),
9927 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
9929 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
9930 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
9931 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
9932 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
9933 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
9934 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
9935 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
9936 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
9937 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
9938 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
9939 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
9940 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
9941 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
9942 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
9943 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
9944 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
9945 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
9946 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
9947 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
9948 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
9949 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
9950 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
9951 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
9952 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
9953 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
9954 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
9955 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
9956 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
9957 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
9958 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
9959 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
9960 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
9961 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
9962 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
9963 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
9964 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
9965 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
9966 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
9967 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
9968 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
9969 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
9970 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
9971 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
9972 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
9973 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
9974 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
9975 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
9976 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
9977 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
9978 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
9979 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
9980 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
9981 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
9982 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
9983 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
9984 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
9985 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
9986 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
9987 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
9988 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
9989 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
9990 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
9991 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
9992 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
9993 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
9994 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
9995 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
9996 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
9997 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
9998 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
9999 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
10000 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
10001 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
10002 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
10003 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
10004 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
10005 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
10006 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
10007 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
10008 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
10009 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10010 PPC_NONE
, PPC2_BOOKE206
),
10011 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10012 PPC_NONE
, PPC2_BOOKE206
),
10013 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10014 PPC_NONE
, PPC2_BOOKE206
),
10015 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10016 PPC_NONE
, PPC2_BOOKE206
),
10017 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10018 PPC_NONE
, PPC2_BOOKE206
),
10019 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10020 PPC_NONE
, PPC2_PRCNTL
),
10021 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10022 PPC_NONE
, PPC2_PRCNTL
),
10023 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
10024 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
10025 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
10026 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
10027 PPC_BOOKE
, PPC2_BOOKE206
),
10028 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
),
10029 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10030 PPC_BOOKE
, PPC2_BOOKE206
),
10031 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
10032 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
10033 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
10034 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
10035 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
10036 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
),
10037 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
),
10038 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
),
10039 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
),
10041 #undef GEN_INT_ARITH_ADD
10042 #undef GEN_INT_ARITH_ADD_CONST
10043 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10044 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10045 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10046 add_ca, compute_ca, compute_ov) \
10047 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10048 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
10049 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
10050 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
10051 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
10052 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
10053 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
10054 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
10055 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
10056 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
10057 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
10059 #undef GEN_INT_ARITH_DIVW
10060 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10061 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10062 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
10063 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
10064 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
10065 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
10066 GEN_HANDLER_E(divwe
, 0x1F, 0x0B, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10067 GEN_HANDLER_E(divweo
, 0x1F, 0x0B, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10068 GEN_HANDLER_E(divweu
, 0x1F, 0x0B, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10069 GEN_HANDLER_E(divweuo
, 0x1F, 0x0B, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10071 #if defined(TARGET_PPC64)
10072 #undef GEN_INT_ARITH_DIVD
10073 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10074 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10075 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
10076 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
10077 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
10078 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
10080 GEN_HANDLER_E(divdeu
, 0x1F, 0x09, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10081 GEN_HANDLER_E(divdeuo
, 0x1F, 0x09, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10082 GEN_HANDLER_E(divde
, 0x1F, 0x09, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10083 GEN_HANDLER_E(divdeo
, 0x1F, 0x09, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10085 #undef GEN_INT_ARITH_MUL_HELPER
10086 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10087 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10088 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
10089 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
10090 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
10093 #undef GEN_INT_ARITH_SUBF
10094 #undef GEN_INT_ARITH_SUBF_CONST
10095 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10096 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10097 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10098 add_ca, compute_ca, compute_ov) \
10099 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10100 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
10101 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
10102 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
10103 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
10104 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
10105 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
10106 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
10107 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
10108 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
10109 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
10111 #undef GEN_LOGICAL1
10112 #undef GEN_LOGICAL2
10113 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10114 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10115 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10116 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10117 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
10118 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
10119 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
10120 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
10121 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
10122 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
10123 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
10124 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
10125 #if defined(TARGET_PPC64)
10126 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
10129 #if defined(TARGET_PPC64)
10130 #undef GEN_PPC64_R2
10131 #undef GEN_PPC64_R4
10132 #define GEN_PPC64_R2(name, opc1, opc2) \
10133 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10134 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10136 #define GEN_PPC64_R4(name, opc1, opc2) \
10137 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10138 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10140 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10142 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10144 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
10145 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
10146 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
10147 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
10148 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
10149 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
10152 #undef _GEN_FLOAT_ACB
10153 #undef GEN_FLOAT_ACB
10154 #undef _GEN_FLOAT_AB
10155 #undef GEN_FLOAT_AB
10156 #undef _GEN_FLOAT_AC
10157 #undef GEN_FLOAT_AC
10159 #undef GEN_FLOAT_BS
10160 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10161 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10162 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10163 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10164 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10165 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10166 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10167 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10168 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10169 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10170 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10171 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10172 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10173 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10174 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10175 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10176 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10177 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10178 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10180 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
),
10181 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
),
10182 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
),
10183 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
),
10184 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
),
10185 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
),
10186 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
),
10187 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
),
10188 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
),
10189 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
),
10190 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
),
10191 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
),
10192 GEN_HANDLER_E(ftdiv
, 0x3F, 0x00, 0x04, 1, PPC_NONE
, PPC2_FP_TST_ISA206
),
10193 GEN_HANDLER_E(ftsqrt
, 0x3F, 0x00, 0x05, 1, PPC_NONE
, PPC2_FP_TST_ISA206
),
10194 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
),
10195 GEN_HANDLER_E(fctiwu
, 0x3F, 0x0E, 0x04, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10196 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
),
10197 GEN_HANDLER_E(fctiwuz
, 0x3F, 0x0F, 0x04, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10198 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
),
10199 GEN_HANDLER_E(fcfid
, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE
, PPC2_FP_CVT_S64
),
10200 GEN_HANDLER_E(fcfids
, 0x3B, 0x0E, 0x1A, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10201 GEN_HANDLER_E(fcfidu
, 0x3F, 0x0E, 0x1E, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10202 GEN_HANDLER_E(fcfidus
, 0x3B, 0x0E, 0x1E, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10203 GEN_HANDLER_E(fctid
, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE
, PPC2_FP_CVT_S64
),
10204 GEN_HANDLER_E(fctidu
, 0x3F, 0x0E, 0x1D, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10205 GEN_HANDLER_E(fctidz
, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE
, PPC2_FP_CVT_S64
),
10206 GEN_HANDLER_E(fctiduz
, 0x3F, 0x0F, 0x1D, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10207 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
),
10208 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
),
10209 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
),
10210 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
),
10217 #define GEN_LD(name, ldop, opc, type) \
10218 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10219 #define GEN_LDU(name, ldop, opc, type) \
10220 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10221 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10222 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10223 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10224 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10225 #define GEN_LDS(name, ldop, op, type) \
10226 GEN_LD(name, ldop, op | 0x20, type) \
10227 GEN_LDU(name, ldop, op | 0x21, type) \
10228 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10229 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10231 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
10232 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
10233 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
10234 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
10235 #if defined(TARGET_PPC64)
10236 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
10237 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
10238 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
)
10239 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
)
10240 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
)
10242 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
10243 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
10250 #define GEN_ST(name, stop, opc, type) \
10251 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10252 #define GEN_STU(name, stop, opc, type) \
10253 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10254 #define GEN_STUX(name, stop, opc2, opc3, type) \
10255 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10256 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10257 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10258 #define GEN_STS(name, stop, op, type) \
10259 GEN_ST(name, stop, op | 0x20, type) \
10260 GEN_STU(name, stop, op | 0x21, type) \
10261 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10262 GEN_STX(name, stop, 0x17, op | 0x00, type)
10264 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
10265 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
10266 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
10267 #if defined(TARGET_PPC64)
10268 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
)
10269 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
)
10270 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
)
10272 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
10273 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
10280 #define GEN_LDF(name, ldop, opc, type) \
10281 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10282 #define GEN_LDUF(name, ldop, opc, type) \
10283 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10284 #define GEN_LDUXF(name, ldop, opc, type) \
10285 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10286 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10287 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10288 #define GEN_LDFS(name, ldop, op, type) \
10289 GEN_LDF(name, ldop, op | 0x20, type) \
10290 GEN_LDUF(name, ldop, op | 0x21, type) \
10291 GEN_LDUXF(name, ldop, op | 0x01, type) \
10292 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10294 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
)
10295 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
)
10296 GEN_HANDLER_E(lfiwax
, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE
, PPC2_ISA205
),
10297 GEN_HANDLER_E(lfiwzx
, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10298 GEN_HANDLER_E(lfdp
, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE
, PPC2_ISA205
),
10299 GEN_HANDLER_E(lfdpx
, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE
, PPC2_ISA205
),
10306 #define GEN_STF(name, stop, opc, type) \
10307 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10308 #define GEN_STUF(name, stop, opc, type) \
10309 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10310 #define GEN_STUXF(name, stop, opc, type) \
10311 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10312 #define GEN_STXF(name, stop, opc2, opc3, type) \
10313 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10314 #define GEN_STFS(name, stop, op, type) \
10315 GEN_STF(name, stop, op | 0x20, type) \
10316 GEN_STUF(name, stop, op | 0x21, type) \
10317 GEN_STUXF(name, stop, op | 0x01, type) \
10318 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10320 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
)
10321 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
)
10322 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
)
10323 GEN_HANDLER_E(stfdp
, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE
, PPC2_ISA205
),
10324 GEN_HANDLER_E(stfdpx
, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE
, PPC2_ISA205
),
10327 #define GEN_CRLOGIC(name, tcg_op, opc) \
10328 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10329 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
10330 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
10331 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
10332 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
10333 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
10334 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
10335 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
10336 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
10338 #undef GEN_MAC_HANDLER
10339 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10340 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10341 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
10342 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
10343 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
10344 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
10345 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
10346 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
10347 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
10348 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
10349 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
10350 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
10351 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
10352 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
10353 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
10354 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
10355 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
10356 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
10357 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
10358 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
10359 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
10360 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
10361 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
10362 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
10363 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
10364 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
10365 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
10366 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
10367 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
10368 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
10369 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
10370 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
10371 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
10372 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
10373 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
10374 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
10375 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
10376 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
10377 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
10378 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
10379 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
10380 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
10381 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
10382 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
10388 #define GEN_VR_LDX(name, opc2, opc3) \
10389 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10390 #define GEN_VR_STX(name, opc2, opc3) \
10391 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10392 #define GEN_VR_LVE(name, opc2, opc3) \
10393 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10394 #define GEN_VR_STVE(name, opc2, opc3) \
10395 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10396 GEN_VR_LDX(lvx
, 0x07, 0x03),
10397 GEN_VR_LDX(lvxl
, 0x07, 0x0B),
10398 GEN_VR_LVE(bx
, 0x07, 0x00),
10399 GEN_VR_LVE(hx
, 0x07, 0x01),
10400 GEN_VR_LVE(wx
, 0x07, 0x02),
10401 GEN_VR_STX(svx
, 0x07, 0x07),
10402 GEN_VR_STX(svxl
, 0x07, 0x0F),
10403 GEN_VR_STVE(bx
, 0x07, 0x04),
10404 GEN_VR_STVE(hx
, 0x07, 0x05),
10405 GEN_VR_STVE(wx
, 0x07, 0x06),
10407 #undef GEN_VX_LOGICAL
10408 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10409 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10411 #undef GEN_VX_LOGICAL_207
10412 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10413 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10415 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16),
10416 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17),
10417 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18),
10418 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19),
10419 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20),
10420 GEN_VX_LOGICAL_207(veqv
, tcg_gen_eqv_i64
, 2, 26),
10421 GEN_VX_LOGICAL_207(vnand
, tcg_gen_nand_i64
, 2, 22),
10422 GEN_VX_LOGICAL_207(vorc
, tcg_gen_orc_i64
, 2, 21),
10425 #define GEN_VXFORM(name, opc2, opc3) \
10426 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10428 #undef GEN_VXFORM_207
10429 #define GEN_VXFORM_207(name, opc2, opc3) \
10430 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10432 #undef GEN_VXFORM_DUAL
10433 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10434 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10436 #undef GEN_VXRFORM_DUAL
10437 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10438 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10439 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10441 GEN_VXFORM(vaddubm
, 0, 0),
10442 GEN_VXFORM(vadduhm
, 0, 1),
10443 GEN_VXFORM(vadduwm
, 0, 2),
10444 GEN_VXFORM_207(vaddudm
, 0, 3),
10445 GEN_VXFORM_DUAL(vsububm
, bcdadd
, 0, 16, PPC_ALTIVEC
, PPC_NONE
),
10446 GEN_VXFORM_DUAL(vsubuhm
, bcdsub
, 0, 17, PPC_ALTIVEC
, PPC_NONE
),
10447 GEN_VXFORM(vsubuwm
, 0, 18),
10448 GEN_VXFORM_207(vsubudm
, 0, 19),
10449 GEN_VXFORM(vmaxub
, 1, 0),
10450 GEN_VXFORM(vmaxuh
, 1, 1),
10451 GEN_VXFORM(vmaxuw
, 1, 2),
10452 GEN_VXFORM_207(vmaxud
, 1, 3),
10453 GEN_VXFORM(vmaxsb
, 1, 4),
10454 GEN_VXFORM(vmaxsh
, 1, 5),
10455 GEN_VXFORM(vmaxsw
, 1, 6),
10456 GEN_VXFORM_207(vmaxsd
, 1, 7),
10457 GEN_VXFORM(vminub
, 1, 8),
10458 GEN_VXFORM(vminuh
, 1, 9),
10459 GEN_VXFORM(vminuw
, 1, 10),
10460 GEN_VXFORM_207(vminud
, 1, 11),
10461 GEN_VXFORM(vminsb
, 1, 12),
10462 GEN_VXFORM(vminsh
, 1, 13),
10463 GEN_VXFORM(vminsw
, 1, 14),
10464 GEN_VXFORM_207(vminsd
, 1, 15),
10465 GEN_VXFORM(vavgub
, 1, 16),
10466 GEN_VXFORM(vavguh
, 1, 17),
10467 GEN_VXFORM(vavguw
, 1, 18),
10468 GEN_VXFORM(vavgsb
, 1, 20),
10469 GEN_VXFORM(vavgsh
, 1, 21),
10470 GEN_VXFORM(vavgsw
, 1, 22),
10471 GEN_VXFORM(vmrghb
, 6, 0),
10472 GEN_VXFORM(vmrghh
, 6, 1),
10473 GEN_VXFORM(vmrghw
, 6, 2),
10474 GEN_VXFORM(vmrglb
, 6, 4),
10475 GEN_VXFORM(vmrglh
, 6, 5),
10476 GEN_VXFORM(vmrglw
, 6, 6),
10477 GEN_VXFORM_207(vmrgew
, 6, 30),
10478 GEN_VXFORM_207(vmrgow
, 6, 26),
10479 GEN_VXFORM(vmuloub
, 4, 0),
10480 GEN_VXFORM(vmulouh
, 4, 1),
10481 GEN_VXFORM_DUAL(vmulouw
, vmuluwm
, 4, 2, PPC_ALTIVEC
, PPC_NONE
),
10482 GEN_VXFORM(vmulosb
, 4, 4),
10483 GEN_VXFORM(vmulosh
, 4, 5),
10484 GEN_VXFORM_207(vmulosw
, 4, 6),
10485 GEN_VXFORM(vmuleub
, 4, 8),
10486 GEN_VXFORM(vmuleuh
, 4, 9),
10487 GEN_VXFORM_207(vmuleuw
, 4, 10),
10488 GEN_VXFORM(vmulesb
, 4, 12),
10489 GEN_VXFORM(vmulesh
, 4, 13),
10490 GEN_VXFORM_207(vmulesw
, 4, 14),
10491 GEN_VXFORM(vslb
, 2, 4),
10492 GEN_VXFORM(vslh
, 2, 5),
10493 GEN_VXFORM(vslw
, 2, 6),
10494 GEN_VXFORM_207(vsld
, 2, 23),
10495 GEN_VXFORM(vsrb
, 2, 8),
10496 GEN_VXFORM(vsrh
, 2, 9),
10497 GEN_VXFORM(vsrw
, 2, 10),
10498 GEN_VXFORM_207(vsrd
, 2, 27),
10499 GEN_VXFORM(vsrab
, 2, 12),
10500 GEN_VXFORM(vsrah
, 2, 13),
10501 GEN_VXFORM(vsraw
, 2, 14),
10502 GEN_VXFORM_207(vsrad
, 2, 15),
10503 GEN_VXFORM(vslo
, 6, 16),
10504 GEN_VXFORM(vsro
, 6, 17),
10505 GEN_VXFORM(vaddcuw
, 0, 6),
10506 GEN_VXFORM(vsubcuw
, 0, 22),
10507 GEN_VXFORM(vaddubs
, 0, 8),
10508 GEN_VXFORM(vadduhs
, 0, 9),
10509 GEN_VXFORM(vadduws
, 0, 10),
10510 GEN_VXFORM(vaddsbs
, 0, 12),
10511 GEN_VXFORM(vaddshs
, 0, 13),
10512 GEN_VXFORM(vaddsws
, 0, 14),
10513 GEN_VXFORM_DUAL(vsububs
, bcdadd
, 0, 24, PPC_ALTIVEC
, PPC_NONE
),
10514 GEN_VXFORM_DUAL(vsubuhs
, bcdsub
, 0, 25, PPC_ALTIVEC
, PPC_NONE
),
10515 GEN_VXFORM(vsubuws
, 0, 26),
10516 GEN_VXFORM(vsubsbs
, 0, 28),
10517 GEN_VXFORM(vsubshs
, 0, 29),
10518 GEN_VXFORM(vsubsws
, 0, 30),
10519 GEN_VXFORM_207(vadduqm
, 0, 4),
10520 GEN_VXFORM_207(vaddcuq
, 0, 5),
10521 GEN_VXFORM_DUAL(vaddeuqm
, vaddecuq
, 30, 0xFF, PPC_NONE
, PPC2_ALTIVEC_207
),
10522 GEN_VXFORM_207(vsubuqm
, 0, 20),
10523 GEN_VXFORM_207(vsubcuq
, 0, 21),
10524 GEN_VXFORM_DUAL(vsubeuqm
, vsubecuq
, 31, 0xFF, PPC_NONE
, PPC2_ALTIVEC_207
),
10525 GEN_VXFORM(vrlb
, 2, 0),
10526 GEN_VXFORM(vrlh
, 2, 1),
10527 GEN_VXFORM(vrlw
, 2, 2),
10528 GEN_VXFORM_207(vrld
, 2, 3),
10529 GEN_VXFORM(vsl
, 2, 7),
10530 GEN_VXFORM(vsr
, 2, 11),
10531 GEN_VXFORM(vpkuhum
, 7, 0),
10532 GEN_VXFORM(vpkuwum
, 7, 1),
10533 GEN_VXFORM_207(vpkudum
, 7, 17),
10534 GEN_VXFORM(vpkuhus
, 7, 2),
10535 GEN_VXFORM(vpkuwus
, 7, 3),
10536 GEN_VXFORM_207(vpkudus
, 7, 19),
10537 GEN_VXFORM(vpkshus
, 7, 4),
10538 GEN_VXFORM(vpkswus
, 7, 5),
10539 GEN_VXFORM_207(vpksdus
, 7, 21),
10540 GEN_VXFORM(vpkshss
, 7, 6),
10541 GEN_VXFORM(vpkswss
, 7, 7),
10542 GEN_VXFORM_207(vpksdss
, 7, 23),
10543 GEN_VXFORM(vpkpx
, 7, 12),
10544 GEN_VXFORM(vsum4ubs
, 4, 24),
10545 GEN_VXFORM(vsum4sbs
, 4, 28),
10546 GEN_VXFORM(vsum4shs
, 4, 25),
10547 GEN_VXFORM(vsum2sws
, 4, 26),
10548 GEN_VXFORM(vsumsws
, 4, 30),
10549 GEN_VXFORM(vaddfp
, 5, 0),
10550 GEN_VXFORM(vsubfp
, 5, 1),
10551 GEN_VXFORM(vmaxfp
, 5, 16),
10552 GEN_VXFORM(vminfp
, 5, 17),
10554 #undef GEN_VXRFORM1
10556 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10557 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10558 #define GEN_VXRFORM(name, opc2, opc3) \
10559 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10560 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10561 GEN_VXRFORM(vcmpequb
, 3, 0)
10562 GEN_VXRFORM(vcmpequh
, 3, 1)
10563 GEN_VXRFORM(vcmpequw
, 3, 2)
10564 GEN_VXRFORM(vcmpgtsb
, 3, 12)
10565 GEN_VXRFORM(vcmpgtsh
, 3, 13)
10566 GEN_VXRFORM(vcmpgtsw
, 3, 14)
10567 GEN_VXRFORM(vcmpgtub
, 3, 8)
10568 GEN_VXRFORM(vcmpgtuh
, 3, 9)
10569 GEN_VXRFORM(vcmpgtuw
, 3, 10)
10570 GEN_VXRFORM_DUAL(vcmpeqfp
, vcmpequd
, 3, 3, PPC_ALTIVEC
, PPC_NONE
)
10571 GEN_VXRFORM(vcmpgefp
, 3, 7)
10572 GEN_VXRFORM_DUAL(vcmpgtfp
, vcmpgtud
, 3, 11, PPC_ALTIVEC
, PPC_NONE
)
10573 GEN_VXRFORM_DUAL(vcmpbfp
, vcmpgtsd
, 3, 15, PPC_ALTIVEC
, PPC_NONE
)
10575 #undef GEN_VXFORM_SIMM
10576 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10577 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10578 GEN_VXFORM_SIMM(vspltisb
, 6, 12),
10579 GEN_VXFORM_SIMM(vspltish
, 6, 13),
10580 GEN_VXFORM_SIMM(vspltisw
, 6, 14),
10582 #undef GEN_VXFORM_NOA
10583 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10584 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10585 GEN_VXFORM_NOA(vupkhsb
, 7, 8),
10586 GEN_VXFORM_NOA(vupkhsh
, 7, 9),
10587 GEN_VXFORM_207(vupkhsw
, 7, 25),
10588 GEN_VXFORM_NOA(vupklsb
, 7, 10),
10589 GEN_VXFORM_NOA(vupklsh
, 7, 11),
10590 GEN_VXFORM_207(vupklsw
, 7, 27),
10591 GEN_VXFORM_NOA(vupkhpx
, 7, 13),
10592 GEN_VXFORM_NOA(vupklpx
, 7, 15),
10593 GEN_VXFORM_NOA(vrefp
, 5, 4),
10594 GEN_VXFORM_NOA(vrsqrtefp
, 5, 5),
10595 GEN_VXFORM_NOA(vexptefp
, 5, 6),
10596 GEN_VXFORM_NOA(vlogefp
, 5, 7),
10597 GEN_VXFORM_NOA(vrfim
, 5, 11),
10598 GEN_VXFORM_NOA(vrfin
, 5, 8),
10599 GEN_VXFORM_NOA(vrfip
, 5, 10),
10600 GEN_VXFORM_NOA(vrfiz
, 5, 9),
10602 #undef GEN_VXFORM_UIMM
10603 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10604 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10605 GEN_VXFORM_UIMM(vspltb
, 6, 8),
10606 GEN_VXFORM_UIMM(vsplth
, 6, 9),
10607 GEN_VXFORM_UIMM(vspltw
, 6, 10),
10608 GEN_VXFORM_UIMM(vcfux
, 5, 12),
10609 GEN_VXFORM_UIMM(vcfsx
, 5, 13),
10610 GEN_VXFORM_UIMM(vctuxs
, 5, 14),
10611 GEN_VXFORM_UIMM(vctsxs
, 5, 15),
10613 #undef GEN_VAFORM_PAIRED
10614 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10615 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10616 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16),
10617 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18),
10618 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19),
10619 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20),
10620 GEN_VAFORM_PAIRED(vsel
, vperm
, 21),
10621 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23),
10623 GEN_VXFORM_DUAL(vclzb
, vpopcntb
, 1, 28, PPC_NONE
, PPC2_ALTIVEC_207
),
10624 GEN_VXFORM_DUAL(vclzh
, vpopcnth
, 1, 29, PPC_NONE
, PPC2_ALTIVEC_207
),
10625 GEN_VXFORM_DUAL(vclzw
, vpopcntw
, 1, 30, PPC_NONE
, PPC2_ALTIVEC_207
),
10626 GEN_VXFORM_DUAL(vclzd
, vpopcntd
, 1, 31, PPC_NONE
, PPC2_ALTIVEC_207
),
10628 GEN_VXFORM_207(vbpermq
, 6, 21),
10629 GEN_VXFORM_207(vgbbd
, 6, 20),
10630 GEN_VXFORM_207(vpmsumb
, 4, 16),
10631 GEN_VXFORM_207(vpmsumh
, 4, 17),
10632 GEN_VXFORM_207(vpmsumw
, 4, 18),
10633 GEN_VXFORM_207(vpmsumd
, 4, 19),
10635 GEN_VXFORM_207(vsbox
, 4, 23),
10637 GEN_VXFORM_DUAL(vcipher
, vcipherlast
, 4, 20, PPC_NONE
, PPC2_ALTIVEC_207
),
10638 GEN_VXFORM_DUAL(vncipher
, vncipherlast
, 4, 21, PPC_NONE
, PPC2_ALTIVEC_207
),
10640 GEN_VXFORM_207(vshasigmaw
, 1, 26),
10641 GEN_VXFORM_207(vshasigmad
, 1, 27),
10643 GEN_VXFORM_DUAL(vsldoi
, vpermxor
, 22, 0xFF, PPC_ALTIVEC
, PPC_NONE
),
10645 GEN_HANDLER_E(lxsdx
, 0x1F, 0x0C, 0x12, 0, PPC_NONE
, PPC2_VSX
),
10646 GEN_HANDLER_E(lxsiwax
, 0x1F, 0x0C, 0x02, 0, PPC_NONE
, PPC2_VSX207
),
10647 GEN_HANDLER_E(lxsiwzx
, 0x1F, 0x0C, 0x00, 0, PPC_NONE
, PPC2_VSX207
),
10648 GEN_HANDLER_E(lxsspx
, 0x1F, 0x0C, 0x10, 0, PPC_NONE
, PPC2_VSX207
),
10649 GEN_HANDLER_E(lxvd2x
, 0x1F, 0x0C, 0x1A, 0, PPC_NONE
, PPC2_VSX
),
10650 GEN_HANDLER_E(lxvdsx
, 0x1F, 0x0C, 0x0A, 0, PPC_NONE
, PPC2_VSX
),
10651 GEN_HANDLER_E(lxvw4x
, 0x1F, 0x0C, 0x18, 0, PPC_NONE
, PPC2_VSX
),
10653 GEN_HANDLER_E(stxsdx
, 0x1F, 0xC, 0x16, 0, PPC_NONE
, PPC2_VSX
),
10654 GEN_HANDLER_E(stxsiwx
, 0x1F, 0xC, 0x04, 0, PPC_NONE
, PPC2_VSX207
),
10655 GEN_HANDLER_E(stxsspx
, 0x1F, 0xC, 0x14, 0, PPC_NONE
, PPC2_VSX207
),
10656 GEN_HANDLER_E(stxvd2x
, 0x1F, 0xC, 0x1E, 0, PPC_NONE
, PPC2_VSX
),
10657 GEN_HANDLER_E(stxvw4x
, 0x1F, 0xC, 0x1C, 0, PPC_NONE
, PPC2_VSX
),
10659 GEN_HANDLER_E(mfvsrwz
, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10660 GEN_HANDLER_E(mtvsrwa
, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10661 GEN_HANDLER_E(mtvsrwz
, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10662 #if defined(TARGET_PPC64)
10663 GEN_HANDLER_E(mfvsrd
, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10664 GEN_HANDLER_E(mtvsrd
, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10668 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10669 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10670 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10673 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10674 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10675 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10676 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10677 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10679 #undef GEN_XX3_RC_FORM
10680 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10681 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10682 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10683 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10684 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10685 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10686 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10687 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10688 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10690 #undef GEN_XX3FORM_DM
10691 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10692 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10693 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10694 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10695 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10696 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10697 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10698 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10699 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10700 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10701 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10702 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10703 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10704 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10705 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10706 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10707 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10709 GEN_XX2FORM(xsabsdp
, 0x12, 0x15, PPC2_VSX
),
10710 GEN_XX2FORM(xsnabsdp
, 0x12, 0x16, PPC2_VSX
),
10711 GEN_XX2FORM(xsnegdp
, 0x12, 0x17, PPC2_VSX
),
10712 GEN_XX3FORM(xscpsgndp
, 0x00, 0x16, PPC2_VSX
),
10714 GEN_XX2FORM(xvabsdp
, 0x12, 0x1D, PPC2_VSX
),
10715 GEN_XX2FORM(xvnabsdp
, 0x12, 0x1E, PPC2_VSX
),
10716 GEN_XX2FORM(xvnegdp
, 0x12, 0x1F, PPC2_VSX
),
10717 GEN_XX3FORM(xvcpsgndp
, 0x00, 0x1E, PPC2_VSX
),
10718 GEN_XX2FORM(xvabssp
, 0x12, 0x19, PPC2_VSX
),
10719 GEN_XX2FORM(xvnabssp
, 0x12, 0x1A, PPC2_VSX
),
10720 GEN_XX2FORM(xvnegsp
, 0x12, 0x1B, PPC2_VSX
),
10721 GEN_XX3FORM(xvcpsgnsp
, 0x00, 0x1A, PPC2_VSX
),
10723 GEN_XX3FORM(xsadddp
, 0x00, 0x04, PPC2_VSX
),
10724 GEN_XX3FORM(xssubdp
, 0x00, 0x05, PPC2_VSX
),
10725 GEN_XX3FORM(xsmuldp
, 0x00, 0x06, PPC2_VSX
),
10726 GEN_XX3FORM(xsdivdp
, 0x00, 0x07, PPC2_VSX
),
10727 GEN_XX2FORM(xsredp
, 0x14, 0x05, PPC2_VSX
),
10728 GEN_XX2FORM(xssqrtdp
, 0x16, 0x04, PPC2_VSX
),
10729 GEN_XX2FORM(xsrsqrtedp
, 0x14, 0x04, PPC2_VSX
),
10730 GEN_XX3FORM(xstdivdp
, 0x14, 0x07, PPC2_VSX
),
10731 GEN_XX2FORM(xstsqrtdp
, 0x14, 0x06, PPC2_VSX
),
10732 GEN_XX3FORM(xsmaddadp
, 0x04, 0x04, PPC2_VSX
),
10733 GEN_XX3FORM(xsmaddmdp
, 0x04, 0x05, PPC2_VSX
),
10734 GEN_XX3FORM(xsmsubadp
, 0x04, 0x06, PPC2_VSX
),
10735 GEN_XX3FORM(xsmsubmdp
, 0x04, 0x07, PPC2_VSX
),
10736 GEN_XX3FORM(xsnmaddadp
, 0x04, 0x14, PPC2_VSX
),
10737 GEN_XX3FORM(xsnmaddmdp
, 0x04, 0x15, PPC2_VSX
),
10738 GEN_XX3FORM(xsnmsubadp
, 0x04, 0x16, PPC2_VSX
),
10739 GEN_XX3FORM(xsnmsubmdp
, 0x04, 0x17, PPC2_VSX
),
10740 GEN_XX2FORM(xscmpodp
, 0x0C, 0x05, PPC2_VSX
),
10741 GEN_XX2FORM(xscmpudp
, 0x0C, 0x04, PPC2_VSX
),
10742 GEN_XX3FORM(xsmaxdp
, 0x00, 0x14, PPC2_VSX
),
10743 GEN_XX3FORM(xsmindp
, 0x00, 0x15, PPC2_VSX
),
10744 GEN_XX2FORM(xscvdpsp
, 0x12, 0x10, PPC2_VSX
),
10745 GEN_XX2FORM(xscvdpspn
, 0x16, 0x10, PPC2_VSX207
),
10746 GEN_XX2FORM(xscvspdp
, 0x12, 0x14, PPC2_VSX
),
10747 GEN_XX2FORM(xscvspdpn
, 0x16, 0x14, PPC2_VSX207
),
10748 GEN_XX2FORM(xscvdpsxds
, 0x10, 0x15, PPC2_VSX
),
10749 GEN_XX2FORM(xscvdpsxws
, 0x10, 0x05, PPC2_VSX
),
10750 GEN_XX2FORM(xscvdpuxds
, 0x10, 0x14, PPC2_VSX
),
10751 GEN_XX2FORM(xscvdpuxws
, 0x10, 0x04, PPC2_VSX
),
10752 GEN_XX2FORM(xscvsxddp
, 0x10, 0x17, PPC2_VSX
),
10753 GEN_XX2FORM(xscvuxddp
, 0x10, 0x16, PPC2_VSX
),
10754 GEN_XX2FORM(xsrdpi
, 0x12, 0x04, PPC2_VSX
),
10755 GEN_XX2FORM(xsrdpic
, 0x16, 0x06, PPC2_VSX
),
10756 GEN_XX2FORM(xsrdpim
, 0x12, 0x07, PPC2_VSX
),
10757 GEN_XX2FORM(xsrdpip
, 0x12, 0x06, PPC2_VSX
),
10758 GEN_XX2FORM(xsrdpiz
, 0x12, 0x05, PPC2_VSX
),
10760 GEN_XX3FORM(xsaddsp
, 0x00, 0x00, PPC2_VSX207
),
10761 GEN_XX3FORM(xssubsp
, 0x00, 0x01, PPC2_VSX207
),
10762 GEN_XX3FORM(xsmulsp
, 0x00, 0x02, PPC2_VSX207
),
10763 GEN_XX3FORM(xsdivsp
, 0x00, 0x03, PPC2_VSX207
),
10764 GEN_XX2FORM(xsresp
, 0x14, 0x01, PPC2_VSX207
),
10765 GEN_XX2FORM(xsrsp
, 0x12, 0x11, PPC2_VSX207
),
10766 GEN_XX2FORM(xssqrtsp
, 0x16, 0x00, PPC2_VSX207
),
10767 GEN_XX2FORM(xsrsqrtesp
, 0x14, 0x00, PPC2_VSX207
),
10768 GEN_XX3FORM(xsmaddasp
, 0x04, 0x00, PPC2_VSX207
),
10769 GEN_XX3FORM(xsmaddmsp
, 0x04, 0x01, PPC2_VSX207
),
10770 GEN_XX3FORM(xsmsubasp
, 0x04, 0x02, PPC2_VSX207
),
10771 GEN_XX3FORM(xsmsubmsp
, 0x04, 0x03, PPC2_VSX207
),
10772 GEN_XX3FORM(xsnmaddasp
, 0x04, 0x10, PPC2_VSX207
),
10773 GEN_XX3FORM(xsnmaddmsp
, 0x04, 0x11, PPC2_VSX207
),
10774 GEN_XX3FORM(xsnmsubasp
, 0x04, 0x12, PPC2_VSX207
),
10775 GEN_XX3FORM(xsnmsubmsp
, 0x04, 0x13, PPC2_VSX207
),
10776 GEN_XX2FORM(xscvsxdsp
, 0x10, 0x13, PPC2_VSX207
),
10777 GEN_XX2FORM(xscvuxdsp
, 0x10, 0x12, PPC2_VSX207
),
10779 GEN_XX3FORM(xvadddp
, 0x00, 0x0C, PPC2_VSX
),
10780 GEN_XX3FORM(xvsubdp
, 0x00, 0x0D, PPC2_VSX
),
10781 GEN_XX3FORM(xvmuldp
, 0x00, 0x0E, PPC2_VSX
),
10782 GEN_XX3FORM(xvdivdp
, 0x00, 0x0F, PPC2_VSX
),
10783 GEN_XX2FORM(xvredp
, 0x14, 0x0D, PPC2_VSX
),
10784 GEN_XX2FORM(xvsqrtdp
, 0x16, 0x0C, PPC2_VSX
),
10785 GEN_XX2FORM(xvrsqrtedp
, 0x14, 0x0C, PPC2_VSX
),
10786 GEN_XX3FORM(xvtdivdp
, 0x14, 0x0F, PPC2_VSX
),
10787 GEN_XX2FORM(xvtsqrtdp
, 0x14, 0x0E, PPC2_VSX
),
10788 GEN_XX3FORM(xvmaddadp
, 0x04, 0x0C, PPC2_VSX
),
10789 GEN_XX3FORM(xvmaddmdp
, 0x04, 0x0D, PPC2_VSX
),
10790 GEN_XX3FORM(xvmsubadp
, 0x04, 0x0E, PPC2_VSX
),
10791 GEN_XX3FORM(xvmsubmdp
, 0x04, 0x0F, PPC2_VSX
),
10792 GEN_XX3FORM(xvnmaddadp
, 0x04, 0x1C, PPC2_VSX
),
10793 GEN_XX3FORM(xvnmaddmdp
, 0x04, 0x1D, PPC2_VSX
),
10794 GEN_XX3FORM(xvnmsubadp
, 0x04, 0x1E, PPC2_VSX
),
10795 GEN_XX3FORM(xvnmsubmdp
, 0x04, 0x1F, PPC2_VSX
),
10796 GEN_XX3FORM(xvmaxdp
, 0x00, 0x1C, PPC2_VSX
),
10797 GEN_XX3FORM(xvmindp
, 0x00, 0x1D, PPC2_VSX
),
10798 GEN_XX3_RC_FORM(xvcmpeqdp
, 0x0C, 0x0C, PPC2_VSX
),
10799 GEN_XX3_RC_FORM(xvcmpgtdp
, 0x0C, 0x0D, PPC2_VSX
),
10800 GEN_XX3_RC_FORM(xvcmpgedp
, 0x0C, 0x0E, PPC2_VSX
),
10801 GEN_XX2FORM(xvcvdpsp
, 0x12, 0x18, PPC2_VSX
),
10802 GEN_XX2FORM(xvcvdpsxds
, 0x10, 0x1D, PPC2_VSX
),
10803 GEN_XX2FORM(xvcvdpsxws
, 0x10, 0x0D, PPC2_VSX
),
10804 GEN_XX2FORM(xvcvdpuxds
, 0x10, 0x1C, PPC2_VSX
),
10805 GEN_XX2FORM(xvcvdpuxws
, 0x10, 0x0C, PPC2_VSX
),
10806 GEN_XX2FORM(xvcvsxddp
, 0x10, 0x1F, PPC2_VSX
),
10807 GEN_XX2FORM(xvcvuxddp
, 0x10, 0x1E, PPC2_VSX
),
10808 GEN_XX2FORM(xvcvsxwdp
, 0x10, 0x0F, PPC2_VSX
),
10809 GEN_XX2FORM(xvcvuxwdp
, 0x10, 0x0E, PPC2_VSX
),
10810 GEN_XX2FORM(xvrdpi
, 0x12, 0x0C, PPC2_VSX
),
10811 GEN_XX2FORM(xvrdpic
, 0x16, 0x0E, PPC2_VSX
),
10812 GEN_XX2FORM(xvrdpim
, 0x12, 0x0F, PPC2_VSX
),
10813 GEN_XX2FORM(xvrdpip
, 0x12, 0x0E, PPC2_VSX
),
10814 GEN_XX2FORM(xvrdpiz
, 0x12, 0x0D, PPC2_VSX
),
10816 GEN_XX3FORM(xvaddsp
, 0x00, 0x08, PPC2_VSX
),
10817 GEN_XX3FORM(xvsubsp
, 0x00, 0x09, PPC2_VSX
),
10818 GEN_XX3FORM(xvmulsp
, 0x00, 0x0A, PPC2_VSX
),
10819 GEN_XX3FORM(xvdivsp
, 0x00, 0x0B, PPC2_VSX
),
10820 GEN_XX2FORM(xvresp
, 0x14, 0x09, PPC2_VSX
),
10821 GEN_XX2FORM(xvsqrtsp
, 0x16, 0x08, PPC2_VSX
),
10822 GEN_XX2FORM(xvrsqrtesp
, 0x14, 0x08, PPC2_VSX
),
10823 GEN_XX3FORM(xvtdivsp
, 0x14, 0x0B, PPC2_VSX
),
10824 GEN_XX2FORM(xvtsqrtsp
, 0x14, 0x0A, PPC2_VSX
),
10825 GEN_XX3FORM(xvmaddasp
, 0x04, 0x08, PPC2_VSX
),
10826 GEN_XX3FORM(xvmaddmsp
, 0x04, 0x09, PPC2_VSX
),
10827 GEN_XX3FORM(xvmsubasp
, 0x04, 0x0A, PPC2_VSX
),
10828 GEN_XX3FORM(xvmsubmsp
, 0x04, 0x0B, PPC2_VSX
),
10829 GEN_XX3FORM(xvnmaddasp
, 0x04, 0x18, PPC2_VSX
),
10830 GEN_XX3FORM(xvnmaddmsp
, 0x04, 0x19, PPC2_VSX
),
10831 GEN_XX3FORM(xvnmsubasp
, 0x04, 0x1A, PPC2_VSX
),
10832 GEN_XX3FORM(xvnmsubmsp
, 0x04, 0x1B, PPC2_VSX
),
10833 GEN_XX3FORM(xvmaxsp
, 0x00, 0x18, PPC2_VSX
),
10834 GEN_XX3FORM(xvminsp
, 0x00, 0x19, PPC2_VSX
),
10835 GEN_XX3_RC_FORM(xvcmpeqsp
, 0x0C, 0x08, PPC2_VSX
),
10836 GEN_XX3_RC_FORM(xvcmpgtsp
, 0x0C, 0x09, PPC2_VSX
),
10837 GEN_XX3_RC_FORM(xvcmpgesp
, 0x0C, 0x0A, PPC2_VSX
),
10838 GEN_XX2FORM(xvcvspdp
, 0x12, 0x1C, PPC2_VSX
),
10839 GEN_XX2FORM(xvcvspsxds
, 0x10, 0x19, PPC2_VSX
),
10840 GEN_XX2FORM(xvcvspsxws
, 0x10, 0x09, PPC2_VSX
),
10841 GEN_XX2FORM(xvcvspuxds
, 0x10, 0x18, PPC2_VSX
),
10842 GEN_XX2FORM(xvcvspuxws
, 0x10, 0x08, PPC2_VSX
),
10843 GEN_XX2FORM(xvcvsxdsp
, 0x10, 0x1B, PPC2_VSX
),
10844 GEN_XX2FORM(xvcvuxdsp
, 0x10, 0x1A, PPC2_VSX
),
10845 GEN_XX2FORM(xvcvsxwsp
, 0x10, 0x0B, PPC2_VSX
),
10846 GEN_XX2FORM(xvcvuxwsp
, 0x10, 0x0A, PPC2_VSX
),
10847 GEN_XX2FORM(xvrspi
, 0x12, 0x08, PPC2_VSX
),
10848 GEN_XX2FORM(xvrspic
, 0x16, 0x0A, PPC2_VSX
),
10849 GEN_XX2FORM(xvrspim
, 0x12, 0x0B, PPC2_VSX
),
10850 GEN_XX2FORM(xvrspip
, 0x12, 0x0A, PPC2_VSX
),
10851 GEN_XX2FORM(xvrspiz
, 0x12, 0x09, PPC2_VSX
),
10854 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10855 GEN_XX3FORM(name, opc2, opc3, fl2)
10857 VSX_LOGICAL(xxland
, 0x8, 0x10, PPC2_VSX
),
10858 VSX_LOGICAL(xxlandc
, 0x8, 0x11, PPC2_VSX
),
10859 VSX_LOGICAL(xxlor
, 0x8, 0x12, PPC2_VSX
),
10860 VSX_LOGICAL(xxlxor
, 0x8, 0x13, PPC2_VSX
),
10861 VSX_LOGICAL(xxlnor
, 0x8, 0x14, PPC2_VSX
),
10862 VSX_LOGICAL(xxleqv
, 0x8, 0x17, PPC2_VSX207
),
10863 VSX_LOGICAL(xxlnand
, 0x8, 0x16, PPC2_VSX207
),
10864 VSX_LOGICAL(xxlorc
, 0x8, 0x15, PPC2_VSX207
),
10865 GEN_XX3FORM(xxmrghw
, 0x08, 0x02, PPC2_VSX
),
10866 GEN_XX3FORM(xxmrglw
, 0x08, 0x06, PPC2_VSX
),
10867 GEN_XX2FORM(xxspltw
, 0x08, 0x0A, PPC2_VSX
),
10868 GEN_XX3FORM_DM(xxsldwi
, 0x08, 0x00),
10870 #define GEN_XXSEL_ROW(opc3) \
10871 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10872 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10873 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10874 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10875 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10876 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10877 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10878 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10880 GEN_XXSEL_ROW(0x00)
10881 GEN_XXSEL_ROW(0x01)
10882 GEN_XXSEL_ROW(0x02)
10883 GEN_XXSEL_ROW(0x03)
10884 GEN_XXSEL_ROW(0x04)
10885 GEN_XXSEL_ROW(0x05)
10886 GEN_XXSEL_ROW(0x06)
10887 GEN_XXSEL_ROW(0x07)
10888 GEN_XXSEL_ROW(0x08)
10889 GEN_XXSEL_ROW(0x09)
10890 GEN_XXSEL_ROW(0x0A)
10891 GEN_XXSEL_ROW(0x0B)
10892 GEN_XXSEL_ROW(0x0C)
10893 GEN_XXSEL_ROW(0x0D)
10894 GEN_XXSEL_ROW(0x0E)
10895 GEN_XXSEL_ROW(0x0F)
10896 GEN_XXSEL_ROW(0x10)
10897 GEN_XXSEL_ROW(0x11)
10898 GEN_XXSEL_ROW(0x12)
10899 GEN_XXSEL_ROW(0x13)
10900 GEN_XXSEL_ROW(0x14)
10901 GEN_XXSEL_ROW(0x15)
10902 GEN_XXSEL_ROW(0x16)
10903 GEN_XXSEL_ROW(0x17)
10904 GEN_XXSEL_ROW(0x18)
10905 GEN_XXSEL_ROW(0x19)
10906 GEN_XXSEL_ROW(0x1A)
10907 GEN_XXSEL_ROW(0x1B)
10908 GEN_XXSEL_ROW(0x1C)
10909 GEN_XXSEL_ROW(0x1D)
10910 GEN_XXSEL_ROW(0x1E)
10911 GEN_XXSEL_ROW(0x1F)
10913 GEN_XX3FORM_DM(xxpermdi
, 0x08, 0x01),
10915 #undef GEN_DFP_T_A_B_Rc
10916 #undef GEN_DFP_BF_A_B
10917 #undef GEN_DFP_BF_A_DCM
10918 #undef GEN_DFP_T_B_U32_U32_Rc
10919 #undef GEN_DFP_T_A_B_I32_Rc
10920 #undef GEN_DFP_T_B_Rc
10921 #undef GEN_DFP_T_FPR_I32_Rc
10923 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10924 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10926 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10927 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10928 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10930 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10931 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10932 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10933 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10934 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10936 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10937 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10939 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10940 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10941 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10943 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10944 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10945 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10946 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10947 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10949 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10950 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10952 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10953 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10955 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10956 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10958 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10959 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10961 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10962 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10964 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10965 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10967 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10968 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10970 #define GEN_DFP_BF_A_B(name, op1, op2) \
10971 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10973 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10974 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10976 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
10977 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10979 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
10980 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10982 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10983 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10985 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10986 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10988 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10989 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10991 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10992 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10994 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10995 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10997 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10998 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11000 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11001 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11003 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11004 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11006 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11007 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11009 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11010 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11012 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11013 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11015 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11016 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11018 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11019 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11021 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11022 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11024 GEN_DFP_T_A_B_Rc(dadd
, 0x02, 0x00),
11025 GEN_DFP_Tp_Ap_Bp_Rc(daddq
, 0x02, 0x00),
11026 GEN_DFP_T_A_B_Rc(dsub
, 0x02, 0x10),
11027 GEN_DFP_Tp_Ap_Bp_Rc(dsubq
, 0x02, 0x10),
11028 GEN_DFP_T_A_B_Rc(dmul
, 0x02, 0x01),
11029 GEN_DFP_Tp_Ap_Bp_Rc(dmulq
, 0x02, 0x01),
11030 GEN_DFP_T_A_B_Rc(ddiv
, 0x02, 0x11),
11031 GEN_DFP_Tp_Ap_Bp_Rc(ddivq
, 0x02, 0x11),
11032 GEN_DFP_BF_A_B(dcmpu
, 0x02, 0x14),
11033 GEN_DFP_BF_Ap_Bp(dcmpuq
, 0x02, 0x14),
11034 GEN_DFP_BF_A_B(dcmpo
, 0x02, 0x04),
11035 GEN_DFP_BF_Ap_Bp(dcmpoq
, 0x02, 0x04),
11036 GEN_DFP_BF_A_DCM(dtstdc
, 0x02, 0x06),
11037 GEN_DFP_BF_Ap_DCM(dtstdcq
, 0x02, 0x06),
11038 GEN_DFP_BF_A_DCM(dtstdg
, 0x02, 0x07),
11039 GEN_DFP_BF_Ap_DCM(dtstdgq
, 0x02, 0x07),
11040 GEN_DFP_BF_A_B(dtstex
, 0x02, 0x05),
11041 GEN_DFP_BF_Ap_Bp(dtstexq
, 0x02, 0x05),
11042 GEN_DFP_BF_A_B(dtstsf
, 0x02, 0x15),
11043 GEN_DFP_BF_A_Bp(dtstsfq
, 0x02, 0x15),
11044 GEN_DFP_TE_T_B_RMC_Rc(dquai
, 0x03, 0x02),
11045 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq
, 0x03, 0x02),
11046 GEN_DFP_T_A_B_RMC_Rc(dqua
, 0x03, 0x00),
11047 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq
, 0x03, 0x00),
11048 GEN_DFP_T_A_B_RMC_Rc(drrnd
, 0x03, 0x01),
11049 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq
, 0x03, 0x01),
11050 GEN_DFP_R_T_B_RMC_Rc(drintx
, 0x03, 0x03),
11051 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq
, 0x03, 0x03),
11052 GEN_DFP_R_T_B_RMC_Rc(drintn
, 0x03, 0x07),
11053 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq
, 0x03, 0x07),
11054 GEN_DFP_T_B_Rc(dctdp
, 0x02, 0x08),
11055 GEN_DFP_Tp_B_Rc(dctqpq
, 0x02, 0x08),
11056 GEN_DFP_T_B_Rc(drsp
, 0x02, 0x18),
11057 GEN_DFP_Tp_Bp_Rc(drdpq
, 0x02, 0x18),
11058 GEN_DFP_T_B_Rc(dcffix
, 0x02, 0x19),
11059 GEN_DFP_Tp_B_Rc(dcffixq
, 0x02, 0x19),
11060 GEN_DFP_T_B_Rc(dctfix
, 0x02, 0x09),
11061 GEN_DFP_T_Bp_Rc(dctfixq
, 0x02, 0x09),
11062 GEN_DFP_SP_T_B_Rc(ddedpd
, 0x02, 0x0a),
11063 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq
, 0x02, 0x0a),
11064 GEN_DFP_S_T_B_Rc(denbcd
, 0x02, 0x1a),
11065 GEN_DFP_S_Tp_Bp_Rc(denbcdq
, 0x02, 0x1a),
11066 GEN_DFP_T_B_Rc(dxex
, 0x02, 0x0b),
11067 GEN_DFP_T_Bp_Rc(dxexq
, 0x02, 0x0b),
11068 GEN_DFP_T_A_B_Rc(diex
, 0x02, 0x1b),
11069 GEN_DFP_Tp_A_Bp_Rc(diexq
, 0x02, 0x1b),
11070 GEN_DFP_T_A_SH_Rc(dscli
, 0x02, 0x02),
11071 GEN_DFP_Tp_Ap_SH_Rc(dscliq
, 0x02, 0x02),
11072 GEN_DFP_T_A_SH_Rc(dscri
, 0x02, 0x03),
11073 GEN_DFP_Tp_Ap_SH_Rc(dscriq
, 0x02, 0x03),
11076 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11077 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11078 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11079 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11080 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11081 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11082 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
11083 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
11084 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
11085 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
),
11086 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
),
11087 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
11088 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11089 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11090 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11091 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
11092 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
11093 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
),
11094 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
11095 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11096 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11097 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11098 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11099 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11100 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
11101 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
11102 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11103 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11104 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
11105 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
11106 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
),
11108 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11109 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
11110 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11111 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11112 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11113 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11114 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11115 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11116 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11117 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11118 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11119 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11120 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11121 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11123 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11124 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
11125 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11126 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11127 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11128 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
),
11129 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11130 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11131 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11132 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11133 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11134 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11135 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11136 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11138 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
11139 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11140 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
),
11141 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11142 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
11143 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11144 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
11145 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
),
11146 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11147 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11148 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11149 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11150 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11151 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11152 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
11153 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11155 #undef GEN_SPEOP_LDST
11156 #define GEN_SPEOP_LDST(name, opc2, sh) \
11157 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11158 GEN_SPEOP_LDST(evldd
, 0x00, 3),
11159 GEN_SPEOP_LDST(evldw
, 0x01, 3),
11160 GEN_SPEOP_LDST(evldh
, 0x02, 3),
11161 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1),
11162 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1),
11163 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1),
11164 GEN_SPEOP_LDST(evlwhe
, 0x08, 2),
11165 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2),
11166 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2),
11167 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2),
11168 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2),
11170 GEN_SPEOP_LDST(evstdd
, 0x10, 3),
11171 GEN_SPEOP_LDST(evstdw
, 0x11, 3),
11172 GEN_SPEOP_LDST(evstdh
, 0x12, 3),
11173 GEN_SPEOP_LDST(evstwhe
, 0x18, 2),
11174 GEN_SPEOP_LDST(evstwho
, 0x1A, 2),
11175 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2),
11176 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2),
11178 GEN_HANDLER2_E(tbegin
, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11179 PPC_NONE
, PPC2_TM
),
11180 GEN_HANDLER2_E(tend
, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11181 PPC_NONE
, PPC2_TM
),
11182 GEN_HANDLER2_E(tabort
, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11183 PPC_NONE
, PPC2_TM
),
11184 GEN_HANDLER2_E(tabortwc
, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11185 PPC_NONE
, PPC2_TM
),
11186 GEN_HANDLER2_E(tabortwci
, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11187 PPC_NONE
, PPC2_TM
),
11188 GEN_HANDLER2_E(tabortdc
, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11189 PPC_NONE
, PPC2_TM
),
11190 GEN_HANDLER2_E(tabortdci
, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11191 PPC_NONE
, PPC2_TM
),
11192 GEN_HANDLER2_E(tsr
, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11193 PPC_NONE
, PPC2_TM
),
11194 GEN_HANDLER2_E(tcheck
, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11195 PPC_NONE
, PPC2_TM
),
11196 GEN_HANDLER2_E(treclaim
, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11197 PPC_NONE
, PPC2_TM
),
11198 GEN_HANDLER2_E(trechkpt
, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11199 PPC_NONE
, PPC2_TM
),
11202 #include "helper_regs.h"
11203 #include "translate_init.c"
11205 /*****************************************************************************/
11206 /* Misc PowerPC helpers */
11207 void ppc_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
11213 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
11214 CPUPPCState
*env
= &cpu
->env
;
11217 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
11218 TARGET_FMT_lx
" XER " TARGET_FMT_lx
"\n",
11219 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
));
11220 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
11221 TARGET_FMT_lx
" idx %d\n", env
->msr
, env
->spr
[SPR_HID0
],
11222 env
->hflags
, env
->mmu_idx
);
11223 #if !defined(NO_TIMER_DUMP)
11224 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
11225 #if !defined(CONFIG_USER_ONLY)
11229 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
11230 #if !defined(CONFIG_USER_ONLY)
11231 , cpu_ppc_load_decr(env
)
11235 for (i
= 0; i
< 32; i
++) {
11236 if ((i
& (RGPL
- 1)) == 0)
11237 cpu_fprintf(f
, "GPR%02d", i
);
11238 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
11239 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
11240 cpu_fprintf(f
, "\n");
11242 cpu_fprintf(f
, "CR ");
11243 for (i
= 0; i
< 8; i
++)
11244 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
11245 cpu_fprintf(f
, " [");
11246 for (i
= 0; i
< 8; i
++) {
11248 if (env
->crf
[i
] & 0x08)
11250 else if (env
->crf
[i
] & 0x04)
11252 else if (env
->crf
[i
] & 0x02)
11254 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
11256 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
11257 env
->reserve_addr
);
11258 for (i
= 0; i
< 32; i
++) {
11259 if ((i
& (RFPL
- 1)) == 0)
11260 cpu_fprintf(f
, "FPR%02d", i
);
11261 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
11262 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
11263 cpu_fprintf(f
, "\n");
11265 cpu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
11266 #if !defined(CONFIG_USER_ONLY)
11267 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
11268 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
11269 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
11270 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
11272 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
11273 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
11274 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
11275 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
11277 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
11278 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
11279 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
11280 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
11282 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
11283 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
11284 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
11285 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
11286 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
11288 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
11289 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
11290 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
11291 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
11293 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
11294 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
11295 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
11296 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
11298 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
11299 " EPR " TARGET_FMT_lx
"\n",
11300 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
11301 env
->spr
[SPR_BOOKE_EPR
]);
11304 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
11305 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
11306 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
11307 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
11310 * IVORs are left out as they are large and do not change often --
11311 * they can be read with "p $ivor0", "p $ivor1", etc.
11315 #if defined(TARGET_PPC64)
11316 if (env
->flags
& POWERPC_FLAG_CFAR
) {
11317 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
11321 switch (env
->mmu_model
) {
11322 case POWERPC_MMU_32B
:
11323 case POWERPC_MMU_601
:
11324 case POWERPC_MMU_SOFT_6xx
:
11325 case POWERPC_MMU_SOFT_74xx
:
11326 #if defined(TARGET_PPC64)
11327 case POWERPC_MMU_64B
:
11328 case POWERPC_MMU_2_06
:
11329 case POWERPC_MMU_2_06a
:
11330 case POWERPC_MMU_2_06d
:
11332 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
" DAR " TARGET_FMT_lx
11333 " DSISR " TARGET_FMT_lx
"\n", env
->spr
[SPR_SDR1
],
11334 env
->spr
[SPR_DAR
], env
->spr
[SPR_DSISR
]);
11336 case POWERPC_MMU_BOOKE206
:
11337 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
11338 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
11339 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
11340 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
11342 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
11343 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
11344 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
11345 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
11347 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
11348 " TLB1CFG " TARGET_FMT_lx
"\n",
11349 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
11350 env
->spr
[SPR_BOOKE_TLB1CFG
]);
11361 void ppc_cpu_dump_statistics(CPUState
*cs
, FILE*f
,
11362 fprintf_function cpu_fprintf
, int flags
)
11364 #if defined(DO_PPC_STATISTICS)
11365 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
11366 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
11369 t1
= cpu
->env
.opcodes
;
11370 for (op1
= 0; op1
< 64; op1
++) {
11372 if (is_indirect_opcode(handler
)) {
11373 t2
= ind_table(handler
);
11374 for (op2
= 0; op2
< 32; op2
++) {
11376 if (is_indirect_opcode(handler
)) {
11377 t3
= ind_table(handler
);
11378 for (op3
= 0; op3
< 32; op3
++) {
11380 if (handler
->count
== 0)
11382 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
11383 "%016" PRIx64
" %" PRId64
"\n",
11384 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
11386 handler
->count
, handler
->count
);
11389 if (handler
->count
== 0)
11391 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
11392 "%016" PRIx64
" %" PRId64
"\n",
11393 op1
, op2
, op1
, op2
, handler
->oname
,
11394 handler
->count
, handler
->count
);
11398 if (handler
->count
== 0)
11400 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
11402 op1
, op1
, handler
->oname
,
11403 handler
->count
, handler
->count
);
11409 /*****************************************************************************/
11410 static inline void gen_intermediate_code_internal(PowerPCCPU
*cpu
,
11411 TranslationBlock
*tb
,
11414 CPUState
*cs
= CPU(cpu
);
11415 CPUPPCState
*env
= &cpu
->env
;
11416 DisasContext ctx
, *ctxp
= &ctx
;
11417 opc_handler_t
**table
, *handler
;
11418 target_ulong pc_start
;
11419 uint16_t *gen_opc_end
;
11426 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
11427 ctx
.nip
= pc_start
;
11429 ctx
.exception
= POWERPC_EXCP_NONE
;
11430 ctx
.spr_cb
= env
->spr_cb
;
11432 ctx
.hv
= !msr_pr
&& msr_hv
;
11433 ctx
.mem_idx
= env
->mmu_idx
;
11434 ctx
.insns_flags
= env
->insns_flags
;
11435 ctx
.insns_flags2
= env
->insns_flags2
;
11436 ctx
.access_type
= -1;
11437 ctx
.le_mode
= env
->hflags
& (1 << MSR_LE
) ? 1 : 0;
11438 ctx
.default_tcg_memop_mask
= ctx
.le_mode
? MO_LE
: MO_BE
;
11439 #if defined(TARGET_PPC64)
11440 ctx
.sf_mode
= msr_is_64bit(env
, env
->msr
);
11441 ctx
.has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
11443 ctx
.fpu_enabled
= msr_fp
;
11444 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
11445 ctx
.spe_enabled
= msr_spe
;
11447 ctx
.spe_enabled
= 0;
11448 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
11449 ctx
.altivec_enabled
= msr_vr
;
11451 ctx
.altivec_enabled
= 0;
11452 if ((env
->flags
& POWERPC_FLAG_VSX
) && msr_vsx
) {
11453 ctx
.vsx_enabled
= msr_vsx
;
11455 ctx
.vsx_enabled
= 0;
11457 #if defined(TARGET_PPC64)
11458 if ((env
->flags
& POWERPC_FLAG_TM
) && msr_tm
) {
11459 ctx
.tm_enabled
= msr_tm
;
11461 ctx
.tm_enabled
= 0;
11464 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
11465 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
11467 ctx
.singlestep_enabled
= 0;
11468 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
11469 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
11470 if (unlikely(cs
->singlestep_enabled
)) {
11471 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
11473 #if defined (DO_SINGLE_STEP) && 0
11474 /* Single step trace mode */
11478 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11479 if (max_insns
== 0)
11480 max_insns
= CF_COUNT_MASK
;
11483 tcg_clear_temp_count();
11484 /* Set env in case of segfault during code fetch */
11485 while (ctx
.exception
== POWERPC_EXCP_NONE
11486 && tcg_ctx
.gen_opc_ptr
< gen_opc_end
) {
11487 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
11488 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
11489 if (bp
->pc
== ctx
.nip
) {
11490 gen_debug_exception(ctxp
);
11495 if (unlikely(search_pc
)) {
11496 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
11500 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
11502 tcg_ctx
.gen_opc_pc
[lj
] = ctx
.nip
;
11503 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
11504 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
11506 LOG_DISAS("----------------\n");
11507 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
11508 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
11509 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
11511 if (unlikely(need_byteswap(&ctx
))) {
11512 ctx
.opcode
= bswap32(cpu_ldl_code(env
, ctx
.nip
));
11514 ctx
.opcode
= cpu_ldl_code(env
, ctx
.nip
);
11516 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11517 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
11518 opc3(ctx
.opcode
), ctx
.le_mode
? "little" : "big");
11519 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
11520 tcg_gen_debug_insn_start(ctx
.nip
);
11523 table
= env
->opcodes
;
11525 handler
= table
[opc1(ctx
.opcode
)];
11526 if (is_indirect_opcode(handler
)) {
11527 table
= ind_table(handler
);
11528 handler
= table
[opc2(ctx
.opcode
)];
11529 if (is_indirect_opcode(handler
)) {
11530 table
= ind_table(handler
);
11531 handler
= table
[opc3(ctx
.opcode
)];
11534 /* Is opcode *REALLY* valid ? */
11535 if (unlikely(handler
->handler
== &gen_invalid
)) {
11536 if (qemu_log_enabled()) {
11537 qemu_log("invalid/unsupported opcode: "
11538 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
" %d\n",
11539 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
11540 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
11545 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
) && Rc(ctx
.opcode
))) {
11546 inval
= handler
->inval2
;
11548 inval
= handler
->inval1
;
11551 if (unlikely((ctx
.opcode
& inval
) != 0)) {
11552 if (qemu_log_enabled()) {
11553 qemu_log("invalid bits: %08x for opcode: "
11554 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
"\n",
11555 ctx
.opcode
& inval
, opc1(ctx
.opcode
),
11556 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
11557 ctx
.opcode
, ctx
.nip
- 4);
11559 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
11563 (*(handler
->handler
))(&ctx
);
11564 #if defined(DO_PPC_STATISTICS)
11567 /* Check trace mode exceptions */
11568 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
11569 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
11570 ctx
.exception
!= POWERPC_SYSCALL
&&
11571 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
11572 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
11573 gen_exception(ctxp
, POWERPC_EXCP_TRACE
);
11574 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
11575 (cs
->singlestep_enabled
) ||
11577 num_insns
>= max_insns
)) {
11578 /* if we reach a page boundary or are single stepping, stop
11583 if (tcg_check_temp_count()) {
11584 fprintf(stderr
, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11585 opc1(ctx
.opcode
), opc2(ctx
.opcode
), opc3(ctx
.opcode
),
11590 if (tb
->cflags
& CF_LAST_IO
)
11592 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
11593 gen_goto_tb(&ctx
, 0, ctx
.nip
);
11594 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
11595 if (unlikely(cs
->singlestep_enabled
)) {
11596 gen_debug_exception(ctxp
);
11598 /* Generate the return instruction */
11599 tcg_gen_exit_tb(0);
11601 gen_tb_end(tb
, num_insns
);
11602 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
11603 if (unlikely(search_pc
)) {
11604 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
11607 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
11609 tb
->size
= ctx
.nip
- pc_start
;
11610 tb
->icount
= num_insns
;
11612 #if defined(DEBUG_DISAS)
11613 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
11615 flags
= env
->bfd_mach
;
11616 flags
|= ctx
.le_mode
<< 16;
11617 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11618 log_target_disas(env
, pc_start
, ctx
.nip
- pc_start
, flags
);
11624 void gen_intermediate_code (CPUPPCState
*env
, struct TranslationBlock
*tb
)
11626 gen_intermediate_code_internal(ppc_env_get_cpu(env
), tb
, false);
11629 void gen_intermediate_code_pc (CPUPPCState
*env
, struct TranslationBlock
*tb
)
11631 gen_intermediate_code_internal(ppc_env_get_cpu(env
), tb
, true);
11634 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
, int pc_pos
)
11636 env
->nip
= tcg_ctx
.gen_opc_pc
[pc_pos
];