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i386: Add new Hygon 'Dhyana' CPU model
[qemu/ar7.git] / target / i386 / cpu.c
blobd92b0f6fcc44c0abf6059d7032b74c9730d5968e
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24 #include "qemu/qemu-print.h"
25
26 #include "cpu.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/hvf.h"
30 #include "sysemu/cpus.h"
31 #include "kvm_i386.h"
32 #include "sev_i386.h"
33
34 #include "qemu/error-report.h"
35 #include "qemu/option.h"
36 #include "qemu/config-file.h"
37 #include "qapi/error.h"
38 #include "qapi/qapi-visit-misc.h"
39 #include "qapi/qapi-visit-run-state.h"
40 #include "qapi/qmp/qdict.h"
41 #include "qapi/qmp/qerror.h"
42 #include "qapi/visitor.h"
43 #include "qom/qom-qobject.h"
44 #include "sysemu/arch_init.h"
45 #include "qapi/qapi-commands-target.h"
46
47 #include "standard-headers/asm-x86/kvm_para.h"
48
49 #include "sysemu/sysemu.h"
50 #include "hw/qdev-properties.h"
51 #include "hw/i386/topology.h"
52 #ifndef CONFIG_USER_ONLY
53 #include "exec/address-spaces.h"
54 #include "hw/hw.h"
55 #include "hw/xen/xen.h"
56 #include "hw/i386/apic_internal.h"
57 #endif
58
59 #include "disas/capstone.h"
60
61 /* Helpers for building CPUID[2] descriptors: */
62
63 struct CPUID2CacheDescriptorInfo {
64 enum CacheType type;
65 int level;
66 int size;
67 int line_size;
68 int associativity;
69 };
70
71 /*
72 * Known CPUID 2 cache descriptors.
73 * From Intel SDM Volume 2A, CPUID instruction
74 */
75 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
76 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
77 .associativity = 4, .line_size = 32, },
78 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
79 .associativity = 4, .line_size = 32, },
80 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
81 .associativity = 4, .line_size = 64, },
82 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
83 .associativity = 2, .line_size = 32, },
84 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
85 .associativity = 4, .line_size = 32, },
86 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
87 .associativity = 4, .line_size = 64, },
88 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
89 .associativity = 6, .line_size = 64, },
90 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
91 .associativity = 2, .line_size = 64, },
92 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
93 .associativity = 8, .line_size = 64, },
94 /* lines per sector is not supported cpuid2_cache_descriptor(),
95 * so descriptors 0x22, 0x23 are not included
96 */
97 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
98 .associativity = 16, .line_size = 64, },
99 /* lines per sector is not supported cpuid2_cache_descriptor(),
100 * so descriptors 0x25, 0x20 are not included
101 */
102 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
103 .associativity = 8, .line_size = 64, },
104 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
105 .associativity = 8, .line_size = 64, },
106 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
107 .associativity = 4, .line_size = 32, },
108 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
109 .associativity = 4, .line_size = 32, },
110 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
111 .associativity = 4, .line_size = 32, },
112 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
113 .associativity = 4, .line_size = 32, },
114 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
115 .associativity = 4, .line_size = 32, },
116 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
117 .associativity = 4, .line_size = 64, },
118 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
119 .associativity = 8, .line_size = 64, },
120 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
121 .associativity = 12, .line_size = 64, },
122 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
123 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
124 .associativity = 12, .line_size = 64, },
125 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
126 .associativity = 16, .line_size = 64, },
127 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
128 .associativity = 12, .line_size = 64, },
129 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
130 .associativity = 16, .line_size = 64, },
131 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
132 .associativity = 24, .line_size = 64, },
133 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
134 .associativity = 8, .line_size = 64, },
135 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
136 .associativity = 4, .line_size = 64, },
137 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
138 .associativity = 4, .line_size = 64, },
139 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
140 .associativity = 4, .line_size = 64, },
141 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
142 .associativity = 4, .line_size = 64, },
143 /* lines per sector is not supported cpuid2_cache_descriptor(),
144 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
145 */
146 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
147 .associativity = 8, .line_size = 64, },
148 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
149 .associativity = 2, .line_size = 64, },
150 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
151 .associativity = 8, .line_size = 64, },
152 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
153 .associativity = 8, .line_size = 32, },
154 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
155 .associativity = 8, .line_size = 32, },
156 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
157 .associativity = 8, .line_size = 32, },
158 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
159 .associativity = 8, .line_size = 32, },
160 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
161 .associativity = 4, .line_size = 64, },
162 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
163 .associativity = 8, .line_size = 64, },
164 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
165 .associativity = 4, .line_size = 64, },
166 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
167 .associativity = 4, .line_size = 64, },
168 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
169 .associativity = 4, .line_size = 64, },
170 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
171 .associativity = 8, .line_size = 64, },
172 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
173 .associativity = 8, .line_size = 64, },
174 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
175 .associativity = 8, .line_size = 64, },
176 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
177 .associativity = 12, .line_size = 64, },
178 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
179 .associativity = 12, .line_size = 64, },
180 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
181 .associativity = 12, .line_size = 64, },
182 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
183 .associativity = 16, .line_size = 64, },
184 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
185 .associativity = 16, .line_size = 64, },
186 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
187 .associativity = 16, .line_size = 64, },
188 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
189 .associativity = 24, .line_size = 64, },
190 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
191 .associativity = 24, .line_size = 64, },
192 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
193 .associativity = 24, .line_size = 64, },
194 };
195
196 /*
197 * "CPUID leaf 2 does not report cache descriptor information,
198 * use CPUID leaf 4 to query cache parameters"
199 */
200 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
201
202 /*
203 * Return a CPUID 2 cache descriptor for a given cache.
204 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
205 */
206 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
207 {
208 int i;
209
210 assert(cache->size > 0);
211 assert(cache->level > 0);
212 assert(cache->line_size > 0);
213 assert(cache->associativity > 0);
214 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
215 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
216 if (d->level == cache->level && d->type == cache->type &&
217 d->size == cache->size && d->line_size == cache->line_size &&
218 d->associativity == cache->associativity) {
219 return i;
220 }
221 }
222
223 return CACHE_DESCRIPTOR_UNAVAILABLE;
224 }
225
226 /* CPUID Leaf 4 constants: */
227
228 /* EAX: */
229 #define CACHE_TYPE_D 1
230 #define CACHE_TYPE_I 2
231 #define CACHE_TYPE_UNIFIED 3
232
233 #define CACHE_LEVEL(l) (l << 5)
234
235 #define CACHE_SELF_INIT_LEVEL (1 << 8)
236
237 /* EDX: */
238 #define CACHE_NO_INVD_SHARING (1 << 0)
239 #define CACHE_INCLUSIVE (1 << 1)
240 #define CACHE_COMPLEX_IDX (1 << 2)
241
242 /* Encode CacheType for CPUID[4].EAX */
243 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
244 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
245 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
246 0 /* Invalid value */)
247
248
249 /* Encode cache info for CPUID[4] */
250 static void encode_cache_cpuid4(CPUCacheInfo *cache,
251 int num_apic_ids, int num_cores,
252 uint32_t *eax, uint32_t *ebx,
253 uint32_t *ecx, uint32_t *edx)
254 {
255 assert(cache->size == cache->line_size * cache->associativity *
256 cache->partitions * cache->sets);
257
258 assert(num_apic_ids > 0);
259 *eax = CACHE_TYPE(cache->type) |
260 CACHE_LEVEL(cache->level) |
261 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
262 ((num_cores - 1) << 26) |
263 ((num_apic_ids - 1) << 14);
264
265 assert(cache->line_size > 0);
266 assert(cache->partitions > 0);
267 assert(cache->associativity > 0);
268 /* We don't implement fully-associative caches */
269 assert(cache->associativity < cache->sets);
270 *ebx = (cache->line_size - 1) |
271 ((cache->partitions - 1) << 12) |
272 ((cache->associativity - 1) << 22);
273
274 assert(cache->sets > 0);
275 *ecx = cache->sets - 1;
276
277 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
278 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
279 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
280 }
281
282 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
283 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
284 {
285 assert(cache->size % 1024 == 0);
286 assert(cache->lines_per_tag > 0);
287 assert(cache->associativity > 0);
288 assert(cache->line_size > 0);
289 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
290 (cache->lines_per_tag << 8) | (cache->line_size);
291 }
292
293 #define ASSOC_FULL 0xFF
294
295 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
296 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
297 a == 2 ? 0x2 : \
298 a == 4 ? 0x4 : \
299 a == 8 ? 0x6 : \
300 a == 16 ? 0x8 : \
301 a == 32 ? 0xA : \
302 a == 48 ? 0xB : \
303 a == 64 ? 0xC : \
304 a == 96 ? 0xD : \
305 a == 128 ? 0xE : \
306 a == ASSOC_FULL ? 0xF : \
307 0 /* invalid value */)
308
309 /*
310 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
311 * @l3 can be NULL.
312 */
313 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
314 CPUCacheInfo *l3,
315 uint32_t *ecx, uint32_t *edx)
316 {
317 assert(l2->size % 1024 == 0);
318 assert(l2->associativity > 0);
319 assert(l2->lines_per_tag > 0);
320 assert(l2->line_size > 0);
321 *ecx = ((l2->size / 1024) << 16) |
322 (AMD_ENC_ASSOC(l2->associativity) << 12) |
323 (l2->lines_per_tag << 8) | (l2->line_size);
324
325 if (l3) {
326 assert(l3->size % (512 * 1024) == 0);
327 assert(l3->associativity > 0);
328 assert(l3->lines_per_tag > 0);
329 assert(l3->line_size > 0);
330 *edx = ((l3->size / (512 * 1024)) << 18) |
331 (AMD_ENC_ASSOC(l3->associativity) << 12) |
332 (l3->lines_per_tag << 8) | (l3->line_size);
333 } else {
334 *edx = 0;
335 }
336 }
337
338 /*
339 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
340 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
341 * Define the constants to build the cpu topology. Right now, TOPOEXT
342 * feature is enabled only on EPYC. So, these constants are based on
343 * EPYC supported configurations. We may need to handle the cases if
344 * these values change in future.
345 */
346 /* Maximum core complexes in a node */
347 #define MAX_CCX 2
348 /* Maximum cores in a core complex */
349 #define MAX_CORES_IN_CCX 4
350 /* Maximum cores in a node */
351 #define MAX_CORES_IN_NODE 8
352 /* Maximum nodes in a socket */
353 #define MAX_NODES_PER_SOCKET 4
354
355 /*
356 * Figure out the number of nodes required to build this config.
357 * Max cores in a node is 8
358 */
359 static int nodes_in_socket(int nr_cores)
360 {
361 int nodes;
362
363 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
364
365 /* Hardware does not support config with 3 nodes, return 4 in that case */
366 return (nodes == 3) ? 4 : nodes;
367 }
368
369 /*
370 * Decide the number of cores in a core complex with the given nr_cores using
371 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
372 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
373 * L3 cache is shared across all cores in a core complex. So, this will also
374 * tell us how many cores are sharing the L3 cache.
375 */
376 static int cores_in_core_complex(int nr_cores)
377 {
378 int nodes;
379
380 /* Check if we can fit all the cores in one core complex */
381 if (nr_cores <= MAX_CORES_IN_CCX) {
382 return nr_cores;
383 }
384 /* Get the number of nodes required to build this config */
385 nodes = nodes_in_socket(nr_cores);
386
387 /*
388 * Divide the cores accros all the core complexes
389 * Return rounded up value
390 */
391 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
392 }
393
394 /* Encode cache info for CPUID[8000001D] */
395 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
396 uint32_t *eax, uint32_t *ebx,
397 uint32_t *ecx, uint32_t *edx)
398 {
399 uint32_t l3_cores;
400 assert(cache->size == cache->line_size * cache->associativity *
401 cache->partitions * cache->sets);
402
403 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
404 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
405
406 /* L3 is shared among multiple cores */
407 if (cache->level == 3) {
408 l3_cores = cores_in_core_complex(cs->nr_cores);
409 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
410 } else {
411 *eax |= ((cs->nr_threads - 1) << 14);
412 }
413
414 assert(cache->line_size > 0);
415 assert(cache->partitions > 0);
416 assert(cache->associativity > 0);
417 /* We don't implement fully-associative caches */
418 assert(cache->associativity < cache->sets);
419 *ebx = (cache->line_size - 1) |
420 ((cache->partitions - 1) << 12) |
421 ((cache->associativity - 1) << 22);
422
423 assert(cache->sets > 0);
424 *ecx = cache->sets - 1;
425
426 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
427 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
428 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
429 }
430
431 /* Data structure to hold the configuration info for a given core index */
432 struct core_topology {
433 /* core complex id of the current core index */
434 int ccx_id;
435 /*
436 * Adjusted core index for this core in the topology
437 * This can be 0,1,2,3 with max 4 cores in a core complex
438 */
439 int core_id;
440 /* Node id for this core index */
441 int node_id;
442 /* Number of nodes in this config */
443 int num_nodes;
444 };
445
446 /*
447 * Build the configuration closely match the EPYC hardware. Using the EPYC
448 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
449 * right now. This could change in future.
450 * nr_cores : Total number of cores in the config
451 * core_id : Core index of the current CPU
452 * topo : Data structure to hold all the config info for this core index
453 */
454 static void build_core_topology(int nr_cores, int core_id,
455 struct core_topology *topo)
456 {
457 int nodes, cores_in_ccx;
458
459 /* First get the number of nodes required */
460 nodes = nodes_in_socket(nr_cores);
461
462 cores_in_ccx = cores_in_core_complex(nr_cores);
463
464 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
465 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
466 topo->core_id = core_id % cores_in_ccx;
467 topo->num_nodes = nodes;
468 }
469
470 /* Encode cache info for CPUID[8000001E] */
471 static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
472 uint32_t *eax, uint32_t *ebx,
473 uint32_t *ecx, uint32_t *edx)
474 {
475 struct core_topology topo = {0};
476 unsigned long nodes;
477 int shift;
478
479 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
480 *eax = cpu->apic_id;
481 /*
482 * CPUID_Fn8000001E_EBX
483 * 31:16 Reserved
484 * 15:8 Threads per core (The number of threads per core is
485 * Threads per core + 1)
486 * 7:0 Core id (see bit decoding below)
487 * SMT:
488 * 4:3 node id
489 * 2 Core complex id
490 * 1:0 Core id
491 * Non SMT:
492 * 5:4 node id
493 * 3 Core complex id
494 * 1:0 Core id
495 */
496 if (cs->nr_threads - 1) {
497 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
498 (topo.ccx_id << 2) | topo.core_id;
499 } else {
500 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
501 }
502 /*
503 * CPUID_Fn8000001E_ECX
504 * 31:11 Reserved
505 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
506 * 7:0 Node id (see bit decoding below)
507 * 2 Socket id
508 * 1:0 Node id
509 */
510 if (topo.num_nodes <= 4) {
511 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
512 topo.node_id;
513 } else {
514 /*
515 * Node id fix up. Actual hardware supports up to 4 nodes. But with
516 * more than 32 cores, we may end up with more than 4 nodes.
517 * Node id is a combination of socket id and node id. Only requirement
518 * here is that this number should be unique accross the system.
519 * Shift the socket id to accommodate more nodes. We dont expect both
520 * socket id and node id to be big number at the same time. This is not
521 * an ideal config but we need to to support it. Max nodes we can have
522 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
523 * 5 bits for nodes. Find the left most set bit to represent the total
524 * number of nodes. find_last_bit returns last set bit(0 based). Left
525 * shift(+1) the socket id to represent all the nodes.
526 */
527 nodes = topo.num_nodes - 1;
528 shift = find_last_bit(&nodes, 8);
529 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
530 topo.node_id;
531 }
532 *edx = 0;
533 }
534
535 /*
536 * Definitions of the hardcoded cache entries we expose:
537 * These are legacy cache values. If there is a need to change any
538 * of these values please use builtin_x86_defs
539 */
540
541 /* L1 data cache: */
542 static CPUCacheInfo legacy_l1d_cache = {
543 .type = DATA_CACHE,
544 .level = 1,
545 .size = 32 * KiB,
546 .self_init = 1,
547 .line_size = 64,
548 .associativity = 8,
549 .sets = 64,
550 .partitions = 1,
551 .no_invd_sharing = true,
552 };
553
554 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
555 static CPUCacheInfo legacy_l1d_cache_amd = {
556 .type = DATA_CACHE,
557 .level = 1,
558 .size = 64 * KiB,
559 .self_init = 1,
560 .line_size = 64,
561 .associativity = 2,
562 .sets = 512,
563 .partitions = 1,
564 .lines_per_tag = 1,
565 .no_invd_sharing = true,
566 };
567
568 /* L1 instruction cache: */
569 static CPUCacheInfo legacy_l1i_cache = {
570 .type = INSTRUCTION_CACHE,
571 .level = 1,
572 .size = 32 * KiB,
573 .self_init = 1,
574 .line_size = 64,
575 .associativity = 8,
576 .sets = 64,
577 .partitions = 1,
578 .no_invd_sharing = true,
579 };
580
581 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
582 static CPUCacheInfo legacy_l1i_cache_amd = {
583 .type = INSTRUCTION_CACHE,
584 .level = 1,
585 .size = 64 * KiB,
586 .self_init = 1,
587 .line_size = 64,
588 .associativity = 2,
589 .sets = 512,
590 .partitions = 1,
591 .lines_per_tag = 1,
592 .no_invd_sharing = true,
593 };
594
595 /* Level 2 unified cache: */
596 static CPUCacheInfo legacy_l2_cache = {
597 .type = UNIFIED_CACHE,
598 .level = 2,
599 .size = 4 * MiB,
600 .self_init = 1,
601 .line_size = 64,
602 .associativity = 16,
603 .sets = 4096,
604 .partitions = 1,
605 .no_invd_sharing = true,
606 };
607
608 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
609 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
610 .type = UNIFIED_CACHE,
611 .level = 2,
612 .size = 2 * MiB,
613 .line_size = 64,
614 .associativity = 8,
615 };
616
617
618 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
619 static CPUCacheInfo legacy_l2_cache_amd = {
620 .type = UNIFIED_CACHE,
621 .level = 2,
622 .size = 512 * KiB,
623 .line_size = 64,
624 .lines_per_tag = 1,
625 .associativity = 16,
626 .sets = 512,
627 .partitions = 1,
628 };
629
630 /* Level 3 unified cache: */
631 static CPUCacheInfo legacy_l3_cache = {
632 .type = UNIFIED_CACHE,
633 .level = 3,
634 .size = 16 * MiB,
635 .line_size = 64,
636 .associativity = 16,
637 .sets = 16384,
638 .partitions = 1,
639 .lines_per_tag = 1,
640 .self_init = true,
641 .inclusive = true,
642 .complex_indexing = true,
643 };
644
645 /* TLB definitions: */
646
647 #define L1_DTLB_2M_ASSOC 1
648 #define L1_DTLB_2M_ENTRIES 255
649 #define L1_DTLB_4K_ASSOC 1
650 #define L1_DTLB_4K_ENTRIES 255
651
652 #define L1_ITLB_2M_ASSOC 1
653 #define L1_ITLB_2M_ENTRIES 255
654 #define L1_ITLB_4K_ASSOC 1
655 #define L1_ITLB_4K_ENTRIES 255
656
657 #define L2_DTLB_2M_ASSOC 0 /* disabled */
658 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
659 #define L2_DTLB_4K_ASSOC 4
660 #define L2_DTLB_4K_ENTRIES 512
661
662 #define L2_ITLB_2M_ASSOC 0 /* disabled */
663 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
664 #define L2_ITLB_4K_ASSOC 4
665 #define L2_ITLB_4K_ENTRIES 512
666
667 /* CPUID Leaf 0x14 constants: */
668 #define INTEL_PT_MAX_SUBLEAF 0x1
669 /*
670 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
671 * MSR can be accessed;
672 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
673 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
674 * of Intel PT MSRs across warm reset;
675 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
676 */
677 #define INTEL_PT_MINIMAL_EBX 0xf
678 /*
679 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
680 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
681 * accessed;
682 * bit[01]: ToPA tables can hold any number of output entries, up to the
683 * maximum allowed by the MaskOrTableOffset field of
684 * IA32_RTIT_OUTPUT_MASK_PTRS;
685 * bit[02]: Support Single-Range Output scheme;
686 */
687 #define INTEL_PT_MINIMAL_ECX 0x7
688 /* generated packets which contain IP payloads have LIP values */
689 #define INTEL_PT_IP_LIP (1 << 31)
690 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
691 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
692 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
693 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
694 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
695
696 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
697 uint32_t vendor2, uint32_t vendor3)
698 {
699 int i;
700 for (i = 0; i < 4; i++) {
701 dst[i] = vendor1 >> (8 * i);
702 dst[i + 4] = vendor2 >> (8 * i);
703 dst[i + 8] = vendor3 >> (8 * i);
704 }
705 dst[CPUID_VENDOR_SZ] = '\0';
706 }
707
708 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
709 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
710 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
711 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
712 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
713 CPUID_PSE36 | CPUID_FXSR)
714 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
715 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
716 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
717 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
718 CPUID_PAE | CPUID_SEP | CPUID_APIC)
719
720 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
721 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
722 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
723 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
724 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
725 /* partly implemented:
726 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
727 /* missing:
728 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
729 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
730 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
731 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
732 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
733 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
734 /* missing:
735 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
736 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
737 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
738 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
739 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
740
741 #ifdef TARGET_X86_64
742 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
743 #else
744 #define TCG_EXT2_X86_64_FEATURES 0
745 #endif
746
747 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
748 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
749 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
750 TCG_EXT2_X86_64_FEATURES)
751 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
752 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
753 #define TCG_EXT4_FEATURES 0
754 #define TCG_SVM_FEATURES CPUID_SVM_NPT
755 #define TCG_KVM_FEATURES 0
756 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
757 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
758 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
759 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
760 CPUID_7_0_EBX_ERMS)
761 /* missing:
762 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
763 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
764 CPUID_7_0_EBX_RDSEED */
765 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
766 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
767 CPUID_7_0_ECX_LA57)
768 #define TCG_7_0_EDX_FEATURES 0
769 #define TCG_APM_FEATURES 0
770 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
771 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
772 /* missing:
773 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
774
775 typedef enum FeatureWordType {
776 CPUID_FEATURE_WORD,
777 MSR_FEATURE_WORD,
778 } FeatureWordType;
779
780 typedef struct FeatureWordInfo {
781 FeatureWordType type;
782 /* feature flags names are taken from "Intel Processor Identification and
783 * the CPUID Instruction" and AMD's "CPUID Specification".
784 * In cases of disagreement between feature naming conventions,
785 * aliases may be added.
786 */
787 const char *feat_names[32];
788 union {
789 /* If type==CPUID_FEATURE_WORD */
790 struct {
791 uint32_t eax; /* Input EAX for CPUID */
792 bool needs_ecx; /* CPUID instruction uses ECX as input */
793 uint32_t ecx; /* Input ECX value for CPUID */
794 int reg; /* output register (R_* constant) */
795 } cpuid;
796 /* If type==MSR_FEATURE_WORD */
797 struct {
798 uint32_t index;
799 struct { /*CPUID that enumerate this MSR*/
800 FeatureWord cpuid_class;
801 uint32_t cpuid_flag;
802 } cpuid_dep;
803 } msr;
804 };
805 uint32_t tcg_features; /* Feature flags supported by TCG */
806 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
807 uint32_t migratable_flags; /* Feature flags known to be migratable */
808 /* Features that shouldn't be auto-enabled by "-cpu host" */
809 uint32_t no_autoenable_flags;
810 } FeatureWordInfo;
811
812 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
813 [FEAT_1_EDX] = {
814 .type = CPUID_FEATURE_WORD,
815 .feat_names = {
816 "fpu", "vme", "de", "pse",
817 "tsc", "msr", "pae", "mce",
818 "cx8", "apic", NULL, "sep",
819 "mtrr", "pge", "mca", "cmov",
820 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
821 NULL, "ds" /* Intel dts */, "acpi", "mmx",
822 "fxsr", "sse", "sse2", "ss",
823 "ht" /* Intel htt */, "tm", "ia64", "pbe",
824 },
825 .cpuid = {.eax = 1, .reg = R_EDX, },
826 .tcg_features = TCG_FEATURES,
827 },
828 [FEAT_1_ECX] = {
829 .type = CPUID_FEATURE_WORD,
830 .feat_names = {
831 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
832 "ds-cpl", "vmx", "smx", "est",
833 "tm2", "ssse3", "cid", NULL,
834 "fma", "cx16", "xtpr", "pdcm",
835 NULL, "pcid", "dca", "sse4.1",
836 "sse4.2", "x2apic", "movbe", "popcnt",
837 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
838 "avx", "f16c", "rdrand", "hypervisor",
839 },
840 .cpuid = { .eax = 1, .reg = R_ECX, },
841 .tcg_features = TCG_EXT_FEATURES,
842 },
843 /* Feature names that are already defined on feature_name[] but
844 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
845 * names on feat_names below. They are copied automatically
846 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
847 */
848 [FEAT_8000_0001_EDX] = {
849 .type = CPUID_FEATURE_WORD,
850 .feat_names = {
851 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
852 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
853 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
854 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
855 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
856 "nx", NULL, "mmxext", NULL /* mmx */,
857 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
858 NULL, "lm", "3dnowext", "3dnow",
859 },
860 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
861 .tcg_features = TCG_EXT2_FEATURES,
862 },
863 [FEAT_8000_0001_ECX] = {
864 .type = CPUID_FEATURE_WORD,
865 .feat_names = {
866 "lahf-lm", "cmp-legacy", "svm", "extapic",
867 "cr8legacy", "abm", "sse4a", "misalignsse",
868 "3dnowprefetch", "osvw", "ibs", "xop",
869 "skinit", "wdt", NULL, "lwp",
870 "fma4", "tce", NULL, "nodeid-msr",
871 NULL, "tbm", "topoext", "perfctr-core",
872 "perfctr-nb", NULL, NULL, NULL,
873 NULL, NULL, NULL, NULL,
874 },
875 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
876 .tcg_features = TCG_EXT3_FEATURES,
877 /*
878 * TOPOEXT is always allowed but can't be enabled blindly by
879 * "-cpu host", as it requires consistent cache topology info
880 * to be provided so it doesn't confuse guests.
881 */
882 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
883 },
884 [FEAT_C000_0001_EDX] = {
885 .type = CPUID_FEATURE_WORD,
886 .feat_names = {
887 NULL, NULL, "xstore", "xstore-en",
888 NULL, NULL, "xcrypt", "xcrypt-en",
889 "ace2", "ace2-en", "phe", "phe-en",
890 "pmm", "pmm-en", NULL, NULL,
891 NULL, NULL, NULL, NULL,
892 NULL, NULL, NULL, NULL,
893 NULL, NULL, NULL, NULL,
894 NULL, NULL, NULL, NULL,
895 },
896 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
897 .tcg_features = TCG_EXT4_FEATURES,
898 },
899 [FEAT_KVM] = {
900 .type = CPUID_FEATURE_WORD,
901 .feat_names = {
902 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
903 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
904 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
905 NULL, NULL, NULL, NULL,
906 NULL, NULL, NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 "kvmclock-stable-bit", NULL, NULL, NULL,
909 NULL, NULL, NULL, NULL,
910 },
911 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
912 .tcg_features = TCG_KVM_FEATURES,
913 },
914 [FEAT_KVM_HINTS] = {
915 .type = CPUID_FEATURE_WORD,
916 .feat_names = {
917 "kvm-hint-dedicated", NULL, NULL, NULL,
918 NULL, NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 NULL, NULL, NULL, NULL,
924 NULL, NULL, NULL, NULL,
925 },
926 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
927 .tcg_features = TCG_KVM_FEATURES,
928 /*
929 * KVM hints aren't auto-enabled by -cpu host, they need to be
930 * explicitly enabled in the command-line.
931 */
932 .no_autoenable_flags = ~0U,
933 },
934 /*
935 * .feat_names are commented out for Hyper-V enlightenments because we
936 * don't want to have two different ways for enabling them on QEMU command
937 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
938 * enabling several feature bits simultaneously, exposing these bits
939 * individually may just confuse guests.
940 */
941 [FEAT_HYPERV_EAX] = {
942 .type = CPUID_FEATURE_WORD,
943 .feat_names = {
944 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
945 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
946 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
947 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
948 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
949 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
950 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
951 NULL, NULL,
952 NULL, NULL, NULL, NULL,
953 NULL, NULL, NULL, NULL,
954 NULL, NULL, NULL, NULL,
955 NULL, NULL, NULL, NULL,
956 },
957 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
958 },
959 [FEAT_HYPERV_EBX] = {
960 .type = CPUID_FEATURE_WORD,
961 .feat_names = {
962 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
963 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
964 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
965 NULL /* hv_create_port */, NULL /* hv_connect_port */,
966 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
967 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
968 NULL, NULL,
969 NULL, NULL, NULL, NULL,
970 NULL, NULL, NULL, NULL,
971 NULL, NULL, NULL, NULL,
972 NULL, NULL, NULL, NULL,
973 },
974 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
975 },
976 [FEAT_HYPERV_EDX] = {
977 .type = CPUID_FEATURE_WORD,
978 .feat_names = {
979 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
980 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
981 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
982 NULL, NULL,
983 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
984 NULL, NULL, NULL, NULL,
985 NULL, NULL, NULL, NULL,
986 NULL, NULL, NULL, NULL,
987 NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL,
989 },
990 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
991 },
992 [FEAT_HV_RECOMM_EAX] = {
993 .type = CPUID_FEATURE_WORD,
994 .feat_names = {
995 NULL /* hv_recommend_pv_as_switch */,
996 NULL /* hv_recommend_pv_tlbflush_local */,
997 NULL /* hv_recommend_pv_tlbflush_remote */,
998 NULL /* hv_recommend_msr_apic_access */,
999 NULL /* hv_recommend_msr_reset */,
1000 NULL /* hv_recommend_relaxed_timing */,
1001 NULL /* hv_recommend_dma_remapping */,
1002 NULL /* hv_recommend_int_remapping */,
1003 NULL /* hv_recommend_x2apic_msrs */,
1004 NULL /* hv_recommend_autoeoi_deprecation */,
1005 NULL /* hv_recommend_pv_ipi */,
1006 NULL /* hv_recommend_ex_hypercalls */,
1007 NULL /* hv_hypervisor_is_nested */,
1008 NULL /* hv_recommend_int_mbec */,
1009 NULL /* hv_recommend_evmcs */,
1010 NULL,
1011 NULL, NULL, NULL, NULL,
1012 NULL, NULL, NULL, NULL,
1013 NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL,
1015 },
1016 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
1017 },
1018 [FEAT_HV_NESTED_EAX] = {
1019 .type = CPUID_FEATURE_WORD,
1020 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
1021 },
1022 [FEAT_SVM] = {
1023 .type = CPUID_FEATURE_WORD,
1024 .feat_names = {
1025 "npt", "lbrv", "svm-lock", "nrip-save",
1026 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1027 NULL, NULL, "pause-filter", NULL,
1028 "pfthreshold", NULL, NULL, NULL,
1029 NULL, NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, NULL, NULL, NULL,
1032 NULL, NULL, NULL, NULL,
1033 },
1034 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
1035 .tcg_features = TCG_SVM_FEATURES,
1036 },
1037 [FEAT_7_0_EBX] = {
1038 .type = CPUID_FEATURE_WORD,
1039 .feat_names = {
1040 "fsgsbase", "tsc-adjust", NULL, "bmi1",
1041 "hle", "avx2", NULL, "smep",
1042 "bmi2", "erms", "invpcid", "rtm",
1043 NULL, NULL, "mpx", NULL,
1044 "avx512f", "avx512dq", "rdseed", "adx",
1045 "smap", "avx512ifma", "pcommit", "clflushopt",
1046 "clwb", "intel-pt", "avx512pf", "avx512er",
1047 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1048 },
1049 .cpuid = {
1050 .eax = 7,
1051 .needs_ecx = true, .ecx = 0,
1052 .reg = R_EBX,
1053 },
1054 .tcg_features = TCG_7_0_EBX_FEATURES,
1055 },
1056 [FEAT_7_0_ECX] = {
1057 .type = CPUID_FEATURE_WORD,
1058 .feat_names = {
1059 NULL, "avx512vbmi", "umip", "pku",
1060 NULL /* ospke */, NULL, "avx512vbmi2", NULL,
1061 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1062 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
1063 "la57", NULL, NULL, NULL,
1064 NULL, NULL, "rdpid", NULL,
1065 NULL, "cldemote", NULL, "movdiri",
1066 "movdir64b", NULL, NULL, NULL,
1067 },
1068 .cpuid = {
1069 .eax = 7,
1070 .needs_ecx = true, .ecx = 0,
1071 .reg = R_ECX,
1072 },
1073 .tcg_features = TCG_7_0_ECX_FEATURES,
1074 },
1075 [FEAT_7_0_EDX] = {
1076 .type = CPUID_FEATURE_WORD,
1077 .feat_names = {
1078 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1079 NULL, NULL, NULL, NULL,
1080 NULL, NULL, NULL, NULL,
1081 NULL, NULL, NULL, NULL,
1082 NULL, NULL, NULL, NULL,
1083 NULL, NULL, NULL, NULL,
1084 NULL, NULL, "spec-ctrl", "stibp",
1085 NULL, "arch-capabilities", NULL, "ssbd",
1086 },
1087 .cpuid = {
1088 .eax = 7,
1089 .needs_ecx = true, .ecx = 0,
1090 .reg = R_EDX,
1091 },
1092 .tcg_features = TCG_7_0_EDX_FEATURES,
1093 },
1094 [FEAT_8000_0007_EDX] = {
1095 .type = CPUID_FEATURE_WORD,
1096 .feat_names = {
1097 NULL, NULL, NULL, NULL,
1098 NULL, NULL, NULL, NULL,
1099 "invtsc", NULL, NULL, NULL,
1100 NULL, NULL, NULL, NULL,
1101 NULL, NULL, NULL, NULL,
1102 NULL, NULL, NULL, NULL,
1103 NULL, NULL, NULL, NULL,
1104 NULL, NULL, NULL, NULL,
1105 },
1106 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1107 .tcg_features = TCG_APM_FEATURES,
1108 .unmigratable_flags = CPUID_APM_INVTSC,
1109 },
1110 [FEAT_8000_0008_EBX] = {
1111 .type = CPUID_FEATURE_WORD,
1112 .feat_names = {
1113 NULL, NULL, NULL, NULL,
1114 NULL, NULL, NULL, NULL,
1115 NULL, "wbnoinvd", NULL, NULL,
1116 "ibpb", NULL, NULL, NULL,
1117 NULL, NULL, NULL, NULL,
1118 NULL, NULL, NULL, NULL,
1119 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1120 NULL, NULL, NULL, NULL,
1121 },
1122 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1123 .tcg_features = 0,
1124 .unmigratable_flags = 0,
1125 },
1126 [FEAT_XSAVE] = {
1127 .type = CPUID_FEATURE_WORD,
1128 .feat_names = {
1129 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1130 NULL, NULL, NULL, NULL,
1131 NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 },
1138 .cpuid = {
1139 .eax = 0xd,
1140 .needs_ecx = true, .ecx = 1,
1141 .reg = R_EAX,
1142 },
1143 .tcg_features = TCG_XSAVE_FEATURES,
1144 },
1145 [FEAT_6_EAX] = {
1146 .type = CPUID_FEATURE_WORD,
1147 .feat_names = {
1148 NULL, NULL, "arat", NULL,
1149 NULL, NULL, NULL, NULL,
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, NULL, NULL, NULL,
1156 },
1157 .cpuid = { .eax = 6, .reg = R_EAX, },
1158 .tcg_features = TCG_6_EAX_FEATURES,
1159 },
1160 [FEAT_XSAVE_COMP_LO] = {
1161 .type = CPUID_FEATURE_WORD,
1162 .cpuid = {
1163 .eax = 0xD,
1164 .needs_ecx = true, .ecx = 0,
1165 .reg = R_EAX,
1166 },
1167 .tcg_features = ~0U,
1168 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1169 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1170 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1171 XSTATE_PKRU_MASK,
1172 },
1173 [FEAT_XSAVE_COMP_HI] = {
1174 .type = CPUID_FEATURE_WORD,
1175 .cpuid = {
1176 .eax = 0xD,
1177 .needs_ecx = true, .ecx = 0,
1178 .reg = R_EDX,
1179 },
1180 .tcg_features = ~0U,
1181 },
1182 /*Below are MSR exposed features*/
1183 [FEAT_ARCH_CAPABILITIES] = {
1184 .type = MSR_FEATURE_WORD,
1185 .feat_names = {
1186 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1187 "ssb-no", NULL, NULL, NULL,
1188 NULL, NULL, NULL, NULL,
1189 NULL, NULL, NULL, NULL,
1190 NULL, NULL, NULL, NULL,
1191 NULL, NULL, NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 NULL, NULL, NULL, NULL,
1194 },
1195 .msr = {
1196 .index = MSR_IA32_ARCH_CAPABILITIES,
1197 .cpuid_dep = {
1198 FEAT_7_0_EDX,
1199 CPUID_7_0_EDX_ARCH_CAPABILITIES
1200 }
1201 },
1202 },
1203 };
1204
1205 typedef struct X86RegisterInfo32 {
1206 /* Name of register */
1207 const char *name;
1208 /* QAPI enum value register */
1209 X86CPURegister32 qapi_enum;
1210 } X86RegisterInfo32;
1211
1212 #define REGISTER(reg) \
1213 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1214 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1215 REGISTER(EAX),
1216 REGISTER(ECX),
1217 REGISTER(EDX),
1218 REGISTER(EBX),
1219 REGISTER(ESP),
1220 REGISTER(EBP),
1221 REGISTER(ESI),
1222 REGISTER(EDI),
1223 };
1224 #undef REGISTER
1225
1226 typedef struct ExtSaveArea {
1227 uint32_t feature, bits;
1228 uint32_t offset, size;
1229 } ExtSaveArea;
1230
1231 static const ExtSaveArea x86_ext_save_areas[] = {
1232 [XSTATE_FP_BIT] = {
1233 /* x87 FP state component is always enabled if XSAVE is supported */
1234 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1235 /* x87 state is in the legacy region of the XSAVE area */
1236 .offset = 0,
1237 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1238 },
1239 [XSTATE_SSE_BIT] = {
1240 /* SSE state component is always enabled if XSAVE is supported */
1241 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1242 /* SSE state is in the legacy region of the XSAVE area */
1243 .offset = 0,
1244 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1245 },
1246 [XSTATE_YMM_BIT] =
1247 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1248 .offset = offsetof(X86XSaveArea, avx_state),
1249 .size = sizeof(XSaveAVX) },
1250 [XSTATE_BNDREGS_BIT] =
1251 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1252 .offset = offsetof(X86XSaveArea, bndreg_state),
1253 .size = sizeof(XSaveBNDREG) },
1254 [XSTATE_BNDCSR_BIT] =
1255 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1256 .offset = offsetof(X86XSaveArea, bndcsr_state),
1257 .size = sizeof(XSaveBNDCSR) },
1258 [XSTATE_OPMASK_BIT] =
1259 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1260 .offset = offsetof(X86XSaveArea, opmask_state),
1261 .size = sizeof(XSaveOpmask) },
1262 [XSTATE_ZMM_Hi256_BIT] =
1263 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1264 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1265 .size = sizeof(XSaveZMM_Hi256) },
1266 [XSTATE_Hi16_ZMM_BIT] =
1267 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1268 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1269 .size = sizeof(XSaveHi16_ZMM) },
1270 [XSTATE_PKRU_BIT] =
1271 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1272 .offset = offsetof(X86XSaveArea, pkru_state),
1273 .size = sizeof(XSavePKRU) },
1274 };
1275
1276 static uint32_t xsave_area_size(uint64_t mask)
1277 {
1278 int i;
1279 uint64_t ret = 0;
1280
1281 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1282 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1283 if ((mask >> i) & 1) {
1284 ret = MAX(ret, esa->offset + esa->size);
1285 }
1286 }
1287 return ret;
1288 }
1289
1290 static inline bool accel_uses_host_cpuid(void)
1291 {
1292 return kvm_enabled() || hvf_enabled();
1293 }
1294
1295 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1296 {
1297 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1298 cpu->env.features[FEAT_XSAVE_COMP_LO];
1299 }
1300
1301 const char *get_register_name_32(unsigned int reg)
1302 {
1303 if (reg >= CPU_NB_REGS32) {
1304 return NULL;
1305 }
1306 return x86_reg_info_32[reg].name;
1307 }
1308
1309 /*
1310 * Returns the set of feature flags that are supported and migratable by
1311 * QEMU, for a given FeatureWord.
1312 */
1313 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1314 {
1315 FeatureWordInfo *wi = &feature_word_info[w];
1316 uint32_t r = 0;
1317 int i;
1318
1319 for (i = 0; i < 32; i++) {
1320 uint32_t f = 1U << i;
1321
1322 /* If the feature name is known, it is implicitly considered migratable,
1323 * unless it is explicitly set in unmigratable_flags */
1324 if ((wi->migratable_flags & f) ||
1325 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1326 r |= f;
1327 }
1328 }
1329 return r;
1330 }
1331
1332 void host_cpuid(uint32_t function, uint32_t count,
1333 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1334 {
1335 uint32_t vec[4];
1336
1337 #ifdef __x86_64__
1338 asm volatile("cpuid"
1339 : "=a"(vec[0]), "=b"(vec[1]),
1340 "=c"(vec[2]), "=d"(vec[3])
1341 : "0"(function), "c"(count) : "cc");
1342 #elif defined(__i386__)
1343 asm volatile("pusha \n\t"
1344 "cpuid \n\t"
1345 "mov %%eax, 0(%2) \n\t"
1346 "mov %%ebx, 4(%2) \n\t"
1347 "mov %%ecx, 8(%2) \n\t"
1348 "mov %%edx, 12(%2) \n\t"
1349 "popa"
1350 : : "a"(function), "c"(count), "S"(vec)
1351 : "memory", "cc");
1352 #else
1353 abort();
1354 #endif
1355
1356 if (eax)
1357 *eax = vec[0];
1358 if (ebx)
1359 *ebx = vec[1];
1360 if (ecx)
1361 *ecx = vec[2];
1362 if (edx)
1363 *edx = vec[3];
1364 }
1365
1366 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1367 {
1368 uint32_t eax, ebx, ecx, edx;
1369
1370 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1371 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1372
1373 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1374 if (family) {
1375 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1376 }
1377 if (model) {
1378 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1379 }
1380 if (stepping) {
1381 *stepping = eax & 0x0F;
1382 }
1383 }
1384
1385 /* CPU class name definitions: */
1386
1387 /* Return type name for a given CPU model name
1388 * Caller is responsible for freeing the returned string.
1389 */
1390 static char *x86_cpu_type_name(const char *model_name)
1391 {
1392 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1393 }
1394
1395 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1396 {
1397 ObjectClass *oc;
1398 char *typename = x86_cpu_type_name(cpu_model);
1399 oc = object_class_by_name(typename);
1400 g_free(typename);
1401 return oc;
1402 }
1403
1404 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1405 {
1406 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1407 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1408 return g_strndup(class_name,
1409 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1410 }
1411
1412 struct X86CPUDefinition {
1413 const char *name;
1414 uint32_t level;
1415 uint32_t xlevel;
1416 /* vendor is zero-terminated, 12 character ASCII string */
1417 char vendor[CPUID_VENDOR_SZ + 1];
1418 int family;
1419 int model;
1420 int stepping;
1421 FeatureWordArray features;
1422 const char *model_id;
1423 CPUCaches *cache_info;
1424 };
1425
1426 static CPUCaches epyc_cache_info = {
1427 .l1d_cache = &(CPUCacheInfo) {
1428 .type = DATA_CACHE,
1429 .level = 1,
1430 .size = 32 * KiB,
1431 .line_size = 64,
1432 .associativity = 8,
1433 .partitions = 1,
1434 .sets = 64,
1435 .lines_per_tag = 1,
1436 .self_init = 1,
1437 .no_invd_sharing = true,
1438 },
1439 .l1i_cache = &(CPUCacheInfo) {
1440 .type = INSTRUCTION_CACHE,
1441 .level = 1,
1442 .size = 64 * KiB,
1443 .line_size = 64,
1444 .associativity = 4,
1445 .partitions = 1,
1446 .sets = 256,
1447 .lines_per_tag = 1,
1448 .self_init = 1,
1449 .no_invd_sharing = true,
1450 },
1451 .l2_cache = &(CPUCacheInfo) {
1452 .type = UNIFIED_CACHE,
1453 .level = 2,
1454 .size = 512 * KiB,
1455 .line_size = 64,
1456 .associativity = 8,
1457 .partitions = 1,
1458 .sets = 1024,
1459 .lines_per_tag = 1,
1460 },
1461 .l3_cache = &(CPUCacheInfo) {
1462 .type = UNIFIED_CACHE,
1463 .level = 3,
1464 .size = 8 * MiB,
1465 .line_size = 64,
1466 .associativity = 16,
1467 .partitions = 1,
1468 .sets = 8192,
1469 .lines_per_tag = 1,
1470 .self_init = true,
1471 .inclusive = true,
1472 .complex_indexing = true,
1473 },
1474 };
1475
1476 static X86CPUDefinition builtin_x86_defs[] = {
1477 {
1478 .name = "qemu64",
1479 .level = 0xd,
1480 .vendor = CPUID_VENDOR_AMD,
1481 .family = 6,
1482 .model = 6,
1483 .stepping = 3,
1484 .features[FEAT_1_EDX] =
1485 PPRO_FEATURES |
1486 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1487 CPUID_PSE36,
1488 .features[FEAT_1_ECX] =
1489 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1490 .features[FEAT_8000_0001_EDX] =
1491 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1492 .features[FEAT_8000_0001_ECX] =
1493 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1494 .xlevel = 0x8000000A,
1495 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1496 },
1497 {
1498 .name = "phenom",
1499 .level = 5,
1500 .vendor = CPUID_VENDOR_AMD,
1501 .family = 16,
1502 .model = 2,
1503 .stepping = 3,
1504 /* Missing: CPUID_HT */
1505 .features[FEAT_1_EDX] =
1506 PPRO_FEATURES |
1507 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1508 CPUID_PSE36 | CPUID_VME,
1509 .features[FEAT_1_ECX] =
1510 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1511 CPUID_EXT_POPCNT,
1512 .features[FEAT_8000_0001_EDX] =
1513 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1514 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1515 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1516 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1517 CPUID_EXT3_CR8LEG,
1518 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1519 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1520 .features[FEAT_8000_0001_ECX] =
1521 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1522 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1523 /* Missing: CPUID_SVM_LBRV */
1524 .features[FEAT_SVM] =
1525 CPUID_SVM_NPT,
1526 .xlevel = 0x8000001A,
1527 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1528 },
1529 {
1530 .name = "core2duo",
1531 .level = 10,
1532 .vendor = CPUID_VENDOR_INTEL,
1533 .family = 6,
1534 .model = 15,
1535 .stepping = 11,
1536 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1537 .features[FEAT_1_EDX] =
1538 PPRO_FEATURES |
1539 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1540 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1541 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1542 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1543 .features[FEAT_1_ECX] =
1544 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1545 CPUID_EXT_CX16,
1546 .features[FEAT_8000_0001_EDX] =
1547 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1548 .features[FEAT_8000_0001_ECX] =
1549 CPUID_EXT3_LAHF_LM,
1550 .xlevel = 0x80000008,
1551 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1552 },
1553 {
1554 .name = "kvm64",
1555 .level = 0xd,
1556 .vendor = CPUID_VENDOR_INTEL,
1557 .family = 15,
1558 .model = 6,
1559 .stepping = 1,
1560 /* Missing: CPUID_HT */
1561 .features[FEAT_1_EDX] =
1562 PPRO_FEATURES | CPUID_VME |
1563 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1564 CPUID_PSE36,
1565 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1566 .features[FEAT_1_ECX] =
1567 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1568 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1569 .features[FEAT_8000_0001_EDX] =
1570 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1571 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1572 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1573 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1574 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1575 .features[FEAT_8000_0001_ECX] =
1576 0,
1577 .xlevel = 0x80000008,
1578 .model_id = "Common KVM processor"
1579 },
1580 {
1581 .name = "qemu32",
1582 .level = 4,
1583 .vendor = CPUID_VENDOR_INTEL,
1584 .family = 6,
1585 .model = 6,
1586 .stepping = 3,
1587 .features[FEAT_1_EDX] =
1588 PPRO_FEATURES,
1589 .features[FEAT_1_ECX] =
1590 CPUID_EXT_SSE3,
1591 .xlevel = 0x80000004,
1592 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1593 },
1594 {
1595 .name = "kvm32",
1596 .level = 5,
1597 .vendor = CPUID_VENDOR_INTEL,
1598 .family = 15,
1599 .model = 6,
1600 .stepping = 1,
1601 .features[FEAT_1_EDX] =
1602 PPRO_FEATURES | CPUID_VME |
1603 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1604 .features[FEAT_1_ECX] =
1605 CPUID_EXT_SSE3,
1606 .features[FEAT_8000_0001_ECX] =
1607 0,
1608 .xlevel = 0x80000008,
1609 .model_id = "Common 32-bit KVM processor"
1610 },
1611 {
1612 .name = "coreduo",
1613 .level = 10,
1614 .vendor = CPUID_VENDOR_INTEL,
1615 .family = 6,
1616 .model = 14,
1617 .stepping = 8,
1618 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1619 .features[FEAT_1_EDX] =
1620 PPRO_FEATURES | CPUID_VME |
1621 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1622 CPUID_SS,
1623 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
1624 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
1625 .features[FEAT_1_ECX] =
1626 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
1627 .features[FEAT_8000_0001_EDX] =
1628 CPUID_EXT2_NX,
1629 .xlevel = 0x80000008,
1630 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1631 },
1632 {
1633 .name = "486",
1634 .level = 1,
1635 .vendor = CPUID_VENDOR_INTEL,
1636 .family = 4,
1637 .model = 8,
1638 .stepping = 0,
1639 .features[FEAT_1_EDX] =
1640 I486_FEATURES,
1641 .xlevel = 0,
1642 .model_id = "",
1643 },
1644 {
1645 .name = "pentium",
1646 .level = 1,
1647 .vendor = CPUID_VENDOR_INTEL,
1648 .family = 5,
1649 .model = 4,
1650 .stepping = 3,
1651 .features[FEAT_1_EDX] =
1652 PENTIUM_FEATURES,
1653 .xlevel = 0,
1654 .model_id = "",
1655 },
1656 {
1657 .name = "pentium2",
1658 .level = 2,
1659 .vendor = CPUID_VENDOR_INTEL,
1660 .family = 6,
1661 .model = 5,
1662 .stepping = 2,
1663 .features[FEAT_1_EDX] =
1664 PENTIUM2_FEATURES,
1665 .xlevel = 0,
1666 .model_id = "",
1667 },
1668 {
1669 .name = "pentium3",
1670 .level = 3,
1671 .vendor = CPUID_VENDOR_INTEL,
1672 .family = 6,
1673 .model = 7,
1674 .stepping = 3,
1675 .features[FEAT_1_EDX] =
1676 PENTIUM3_FEATURES,
1677 .xlevel = 0,
1678 .model_id = "",
1679 },
1680 {
1681 .name = "athlon",
1682 .level = 2,
1683 .vendor = CPUID_VENDOR_AMD,
1684 .family = 6,
1685 .model = 2,
1686 .stepping = 3,
1687 .features[FEAT_1_EDX] =
1688 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
1689 CPUID_MCA,
1690 .features[FEAT_8000_0001_EDX] =
1691 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
1692 .xlevel = 0x80000008,
1693 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1694 },
1695 {
1696 .name = "n270",
1697 .level = 10,
1698 .vendor = CPUID_VENDOR_INTEL,
1699 .family = 6,
1700 .model = 28,
1701 .stepping = 2,
1702 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1703 .features[FEAT_1_EDX] =
1704 PPRO_FEATURES |
1705 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1706 CPUID_ACPI | CPUID_SS,
1707 /* Some CPUs got no CPUID_SEP */
1708 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1709 * CPUID_EXT_XTPR */
1710 .features[FEAT_1_ECX] =
1711 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1712 CPUID_EXT_MOVBE,
1713 .features[FEAT_8000_0001_EDX] =
1714 CPUID_EXT2_NX,
1715 .features[FEAT_8000_0001_ECX] =
1716 CPUID_EXT3_LAHF_LM,
1717 .xlevel = 0x80000008,
1718 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1719 },
1720 {
1721 .name = "Conroe",
1722 .level = 10,
1723 .vendor = CPUID_VENDOR_INTEL,
1724 .family = 6,
1725 .model = 15,
1726 .stepping = 3,
1727 .features[FEAT_1_EDX] =
1728 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1729 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1730 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1731 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1732 CPUID_DE | CPUID_FP87,
1733 .features[FEAT_1_ECX] =
1734 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1735 .features[FEAT_8000_0001_EDX] =
1736 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1737 .features[FEAT_8000_0001_ECX] =
1738 CPUID_EXT3_LAHF_LM,
1739 .xlevel = 0x80000008,
1740 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1741 },
1742 {
1743 .name = "Penryn",
1744 .level = 10,
1745 .vendor = CPUID_VENDOR_INTEL,
1746 .family = 6,
1747 .model = 23,
1748 .stepping = 3,
1749 .features[FEAT_1_EDX] =
1750 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1751 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1752 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1753 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1754 CPUID_DE | CPUID_FP87,
1755 .features[FEAT_1_ECX] =
1756 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1757 CPUID_EXT_SSE3,
1758 .features[FEAT_8000_0001_EDX] =
1759 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1760 .features[FEAT_8000_0001_ECX] =
1761 CPUID_EXT3_LAHF_LM,
1762 .xlevel = 0x80000008,
1763 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1764 },
1765 {
1766 .name = "Nehalem",
1767 .level = 11,
1768 .vendor = CPUID_VENDOR_INTEL,
1769 .family = 6,
1770 .model = 26,
1771 .stepping = 3,
1772 .features[FEAT_1_EDX] =
1773 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1774 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1775 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1776 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1777 CPUID_DE | CPUID_FP87,
1778 .features[FEAT_1_ECX] =
1779 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1780 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1781 .features[FEAT_8000_0001_EDX] =
1782 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1783 .features[FEAT_8000_0001_ECX] =
1784 CPUID_EXT3_LAHF_LM,
1785 .xlevel = 0x80000008,
1786 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1787 },
1788 {
1789 .name = "Nehalem-IBRS",
1790 .level = 11,
1791 .vendor = CPUID_VENDOR_INTEL,
1792 .family = 6,
1793 .model = 26,
1794 .stepping = 3,
1795 .features[FEAT_1_EDX] =
1796 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1797 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1798 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1799 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1800 CPUID_DE | CPUID_FP87,
1801 .features[FEAT_1_ECX] =
1802 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1803 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1804 .features[FEAT_7_0_EDX] =
1805 CPUID_7_0_EDX_SPEC_CTRL,
1806 .features[FEAT_8000_0001_EDX] =
1807 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1808 .features[FEAT_8000_0001_ECX] =
1809 CPUID_EXT3_LAHF_LM,
1810 .xlevel = 0x80000008,
1811 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1812 },
1813 {
1814 .name = "Westmere",
1815 .level = 11,
1816 .vendor = CPUID_VENDOR_INTEL,
1817 .family = 6,
1818 .model = 44,
1819 .stepping = 1,
1820 .features[FEAT_1_EDX] =
1821 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1822 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1823 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1824 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1825 CPUID_DE | CPUID_FP87,
1826 .features[FEAT_1_ECX] =
1827 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1828 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1829 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1830 .features[FEAT_8000_0001_EDX] =
1831 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1832 .features[FEAT_8000_0001_ECX] =
1833 CPUID_EXT3_LAHF_LM,
1834 .features[FEAT_6_EAX] =
1835 CPUID_6_EAX_ARAT,
1836 .xlevel = 0x80000008,
1837 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1838 },
1839 {
1840 .name = "Westmere-IBRS",
1841 .level = 11,
1842 .vendor = CPUID_VENDOR_INTEL,
1843 .family = 6,
1844 .model = 44,
1845 .stepping = 1,
1846 .features[FEAT_1_EDX] =
1847 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1848 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1849 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1850 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1851 CPUID_DE | CPUID_FP87,
1852 .features[FEAT_1_ECX] =
1853 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1854 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1855 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1856 .features[FEAT_8000_0001_EDX] =
1857 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1858 .features[FEAT_8000_0001_ECX] =
1859 CPUID_EXT3_LAHF_LM,
1860 .features[FEAT_7_0_EDX] =
1861 CPUID_7_0_EDX_SPEC_CTRL,
1862 .features[FEAT_6_EAX] =
1863 CPUID_6_EAX_ARAT,
1864 .xlevel = 0x80000008,
1865 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1866 },
1867 {
1868 .name = "SandyBridge",
1869 .level = 0xd,
1870 .vendor = CPUID_VENDOR_INTEL,
1871 .family = 6,
1872 .model = 42,
1873 .stepping = 1,
1874 .features[FEAT_1_EDX] =
1875 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1876 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1877 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1878 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1879 CPUID_DE | CPUID_FP87,
1880 .features[FEAT_1_ECX] =
1881 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1882 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1883 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1884 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1885 CPUID_EXT_SSE3,
1886 .features[FEAT_8000_0001_EDX] =
1887 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1888 CPUID_EXT2_SYSCALL,
1889 .features[FEAT_8000_0001_ECX] =
1890 CPUID_EXT3_LAHF_LM,
1891 .features[FEAT_XSAVE] =
1892 CPUID_XSAVE_XSAVEOPT,
1893 .features[FEAT_6_EAX] =
1894 CPUID_6_EAX_ARAT,
1895 .xlevel = 0x80000008,
1896 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1897 },
1898 {
1899 .name = "SandyBridge-IBRS",
1900 .level = 0xd,
1901 .vendor = CPUID_VENDOR_INTEL,
1902 .family = 6,
1903 .model = 42,
1904 .stepping = 1,
1905 .features[FEAT_1_EDX] =
1906 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1907 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1908 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1909 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1910 CPUID_DE | CPUID_FP87,
1911 .features[FEAT_1_ECX] =
1912 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1913 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1914 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1915 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1916 CPUID_EXT_SSE3,
1917 .features[FEAT_8000_0001_EDX] =
1918 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1919 CPUID_EXT2_SYSCALL,
1920 .features[FEAT_8000_0001_ECX] =
1921 CPUID_EXT3_LAHF_LM,
1922 .features[FEAT_7_0_EDX] =
1923 CPUID_7_0_EDX_SPEC_CTRL,
1924 .features[FEAT_XSAVE] =
1925 CPUID_XSAVE_XSAVEOPT,
1926 .features[FEAT_6_EAX] =
1927 CPUID_6_EAX_ARAT,
1928 .xlevel = 0x80000008,
1929 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1930 },
1931 {
1932 .name = "IvyBridge",
1933 .level = 0xd,
1934 .vendor = CPUID_VENDOR_INTEL,
1935 .family = 6,
1936 .model = 58,
1937 .stepping = 9,
1938 .features[FEAT_1_EDX] =
1939 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1940 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1941 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1942 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1943 CPUID_DE | CPUID_FP87,
1944 .features[FEAT_1_ECX] =
1945 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1946 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1947 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1948 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1949 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1950 .features[FEAT_7_0_EBX] =
1951 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1952 CPUID_7_0_EBX_ERMS,
1953 .features[FEAT_8000_0001_EDX] =
1954 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1955 CPUID_EXT2_SYSCALL,
1956 .features[FEAT_8000_0001_ECX] =
1957 CPUID_EXT3_LAHF_LM,
1958 .features[FEAT_XSAVE] =
1959 CPUID_XSAVE_XSAVEOPT,
1960 .features[FEAT_6_EAX] =
1961 CPUID_6_EAX_ARAT,
1962 .xlevel = 0x80000008,
1963 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1964 },
1965 {
1966 .name = "IvyBridge-IBRS",
1967 .level = 0xd,
1968 .vendor = CPUID_VENDOR_INTEL,
1969 .family = 6,
1970 .model = 58,
1971 .stepping = 9,
1972 .features[FEAT_1_EDX] =
1973 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1974 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1975 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1976 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1977 CPUID_DE | CPUID_FP87,
1978 .features[FEAT_1_ECX] =
1979 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1980 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1981 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1982 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1983 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1984 .features[FEAT_7_0_EBX] =
1985 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1986 CPUID_7_0_EBX_ERMS,
1987 .features[FEAT_8000_0001_EDX] =
1988 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1989 CPUID_EXT2_SYSCALL,
1990 .features[FEAT_8000_0001_ECX] =
1991 CPUID_EXT3_LAHF_LM,
1992 .features[FEAT_7_0_EDX] =
1993 CPUID_7_0_EDX_SPEC_CTRL,
1994 .features[FEAT_XSAVE] =
1995 CPUID_XSAVE_XSAVEOPT,
1996 .features[FEAT_6_EAX] =
1997 CPUID_6_EAX_ARAT,
1998 .xlevel = 0x80000008,
1999 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
2000 },
2001 {
2002 .name = "Haswell-noTSX",
2003 .level = 0xd,
2004 .vendor = CPUID_VENDOR_INTEL,
2005 .family = 6,
2006 .model = 60,
2007 .stepping = 1,
2008 .features[FEAT_1_EDX] =
2009 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2010 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2011 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2012 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2013 CPUID_DE | CPUID_FP87,
2014 .features[FEAT_1_ECX] =
2015 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2016 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2017 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2018 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2019 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2020 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2021 .features[FEAT_8000_0001_EDX] =
2022 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2023 CPUID_EXT2_SYSCALL,
2024 .features[FEAT_8000_0001_ECX] =
2025 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2026 .features[FEAT_7_0_EBX] =
2027 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2028 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2029 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2030 .features[FEAT_XSAVE] =
2031 CPUID_XSAVE_XSAVEOPT,
2032 .features[FEAT_6_EAX] =
2033 CPUID_6_EAX_ARAT,
2034 .xlevel = 0x80000008,
2035 .model_id = "Intel Core Processor (Haswell, no TSX)",
2036 },
2037 {
2038 .name = "Haswell-noTSX-IBRS",
2039 .level = 0xd,
2040 .vendor = CPUID_VENDOR_INTEL,
2041 .family = 6,
2042 .model = 60,
2043 .stepping = 1,
2044 .features[FEAT_1_EDX] =
2045 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2046 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2047 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2048 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2049 CPUID_DE | CPUID_FP87,
2050 .features[FEAT_1_ECX] =
2051 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2052 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2053 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2054 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2055 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2056 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2057 .features[FEAT_8000_0001_EDX] =
2058 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2059 CPUID_EXT2_SYSCALL,
2060 .features[FEAT_8000_0001_ECX] =
2061 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2062 .features[FEAT_7_0_EDX] =
2063 CPUID_7_0_EDX_SPEC_CTRL,
2064 .features[FEAT_7_0_EBX] =
2065 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2066 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2067 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2068 .features[FEAT_XSAVE] =
2069 CPUID_XSAVE_XSAVEOPT,
2070 .features[FEAT_6_EAX] =
2071 CPUID_6_EAX_ARAT,
2072 .xlevel = 0x80000008,
2073 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
2074 },
2075 {
2076 .name = "Haswell",
2077 .level = 0xd,
2078 .vendor = CPUID_VENDOR_INTEL,
2079 .family = 6,
2080 .model = 60,
2081 .stepping = 4,
2082 .features[FEAT_1_EDX] =
2083 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2084 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2085 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2086 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2087 CPUID_DE | CPUID_FP87,
2088 .features[FEAT_1_ECX] =
2089 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2090 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2091 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2092 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2093 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2094 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2095 .features[FEAT_8000_0001_EDX] =
2096 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2097 CPUID_EXT2_SYSCALL,
2098 .features[FEAT_8000_0001_ECX] =
2099 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2100 .features[FEAT_7_0_EBX] =
2101 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2102 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2103 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2104 CPUID_7_0_EBX_RTM,
2105 .features[FEAT_XSAVE] =
2106 CPUID_XSAVE_XSAVEOPT,
2107 .features[FEAT_6_EAX] =
2108 CPUID_6_EAX_ARAT,
2109 .xlevel = 0x80000008,
2110 .model_id = "Intel Core Processor (Haswell)",
2111 },
2112 {
2113 .name = "Haswell-IBRS",
2114 .level = 0xd,
2115 .vendor = CPUID_VENDOR_INTEL,
2116 .family = 6,
2117 .model = 60,
2118 .stepping = 4,
2119 .features[FEAT_1_EDX] =
2120 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2121 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2122 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2123 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2124 CPUID_DE | CPUID_FP87,
2125 .features[FEAT_1_ECX] =
2126 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2127 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2128 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2129 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2130 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2131 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2132 .features[FEAT_8000_0001_EDX] =
2133 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2134 CPUID_EXT2_SYSCALL,
2135 .features[FEAT_8000_0001_ECX] =
2136 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2137 .features[FEAT_7_0_EDX] =
2138 CPUID_7_0_EDX_SPEC_CTRL,
2139 .features[FEAT_7_0_EBX] =
2140 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2141 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2142 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2143 CPUID_7_0_EBX_RTM,
2144 .features[FEAT_XSAVE] =
2145 CPUID_XSAVE_XSAVEOPT,
2146 .features[FEAT_6_EAX] =
2147 CPUID_6_EAX_ARAT,
2148 .xlevel = 0x80000008,
2149 .model_id = "Intel Core Processor (Haswell, IBRS)",
2150 },
2151 {
2152 .name = "Broadwell-noTSX",
2153 .level = 0xd,
2154 .vendor = CPUID_VENDOR_INTEL,
2155 .family = 6,
2156 .model = 61,
2157 .stepping = 2,
2158 .features[FEAT_1_EDX] =
2159 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2160 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2161 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2162 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2163 CPUID_DE | CPUID_FP87,
2164 .features[FEAT_1_ECX] =
2165 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2166 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2167 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2168 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2169 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2170 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2171 .features[FEAT_8000_0001_EDX] =
2172 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2173 CPUID_EXT2_SYSCALL,
2174 .features[FEAT_8000_0001_ECX] =
2175 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2176 .features[FEAT_7_0_EBX] =
2177 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2178 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2179 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2180 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2181 CPUID_7_0_EBX_SMAP,
2182 .features[FEAT_XSAVE] =
2183 CPUID_XSAVE_XSAVEOPT,
2184 .features[FEAT_6_EAX] =
2185 CPUID_6_EAX_ARAT,
2186 .xlevel = 0x80000008,
2187 .model_id = "Intel Core Processor (Broadwell, no TSX)",
2188 },
2189 {
2190 .name = "Broadwell-noTSX-IBRS",
2191 .level = 0xd,
2192 .vendor = CPUID_VENDOR_INTEL,
2193 .family = 6,
2194 .model = 61,
2195 .stepping = 2,
2196 .features[FEAT_1_EDX] =
2197 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2198 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2199 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2200 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2201 CPUID_DE | CPUID_FP87,
2202 .features[FEAT_1_ECX] =
2203 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2204 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2205 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2206 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2207 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2208 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2209 .features[FEAT_8000_0001_EDX] =
2210 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2211 CPUID_EXT2_SYSCALL,
2212 .features[FEAT_8000_0001_ECX] =
2213 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2214 .features[FEAT_7_0_EDX] =
2215 CPUID_7_0_EDX_SPEC_CTRL,
2216 .features[FEAT_7_0_EBX] =
2217 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2218 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2219 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2220 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2221 CPUID_7_0_EBX_SMAP,
2222 .features[FEAT_XSAVE] =
2223 CPUID_XSAVE_XSAVEOPT,
2224 .features[FEAT_6_EAX] =
2225 CPUID_6_EAX_ARAT,
2226 .xlevel = 0x80000008,
2227 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
2228 },
2229 {
2230 .name = "Broadwell",
2231 .level = 0xd,
2232 .vendor = CPUID_VENDOR_INTEL,
2233 .family = 6,
2234 .model = 61,
2235 .stepping = 2,
2236 .features[FEAT_1_EDX] =
2237 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2238 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2239 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2240 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2241 CPUID_DE | CPUID_FP87,
2242 .features[FEAT_1_ECX] =
2243 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2244 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2245 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2246 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2247 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2248 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2249 .features[FEAT_8000_0001_EDX] =
2250 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2251 CPUID_EXT2_SYSCALL,
2252 .features[FEAT_8000_0001_ECX] =
2253 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2254 .features[FEAT_7_0_EBX] =
2255 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2256 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2257 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2258 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2259 CPUID_7_0_EBX_SMAP,
2260 .features[FEAT_XSAVE] =
2261 CPUID_XSAVE_XSAVEOPT,
2262 .features[FEAT_6_EAX] =
2263 CPUID_6_EAX_ARAT,
2264 .xlevel = 0x80000008,
2265 .model_id = "Intel Core Processor (Broadwell)",
2266 },
2267 {
2268 .name = "Broadwell-IBRS",
2269 .level = 0xd,
2270 .vendor = CPUID_VENDOR_INTEL,
2271 .family = 6,
2272 .model = 61,
2273 .stepping = 2,
2274 .features[FEAT_1_EDX] =
2275 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2276 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2277 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2278 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2279 CPUID_DE | CPUID_FP87,
2280 .features[FEAT_1_ECX] =
2281 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2282 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2283 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2284 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2285 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2286 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2287 .features[FEAT_8000_0001_EDX] =
2288 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2289 CPUID_EXT2_SYSCALL,
2290 .features[FEAT_8000_0001_ECX] =
2291 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2292 .features[FEAT_7_0_EDX] =
2293 CPUID_7_0_EDX_SPEC_CTRL,
2294 .features[FEAT_7_0_EBX] =
2295 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2296 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2297 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2298 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2299 CPUID_7_0_EBX_SMAP,
2300 .features[FEAT_XSAVE] =
2301 CPUID_XSAVE_XSAVEOPT,
2302 .features[FEAT_6_EAX] =
2303 CPUID_6_EAX_ARAT,
2304 .xlevel = 0x80000008,
2305 .model_id = "Intel Core Processor (Broadwell, IBRS)",
2306 },
2307 {
2308 .name = "Skylake-Client",
2309 .level = 0xd,
2310 .vendor = CPUID_VENDOR_INTEL,
2311 .family = 6,
2312 .model = 94,
2313 .stepping = 3,
2314 .features[FEAT_1_EDX] =
2315 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2316 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2317 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2318 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2319 CPUID_DE | CPUID_FP87,
2320 .features[FEAT_1_ECX] =
2321 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2322 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2323 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2324 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2325 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2326 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2327 .features[FEAT_8000_0001_EDX] =
2328 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2329 CPUID_EXT2_SYSCALL,
2330 .features[FEAT_8000_0001_ECX] =
2331 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2332 .features[FEAT_7_0_EBX] =
2333 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2334 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2335 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2336 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2337 CPUID_7_0_EBX_SMAP,
2338 /* Missing: XSAVES (not supported by some Linux versions,
2339 * including v4.1 to v4.12).
2340 * KVM doesn't yet expose any XSAVES state save component,
2341 * and the only one defined in Skylake (processor tracing)
2342 * probably will block migration anyway.
2343 */
2344 .features[FEAT_XSAVE] =
2345 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2346 CPUID_XSAVE_XGETBV1,
2347 .features[FEAT_6_EAX] =
2348 CPUID_6_EAX_ARAT,
2349 .xlevel = 0x80000008,
2350 .model_id = "Intel Core Processor (Skylake)",
2351 },
2352 {
2353 .name = "Skylake-Client-IBRS",
2354 .level = 0xd,
2355 .vendor = CPUID_VENDOR_INTEL,
2356 .family = 6,
2357 .model = 94,
2358 .stepping = 3,
2359 .features[FEAT_1_EDX] =
2360 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2361 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2362 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2363 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2364 CPUID_DE | CPUID_FP87,
2365 .features[FEAT_1_ECX] =
2366 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2367 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2368 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2369 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2370 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2371 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2372 .features[FEAT_8000_0001_EDX] =
2373 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2374 CPUID_EXT2_SYSCALL,
2375 .features[FEAT_8000_0001_ECX] =
2376 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2377 .features[FEAT_7_0_EDX] =
2378 CPUID_7_0_EDX_SPEC_CTRL,
2379 .features[FEAT_7_0_EBX] =
2380 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2381 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2382 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2383 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2384 CPUID_7_0_EBX_SMAP,
2385 /* Missing: XSAVES (not supported by some Linux versions,
2386 * including v4.1 to v4.12).
2387 * KVM doesn't yet expose any XSAVES state save component,
2388 * and the only one defined in Skylake (processor tracing)
2389 * probably will block migration anyway.
2390 */
2391 .features[FEAT_XSAVE] =
2392 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2393 CPUID_XSAVE_XGETBV1,
2394 .features[FEAT_6_EAX] =
2395 CPUID_6_EAX_ARAT,
2396 .xlevel = 0x80000008,
2397 .model_id = "Intel Core Processor (Skylake, IBRS)",
2398 },
2399 {
2400 .name = "Skylake-Server",
2401 .level = 0xd,
2402 .vendor = CPUID_VENDOR_INTEL,
2403 .family = 6,
2404 .model = 85,
2405 .stepping = 4,
2406 .features[FEAT_1_EDX] =
2407 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2408 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2409 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2410 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2411 CPUID_DE | CPUID_FP87,
2412 .features[FEAT_1_ECX] =
2413 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2414 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2415 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2416 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2417 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2418 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2419 .features[FEAT_8000_0001_EDX] =
2420 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2421 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2422 .features[FEAT_8000_0001_ECX] =
2423 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2424 .features[FEAT_7_0_EBX] =
2425 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2426 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2427 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2428 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2429 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2430 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2431 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2432 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2433 .features[FEAT_7_0_ECX] =
2434 CPUID_7_0_ECX_PKU,
2435 /* Missing: XSAVES (not supported by some Linux versions,
2436 * including v4.1 to v4.12).
2437 * KVM doesn't yet expose any XSAVES state save component,
2438 * and the only one defined in Skylake (processor tracing)
2439 * probably will block migration anyway.
2440 */
2441 .features[FEAT_XSAVE] =
2442 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2443 CPUID_XSAVE_XGETBV1,
2444 .features[FEAT_6_EAX] =
2445 CPUID_6_EAX_ARAT,
2446 .xlevel = 0x80000008,
2447 .model_id = "Intel Xeon Processor (Skylake)",
2448 },
2449 {
2450 .name = "Skylake-Server-IBRS",
2451 .level = 0xd,
2452 .vendor = CPUID_VENDOR_INTEL,
2453 .family = 6,
2454 .model = 85,
2455 .stepping = 4,
2456 .features[FEAT_1_EDX] =
2457 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2458 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2459 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2460 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2461 CPUID_DE | CPUID_FP87,
2462 .features[FEAT_1_ECX] =
2463 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2464 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2465 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2466 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2467 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2468 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2469 .features[FEAT_8000_0001_EDX] =
2470 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2471 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2472 .features[FEAT_8000_0001_ECX] =
2473 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2474 .features[FEAT_7_0_EDX] =
2475 CPUID_7_0_EDX_SPEC_CTRL,
2476 .features[FEAT_7_0_EBX] =
2477 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2478 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2479 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2480 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2481 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2482 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2483 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2484 CPUID_7_0_EBX_AVX512VL,
2485 .features[FEAT_7_0_ECX] =
2486 CPUID_7_0_ECX_PKU,
2487 /* Missing: XSAVES (not supported by some Linux versions,
2488 * including v4.1 to v4.12).
2489 * KVM doesn't yet expose any XSAVES state save component,
2490 * and the only one defined in Skylake (processor tracing)
2491 * probably will block migration anyway.
2492 */
2493 .features[FEAT_XSAVE] =
2494 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2495 CPUID_XSAVE_XGETBV1,
2496 .features[FEAT_6_EAX] =
2497 CPUID_6_EAX_ARAT,
2498 .xlevel = 0x80000008,
2499 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2500 },
2501 {
2502 .name = "Cascadelake-Server",
2503 .level = 0xd,
2504 .vendor = CPUID_VENDOR_INTEL,
2505 .family = 6,
2506 .model = 85,
2507 .stepping = 6,
2508 .features[FEAT_1_EDX] =
2509 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2510 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2511 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2512 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2513 CPUID_DE | CPUID_FP87,
2514 .features[FEAT_1_ECX] =
2515 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2516 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2517 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2518 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2519 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2520 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2521 .features[FEAT_8000_0001_EDX] =
2522 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2523 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2524 .features[FEAT_8000_0001_ECX] =
2525 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2526 .features[FEAT_7_0_EBX] =
2527 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2528 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2529 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2530 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2531 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2532 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2533 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2534 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2535 .features[FEAT_7_0_ECX] =
2536 CPUID_7_0_ECX_PKU |
2537 CPUID_7_0_ECX_AVX512VNNI,
2538 .features[FEAT_7_0_EDX] =
2539 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2540 /* Missing: XSAVES (not supported by some Linux versions,
2541 * including v4.1 to v4.12).
2542 * KVM doesn't yet expose any XSAVES state save component,
2543 * and the only one defined in Skylake (processor tracing)
2544 * probably will block migration anyway.
2545 */
2546 .features[FEAT_XSAVE] =
2547 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2548 CPUID_XSAVE_XGETBV1,
2549 .features[FEAT_6_EAX] =
2550 CPUID_6_EAX_ARAT,
2551 .xlevel = 0x80000008,
2552 .model_id = "Intel Xeon Processor (Cascadelake)",
2553 },
2554 {
2555 .name = "Icelake-Client",
2556 .level = 0xd,
2557 .vendor = CPUID_VENDOR_INTEL,
2558 .family = 6,
2559 .model = 126,
2560 .stepping = 0,
2561 .features[FEAT_1_EDX] =
2562 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2563 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2564 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2565 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2566 CPUID_DE | CPUID_FP87,
2567 .features[FEAT_1_ECX] =
2568 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2569 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2570 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2571 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2572 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2573 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2574 .features[FEAT_8000_0001_EDX] =
2575 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2576 CPUID_EXT2_SYSCALL,
2577 .features[FEAT_8000_0001_ECX] =
2578 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2579 .features[FEAT_8000_0008_EBX] =
2580 CPUID_8000_0008_EBX_WBNOINVD,
2581 .features[FEAT_7_0_EBX] =
2582 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2583 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2584 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2585 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2586 CPUID_7_0_EBX_SMAP,
2587 .features[FEAT_7_0_ECX] =
2588 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2589 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2590 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2591 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2592 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2593 .features[FEAT_7_0_EDX] =
2594 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2595 /* Missing: XSAVES (not supported by some Linux versions,
2596 * including v4.1 to v4.12).
2597 * KVM doesn't yet expose any XSAVES state save component,
2598 * and the only one defined in Skylake (processor tracing)
2599 * probably will block migration anyway.
2600 */
2601 .features[FEAT_XSAVE] =
2602 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2603 CPUID_XSAVE_XGETBV1,
2604 .features[FEAT_6_EAX] =
2605 CPUID_6_EAX_ARAT,
2606 .xlevel = 0x80000008,
2607 .model_id = "Intel Core Processor (Icelake)",
2608 },
2609 {
2610 .name = "Icelake-Server",
2611 .level = 0xd,
2612 .vendor = CPUID_VENDOR_INTEL,
2613 .family = 6,
2614 .model = 134,
2615 .stepping = 0,
2616 .features[FEAT_1_EDX] =
2617 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2618 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2619 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2620 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2621 CPUID_DE | CPUID_FP87,
2622 .features[FEAT_1_ECX] =
2623 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2624 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2625 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2626 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2627 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2628 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2629 .features[FEAT_8000_0001_EDX] =
2630 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2631 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2632 .features[FEAT_8000_0001_ECX] =
2633 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2634 .features[FEAT_8000_0008_EBX] =
2635 CPUID_8000_0008_EBX_WBNOINVD,
2636 .features[FEAT_7_0_EBX] =
2637 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2638 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2639 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2640 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2641 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2642 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2643 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2644 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2645 .features[FEAT_7_0_ECX] =
2646 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2647 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2648 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2649 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2650 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
2651 .features[FEAT_7_0_EDX] =
2652 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2653 /* Missing: XSAVES (not supported by some Linux versions,
2654 * including v4.1 to v4.12).
2655 * KVM doesn't yet expose any XSAVES state save component,
2656 * and the only one defined in Skylake (processor tracing)
2657 * probably will block migration anyway.
2658 */
2659 .features[FEAT_XSAVE] =
2660 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2661 CPUID_XSAVE_XGETBV1,
2662 .features[FEAT_6_EAX] =
2663 CPUID_6_EAX_ARAT,
2664 .xlevel = 0x80000008,
2665 .model_id = "Intel Xeon Processor (Icelake)",
2666 },
2667 {
2668 .name = "KnightsMill",
2669 .level = 0xd,
2670 .vendor = CPUID_VENDOR_INTEL,
2671 .family = 6,
2672 .model = 133,
2673 .stepping = 0,
2674 .features[FEAT_1_EDX] =
2675 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2676 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2677 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2678 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2679 CPUID_PSE | CPUID_DE | CPUID_FP87,
2680 .features[FEAT_1_ECX] =
2681 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2682 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2683 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2684 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2685 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2686 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2687 .features[FEAT_8000_0001_EDX] =
2688 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2689 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2690 .features[FEAT_8000_0001_ECX] =
2691 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2692 .features[FEAT_7_0_EBX] =
2693 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2694 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2695 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2696 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2697 CPUID_7_0_EBX_AVX512ER,
2698 .features[FEAT_7_0_ECX] =
2699 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2700 .features[FEAT_7_0_EDX] =
2701 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2702 .features[FEAT_XSAVE] =
2703 CPUID_XSAVE_XSAVEOPT,
2704 .features[FEAT_6_EAX] =
2705 CPUID_6_EAX_ARAT,
2706 .xlevel = 0x80000008,
2707 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2708 },
2709 {
2710 .name = "Opteron_G1",
2711 .level = 5,
2712 .vendor = CPUID_VENDOR_AMD,
2713 .family = 15,
2714 .model = 6,
2715 .stepping = 1,
2716 .features[FEAT_1_EDX] =
2717 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2718 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2719 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2720 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2721 CPUID_DE | CPUID_FP87,
2722 .features[FEAT_1_ECX] =
2723 CPUID_EXT_SSE3,
2724 .features[FEAT_8000_0001_EDX] =
2725 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2726 .xlevel = 0x80000008,
2727 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2728 },
2729 {
2730 .name = "Opteron_G2",
2731 .level = 5,
2732 .vendor = CPUID_VENDOR_AMD,
2733 .family = 15,
2734 .model = 6,
2735 .stepping = 1,
2736 .features[FEAT_1_EDX] =
2737 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2738 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2739 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2740 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2741 CPUID_DE | CPUID_FP87,
2742 .features[FEAT_1_ECX] =
2743 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
2744 .features[FEAT_8000_0001_EDX] =
2745 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2746 .features[FEAT_8000_0001_ECX] =
2747 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2748 .xlevel = 0x80000008,
2749 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2750 },
2751 {
2752 .name = "Opteron_G3",
2753 .level = 5,
2754 .vendor = CPUID_VENDOR_AMD,
2755 .family = 16,
2756 .model = 2,
2757 .stepping = 3,
2758 .features[FEAT_1_EDX] =
2759 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2760 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2761 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2762 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2763 CPUID_DE | CPUID_FP87,
2764 .features[FEAT_1_ECX] =
2765 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
2766 CPUID_EXT_SSE3,
2767 .features[FEAT_8000_0001_EDX] =
2768 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
2769 CPUID_EXT2_RDTSCP,
2770 .features[FEAT_8000_0001_ECX] =
2771 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
2772 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2773 .xlevel = 0x80000008,
2774 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2775 },
2776 {
2777 .name = "Opteron_G4",
2778 .level = 0xd,
2779 .vendor = CPUID_VENDOR_AMD,
2780 .family = 21,
2781 .model = 1,
2782 .stepping = 2,
2783 .features[FEAT_1_EDX] =
2784 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2785 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2786 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2787 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2788 CPUID_DE | CPUID_FP87,
2789 .features[FEAT_1_ECX] =
2790 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2791 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2792 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2793 CPUID_EXT_SSE3,
2794 .features[FEAT_8000_0001_EDX] =
2795 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2796 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
2797 .features[FEAT_8000_0001_ECX] =
2798 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
2799 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2800 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2801 CPUID_EXT3_LAHF_LM,
2802 .features[FEAT_SVM] =
2803 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2804 /* no xsaveopt! */
2805 .xlevel = 0x8000001A,
2806 .model_id = "AMD Opteron 62xx class CPU",
2807 },
2808 {
2809 .name = "Opteron_G5",
2810 .level = 0xd,
2811 .vendor = CPUID_VENDOR_AMD,
2812 .family = 21,
2813 .model = 2,
2814 .stepping = 0,
2815 .features[FEAT_1_EDX] =
2816 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2817 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2818 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2819 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2820 CPUID_DE | CPUID_FP87,
2821 .features[FEAT_1_ECX] =
2822 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
2823 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2824 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2825 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2826 .features[FEAT_8000_0001_EDX] =
2827 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2828 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
2829 .features[FEAT_8000_0001_ECX] =
2830 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
2831 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2832 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2833 CPUID_EXT3_LAHF_LM,
2834 .features[FEAT_SVM] =
2835 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2836 /* no xsaveopt! */
2837 .xlevel = 0x8000001A,
2838 .model_id = "AMD Opteron 63xx class CPU",
2839 },
2840 {
2841 .name = "EPYC",
2842 .level = 0xd,
2843 .vendor = CPUID_VENDOR_AMD,
2844 .family = 23,
2845 .model = 1,
2846 .stepping = 2,
2847 .features[FEAT_1_EDX] =
2848 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2849 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2850 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2851 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2852 CPUID_VME | CPUID_FP87,
2853 .features[FEAT_1_ECX] =
2854 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2855 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2856 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2857 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2858 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2859 .features[FEAT_8000_0001_EDX] =
2860 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2861 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2862 CPUID_EXT2_SYSCALL,
2863 .features[FEAT_8000_0001_ECX] =
2864 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2865 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2866 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2867 CPUID_EXT3_TOPOEXT,
2868 .features[FEAT_7_0_EBX] =
2869 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2870 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2871 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2872 CPUID_7_0_EBX_SHA_NI,
2873 /* Missing: XSAVES (not supported by some Linux versions,
2874 * including v4.1 to v4.12).
2875 * KVM doesn't yet expose any XSAVES state save component.
2876 */
2877 .features[FEAT_XSAVE] =
2878 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2879 CPUID_XSAVE_XGETBV1,
2880 .features[FEAT_6_EAX] =
2881 CPUID_6_EAX_ARAT,
2882 .features[FEAT_SVM] =
2883 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2884 .xlevel = 0x8000001E,
2885 .model_id = "AMD EPYC Processor",
2886 .cache_info = &epyc_cache_info,
2887 },
2888 {
2889 .name = "EPYC-IBPB",
2890 .level = 0xd,
2891 .vendor = CPUID_VENDOR_AMD,
2892 .family = 23,
2893 .model = 1,
2894 .stepping = 2,
2895 .features[FEAT_1_EDX] =
2896 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2897 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2898 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2899 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2900 CPUID_VME | CPUID_FP87,
2901 .features[FEAT_1_ECX] =
2902 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2903 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2904 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2905 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2906 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2907 .features[FEAT_8000_0001_EDX] =
2908 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2909 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2910 CPUID_EXT2_SYSCALL,
2911 .features[FEAT_8000_0001_ECX] =
2912 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2913 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2914 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2915 CPUID_EXT3_TOPOEXT,
2916 .features[FEAT_8000_0008_EBX] =
2917 CPUID_8000_0008_EBX_IBPB,
2918 .features[FEAT_7_0_EBX] =
2919 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2920 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2921 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2922 CPUID_7_0_EBX_SHA_NI,
2923 /* Missing: XSAVES (not supported by some Linux versions,
2924 * including v4.1 to v4.12).
2925 * KVM doesn't yet expose any XSAVES state save component.
2926 */
2927 .features[FEAT_XSAVE] =
2928 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2929 CPUID_XSAVE_XGETBV1,
2930 .features[FEAT_6_EAX] =
2931 CPUID_6_EAX_ARAT,
2932 .features[FEAT_SVM] =
2933 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2934 .xlevel = 0x8000001E,
2935 .model_id = "AMD EPYC Processor (with IBPB)",
2936 .cache_info = &epyc_cache_info,
2937 },
2938 {
2939 .name = "Dhyana",
2940 .level = 0xd,
2941 .vendor = CPUID_VENDOR_HYGON,
2942 .family = 24,
2943 .model = 0,
2944 .stepping = 1,
2945 .features[FEAT_1_EDX] =
2946 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2947 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2948 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2949 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2950 CPUID_VME | CPUID_FP87,
2951 .features[FEAT_1_ECX] =
2952 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2953 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
2954 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2955 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2956 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
2957 .features[FEAT_8000_0001_EDX] =
2958 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2959 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2960 CPUID_EXT2_SYSCALL,
2961 .features[FEAT_8000_0001_ECX] =
2962 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2963 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2964 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2965 CPUID_EXT3_TOPOEXT,
2966 .features[FEAT_8000_0008_EBX] =
2967 CPUID_8000_0008_EBX_IBPB,
2968 .features[FEAT_7_0_EBX] =
2969 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2970 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2971 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
2972 /*
2973 * Missing: XSAVES (not supported by some Linux versions,
2974 * including v4.1 to v4.12).
2975 * KVM doesn't yet expose any XSAVES state save component.
2976 */
2977 .features[FEAT_XSAVE] =
2978 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2979 CPUID_XSAVE_XGETBV1,
2980 .features[FEAT_6_EAX] =
2981 CPUID_6_EAX_ARAT,
2982 .features[FEAT_SVM] =
2983 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2984 .xlevel = 0x8000001E,
2985 .model_id = "Hygon Dhyana Processor",
2986 .cache_info = &epyc_cache_info,
2987 },
2988 };
2989
2990 typedef struct PropValue {
2991 const char *prop, *value;
2992 } PropValue;
2993
2994 /* KVM-specific features that are automatically added/removed
2995 * from all CPU models when KVM is enabled.
2996 */
2997 static PropValue kvm_default_props[] = {
2998 { "kvmclock", "on" },
2999 { "kvm-nopiodelay", "on" },
3000 { "kvm-asyncpf", "on" },
3001 { "kvm-steal-time", "on" },
3002 { "kvm-pv-eoi", "on" },
3003 { "kvmclock-stable-bit", "on" },
3004 { "x2apic", "on" },
3005 { "acpi", "off" },
3006 { "monitor", "off" },
3007 { "svm", "off" },
3008 { NULL, NULL },
3009 };
3010
3011 /* TCG-specific defaults that override all CPU models when using TCG
3012 */
3013 static PropValue tcg_default_props[] = {
3014 { "vme", "off" },
3015 { NULL, NULL },
3016 };
3017
3018
3019 void x86_cpu_change_kvm_default(const char *prop, const char *value)
3020 {
3021 PropValue *pv;
3022 for (pv = kvm_default_props; pv->prop; pv++) {
3023 if (!strcmp(pv->prop, prop)) {
3024 pv->value = value;
3025 break;
3026 }
3027 }
3028
3029 /* It is valid to call this function only for properties that
3030 * are already present in the kvm_default_props table.
3031 */
3032 assert(pv->prop);
3033 }
3034
3035 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3036 bool migratable_only);
3037
3038 static bool lmce_supported(void)
3039 {
3040 uint64_t mce_cap = 0;
3041
3042 #ifdef CONFIG_KVM
3043 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
3044 return false;
3045 }
3046 #endif
3047
3048 return !!(mce_cap & MCG_LMCE_P);
3049 }
3050
3051 #define CPUID_MODEL_ID_SZ 48
3052
3053 /**
3054 * cpu_x86_fill_model_id:
3055 * Get CPUID model ID string from host CPU.
3056 *
3057 * @str should have at least CPUID_MODEL_ID_SZ bytes
3058 *
3059 * The function does NOT add a null terminator to the string
3060 * automatically.
3061 */
3062 static int cpu_x86_fill_model_id(char *str)
3063 {
3064 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3065 int i;
3066
3067 for (i = 0; i < 3; i++) {
3068 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
3069 memcpy(str + i * 16 + 0, &eax, 4);
3070 memcpy(str + i * 16 + 4, &ebx, 4);
3071 memcpy(str + i * 16 + 8, &ecx, 4);
3072 memcpy(str + i * 16 + 12, &edx, 4);
3073 }
3074 return 0;
3075 }
3076
3077 static Property max_x86_cpu_properties[] = {
3078 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
3079 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
3080 DEFINE_PROP_END_OF_LIST()
3081 };
3082
3083 static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
3084 {
3085 DeviceClass *dc = DEVICE_CLASS(oc);
3086 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3087
3088 xcc->ordering = 9;
3089
3090 xcc->model_description =
3091 "Enables all features supported by the accelerator in the current host";
3092
3093 dc->props = max_x86_cpu_properties;
3094 }
3095
3096 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
3097
3098 static void max_x86_cpu_initfn(Object *obj)
3099 {
3100 X86CPU *cpu = X86_CPU(obj);
3101 CPUX86State *env = &cpu->env;
3102 KVMState *s = kvm_state;
3103
3104 /* We can't fill the features array here because we don't know yet if
3105 * "migratable" is true or false.
3106 */
3107 cpu->max_features = true;
3108
3109 if (accel_uses_host_cpuid()) {
3110 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
3111 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
3112 int family, model, stepping;
3113 X86CPUDefinition host_cpudef = { };
3114 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3115
3116 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
3117 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
3118
3119 host_vendor_fms(vendor, &family, &model, &stepping);
3120
3121 cpu_x86_fill_model_id(model_id);
3122
3123 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
3124 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
3125 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
3126 object_property_set_int(OBJECT(cpu), stepping, "stepping",
3127 &error_abort);
3128 object_property_set_str(OBJECT(cpu), model_id, "model-id",
3129 &error_abort);
3130
3131 if (kvm_enabled()) {
3132 env->cpuid_min_level =
3133 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
3134 env->cpuid_min_xlevel =
3135 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
3136 env->cpuid_min_xlevel2 =
3137 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
3138 } else {
3139 env->cpuid_min_level =
3140 hvf_get_supported_cpuid(0x0, 0, R_EAX);
3141 env->cpuid_min_xlevel =
3142 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
3143 env->cpuid_min_xlevel2 =
3144 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
3145 }
3146
3147 if (lmce_supported()) {
3148 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
3149 }
3150 } else {
3151 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
3152 "vendor", &error_abort);
3153 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
3154 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
3155 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
3156 object_property_set_str(OBJECT(cpu),
3157 "QEMU TCG CPU version " QEMU_HW_VERSION,
3158 "model-id", &error_abort);
3159 }
3160
3161 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
3162 }
3163
3164 static const TypeInfo max_x86_cpu_type_info = {
3165 .name = X86_CPU_TYPE_NAME("max"),
3166 .parent = TYPE_X86_CPU,
3167 .instance_init = max_x86_cpu_initfn,
3168 .class_init = max_x86_cpu_class_init,
3169 };
3170
3171 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
3172 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
3173 {
3174 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3175
3176 xcc->host_cpuid_required = true;
3177 xcc->ordering = 8;
3178
3179 #if defined(CONFIG_KVM)
3180 xcc->model_description =
3181 "KVM processor with all supported host features ";
3182 #elif defined(CONFIG_HVF)
3183 xcc->model_description =
3184 "HVF processor with all supported host features ";
3185 #endif
3186 }
3187
3188 static const TypeInfo host_x86_cpu_type_info = {
3189 .name = X86_CPU_TYPE_NAME("host"),
3190 .parent = X86_CPU_TYPE_NAME("max"),
3191 .class_init = host_x86_cpu_class_init,
3192 };
3193
3194 #endif
3195
3196 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
3197 {
3198 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
3199
3200 switch (f->type) {
3201 case CPUID_FEATURE_WORD:
3202 {
3203 const char *reg = get_register_name_32(f->cpuid.reg);
3204 assert(reg);
3205 return g_strdup_printf("CPUID.%02XH:%s",
3206 f->cpuid.eax, reg);
3207 }
3208 case MSR_FEATURE_WORD:
3209 return g_strdup_printf("MSR(%02XH)",
3210 f->msr.index);
3211 }
3212
3213 return NULL;
3214 }
3215
3216 static void report_unavailable_features(FeatureWord w, uint32_t mask)
3217 {
3218 FeatureWordInfo *f = &feature_word_info[w];
3219 int i;
3220 char *feat_word_str;
3221
3222 for (i = 0; i < 32; ++i) {
3223 if ((1UL << i) & mask) {
3224 feat_word_str = feature_word_description(f, i);
3225 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
3226 accel_uses_host_cpuid() ? "host" : "TCG",
3227 feat_word_str,
3228 f->feat_names[i] ? "." : "",
3229 f->feat_names[i] ? f->feat_names[i] : "", i);
3230 g_free(feat_word_str);
3231 }
3232 }
3233 }
3234
3235 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
3236 const char *name, void *opaque,
3237 Error **errp)
3238 {
3239 X86CPU *cpu = X86_CPU(obj);
3240 CPUX86State *env = &cpu->env;
3241 int64_t value;
3242
3243 value = (env->cpuid_version >> 8) & 0xf;
3244 if (value == 0xf) {
3245 value += (env->cpuid_version >> 20) & 0xff;
3246 }
3247 visit_type_int(v, name, &value, errp);
3248 }
3249
3250 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
3251 const char *name, void *opaque,
3252 Error **errp)
3253 {
3254 X86CPU *cpu = X86_CPU(obj);
3255 CPUX86State *env = &cpu->env;
3256 const int64_t min = 0;
3257 const int64_t max = 0xff + 0xf;
3258 Error *local_err = NULL;
3259 int64_t value;
3260
3261 visit_type_int(v, name, &value, &local_err);
3262 if (local_err) {
3263 error_propagate(errp, local_err);
3264 return;
3265 }
3266 if (value < min || value > max) {
3267 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3268 name ? name : "null", value, min, max);
3269 return;
3270 }
3271
3272 env->cpuid_version &= ~0xff00f00;
3273 if (value > 0x0f) {
3274 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
3275 } else {
3276 env->cpuid_version |= value << 8;
3277 }
3278 }
3279
3280 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
3281 const char *name, void *opaque,
3282 Error **errp)
3283 {
3284 X86CPU *cpu = X86_CPU(obj);
3285 CPUX86State *env = &cpu->env;
3286 int64_t value;
3287
3288 value = (env->cpuid_version >> 4) & 0xf;
3289 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
3290 visit_type_int(v, name, &value, errp);
3291 }
3292
3293 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
3294 const char *name, void *opaque,
3295 Error **errp)
3296 {
3297 X86CPU *cpu = X86_CPU(obj);
3298 CPUX86State *env = &cpu->env;
3299 const int64_t min = 0;
3300 const int64_t max = 0xff;
3301 Error *local_err = NULL;
3302 int64_t value;
3303
3304 visit_type_int(v, name, &value, &local_err);
3305 if (local_err) {
3306 error_propagate(errp, local_err);
3307 return;
3308 }
3309 if (value < min || value > max) {
3310 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3311 name ? name : "null", value, min, max);
3312 return;
3313 }
3314
3315 env->cpuid_version &= ~0xf00f0;
3316 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
3317 }
3318
3319 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
3320 const char *name, void *opaque,
3321 Error **errp)
3322 {
3323 X86CPU *cpu = X86_CPU(obj);
3324 CPUX86State *env = &cpu->env;
3325 int64_t value;
3326
3327 value = env->cpuid_version & 0xf;
3328 visit_type_int(v, name, &value, errp);
3329 }
3330
3331 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
3332 const char *name, void *opaque,
3333 Error **errp)
3334 {
3335 X86CPU *cpu = X86_CPU(obj);
3336 CPUX86State *env = &cpu->env;
3337 const int64_t min = 0;
3338 const int64_t max = 0xf;
3339 Error *local_err = NULL;
3340 int64_t value;
3341
3342 visit_type_int(v, name, &value, &local_err);
3343 if (local_err) {
3344 error_propagate(errp, local_err);
3345 return;
3346 }
3347 if (value < min || value > max) {
3348 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3349 name ? name : "null", value, min, max);
3350 return;
3351 }
3352
3353 env->cpuid_version &= ~0xf;
3354 env->cpuid_version |= value & 0xf;
3355 }
3356
3357 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
3358 {
3359 X86CPU *cpu = X86_CPU(obj);
3360 CPUX86State *env = &cpu->env;
3361 char *value;
3362
3363 value = g_malloc(CPUID_VENDOR_SZ + 1);
3364 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
3365 env->cpuid_vendor3);
3366 return value;
3367 }
3368
3369 static void x86_cpuid_set_vendor(Object *obj, const char *value,
3370 Error **errp)
3371 {
3372 X86CPU *cpu = X86_CPU(obj);
3373 CPUX86State *env = &cpu->env;
3374 int i;
3375
3376 if (strlen(value) != CPUID_VENDOR_SZ) {
3377 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
3378 return;
3379 }
3380
3381 env->cpuid_vendor1 = 0;
3382 env->cpuid_vendor2 = 0;
3383 env->cpuid_vendor3 = 0;
3384 for (i = 0; i < 4; i++) {
3385 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
3386 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
3387 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
3388 }
3389 }
3390
3391 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
3392 {
3393 X86CPU *cpu = X86_CPU(obj);
3394 CPUX86State *env = &cpu->env;
3395 char *value;
3396 int i;
3397
3398 value = g_malloc(48 + 1);
3399 for (i = 0; i < 48; i++) {
3400 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
3401 }
3402 value[48] = '\0';
3403 return value;
3404 }
3405
3406 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
3407 Error **errp)
3408 {
3409 X86CPU *cpu = X86_CPU(obj);
3410 CPUX86State *env = &cpu->env;
3411 int c, len, i;
3412
3413 if (model_id == NULL) {
3414 model_id = "";
3415 }
3416 len = strlen(model_id);
3417 memset(env->cpuid_model, 0, 48);
3418 for (i = 0; i < 48; i++) {
3419 if (i >= len) {
3420 c = '\0';
3421 } else {
3422 c = (uint8_t)model_id[i];
3423 }
3424 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
3425 }
3426 }
3427
3428 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
3429 void *opaque, Error **errp)
3430 {
3431 X86CPU *cpu = X86_CPU(obj);
3432 int64_t value;
3433
3434 value = cpu->env.tsc_khz * 1000;
3435 visit_type_int(v, name, &value, errp);
3436 }
3437
3438 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
3439 void *opaque, Error **errp)
3440 {
3441 X86CPU *cpu = X86_CPU(obj);
3442 const int64_t min = 0;
3443 const int64_t max = INT64_MAX;
3444 Error *local_err = NULL;
3445 int64_t value;
3446
3447 visit_type_int(v, name, &value, &local_err);
3448 if (local_err) {
3449 error_propagate(errp, local_err);
3450 return;
3451 }
3452 if (value < min || value > max) {
3453 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3454 name ? name : "null", value, min, max);
3455 return;
3456 }
3457
3458 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
3459 }
3460
3461 /* Generic getter for "feature-words" and "filtered-features" properties */
3462 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
3463 const char *name, void *opaque,
3464 Error **errp)
3465 {
3466 uint32_t *array = (uint32_t *)opaque;
3467 FeatureWord w;
3468 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
3469 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
3470 X86CPUFeatureWordInfoList *list = NULL;
3471
3472 for (w = 0; w < FEATURE_WORDS; w++) {
3473 FeatureWordInfo *wi = &feature_word_info[w];
3474 /*
3475 * We didn't have MSR features when "feature-words" was
3476 * introduced. Therefore skipped other type entries.
3477 */
3478 if (wi->type != CPUID_FEATURE_WORD) {
3479 continue;
3480 }
3481 X86CPUFeatureWordInfo *qwi = &word_infos[w];
3482 qwi->cpuid_input_eax = wi->cpuid.eax;
3483 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
3484 qwi->cpuid_input_ecx = wi->cpuid.ecx;
3485 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
3486 qwi->features = array[w];
3487
3488 /* List will be in reverse order, but order shouldn't matter */
3489 list_entries[w].next = list;
3490 list_entries[w].value = &word_infos[w];
3491 list = &list_entries[w];
3492 }
3493
3494 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
3495 }
3496
3497 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3498 void *opaque, Error **errp)
3499 {
3500 X86CPU *cpu = X86_CPU(obj);
3501 int64_t value = cpu->hyperv_spinlock_attempts;
3502
3503 visit_type_int(v, name, &value, errp);
3504 }
3505
3506 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3507 void *opaque, Error **errp)
3508 {
3509 const int64_t min = 0xFFF;
3510 const int64_t max = UINT_MAX;
3511 X86CPU *cpu = X86_CPU(obj);
3512 Error *err = NULL;
3513 int64_t value;
3514
3515 visit_type_int(v, name, &value, &err);
3516 if (err) {
3517 error_propagate(errp, err);
3518 return;
3519 }
3520
3521 if (value < min || value > max) {
3522 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
3523 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
3524 object_get_typename(obj), name ? name : "null",
3525 value, min, max);
3526 return;
3527 }
3528 cpu->hyperv_spinlock_attempts = value;
3529 }
3530
3531 static const PropertyInfo qdev_prop_spinlocks = {
3532 .name = "int",
3533 .get = x86_get_hv_spinlocks,
3534 .set = x86_set_hv_spinlocks,
3535 };
3536
3537 /* Convert all '_' in a feature string option name to '-', to make feature
3538 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3539 */
3540 static inline void feat2prop(char *s)
3541 {
3542 while ((s = strchr(s, '_'))) {
3543 *s = '-';
3544 }
3545 }
3546
3547 /* Return the feature property name for a feature flag bit */
3548 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
3549 {
3550 /* XSAVE components are automatically enabled by other features,
3551 * so return the original feature name instead
3552 */
3553 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
3554 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
3555
3556 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
3557 x86_ext_save_areas[comp].bits) {
3558 w = x86_ext_save_areas[comp].feature;
3559 bitnr = ctz32(x86_ext_save_areas[comp].bits);
3560 }
3561 }
3562
3563 assert(bitnr < 32);
3564 assert(w < FEATURE_WORDS);
3565 return feature_word_info[w].feat_names[bitnr];
3566 }
3567
3568 /* Compatibily hack to maintain legacy +-feat semantic,
3569 * where +-feat overwrites any feature set by
3570 * feat=on|feat even if the later is parsed after +-feat
3571 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3572 */
3573 static GList *plus_features, *minus_features;
3574
3575 static gint compare_string(gconstpointer a, gconstpointer b)
3576 {
3577 return g_strcmp0(a, b);
3578 }
3579
3580 /* Parse "+feature,-feature,feature=foo" CPU feature string
3581 */
3582 static void x86_cpu_parse_featurestr(const char *typename, char *features,
3583 Error **errp)
3584 {
3585 char *featurestr; /* Single 'key=value" string being parsed */
3586 static bool cpu_globals_initialized;
3587 bool ambiguous = false;
3588
3589 if (cpu_globals_initialized) {
3590 return;
3591 }
3592 cpu_globals_initialized = true;
3593
3594 if (!features) {
3595 return;
3596 }
3597
3598 for (featurestr = strtok(features, ",");
3599 featurestr;
3600 featurestr = strtok(NULL, ",")) {
3601 const char *name;
3602 const char *val = NULL;
3603 char *eq = NULL;
3604 char num[32];
3605 GlobalProperty *prop;
3606
3607 /* Compatibility syntax: */
3608 if (featurestr[0] == '+') {
3609 plus_features = g_list_append(plus_features,
3610 g_strdup(featurestr + 1));
3611 continue;
3612 } else if (featurestr[0] == '-') {
3613 minus_features = g_list_append(minus_features,
3614 g_strdup(featurestr + 1));
3615 continue;
3616 }
3617
3618 eq = strchr(featurestr, '=');
3619 if (eq) {
3620 *eq++ = 0;
3621 val = eq;
3622 } else {
3623 val = "on";
3624 }
3625
3626 feat2prop(featurestr);
3627 name = featurestr;
3628
3629 if (g_list_find_custom(plus_features, name, compare_string)) {
3630 warn_report("Ambiguous CPU model string. "
3631 "Don't mix both \"+%s\" and \"%s=%s\"",
3632 name, name, val);
3633 ambiguous = true;
3634 }
3635 if (g_list_find_custom(minus_features, name, compare_string)) {
3636 warn_report("Ambiguous CPU model string. "
3637 "Don't mix both \"-%s\" and \"%s=%s\"",
3638 name, name, val);
3639 ambiguous = true;
3640 }
3641
3642 /* Special case: */
3643 if (!strcmp(name, "tsc-freq")) {
3644 int ret;
3645 uint64_t tsc_freq;
3646
3647 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
3648 if (ret < 0 || tsc_freq > INT64_MAX) {
3649 error_setg(errp, "bad numerical value %s", val);
3650 return;
3651 }
3652 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3653 val = num;
3654 name = "tsc-frequency";
3655 }
3656
3657 prop = g_new0(typeof(*prop), 1);
3658 prop->driver = typename;
3659 prop->property = g_strdup(name);
3660 prop->value = g_strdup(val);
3661 qdev_prop_register_global(prop);
3662 }
3663
3664 if (ambiguous) {
3665 warn_report("Compatibility of ambiguous CPU model "
3666 "strings won't be kept on future QEMU versions");
3667 }
3668 }
3669
3670 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
3671 static int x86_cpu_filter_features(X86CPU *cpu);
3672
3673 /* Check for missing features that may prevent the CPU class from
3674 * running using the current machine and accelerator.
3675 */
3676 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3677 strList **missing_feats)
3678 {
3679 X86CPU *xc;
3680 FeatureWord w;
3681 Error *err = NULL;
3682 strList **next = missing_feats;
3683
3684 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
3685 strList *new = g_new0(strList, 1);
3686 new->value = g_strdup("kvm");
3687 *missing_feats = new;
3688 return;
3689 }
3690
3691 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3692
3693 x86_cpu_expand_features(xc, &err);
3694 if (err) {
3695 /* Errors at x86_cpu_expand_features should never happen,
3696 * but in case it does, just report the model as not
3697 * runnable at all using the "type" property.
3698 */
3699 strList *new = g_new0(strList, 1);
3700 new->value = g_strdup("type");
3701 *next = new;
3702 next = &new->next;
3703 }
3704
3705 x86_cpu_filter_features(xc);
3706
3707 for (w = 0; w < FEATURE_WORDS; w++) {
3708 uint32_t filtered = xc->filtered_features[w];
3709 int i;
3710 for (i = 0; i < 32; i++) {
3711 if (filtered & (1UL << i)) {
3712 strList *new = g_new0(strList, 1);
3713 new->value = g_strdup(x86_cpu_feature_name(w, i));
3714 *next = new;
3715 next = &new->next;
3716 }
3717 }
3718 }
3719
3720 object_unref(OBJECT(xc));
3721 }
3722
3723 /* Print all cpuid feature names in featureset
3724 */
3725 static void listflags(GList *features)
3726 {
3727 size_t len = 0;
3728 GList *tmp;
3729
3730 for (tmp = features; tmp; tmp = tmp->next) {
3731 const char *name = tmp->data;
3732 if ((len + strlen(name) + 1) >= 75) {
3733 qemu_printf("\n");
3734 len = 0;
3735 }
3736 qemu_printf("%s%s", len == 0 ? " " : " ", name);
3737 len += strlen(name) + 1;
3738 }
3739 qemu_printf("\n");
3740 }
3741
3742 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
3743 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3744 {
3745 ObjectClass *class_a = (ObjectClass *)a;
3746 ObjectClass *class_b = (ObjectClass *)b;
3747 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3748 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
3749 char *name_a, *name_b;
3750 int ret;
3751
3752 if (cc_a->ordering != cc_b->ordering) {
3753 ret = cc_a->ordering - cc_b->ordering;
3754 } else {
3755 name_a = x86_cpu_class_get_model_name(cc_a);
3756 name_b = x86_cpu_class_get_model_name(cc_b);
3757 ret = strcmp(name_a, name_b);
3758 g_free(name_a);
3759 g_free(name_b);
3760 }
3761 return ret;
3762 }
3763
3764 static GSList *get_sorted_cpu_model_list(void)
3765 {
3766 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3767 list = g_slist_sort(list, x86_cpu_list_compare);
3768 return list;
3769 }
3770
3771 static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3772 {
3773 ObjectClass *oc = data;
3774 X86CPUClass *cc = X86_CPU_CLASS(oc);
3775 char *name = x86_cpu_class_get_model_name(cc);
3776 const char *desc = cc->model_description;
3777 if (!desc && cc->cpu_def) {
3778 desc = cc->cpu_def->model_id;
3779 }
3780
3781 qemu_printf("x86 %-20s %-48s\n", name, desc);
3782 g_free(name);
3783 }
3784
3785 /* list available CPU models and flags */
3786 void x86_cpu_list(void)
3787 {
3788 int i, j;
3789 GSList *list;
3790 GList *names = NULL;
3791
3792 qemu_printf("Available CPUs:\n");
3793 list = get_sorted_cpu_model_list();
3794 g_slist_foreach(list, x86_cpu_list_entry, NULL);
3795 g_slist_free(list);
3796
3797 names = NULL;
3798 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3799 FeatureWordInfo *fw = &feature_word_info[i];
3800 for (j = 0; j < 32; j++) {
3801 if (fw->feat_names[j]) {
3802 names = g_list_append(names, (gpointer)fw->feat_names[j]);
3803 }
3804 }
3805 }
3806
3807 names = g_list_sort(names, (GCompareFunc)strcmp);
3808
3809 qemu_printf("\nRecognized CPUID flags:\n");
3810 listflags(names);
3811 qemu_printf("\n");
3812 g_list_free(names);
3813 }
3814
3815 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3816 {
3817 ObjectClass *oc = data;
3818 X86CPUClass *cc = X86_CPU_CLASS(oc);
3819 CpuDefinitionInfoList **cpu_list = user_data;
3820 CpuDefinitionInfoList *entry;
3821 CpuDefinitionInfo *info;
3822
3823 info = g_malloc0(sizeof(*info));
3824 info->name = x86_cpu_class_get_model_name(cc);
3825 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3826 info->has_unavailable_features = true;
3827 info->q_typename = g_strdup(object_class_get_name(oc));
3828 info->migration_safe = cc->migration_safe;
3829 info->has_migration_safe = true;
3830 info->q_static = cc->static_model;
3831
3832 entry = g_malloc0(sizeof(*entry));
3833 entry->value = info;
3834 entry->next = *cpu_list;
3835 *cpu_list = entry;
3836 }
3837
3838 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
3839 {
3840 CpuDefinitionInfoList *cpu_list = NULL;
3841 GSList *list = get_sorted_cpu_model_list();
3842 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3843 g_slist_free(list);
3844 return cpu_list;
3845 }
3846
3847 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3848 bool migratable_only)
3849 {
3850 FeatureWordInfo *wi = &feature_word_info[w];
3851 uint32_t r = 0;
3852
3853 if (kvm_enabled()) {
3854 switch (wi->type) {
3855 case CPUID_FEATURE_WORD:
3856 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
3857 wi->cpuid.ecx,
3858 wi->cpuid.reg);
3859 break;
3860 case MSR_FEATURE_WORD:
3861 r = kvm_arch_get_supported_msr_feature(kvm_state,
3862 wi->msr.index);
3863 break;
3864 }
3865 } else if (hvf_enabled()) {
3866 if (wi->type != CPUID_FEATURE_WORD) {
3867 return 0;
3868 }
3869 r = hvf_get_supported_cpuid(wi->cpuid.eax,
3870 wi->cpuid.ecx,
3871 wi->cpuid.reg);
3872 } else if (tcg_enabled()) {
3873 r = wi->tcg_features;
3874 } else {
3875 return ~0;
3876 }
3877 if (migratable_only) {
3878 r &= x86_cpu_get_migratable_flags(w);
3879 }
3880 return r;
3881 }
3882
3883 static void x86_cpu_report_filtered_features(X86CPU *cpu)
3884 {
3885 FeatureWord w;
3886
3887 for (w = 0; w < FEATURE_WORDS; w++) {
3888 report_unavailable_features(w, cpu->filtered_features[w]);
3889 }
3890 }
3891
3892 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3893 {
3894 PropValue *pv;
3895 for (pv = props; pv->prop; pv++) {
3896 if (!pv->value) {
3897 continue;
3898 }
3899 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3900 &error_abort);
3901 }
3902 }
3903
3904 /* Load data from X86CPUDefinition into a X86CPU object
3905 */
3906 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
3907 {
3908 CPUX86State *env = &cpu->env;
3909 const char *vendor;
3910 char host_vendor[CPUID_VENDOR_SZ + 1];
3911 FeatureWord w;
3912
3913 /*NOTE: any property set by this function should be returned by
3914 * x86_cpu_static_props(), so static expansion of
3915 * query-cpu-model-expansion is always complete.
3916 */
3917
3918 /* CPU models only set _minimum_ values for level/xlevel: */
3919 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3920 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
3921
3922 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3923 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3924 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
3925 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
3926 for (w = 0; w < FEATURE_WORDS; w++) {
3927 env->features[w] = def->features[w];
3928 }
3929
3930 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3931 cpu->legacy_cache = !def->cache_info;
3932
3933 /* Special cases not set in the X86CPUDefinition structs: */
3934 /* TODO: in-kernel irqchip for hvf */
3935 if (kvm_enabled()) {
3936 if (!kvm_irqchip_in_kernel()) {
3937 x86_cpu_change_kvm_default("x2apic", "off");
3938 }
3939
3940 x86_cpu_apply_props(cpu, kvm_default_props);
3941 } else if (tcg_enabled()) {
3942 x86_cpu_apply_props(cpu, tcg_default_props);
3943 }
3944
3945 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
3946
3947 /* sysenter isn't supported in compatibility mode on AMD,
3948 * syscall isn't supported in compatibility mode on Intel.
3949 * Normally we advertise the actual CPU vendor, but you can
3950 * override this using the 'vendor' property if you want to use
3951 * KVM's sysenter/syscall emulation in compatibility mode and
3952 * when doing cross vendor migration
3953 */
3954 vendor = def->vendor;
3955 if (accel_uses_host_cpuid()) {
3956 uint32_t ebx = 0, ecx = 0, edx = 0;
3957 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3958 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3959 vendor = host_vendor;
3960 }
3961
3962 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3963
3964 }
3965
3966 #ifndef CONFIG_USER_ONLY
3967 /* Return a QDict containing keys for all properties that can be included
3968 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3969 * must be included in the dictionary.
3970 */
3971 static QDict *x86_cpu_static_props(void)
3972 {
3973 FeatureWord w;
3974 int i;
3975 static const char *props[] = {
3976 "min-level",
3977 "min-xlevel",
3978 "family",
3979 "model",
3980 "stepping",
3981 "model-id",
3982 "vendor",
3983 "lmce",
3984 NULL,
3985 };
3986 static QDict *d;
3987
3988 if (d) {
3989 return d;
3990 }
3991
3992 d = qdict_new();
3993 for (i = 0; props[i]; i++) {
3994 qdict_put_null(d, props[i]);
3995 }
3996
3997 for (w = 0; w < FEATURE_WORDS; w++) {
3998 FeatureWordInfo *fi = &feature_word_info[w];
3999 int bit;
4000 for (bit = 0; bit < 32; bit++) {
4001 if (!fi->feat_names[bit]) {
4002 continue;
4003 }
4004 qdict_put_null(d, fi->feat_names[bit]);
4005 }
4006 }
4007
4008 return d;
4009 }
4010
4011 /* Add an entry to @props dict, with the value for property. */
4012 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
4013 {
4014 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
4015 &error_abort);
4016
4017 qdict_put_obj(props, prop, value);
4018 }
4019
4020 /* Convert CPU model data from X86CPU object to a property dictionary
4021 * that can recreate exactly the same CPU model.
4022 */
4023 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
4024 {
4025 QDict *sprops = x86_cpu_static_props();
4026 const QDictEntry *e;
4027
4028 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
4029 const char *prop = qdict_entry_key(e);
4030 x86_cpu_expand_prop(cpu, props, prop);
4031 }
4032 }
4033
4034 /* Convert CPU model data from X86CPU object to a property dictionary
4035 * that can recreate exactly the same CPU model, including every
4036 * writeable QOM property.
4037 */
4038 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
4039 {
4040 ObjectPropertyIterator iter;
4041 ObjectProperty *prop;
4042
4043 object_property_iter_init(&iter, OBJECT(cpu));
4044 while ((prop = object_property_iter_next(&iter))) {
4045 /* skip read-only or write-only properties */
4046 if (!prop->get || !prop->set) {
4047 continue;
4048 }
4049
4050 /* "hotplugged" is the only property that is configurable
4051 * on the command-line but will be set differently on CPUs
4052 * created using "-cpu ... -smp ..." and by CPUs created
4053 * on the fly by x86_cpu_from_model() for querying. Skip it.
4054 */
4055 if (!strcmp(prop->name, "hotplugged")) {
4056 continue;
4057 }
4058 x86_cpu_expand_prop(cpu, props, prop->name);
4059 }
4060 }
4061
4062 static void object_apply_props(Object *obj, QDict *props, Error **errp)
4063 {
4064 const QDictEntry *prop;
4065 Error *err = NULL;
4066
4067 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
4068 object_property_set_qobject(obj, qdict_entry_value(prop),
4069 qdict_entry_key(prop), &err);
4070 if (err) {
4071 break;
4072 }
4073 }
4074
4075 error_propagate(errp, err);
4076 }
4077
4078 /* Create X86CPU object according to model+props specification */
4079 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
4080 {
4081 X86CPU *xc = NULL;
4082 X86CPUClass *xcc;
4083 Error *err = NULL;
4084
4085 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
4086 if (xcc == NULL) {
4087 error_setg(&err, "CPU model '%s' not found", model);
4088 goto out;
4089 }
4090
4091 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
4092 if (props) {
4093 object_apply_props(OBJECT(xc), props, &err);
4094 if (err) {
4095 goto out;
4096 }
4097 }
4098
4099 x86_cpu_expand_features(xc, &err);
4100 if (err) {
4101 goto out;
4102 }
4103
4104 out:
4105 if (err) {
4106 error_propagate(errp, err);
4107 object_unref(OBJECT(xc));
4108 xc = NULL;
4109 }
4110 return xc;
4111 }
4112
4113 CpuModelExpansionInfo *
4114 qmp_query_cpu_model_expansion(CpuModelExpansionType type,
4115 CpuModelInfo *model,
4116 Error **errp)
4117 {
4118 X86CPU *xc = NULL;
4119 Error *err = NULL;
4120 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
4121 QDict *props = NULL;
4122 const char *base_name;
4123
4124 xc = x86_cpu_from_model(model->name,
4125 model->has_props ?
4126 qobject_to(QDict, model->props) :
4127 NULL, &err);
4128 if (err) {
4129 goto out;
4130 }
4131
4132 props = qdict_new();
4133 ret->model = g_new0(CpuModelInfo, 1);
4134 ret->model->props = QOBJECT(props);
4135 ret->model->has_props = true;
4136
4137 switch (type) {
4138 case CPU_MODEL_EXPANSION_TYPE_STATIC:
4139 /* Static expansion will be based on "base" only */
4140 base_name = "base";
4141 x86_cpu_to_dict(xc, props);
4142 break;
4143 case CPU_MODEL_EXPANSION_TYPE_FULL:
4144 /* As we don't return every single property, full expansion needs
4145 * to keep the original model name+props, and add extra
4146 * properties on top of that.
4147 */
4148 base_name = model->name;
4149 x86_cpu_to_dict_full(xc, props);
4150 break;
4151 default:
4152 error_setg(&err, "Unsupported expansion type");
4153 goto out;
4154 }
4155
4156 x86_cpu_to_dict(xc, props);
4157
4158 ret->model->name = g_strdup(base_name);
4159
4160 out:
4161 object_unref(OBJECT(xc));
4162 if (err) {
4163 error_propagate(errp, err);
4164 qapi_free_CpuModelExpansionInfo(ret);
4165 ret = NULL;
4166 }
4167 return ret;
4168 }
4169 #endif /* !CONFIG_USER_ONLY */
4170
4171 static gchar *x86_gdb_arch_name(CPUState *cs)
4172 {
4173 #ifdef TARGET_X86_64
4174 return g_strdup("i386:x86-64");
4175 #else
4176 return g_strdup("i386");
4177 #endif
4178 }
4179
4180 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
4181 {
4182 X86CPUDefinition *cpudef = data;
4183 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4184
4185 xcc->cpu_def = cpudef;
4186 xcc->migration_safe = true;
4187 }
4188
4189 static void x86_register_cpudef_type(X86CPUDefinition *def)
4190 {
4191 char *typename = x86_cpu_type_name(def->name);
4192 TypeInfo ti = {
4193 .name = typename,
4194 .parent = TYPE_X86_CPU,
4195 .class_init = x86_cpu_cpudef_class_init,
4196 .class_data = def,
4197 };
4198
4199 /* AMD aliases are handled at runtime based on CPUID vendor, so
4200 * they shouldn't be set on the CPU model table.
4201 */
4202 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
4203 /* catch mistakes instead of silently truncating model_id when too long */
4204 assert(def->model_id && strlen(def->model_id) <= 48);
4205
4206
4207 type_register(&ti);
4208 g_free(typename);
4209 }
4210
4211 #if !defined(CONFIG_USER_ONLY)
4212
4213 void cpu_clear_apic_feature(CPUX86State *env)
4214 {
4215 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
4216 }
4217
4218 #endif /* !CONFIG_USER_ONLY */
4219
4220 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
4221 uint32_t *eax, uint32_t *ebx,
4222 uint32_t *ecx, uint32_t *edx)
4223 {
4224 X86CPU *cpu = x86_env_get_cpu(env);
4225 CPUState *cs = CPU(cpu);
4226 uint32_t pkg_offset;
4227 uint32_t limit;
4228 uint32_t signature[3];
4229
4230 /* Calculate & apply limits for different index ranges */
4231 if (index >= 0xC0000000) {
4232 limit = env->cpuid_xlevel2;
4233 } else if (index >= 0x80000000) {
4234 limit = env->cpuid_xlevel;
4235 } else if (index >= 0x40000000) {
4236 limit = 0x40000001;
4237 } else {
4238 limit = env->cpuid_level;
4239 }
4240
4241 if (index > limit) {
4242 /* Intel documentation states that invalid EAX input will
4243 * return the same information as EAX=cpuid_level
4244 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4245 */
4246 index = env->cpuid_level;
4247 }
4248
4249 switch(index) {
4250 case 0:
4251 *eax = env->cpuid_level;
4252 *ebx = env->cpuid_vendor1;
4253 *edx = env->cpuid_vendor2;
4254 *ecx = env->cpuid_vendor3;
4255 break;
4256 case 1:
4257 *eax = env->cpuid_version;
4258 *ebx = (cpu->apic_id << 24) |
4259 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
4260 *ecx = env->features[FEAT_1_ECX];
4261 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
4262 *ecx |= CPUID_EXT_OSXSAVE;
4263 }
4264 *edx = env->features[FEAT_1_EDX];
4265 if (cs->nr_cores * cs->nr_threads > 1) {
4266 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
4267 *edx |= CPUID_HT;
4268 }
4269 break;
4270 case 2:
4271 /* cache info: needed for Pentium Pro compatibility */
4272 if (cpu->cache_info_passthrough) {
4273 host_cpuid(index, 0, eax, ebx, ecx, edx);
4274 break;
4275 }
4276 *eax = 1; /* Number of CPUID[EAX=2] calls required */
4277 *ebx = 0;
4278 if (!cpu->enable_l3_cache) {
4279 *ecx = 0;
4280 } else {
4281 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
4282 }
4283 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
4284 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
4285 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
4286 break;
4287 case 4:
4288 /* cache info: needed for Core compatibility */
4289 if (cpu->cache_info_passthrough) {
4290 host_cpuid(index, count, eax, ebx, ecx, edx);
4291 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
4292 *eax &= ~0xFC000000;
4293 if ((*eax & 31) && cs->nr_cores > 1) {
4294 *eax |= (cs->nr_cores - 1) << 26;
4295 }
4296 } else {
4297 *eax = 0;
4298 switch (count) {
4299 case 0: /* L1 dcache info */
4300 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
4301 1, cs->nr_cores,
4302 eax, ebx, ecx, edx);
4303 break;
4304 case 1: /* L1 icache info */
4305 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
4306 1, cs->nr_cores,
4307 eax, ebx, ecx, edx);
4308 break;
4309 case 2: /* L2 cache info */
4310 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
4311 cs->nr_threads, cs->nr_cores,
4312 eax, ebx, ecx, edx);
4313 break;
4314 case 3: /* L3 cache info */
4315 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4316 if (cpu->enable_l3_cache) {
4317 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
4318 (1 << pkg_offset), cs->nr_cores,
4319 eax, ebx, ecx, edx);
4320 break;
4321 }
4322 /* fall through */
4323 default: /* end of info */
4324 *eax = *ebx = *ecx = *edx = 0;
4325 break;
4326 }
4327 }
4328 break;
4329 case 5:
4330 /* MONITOR/MWAIT Leaf */
4331 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
4332 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
4333 *ecx = cpu->mwait.ecx; /* flags */
4334 *edx = cpu->mwait.edx; /* mwait substates */
4335 break;
4336 case 6:
4337 /* Thermal and Power Leaf */
4338 *eax = env->features[FEAT_6_EAX];
4339 *ebx = 0;
4340 *ecx = 0;
4341 *edx = 0;
4342 break;
4343 case 7:
4344 /* Structured Extended Feature Flags Enumeration Leaf */
4345 if (count == 0) {
4346 *eax = 0; /* Maximum ECX value for sub-leaves */
4347 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
4348 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
4349 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
4350 *ecx |= CPUID_7_0_ECX_OSPKE;
4351 }
4352 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
4353 } else {
4354 *eax = 0;
4355 *ebx = 0;
4356 *ecx = 0;
4357 *edx = 0;
4358 }
4359 break;
4360 case 9:
4361 /* Direct Cache Access Information Leaf */
4362 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
4363 *ebx = 0;
4364 *ecx = 0;
4365 *edx = 0;
4366 break;
4367 case 0xA:
4368 /* Architectural Performance Monitoring Leaf */
4369 if (kvm_enabled() && cpu->enable_pmu) {
4370 KVMState *s = cs->kvm_state;
4371
4372 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
4373 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
4374 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
4375 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
4376 } else if (hvf_enabled() && cpu->enable_pmu) {
4377 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
4378 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
4379 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
4380 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
4381 } else {
4382 *eax = 0;
4383 *ebx = 0;
4384 *ecx = 0;
4385 *edx = 0;
4386 }
4387 break;
4388 case 0xB:
4389 /* Extended Topology Enumeration Leaf */
4390 if (!cpu->enable_cpuid_0xb) {
4391 *eax = *ebx = *ecx = *edx = 0;
4392 break;
4393 }
4394
4395 *ecx = count & 0xff;
4396 *edx = cpu->apic_id;
4397
4398 switch (count) {
4399 case 0:
4400 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
4401 *ebx = cs->nr_threads;
4402 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
4403 break;
4404 case 1:
4405 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4406 *ebx = cs->nr_cores * cs->nr_threads;
4407 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4408 break;
4409 default:
4410 *eax = 0;
4411 *ebx = 0;
4412 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4413 }
4414
4415 assert(!(*eax & ~0x1f));
4416 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4417 break;
4418 case 0xD: {
4419 /* Processor Extended State */
4420 *eax = 0;
4421 *ebx = 0;
4422 *ecx = 0;
4423 *edx = 0;
4424 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4425 break;
4426 }
4427
4428 if (count == 0) {
4429 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
4430 *eax = env->features[FEAT_XSAVE_COMP_LO];
4431 *edx = env->features[FEAT_XSAVE_COMP_HI];
4432 *ebx = xsave_area_size(env->xcr0);
4433 } else if (count == 1) {
4434 *eax = env->features[FEAT_XSAVE];
4435 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
4436 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
4437 const ExtSaveArea *esa = &x86_ext_save_areas[count];
4438 *eax = esa->size;
4439 *ebx = esa->offset;
4440 }
4441 }
4442 break;
4443 }
4444 case 0x14: {
4445 /* Intel Processor Trace Enumeration */
4446 *eax = 0;
4447 *ebx = 0;
4448 *ecx = 0;
4449 *edx = 0;
4450 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
4451 !kvm_enabled()) {
4452 break;
4453 }
4454
4455 if (count == 0) {
4456 *eax = INTEL_PT_MAX_SUBLEAF;
4457 *ebx = INTEL_PT_MINIMAL_EBX;
4458 *ecx = INTEL_PT_MINIMAL_ECX;
4459 } else if (count == 1) {
4460 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
4461 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
4462 }
4463 break;
4464 }
4465 case 0x40000000:
4466 /*
4467 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4468 * set here, but we restrict to TCG none the less.
4469 */
4470 if (tcg_enabled() && cpu->expose_tcg) {
4471 memcpy(signature, "TCGTCGTCGTCG", 12);
4472 *eax = 0x40000001;
4473 *ebx = signature[0];
4474 *ecx = signature[1];
4475 *edx = signature[2];
4476 } else {
4477 *eax = 0;
4478 *ebx = 0;
4479 *ecx = 0;
4480 *edx = 0;
4481 }
4482 break;
4483 case 0x40000001:
4484 *eax = 0;
4485 *ebx = 0;
4486 *ecx = 0;
4487 *edx = 0;
4488 break;
4489 case 0x80000000:
4490 *eax = env->cpuid_xlevel;
4491 *ebx = env->cpuid_vendor1;
4492 *edx = env->cpuid_vendor2;
4493 *ecx = env->cpuid_vendor3;
4494 break;
4495 case 0x80000001:
4496 *eax = env->cpuid_version;
4497 *ebx = 0;
4498 *ecx = env->features[FEAT_8000_0001_ECX];
4499 *edx = env->features[FEAT_8000_0001_EDX];
4500
4501 /* The Linux kernel checks for the CMPLegacy bit and
4502 * discards multiple thread information if it is set.
4503 * So don't set it here for Intel to make Linux guests happy.
4504 */
4505 if (cs->nr_cores * cs->nr_threads > 1) {
4506 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
4507 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
4508 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
4509 *ecx |= 1 << 1; /* CmpLegacy bit */
4510 }
4511 }
4512 break;
4513 case 0x80000002:
4514 case 0x80000003:
4515 case 0x80000004:
4516 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
4517 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
4518 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
4519 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
4520 break;
4521 case 0x80000005:
4522 /* cache info (L1 cache) */
4523 if (cpu->cache_info_passthrough) {
4524 host_cpuid(index, 0, eax, ebx, ecx, edx);
4525 break;
4526 }
4527 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4528 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4529 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4530 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
4531 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
4532 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
4533 break;
4534 case 0x80000006:
4535 /* cache info (L2 cache) */
4536 if (cpu->cache_info_passthrough) {
4537 host_cpuid(index, 0, eax, ebx, ecx, edx);
4538 break;
4539 }
4540 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4541 (L2_DTLB_2M_ENTRIES << 16) | \
4542 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4543 (L2_ITLB_2M_ENTRIES);
4544 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4545 (L2_DTLB_4K_ENTRIES << 16) | \
4546 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4547 (L2_ITLB_4K_ENTRIES);
4548 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
4549 cpu->enable_l3_cache ?
4550 env->cache_info_amd.l3_cache : NULL,
4551 ecx, edx);
4552 break;
4553 case 0x80000007:
4554 *eax = 0;
4555 *ebx = 0;
4556 *ecx = 0;
4557 *edx = env->features[FEAT_8000_0007_EDX];
4558 break;
4559 case 0x80000008:
4560 /* virtual & phys address size in low 2 bytes. */
4561 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
4562 /* 64 bit processor */
4563 *eax = cpu->phys_bits; /* configurable physical bits */
4564 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
4565 *eax |= 0x00003900; /* 57 bits virtual */
4566 } else {
4567 *eax |= 0x00003000; /* 48 bits virtual */
4568 }
4569 } else {
4570 *eax = cpu->phys_bits;
4571 }
4572 *ebx = env->features[FEAT_8000_0008_EBX];
4573 *ecx = 0;
4574 *edx = 0;
4575 if (cs->nr_cores * cs->nr_threads > 1) {
4576 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
4577 }
4578 break;
4579 case 0x8000000A:
4580 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
4581 *eax = 0x00000001; /* SVM Revision */
4582 *ebx = 0x00000010; /* nr of ASIDs */
4583 *ecx = 0;
4584 *edx = env->features[FEAT_SVM]; /* optional features */
4585 } else {
4586 *eax = 0;
4587 *ebx = 0;
4588 *ecx = 0;
4589 *edx = 0;
4590 }
4591 break;
4592 case 0x8000001D:
4593 *eax = 0;
4594 switch (count) {
4595 case 0: /* L1 dcache info */
4596 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
4597 eax, ebx, ecx, edx);
4598 break;
4599 case 1: /* L1 icache info */
4600 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
4601 eax, ebx, ecx, edx);
4602 break;
4603 case 2: /* L2 cache info */
4604 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
4605 eax, ebx, ecx, edx);
4606 break;
4607 case 3: /* L3 cache info */
4608 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
4609 eax, ebx, ecx, edx);
4610 break;
4611 default: /* end of info */
4612 *eax = *ebx = *ecx = *edx = 0;
4613 break;
4614 }
4615 break;
4616 case 0x8000001E:
4617 assert(cpu->core_id <= 255);
4618 encode_topo_cpuid8000001e(cs, cpu,
4619 eax, ebx, ecx, edx);
4620 break;
4621 case 0xC0000000:
4622 *eax = env->cpuid_xlevel2;
4623 *ebx = 0;
4624 *ecx = 0;
4625 *edx = 0;
4626 break;
4627 case 0xC0000001:
4628 /* Support for VIA CPU's CPUID instruction */
4629 *eax = env->cpuid_version;
4630 *ebx = 0;
4631 *ecx = 0;
4632 *edx = env->features[FEAT_C000_0001_EDX];
4633 break;
4634 case 0xC0000002:
4635 case 0xC0000003:
4636 case 0xC0000004:
4637 /* Reserved for the future, and now filled with zero */
4638 *eax = 0;
4639 *ebx = 0;
4640 *ecx = 0;
4641 *edx = 0;
4642 break;
4643 case 0x8000001F:
4644 *eax = sev_enabled() ? 0x2 : 0;
4645 *ebx = sev_get_cbit_position();
4646 *ebx |= sev_get_reduced_phys_bits() << 6;
4647 *ecx = 0;
4648 *edx = 0;
4649 break;
4650 default:
4651 /* reserved values: zero */
4652 *eax = 0;
4653 *ebx = 0;
4654 *ecx = 0;
4655 *edx = 0;
4656 break;
4657 }
4658 }
4659
4660 /* CPUClass::reset() */
4661 static void x86_cpu_reset(CPUState *s)
4662 {
4663 X86CPU *cpu = X86_CPU(s);
4664 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
4665 CPUX86State *env = &cpu->env;
4666 target_ulong cr4;
4667 uint64_t xcr0;
4668 int i;
4669
4670 xcc->parent_reset(s);
4671
4672 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
4673
4674 env->old_exception = -1;
4675
4676 /* init to reset state */
4677
4678 env->hflags2 |= HF2_GIF_MASK;
4679
4680 cpu_x86_update_cr0(env, 0x60000010);
4681 env->a20_mask = ~0x0;
4682 env->smbase = 0x30000;
4683 env->msr_smi_count = 0;
4684
4685 env->idt.limit = 0xffff;
4686 env->gdt.limit = 0xffff;
4687 env->ldt.limit = 0xffff;
4688 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4689 env->tr.limit = 0xffff;
4690 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4691
4692 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4693 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4694 DESC_R_MASK | DESC_A_MASK);
4695 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4696 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4697 DESC_A_MASK);
4698 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4699 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4700 DESC_A_MASK);
4701 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4702 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4703 DESC_A_MASK);
4704 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4705 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4706 DESC_A_MASK);
4707 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4708 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4709 DESC_A_MASK);
4710
4711 env->eip = 0xfff0;
4712 env->regs[R_EDX] = env->cpuid_version;
4713
4714 env->eflags = 0x2;
4715
4716 /* FPU init */
4717 for (i = 0; i < 8; i++) {
4718 env->fptags[i] = 1;
4719 }
4720 cpu_set_fpuc(env, 0x37f);
4721
4722 env->mxcsr = 0x1f80;
4723 /* All units are in INIT state. */
4724 env->xstate_bv = 0;
4725
4726 env->pat = 0x0007040600070406ULL;
4727 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4728
4729 memset(env->dr, 0, sizeof(env->dr));
4730 env->dr[6] = DR6_FIXED_1;
4731 env->dr[7] = DR7_FIXED_1;
4732 cpu_breakpoint_remove_all(s, BP_CPU);
4733 cpu_watchpoint_remove_all(s, BP_CPU);
4734
4735 cr4 = 0;
4736 xcr0 = XSTATE_FP_MASK;
4737
4738 #ifdef CONFIG_USER_ONLY
4739 /* Enable all the features for user-mode. */
4740 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4741 xcr0 |= XSTATE_SSE_MASK;
4742 }
4743 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4744 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4745 if (env->features[esa->feature] & esa->bits) {
4746 xcr0 |= 1ull << i;
4747 }
4748 }
4749
4750 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4751 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4752 }
4753 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4754 cr4 |= CR4_FSGSBASE_MASK;
4755 }
4756 #endif
4757
4758 env->xcr0 = xcr0;
4759 cpu_x86_update_cr4(env, cr4);
4760
4761 /*
4762 * SDM 11.11.5 requires:
4763 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4764 * - IA32_MTRR_PHYSMASKn.V = 0
4765 * All other bits are undefined. For simplification, zero it all.
4766 */
4767 env->mtrr_deftype = 0;
4768 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4769 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4770
4771 env->interrupt_injected = -1;
4772 env->exception_injected = -1;
4773 env->nmi_injected = false;
4774 #if !defined(CONFIG_USER_ONLY)
4775 /* We hard-wire the BSP to the first CPU. */
4776 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
4777
4778 s->halted = !cpu_is_bsp(cpu);
4779
4780 if (kvm_enabled()) {
4781 kvm_arch_reset_vcpu(cpu);
4782 }
4783 else if (hvf_enabled()) {
4784 hvf_reset_vcpu(s);
4785 }
4786 #endif
4787 }
4788
4789 #ifndef CONFIG_USER_ONLY
4790 bool cpu_is_bsp(X86CPU *cpu)
4791 {
4792 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
4793 }
4794
4795 /* TODO: remove me, when reset over QOM tree is implemented */
4796 static void x86_cpu_machine_reset_cb(void *opaque)
4797 {
4798 X86CPU *cpu = opaque;
4799 cpu_reset(CPU(cpu));
4800 }
4801 #endif
4802
4803 static void mce_init(X86CPU *cpu)
4804 {
4805 CPUX86State *cenv = &cpu->env;
4806 unsigned int bank;
4807
4808 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
4809 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
4810 (CPUID_MCE | CPUID_MCA)) {
4811 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4812 (cpu->enable_lmce ? MCG_LMCE_P : 0);
4813 cenv->mcg_ctl = ~(uint64_t)0;
4814 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4815 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4816 }
4817 }
4818 }
4819
4820 #ifndef CONFIG_USER_ONLY
4821 APICCommonClass *apic_get_class(void)
4822 {
4823 const char *apic_type = "apic";
4824
4825 /* TODO: in-kernel irqchip for hvf */
4826 if (kvm_apic_in_kernel()) {
4827 apic_type = "kvm-apic";
4828 } else if (xen_enabled()) {
4829 apic_type = "xen-apic";
4830 }
4831
4832 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4833 }
4834
4835 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4836 {
4837 APICCommonState *apic;
4838 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4839
4840 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
4841
4842 object_property_add_child(OBJECT(cpu), "lapic",
4843 OBJECT(cpu->apic_state), &error_abort);
4844 object_unref(OBJECT(cpu->apic_state));
4845
4846 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
4847 /* TODO: convert to link<> */
4848 apic = APIC_COMMON(cpu->apic_state);
4849 apic->cpu = cpu;
4850 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
4851 }
4852
4853 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4854 {
4855 APICCommonState *apic;
4856 static bool apic_mmio_map_once;
4857
4858 if (cpu->apic_state == NULL) {
4859 return;
4860 }
4861 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4862 errp);
4863
4864 /* Map APIC MMIO area */
4865 apic = APIC_COMMON(cpu->apic_state);
4866 if (!apic_mmio_map_once) {
4867 memory_region_add_subregion_overlap(get_system_memory(),
4868 apic->apicbase &
4869 MSR_IA32_APICBASE_BASE,
4870 &apic->io_memory,
4871 0x1000);
4872 apic_mmio_map_once = true;
4873 }
4874 }
4875
4876 static void x86_cpu_machine_done(Notifier *n, void *unused)
4877 {
4878 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4879 MemoryRegion *smram =
4880 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4881
4882 if (smram) {
4883 cpu->smram = g_new(MemoryRegion, 1);
4884 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4885 smram, 0, 1ull << 32);
4886 memory_region_set_enabled(cpu->smram, true);
4887 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4888 }
4889 }
4890 #else
4891 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4892 {
4893 }
4894 #endif
4895
4896 /* Note: Only safe for use on x86(-64) hosts */
4897 static uint32_t x86_host_phys_bits(void)
4898 {
4899 uint32_t eax;
4900 uint32_t host_phys_bits;
4901
4902 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4903 if (eax >= 0x80000008) {
4904 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4905 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4906 * at 23:16 that can specify a maximum physical address bits for
4907 * the guest that can override this value; but I've not seen
4908 * anything with that set.
4909 */
4910 host_phys_bits = eax & 0xff;
4911 } else {
4912 /* It's an odd 64 bit machine that doesn't have the leaf for
4913 * physical address bits; fall back to 36 that's most older
4914 * Intel.
4915 */
4916 host_phys_bits = 36;
4917 }
4918
4919 return host_phys_bits;
4920 }
4921
4922 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4923 {
4924 if (*min < value) {
4925 *min = value;
4926 }
4927 }
4928
4929 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4930 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4931 {
4932 CPUX86State *env = &cpu->env;
4933 FeatureWordInfo *fi = &feature_word_info[w];
4934 uint32_t eax = fi->cpuid.eax;
4935 uint32_t region = eax & 0xF0000000;
4936
4937 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
4938 if (!env->features[w]) {
4939 return;
4940 }
4941
4942 switch (region) {
4943 case 0x00000000:
4944 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4945 break;
4946 case 0x80000000:
4947 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4948 break;
4949 case 0xC0000000:
4950 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4951 break;
4952 }
4953 }
4954
4955 /* Calculate XSAVE components based on the configured CPU feature flags */
4956 static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4957 {
4958 CPUX86State *env = &cpu->env;
4959 int i;
4960 uint64_t mask;
4961
4962 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4963 return;
4964 }
4965
4966 mask = 0;
4967 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4968 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4969 if (env->features[esa->feature] & esa->bits) {
4970 mask |= (1ULL << i);
4971 }
4972 }
4973
4974 env->features[FEAT_XSAVE_COMP_LO] = mask;
4975 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
4976 }
4977
4978 /***** Steps involved on loading and filtering CPUID data
4979 *
4980 * When initializing and realizing a CPU object, the steps
4981 * involved in setting up CPUID data are:
4982 *
4983 * 1) Loading CPU model definition (X86CPUDefinition). This is
4984 * implemented by x86_cpu_load_def() and should be completely
4985 * transparent, as it is done automatically by instance_init.
4986 * No code should need to look at X86CPUDefinition structs
4987 * outside instance_init.
4988 *
4989 * 2) CPU expansion. This is done by realize before CPUID
4990 * filtering, and will make sure host/accelerator data is
4991 * loaded for CPU models that depend on host capabilities
4992 * (e.g. "host"). Done by x86_cpu_expand_features().
4993 *
4994 * 3) CPUID filtering. This initializes extra data related to
4995 * CPUID, and checks if the host supports all capabilities
4996 * required by the CPU. Runnability of a CPU model is
4997 * determined at this step. Done by x86_cpu_filter_features().
4998 *
4999 * Some operations don't require all steps to be performed.
5000 * More precisely:
5001 *
5002 * - CPU instance creation (instance_init) will run only CPU
5003 * model loading. CPU expansion can't run at instance_init-time
5004 * because host/accelerator data may be not available yet.
5005 * - CPU realization will perform both CPU model expansion and CPUID
5006 * filtering, and return an error in case one of them fails.
5007 * - query-cpu-definitions needs to run all 3 steps. It needs
5008 * to run CPUID filtering, as the 'unavailable-features'
5009 * field is set based on the filtering results.
5010 * - The query-cpu-model-expansion QMP command only needs to run
5011 * CPU model loading and CPU expansion. It should not filter
5012 * any CPUID data based on host capabilities.
5013 */
5014
5015 /* Expand CPU configuration data, based on configured features
5016 * and host/accelerator capabilities when appropriate.
5017 */
5018 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
5019 {
5020 CPUX86State *env = &cpu->env;
5021 FeatureWord w;
5022 GList *l;
5023 Error *local_err = NULL;
5024
5025 /*TODO: Now cpu->max_features doesn't overwrite features
5026 * set using QOM properties, and we can convert
5027 * plus_features & minus_features to global properties
5028 * inside x86_cpu_parse_featurestr() too.
5029 */
5030 if (cpu->max_features) {
5031 for (w = 0; w < FEATURE_WORDS; w++) {
5032 /* Override only features that weren't set explicitly
5033 * by the user.
5034 */
5035 env->features[w] |=
5036 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
5037 ~env->user_features[w] & \
5038 ~feature_word_info[w].no_autoenable_flags;
5039 }
5040 }
5041
5042 for (l = plus_features; l; l = l->next) {
5043 const char *prop = l->data;
5044 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
5045 if (local_err) {
5046 goto out;
5047 }
5048 }
5049
5050 for (l = minus_features; l; l = l->next) {
5051 const char *prop = l->data;
5052 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
5053 if (local_err) {
5054 goto out;
5055 }
5056 }
5057
5058 if (!kvm_enabled() || !cpu->expose_kvm) {
5059 env->features[FEAT_KVM] = 0;
5060 }
5061
5062 x86_cpu_enable_xsave_components(cpu);
5063
5064 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
5065 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
5066 if (cpu->full_cpuid_auto_level) {
5067 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
5068 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
5069 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
5070 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
5071 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
5072 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
5073 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
5074 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
5075 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
5076 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
5077 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
5078
5079 /* Intel Processor Trace requires CPUID[0x14] */
5080 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5081 kvm_enabled() && cpu->intel_pt_auto_level) {
5082 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
5083 }
5084
5085 /* SVM requires CPUID[0x8000000A] */
5086 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5087 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
5088 }
5089
5090 /* SEV requires CPUID[0x8000001F] */
5091 if (sev_enabled()) {
5092 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
5093 }
5094 }
5095
5096 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
5097 if (env->cpuid_level == UINT32_MAX) {
5098 env->cpuid_level = env->cpuid_min_level;
5099 }
5100 if (env->cpuid_xlevel == UINT32_MAX) {
5101 env->cpuid_xlevel = env->cpuid_min_xlevel;
5102 }
5103 if (env->cpuid_xlevel2 == UINT32_MAX) {
5104 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
5105 }
5106
5107 out:
5108 if (local_err != NULL) {
5109 error_propagate(errp, local_err);
5110 }
5111 }
5112
5113 /*
5114 * Finishes initialization of CPUID data, filters CPU feature
5115 * words based on host availability of each feature.
5116 *
5117 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
5118 */
5119 static int x86_cpu_filter_features(X86CPU *cpu)
5120 {
5121 CPUX86State *env = &cpu->env;
5122 FeatureWord w;
5123 int rv = 0;
5124
5125 for (w = 0; w < FEATURE_WORDS; w++) {
5126 uint32_t host_feat =
5127 x86_cpu_get_supported_feature_word(w, false);
5128 uint32_t requested_features = env->features[w];
5129 env->features[w] &= host_feat;
5130 cpu->filtered_features[w] = requested_features & ~env->features[w];
5131 if (cpu->filtered_features[w]) {
5132 rv = 1;
5133 }
5134 }
5135
5136 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5137 kvm_enabled()) {
5138 KVMState *s = CPU(cpu)->kvm_state;
5139 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
5140 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
5141 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
5142 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
5143 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
5144
5145 if (!eax_0 ||
5146 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
5147 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
5148 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
5149 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
5150 INTEL_PT_ADDR_RANGES_NUM) ||
5151 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
5152 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
5153 (ecx_0 & INTEL_PT_IP_LIP)) {
5154 /*
5155 * Processor Trace capabilities aren't configurable, so if the
5156 * host can't emulate the capabilities we report on
5157 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
5158 */
5159 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
5160 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
5161 rv = 1;
5162 }
5163 }
5164
5165 return rv;
5166 }
5167
5168 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
5169 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
5170 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
5171 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
5172 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
5173 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
5174 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
5175 {
5176 CPUState *cs = CPU(dev);
5177 X86CPU *cpu = X86_CPU(dev);
5178 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5179 CPUX86State *env = &cpu->env;
5180 Error *local_err = NULL;
5181 static bool ht_warned;
5182
5183 if (xcc->host_cpuid_required) {
5184 if (!accel_uses_host_cpuid()) {
5185 char *name = x86_cpu_class_get_model_name(xcc);
5186 error_setg(&local_err, "CPU model '%s' requires KVM", name);
5187 g_free(name);
5188 goto out;
5189 }
5190
5191 if (enable_cpu_pm) {
5192 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
5193 &cpu->mwait.ecx, &cpu->mwait.edx);
5194 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
5195 }
5196 }
5197
5198 /* mwait extended info: needed for Core compatibility */
5199 /* We always wake on interrupt even if host does not have the capability */
5200 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
5201
5202 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
5203 error_setg(errp, "apic-id property was not initialized properly");
5204 return;
5205 }
5206
5207 x86_cpu_expand_features(cpu, &local_err);
5208 if (local_err) {
5209 goto out;
5210 }
5211
5212 if (x86_cpu_filter_features(cpu) &&
5213 (cpu->check_cpuid || cpu->enforce_cpuid)) {
5214 x86_cpu_report_filtered_features(cpu);
5215 if (cpu->enforce_cpuid) {
5216 error_setg(&local_err,
5217 accel_uses_host_cpuid() ?
5218 "Host doesn't support requested features" :
5219 "TCG doesn't support requested features");
5220 goto out;
5221 }
5222 }
5223
5224 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5225 * CPUID[1].EDX.
5226 */
5227 if (IS_AMD_CPU(env)) {
5228 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
5229 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
5230 & CPUID_EXT2_AMD_ALIASES);
5231 }
5232
5233 /* For 64bit systems think about the number of physical bits to present.
5234 * ideally this should be the same as the host; anything other than matching
5235 * the host can cause incorrect guest behaviour.
5236 * QEMU used to pick the magic value of 40 bits that corresponds to
5237 * consumer AMD devices but nothing else.
5238 */
5239 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
5240 if (accel_uses_host_cpuid()) {
5241 uint32_t host_phys_bits = x86_host_phys_bits();
5242 static bool warned;
5243
5244 if (cpu->host_phys_bits) {
5245 /* The user asked for us to use the host physical bits */
5246 cpu->phys_bits = host_phys_bits;
5247 if (cpu->host_phys_bits_limit &&
5248 cpu->phys_bits > cpu->host_phys_bits_limit) {
5249 cpu->phys_bits = cpu->host_phys_bits_limit;
5250 }
5251 }
5252
5253 /* Print a warning if the user set it to a value that's not the
5254 * host value.
5255 */
5256 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
5257 !warned) {
5258 warn_report("Host physical bits (%u)"
5259 " does not match phys-bits property (%u)",
5260 host_phys_bits, cpu->phys_bits);
5261 warned = true;
5262 }
5263
5264 if (cpu->phys_bits &&
5265 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
5266 cpu->phys_bits < 32)) {
5267 error_setg(errp, "phys-bits should be between 32 and %u "
5268 " (but is %u)",
5269 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
5270 return;
5271 }
5272 } else {
5273 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
5274 error_setg(errp, "TCG only supports phys-bits=%u",
5275 TCG_PHYS_ADDR_BITS);
5276 return;
5277 }
5278 }
5279 /* 0 means it was not explicitly set by the user (or by machine
5280 * compat_props or by the host code above). In this case, the default
5281 * is the value used by TCG (40).
5282 */
5283 if (cpu->phys_bits == 0) {
5284 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
5285 }
5286 } else {
5287 /* For 32 bit systems don't use the user set value, but keep
5288 * phys_bits consistent with what we tell the guest.
5289 */
5290 if (cpu->phys_bits != 0) {
5291 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
5292 return;
5293 }
5294
5295 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
5296 cpu->phys_bits = 36;
5297 } else {
5298 cpu->phys_bits = 32;
5299 }
5300 }
5301
5302 /* Cache information initialization */
5303 if (!cpu->legacy_cache) {
5304 if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
5305 char *name = x86_cpu_class_get_model_name(xcc);
5306 error_setg(errp,
5307 "CPU model '%s' doesn't support legacy-cache=off", name);
5308 g_free(name);
5309 return;
5310 }
5311 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
5312 *xcc->cpu_def->cache_info;
5313 } else {
5314 /* Build legacy cache information */
5315 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
5316 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
5317 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
5318 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
5319
5320 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
5321 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
5322 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
5323 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
5324
5325 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
5326 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
5327 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
5328 env->cache_info_amd.l3_cache = &legacy_l3_cache;
5329 }
5330
5331
5332 cpu_exec_realizefn(cs, &local_err);
5333 if (local_err != NULL) {
5334 error_propagate(errp, local_err);
5335 return;
5336 }
5337
5338 #ifndef CONFIG_USER_ONLY
5339 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
5340
5341 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
5342 x86_cpu_apic_create(cpu, &local_err);
5343 if (local_err != NULL) {
5344 goto out;
5345 }
5346 }
5347 #endif
5348
5349 mce_init(cpu);
5350
5351 #ifndef CONFIG_USER_ONLY
5352 if (tcg_enabled()) {
5353 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
5354 cpu->cpu_as_root = g_new(MemoryRegion, 1);
5355
5356 /* Outer container... */
5357 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
5358 memory_region_set_enabled(cpu->cpu_as_root, true);
5359
5360 /* ... with two regions inside: normal system memory with low
5361 * priority, and...
5362 */
5363 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
5364 get_system_memory(), 0, ~0ull);
5365 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
5366 memory_region_set_enabled(cpu->cpu_as_mem, true);
5367
5368 cs->num_ases = 2;
5369 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
5370 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
5371
5372 /* ... SMRAM with higher priority, linked from /machine/smram. */
5373 cpu->machine_done.notify = x86_cpu_machine_done;
5374 qemu_add_machine_init_done_notifier(&cpu->machine_done);
5375 }
5376 #endif
5377
5378 qemu_init_vcpu(cs);
5379
5380 /*
5381 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5382 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5383 * based on inputs (sockets,cores,threads), it is still better to give
5384 * users a warning.
5385 *
5386 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5387 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5388 */
5389 if (IS_AMD_CPU(env) &&
5390 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
5391 cs->nr_threads > 1 && !ht_warned) {
5392 warn_report("This family of AMD CPU doesn't support "
5393 "hyperthreading(%d)",
5394 cs->nr_threads);
5395 error_printf("Please configure -smp options properly"
5396 " or try enabling topoext feature.\n");
5397 ht_warned = true;
5398 }
5399
5400 x86_cpu_apic_realize(cpu, &local_err);
5401 if (local_err != NULL) {
5402 goto out;
5403 }
5404 cpu_reset(cs);
5405
5406 xcc->parent_realize(dev, &local_err);
5407
5408 out:
5409 if (local_err != NULL) {
5410 error_propagate(errp, local_err);
5411 return;
5412 }
5413 }
5414
5415 static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
5416 {
5417 X86CPU *cpu = X86_CPU(dev);
5418 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5419 Error *local_err = NULL;
5420
5421 #ifndef CONFIG_USER_ONLY
5422 cpu_remove_sync(CPU(dev));
5423 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
5424 #endif
5425
5426 if (cpu->apic_state) {
5427 object_unparent(OBJECT(cpu->apic_state));
5428 cpu->apic_state = NULL;
5429 }
5430
5431 xcc->parent_unrealize(dev, &local_err);
5432 if (local_err != NULL) {
5433 error_propagate(errp, local_err);
5434 return;
5435 }
5436 }
5437
5438 typedef struct BitProperty {
5439 FeatureWord w;
5440 uint32_t mask;
5441 } BitProperty;
5442
5443 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
5444 void *opaque, Error **errp)
5445 {
5446 X86CPU *cpu = X86_CPU(obj);
5447 BitProperty *fp = opaque;
5448 uint32_t f = cpu->env.features[fp->w];
5449 bool value = (f & fp->mask) == fp->mask;
5450 visit_type_bool(v, name, &value, errp);
5451 }
5452
5453 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
5454 void *opaque, Error **errp)
5455 {
5456 DeviceState *dev = DEVICE(obj);
5457 X86CPU *cpu = X86_CPU(obj);
5458 BitProperty *fp = opaque;
5459 Error *local_err = NULL;
5460 bool value;
5461
5462 if (dev->realized) {
5463 qdev_prop_set_after_realize(dev, name, errp);
5464 return;
5465 }
5466
5467 visit_type_bool(v, name, &value, &local_err);
5468 if (local_err) {
5469 error_propagate(errp, local_err);
5470 return;
5471 }
5472
5473 if (value) {
5474 cpu->env.features[fp->w] |= fp->mask;
5475 } else {
5476 cpu->env.features[fp->w] &= ~fp->mask;
5477 }
5478 cpu->env.user_features[fp->w] |= fp->mask;
5479 }
5480
5481 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
5482 void *opaque)
5483 {
5484 BitProperty *prop = opaque;
5485 g_free(prop);
5486 }
5487
5488 /* Register a boolean property to get/set a single bit in a uint32_t field.
5489 *
5490 * The same property name can be registered multiple times to make it affect
5491 * multiple bits in the same FeatureWord. In that case, the getter will return
5492 * true only if all bits are set.
5493 */
5494 static void x86_cpu_register_bit_prop(X86CPU *cpu,
5495 const char *prop_name,
5496 FeatureWord w,
5497 int bitnr)
5498 {
5499 BitProperty *fp;
5500 ObjectProperty *op;
5501 uint32_t mask = (1UL << bitnr);
5502
5503 op = object_property_find(OBJECT(cpu), prop_name, NULL);
5504 if (op) {
5505 fp = op->opaque;
5506 assert(fp->w == w);
5507 fp->mask |= mask;
5508 } else {
5509 fp = g_new0(BitProperty, 1);
5510 fp->w = w;
5511 fp->mask = mask;
5512 object_property_add(OBJECT(cpu), prop_name, "bool",
5513 x86_cpu_get_bit_prop,
5514 x86_cpu_set_bit_prop,
5515 x86_cpu_release_bit_prop, fp, &error_abort);
5516 }
5517 }
5518
5519 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
5520 FeatureWord w,
5521 int bitnr)
5522 {
5523 FeatureWordInfo *fi = &feature_word_info[w];
5524 const char *name = fi->feat_names[bitnr];
5525
5526 if (!name) {
5527 return;
5528 }
5529
5530 /* Property names should use "-" instead of "_".
5531 * Old names containing underscores are registered as aliases
5532 * using object_property_add_alias()
5533 */
5534 assert(!strchr(name, '_'));
5535 /* aliases don't use "|" delimiters anymore, they are registered
5536 * manually using object_property_add_alias() */
5537 assert(!strchr(name, '|'));
5538 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
5539 }
5540
5541 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
5542 {
5543 X86CPU *cpu = X86_CPU(cs);
5544 CPUX86State *env = &cpu->env;
5545 GuestPanicInformation *panic_info = NULL;
5546
5547 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
5548 panic_info = g_malloc0(sizeof(GuestPanicInformation));
5549
5550 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
5551
5552 assert(HV_CRASH_PARAMS >= 5);
5553 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
5554 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
5555 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
5556 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
5557 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
5558 }
5559
5560 return panic_info;
5561 }
5562 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
5563 const char *name, void *opaque,
5564 Error **errp)
5565 {
5566 CPUState *cs = CPU(obj);
5567 GuestPanicInformation *panic_info;
5568
5569 if (!cs->crash_occurred) {
5570 error_setg(errp, "No crash occured");
5571 return;
5572 }
5573
5574 panic_info = x86_cpu_get_crash_info(cs);
5575 if (panic_info == NULL) {
5576 error_setg(errp, "No crash information");
5577 return;
5578 }
5579
5580 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
5581 errp);
5582 qapi_free_GuestPanicInformation(panic_info);
5583 }
5584
5585 static void x86_cpu_initfn(Object *obj)
5586 {
5587 CPUState *cs = CPU(obj);
5588 X86CPU *cpu = X86_CPU(obj);
5589 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
5590 CPUX86State *env = &cpu->env;
5591 FeatureWord w;
5592
5593 cs->env_ptr = env;
5594
5595 object_property_add(obj, "family", "int",
5596 x86_cpuid_version_get_family,
5597 x86_cpuid_version_set_family, NULL, NULL, NULL);
5598 object_property_add(obj, "model", "int",
5599 x86_cpuid_version_get_model,
5600 x86_cpuid_version_set_model, NULL, NULL, NULL);
5601 object_property_add(obj, "stepping", "int",
5602 x86_cpuid_version_get_stepping,
5603 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
5604 object_property_add_str(obj, "vendor",
5605 x86_cpuid_get_vendor,
5606 x86_cpuid_set_vendor, NULL);
5607 object_property_add_str(obj, "model-id",
5608 x86_cpuid_get_model_id,
5609 x86_cpuid_set_model_id, NULL);
5610 object_property_add(obj, "tsc-frequency", "int",
5611 x86_cpuid_get_tsc_freq,
5612 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
5613 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
5614 x86_cpu_get_feature_words,
5615 NULL, NULL, (void *)env->features, NULL);
5616 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
5617 x86_cpu_get_feature_words,
5618 NULL, NULL, (void *)cpu->filtered_features, NULL);
5619
5620 object_property_add(obj, "crash-information", "GuestPanicInformation",
5621 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
5622
5623 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
5624
5625 for (w = 0; w < FEATURE_WORDS; w++) {
5626 int bitnr;
5627
5628 for (bitnr = 0; bitnr < 32; bitnr++) {
5629 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
5630 }
5631 }
5632
5633 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
5634 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
5635 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
5636 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
5637 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
5638 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
5639 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
5640
5641 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
5642 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
5643 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
5644 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
5645 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
5646 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
5647 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
5648 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
5649 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
5650 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
5651 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
5652 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
5653 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
5654 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
5655 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
5656 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
5657 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
5658 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
5659 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
5660 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
5661 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
5662
5663 if (xcc->cpu_def) {
5664 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
5665 }
5666 }
5667
5668 static int64_t x86_cpu_get_arch_id(CPUState *cs)
5669 {
5670 X86CPU *cpu = X86_CPU(cs);
5671
5672 return cpu->apic_id;
5673 }
5674
5675 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
5676 {
5677 X86CPU *cpu = X86_CPU(cs);
5678
5679 return cpu->env.cr[0] & CR0_PG_MASK;
5680 }
5681
5682 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
5683 {
5684 X86CPU *cpu = X86_CPU(cs);
5685
5686 cpu->env.eip = value;
5687 }
5688
5689 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
5690 {
5691 X86CPU *cpu = X86_CPU(cs);
5692
5693 cpu->env.eip = tb->pc - tb->cs_base;
5694 }
5695
5696 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
5697 {
5698 X86CPU *cpu = X86_CPU(cs);
5699 CPUX86State *env = &cpu->env;
5700
5701 #if !defined(CONFIG_USER_ONLY)
5702 if (interrupt_request & CPU_INTERRUPT_POLL) {
5703 return CPU_INTERRUPT_POLL;
5704 }
5705 #endif
5706 if (interrupt_request & CPU_INTERRUPT_SIPI) {
5707 return CPU_INTERRUPT_SIPI;
5708 }
5709
5710 if (env->hflags2 & HF2_GIF_MASK) {
5711 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
5712 !(env->hflags & HF_SMM_MASK)) {
5713 return CPU_INTERRUPT_SMI;
5714 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
5715 !(env->hflags2 & HF2_NMI_MASK)) {
5716 return CPU_INTERRUPT_NMI;
5717 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
5718 return CPU_INTERRUPT_MCE;
5719 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
5720 (((env->hflags2 & HF2_VINTR_MASK) &&
5721 (env->hflags2 & HF2_HIF_MASK)) ||
5722 (!(env->hflags2 & HF2_VINTR_MASK) &&
5723 (env->eflags & IF_MASK &&
5724 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
5725 return CPU_INTERRUPT_HARD;
5726 #if !defined(CONFIG_USER_ONLY)
5727 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
5728 (env->eflags & IF_MASK) &&
5729 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
5730 return CPU_INTERRUPT_VIRQ;
5731 #endif
5732 }
5733 }
5734
5735 return 0;
5736 }
5737
5738 static bool x86_cpu_has_work(CPUState *cs)
5739 {
5740 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
5741 }
5742
5743 static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
5744 {
5745 X86CPU *cpu = X86_CPU(cs);
5746 CPUX86State *env = &cpu->env;
5747
5748 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
5749 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
5750 : bfd_mach_i386_i8086);
5751 info->print_insn = print_insn_i386;
5752
5753 info->cap_arch = CS_ARCH_X86;
5754 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
5755 : env->hflags & HF_CS32_MASK ? CS_MODE_32
5756 : CS_MODE_16);
5757 info->cap_insn_unit = 1;
5758 info->cap_insn_split = 8;
5759 }
5760
5761 void x86_update_hflags(CPUX86State *env)
5762 {
5763 uint32_t hflags;
5764 #define HFLAG_COPY_MASK \
5765 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5766 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5767 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5768 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5769
5770 hflags = env->hflags & HFLAG_COPY_MASK;
5771 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5772 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5773 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5774 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5775 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5776
5777 if (env->cr[4] & CR4_OSFXSR_MASK) {
5778 hflags |= HF_OSFXSR_MASK;
5779 }
5780
5781 if (env->efer & MSR_EFER_LMA) {
5782 hflags |= HF_LMA_MASK;
5783 }
5784
5785 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5786 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5787 } else {
5788 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5789 (DESC_B_SHIFT - HF_CS32_SHIFT);
5790 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5791 (DESC_B_SHIFT - HF_SS32_SHIFT);
5792 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5793 !(hflags & HF_CS32_MASK)) {
5794 hflags |= HF_ADDSEG_MASK;
5795 } else {
5796 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5797 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5798 }
5799 }
5800 env->hflags = hflags;
5801 }
5802
5803 static Property x86_cpu_properties[] = {
5804 #ifdef CONFIG_USER_ONLY
5805 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5806 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
5807 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5808 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5809 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
5810 #else
5811 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
5812 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5813 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5814 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
5815 #endif
5816 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
5817 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
5818 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
5819 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
5820 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
5821 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
5822 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
5823 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
5824 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
5825 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
5826 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
5827 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
5828 DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
5829 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
5830 DEFINE_PROP_BOOL("hv-tlbflush", X86CPU, hyperv_tlbflush, false),
5831 DEFINE_PROP_BOOL("hv-evmcs", X86CPU, hyperv_evmcs, false),
5832 DEFINE_PROP_BOOL("hv-ipi", X86CPU, hyperv_ipi, false),
5833 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
5834 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
5835 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
5836 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
5837 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
5838 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
5839 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
5840 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5841 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5842 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5843 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5844 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5845 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5846 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
5847 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5848 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
5849 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
5850 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
5851 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5852 false),
5853 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
5854 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
5855 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
5856 true),
5857 /*
5858 * lecacy_cache defaults to true unless the CPU model provides its
5859 * own cache information (see x86_cpu_load_def()).
5860 */
5861 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
5862
5863 /*
5864 * From "Requirements for Implementing the Microsoft
5865 * Hypervisor Interface":
5866 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5867 *
5868 * "Starting with Windows Server 2012 and Windows 8, if
5869 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5870 * the hypervisor imposes no specific limit to the number of VPs.
5871 * In this case, Windows Server 2012 guest VMs may use more than
5872 * 64 VPs, up to the maximum supported number of processors applicable
5873 * to the specific Windows version being used."
5874 */
5875 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
5876 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
5877 false),
5878 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
5879 true),
5880 DEFINE_PROP_END_OF_LIST()
5881 };
5882
5883 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5884 {
5885 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5886 CPUClass *cc = CPU_CLASS(oc);
5887 DeviceClass *dc = DEVICE_CLASS(oc);
5888
5889 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5890 &xcc->parent_realize);
5891 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5892 &xcc->parent_unrealize);
5893 dc->props = x86_cpu_properties;
5894
5895 xcc->parent_reset = cc->reset;
5896 cc->reset = x86_cpu_reset;
5897 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
5898
5899 cc->class_by_name = x86_cpu_class_by_name;
5900 cc->parse_features = x86_cpu_parse_featurestr;
5901 cc->has_work = x86_cpu_has_work;
5902 #ifdef CONFIG_TCG
5903 cc->do_interrupt = x86_cpu_do_interrupt;
5904 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
5905 #endif
5906 cc->dump_state = x86_cpu_dump_state;
5907 cc->get_crash_info = x86_cpu_get_crash_info;
5908 cc->set_pc = x86_cpu_set_pc;
5909 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5910 cc->gdb_read_register = x86_cpu_gdb_read_register;
5911 cc->gdb_write_register = x86_cpu_gdb_write_register;
5912 cc->get_arch_id = x86_cpu_get_arch_id;
5913 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
5914 #ifdef CONFIG_USER_ONLY
5915 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
5916 #else
5917 cc->asidx_from_attrs = x86_asidx_from_attrs;
5918 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
5919 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
5920 cc->write_elf64_note = x86_cpu_write_elf64_note;
5921 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5922 cc->write_elf32_note = x86_cpu_write_elf32_note;
5923 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
5924 cc->vmsd = &vmstate_x86_cpu;
5925 #endif
5926 cc->gdb_arch_name = x86_gdb_arch_name;
5927 #ifdef TARGET_X86_64
5928 cc->gdb_core_xml_file = "i386-64bit.xml";
5929 cc->gdb_num_core_regs = 66;
5930 #else
5931 cc->gdb_core_xml_file = "i386-32bit.xml";
5932 cc->gdb_num_core_regs = 50;
5933 #endif
5934 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
5935 cc->debug_excp_handler = breakpoint_handler;
5936 #endif
5937 cc->cpu_exec_enter = x86_cpu_exec_enter;
5938 cc->cpu_exec_exit = x86_cpu_exec_exit;
5939 #ifdef CONFIG_TCG
5940 cc->tcg_initialize = tcg_x86_init;
5941 #endif
5942 cc->disas_set_info = x86_disas_set_info;
5943
5944 dc->user_creatable = true;
5945 }
5946
5947 static const TypeInfo x86_cpu_type_info = {
5948 .name = TYPE_X86_CPU,
5949 .parent = TYPE_CPU,
5950 .instance_size = sizeof(X86CPU),
5951 .instance_init = x86_cpu_initfn,
5952 .abstract = true,
5953 .class_size = sizeof(X86CPUClass),
5954 .class_init = x86_cpu_common_class_init,
5955 };
5956
5957
5958 /* "base" CPU model, used by query-cpu-model-expansion */
5959 static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5960 {
5961 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5962
5963 xcc->static_model = true;
5964 xcc->migration_safe = true;
5965 xcc->model_description = "base CPU model type with no features enabled";
5966 xcc->ordering = 8;
5967 }
5968
5969 static const TypeInfo x86_base_cpu_type_info = {
5970 .name = X86_CPU_TYPE_NAME("base"),
5971 .parent = TYPE_X86_CPU,
5972 .class_init = x86_cpu_base_class_init,
5973 };
5974
5975 static void x86_cpu_register_types(void)
5976 {
5977 int i;
5978
5979 type_register_static(&x86_cpu_type_info);
5980 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5981 x86_register_cpudef_type(&builtin_x86_defs[i]);
5982 }
5983 type_register_static(&max_x86_cpu_type_info);
5984 type_register_static(&x86_base_cpu_type_info);
5985 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
5986 type_register_static(&host_x86_cpu_type_info);
5987 #endif
5988 }
5989
5990 type_init(x86_cpu_register_types)
AR7 emulation for QEMU