hw/block/nvme.c

   1 /*
   2  * QEMU NVM Express Controller
   3  *
   4  * Copyright (c) 2012, Intel Corporation
   5  *
   6  * Written by Keith Busch <keith.busch@intel.com>
   7  *
   8  * This code is licensed under the GNU GPL v2 or later.
   9  */
  10
  11 /**
  12  * Reference Specs: http://www.nvmexpress.org, 1.1, 1.0e
  13  *
  14  *  http://www.nvmexpress.org/resources/
  15  */
  16
  17 /**
  18  * Usage: add options:
  19  *      -drive file=<file>,if=none,id=<drive_id>
  20  *      -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "hw/block/block.h"
  25 #include "hw/hw.h"
  26 #include "hw/pci/msix.h"
  27 #include "hw/pci/pci.h"
  28 #include "sysemu/sysemu.h"
  29 #include "qapi/error.h"
  30 #include "qapi/visitor.h"
  31 #include "sysemu/block-backend.h"
  32
  33 #include "nvme.h"
  34
  35 static void nvme_process_sq(void *opaque);
  36
  37 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
  38 {
  39     return sqid < n->num_queues && n->sq[sqid] != NULL ? 0 : -1;
  40 }
  41
  42 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
  43 {
  44     return cqid < n->num_queues && n->cq[cqid] != NULL ? 0 : -1;
  45 }
  46
  47 static void nvme_inc_cq_tail(NvmeCQueue *cq)
  48 {
  49     cq->tail++;
  50     if (cq->tail >= cq->size) {
  51         cq->tail = 0;
  52         cq->phase = !cq->phase;
  53     }
  54 }
  55
  56 static void nvme_inc_sq_head(NvmeSQueue *sq)
  57 {
  58     sq->head = (sq->head + 1) % sq->size;
  59 }
  60
  61 static uint8_t nvme_cq_full(NvmeCQueue *cq)
  62 {
  63     return (cq->tail + 1) % cq->size == cq->head;
  64 }
  65
  66 static uint8_t nvme_sq_empty(NvmeSQueue *sq)
  67 {
  68     return sq->head == sq->tail;
  69 }
  70
  71 static void nvme_isr_notify(NvmeCtrl *n, NvmeCQueue *cq)
  72 {
  73     if (cq->irq_enabled) {
  74         if (msix_enabled(&(n->parent_obj))) {
  75             msix_notify(&(n->parent_obj), cq->vector);
  76         } else {
  77             pci_irq_pulse(&n->parent_obj);
  78         }
  79     }
  80 }
  81
  82 static uint16_t nvme_map_prp(QEMUSGList *qsg, uint64_t prp1, uint64_t prp2,
  83     uint32_t len, NvmeCtrl *n)
  84 {
  85     hwaddr trans_len = n->page_size - (prp1 % n->page_size);
  86     trans_len = MIN(len, trans_len);
  87     int num_prps = (len >> n->page_bits) + 1;
  88
  89     if (!prp1) {
  90         return NVME_INVALID_FIELD | NVME_DNR;
  91     }
  92
  93     pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
  94     qemu_sglist_add(qsg, prp1, trans_len);
  95     len -= trans_len;
  96     if (len) {
  97         if (!prp2) {
  98             goto unmap;
  99         }
 100         if (len > n->page_size) {
 101             uint64_t prp_list[n->max_prp_ents];
 102             uint32_t nents, prp_trans;
 103             int i = 0;
 104
 105             nents = (len + n->page_size - 1) >> n->page_bits;
 106             prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
 107             pci_dma_read(&n->parent_obj, prp2, (void *)prp_list, prp_trans);
 108             while (len != 0) {
 109                 uint64_t prp_ent = le64_to_cpu(prp_list[i]);
 110
 111                 if (i == n->max_prp_ents - 1 && len > n->page_size) {
 112                     if (!prp_ent || prp_ent & (n->page_size - 1)) {
 113                         goto unmap;
 114                     }
 115
 116                     i = 0;
 117                     nents = (len + n->page_size - 1) >> n->page_bits;
 118                     prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
 119                     pci_dma_read(&n->parent_obj, prp_ent, (void *)prp_list,
 120                         prp_trans);
 121                     prp_ent = le64_to_cpu(prp_list[i]);
 122                 }
 123
 124                 if (!prp_ent || prp_ent & (n->page_size - 1)) {
 125                     goto unmap;
 126                 }
 127
 128                 trans_len = MIN(len, n->page_size);
 129                 qemu_sglist_add(qsg, prp_ent, trans_len);
 130                 len -= trans_len;
 131                 i++;
 132             }
 133         } else {
 134             if (prp2 & (n->page_size - 1)) {
 135                 goto unmap;
 136             }
 137             qemu_sglist_add(qsg, prp2, len);
 138         }
 139     }
 140     return NVME_SUCCESS;
 141
 142  unmap:
 143     qemu_sglist_destroy(qsg);
 144     return NVME_INVALID_FIELD | NVME_DNR;
 145 }
 146
 147 static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
 148     uint64_t prp1, uint64_t prp2)
 149 {
 150     QEMUSGList qsg;
 151
 152     if (nvme_map_prp(&qsg, prp1, prp2, len, n)) {
 153         return NVME_INVALID_FIELD | NVME_DNR;
 154     }
 155     if (dma_buf_read(ptr, len, &qsg)) {
 156         qemu_sglist_destroy(&qsg);
 157         return NVME_INVALID_FIELD | NVME_DNR;
 158     }
 159     qemu_sglist_destroy(&qsg);
 160     return NVME_SUCCESS;
 161 }
 162
 163 static void nvme_post_cqes(void *opaque)
 164 {
 165     NvmeCQueue *cq = opaque;
 166     NvmeCtrl *n = cq->ctrl;
 167     NvmeRequest *req, *next;
 168
 169     QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
 170         NvmeSQueue *sq;
 171         hwaddr addr;
 172
 173         if (nvme_cq_full(cq)) {
 174             break;
 175         }
 176
 177         QTAILQ_REMOVE(&cq->req_list, req, entry);
 178         sq = req->sq;
 179         req->cqe.status = cpu_to_le16((req->status << 1) | cq->phase);
 180         req->cqe.sq_id = cpu_to_le16(sq->sqid);
 181         req->cqe.sq_head = cpu_to_le16(sq->head);
 182         addr = cq->dma_addr + cq->tail * n->cqe_size;
 183         nvme_inc_cq_tail(cq);
 184         pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe,
 185             sizeof(req->cqe));
 186         QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
 187     }
 188     nvme_isr_notify(n, cq);
 189 }
 190
 191 static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
 192 {
 193     assert(cq->cqid == req->sq->cqid);
 194     QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
 195     QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
 196     timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
 197 }
 198
 199 static void nvme_rw_cb(void *opaque, int ret)
 200 {
 201     NvmeRequest *req = opaque;
 202     NvmeSQueue *sq = req->sq;
 203     NvmeCtrl *n = sq->ctrl;
 204     NvmeCQueue *cq = n->cq[sq->cqid];
 205
 206     if (!ret) {
 207         block_acct_done(blk_get_stats(n->conf.blk), &req->acct);
 208         req->status = NVME_SUCCESS;
 209     } else {
 210         block_acct_failed(blk_get_stats(n->conf.blk), &req->acct);
 211         req->status = NVME_INTERNAL_DEV_ERROR;
 212     }
 213     if (req->has_sg) {
 214         qemu_sglist_destroy(&req->qsg);
 215     }
 216     nvme_enqueue_req_completion(cq, req);
 217 }
 218
 219 static uint16_t nvme_flush(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
 220     NvmeRequest *req)
 221 {
 222     req->has_sg = false;
 223     block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
 224          BLOCK_ACCT_FLUSH);
 225     req->aiocb = blk_aio_flush(n->conf.blk, nvme_rw_cb, req);
 226
 227     return NVME_NO_COMPLETE;
 228 }
 229
 230 static uint16_t nvme_write_zeros(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
 231     NvmeRequest *req)
 232 {
 233     NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
 234     const uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
 235     const uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
 236     uint64_t slba = le64_to_cpu(rw->slba);
 237     uint32_t nlb  = le16_to_cpu(rw->nlb) + 1;
 238     uint64_t aio_slba = slba << (data_shift - BDRV_SECTOR_BITS);
 239     uint32_t aio_nlb = nlb << (data_shift - BDRV_SECTOR_BITS);
 240
 241     if (slba + nlb > ns->id_ns.nsze) {
 242         return NVME_LBA_RANGE | NVME_DNR;
 243     }
 244
 245     req->has_sg = false;
 246     block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
 247                      BLOCK_ACCT_WRITE);
 248     req->aiocb = blk_aio_pwrite_zeroes(n->conf.blk, aio_slba, aio_nlb,
 249                                         BDRV_REQ_MAY_UNMAP, nvme_rw_cb, req);
 250     return NVME_NO_COMPLETE;
 251 }
 252
 253 static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
 254     NvmeRequest *req)
 255 {
 256     NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
 257     uint32_t nlb  = le32_to_cpu(rw->nlb) + 1;
 258     uint64_t slba = le64_to_cpu(rw->slba);
 259     uint64_t prp1 = le64_to_cpu(rw->prp1);
 260     uint64_t prp2 = le64_to_cpu(rw->prp2);
 261
 262     uint8_t lba_index  = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
 263     uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
 264     uint64_t data_size = (uint64_t)nlb << data_shift;
 265     uint64_t data_offset = slba << data_shift;
 266     int is_write = rw->opcode == NVME_CMD_WRITE ? 1 : 0;
 267     enum BlockAcctType acct = is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ;
 268
 269     if ((slba + nlb) > ns->id_ns.nsze) {
 270         block_acct_invalid(blk_get_stats(n->conf.blk), acct);
 271         return NVME_LBA_RANGE | NVME_DNR;
 272     }
 273
 274     if (nvme_map_prp(&req->qsg, prp1, prp2, data_size, n)) {
 275         block_acct_invalid(blk_get_stats(n->conf.blk), acct);
 276         return NVME_INVALID_FIELD | NVME_DNR;
 277     }
 278
 279     assert((nlb << data_shift) == req->qsg.size);
 280
 281     req->has_sg = true;
 282     dma_acct_start(n->conf.blk, &req->acct, &req->qsg, acct);
 283     req->aiocb = is_write ?
 284         dma_blk_write(n->conf.blk, &req->qsg, data_offset, BDRV_SECTOR_SIZE,
 285                       nvme_rw_cb, req) :
 286         dma_blk_read(n->conf.blk, &req->qsg, data_offset, BDRV_SECTOR_SIZE,
 287                      nvme_rw_cb, req);
 288
 289     return NVME_NO_COMPLETE;
 290 }
 291
 292 static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 293 {
 294     NvmeNamespace *ns;
 295     uint32_t nsid = le32_to_cpu(cmd->nsid);
 296
 297     if (nsid == 0 || nsid > n->num_namespaces) {
 298         return NVME_INVALID_NSID | NVME_DNR;
 299     }
 300
 301     ns = &n->namespaces[nsid - 1];
 302     switch (cmd->opcode) {
 303     case NVME_CMD_FLUSH:
 304         return nvme_flush(n, ns, cmd, req);
 305     case NVME_CMD_WRITE_ZEROS:
 306         return nvme_write_zeros(n, ns, cmd, req);
 307     case NVME_CMD_WRITE:
 308     case NVME_CMD_READ:
 309         return nvme_rw(n, ns, cmd, req);
 310     default:
 311         return NVME_INVALID_OPCODE | NVME_DNR;
 312     }
 313 }
 314
 315 static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
 316 {
 317     n->sq[sq->sqid] = NULL;
 318     timer_del(sq->timer);
 319     timer_free(sq->timer);
 320     g_free(sq->io_req);
 321     if (sq->sqid) {
 322         g_free(sq);
 323     }
 324 }
 325
 326 static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeCmd *cmd)
 327 {
 328     NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
 329     NvmeRequest *req, *next;
 330     NvmeSQueue *sq;
 331     NvmeCQueue *cq;
 332     uint16_t qid = le16_to_cpu(c->qid);
 333
 334     if (!qid || nvme_check_sqid(n, qid)) {
 335         return NVME_INVALID_QID | NVME_DNR;
 336     }
 337
 338     sq = n->sq[qid];
 339     while (!QTAILQ_EMPTY(&sq->out_req_list)) {
 340         req = QTAILQ_FIRST(&sq->out_req_list);
 341         assert(req->aiocb);
 342         blk_aio_cancel(req->aiocb);
 343     }
 344     if (!nvme_check_cqid(n, sq->cqid)) {
 345         cq = n->cq[sq->cqid];
 346         QTAILQ_REMOVE(&cq->sq_list, sq, entry);
 347
 348         nvme_post_cqes(cq);
 349         QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
 350             if (req->sq == sq) {
 351                 QTAILQ_REMOVE(&cq->req_list, req, entry);
 352                 QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
 353             }
 354         }
 355     }
 356
 357     nvme_free_sq(sq, n);
 358     return NVME_SUCCESS;
 359 }
 360
 361 static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
 362     uint16_t sqid, uint16_t cqid, uint16_t size)
 363 {
 364     int i;
 365     NvmeCQueue *cq;
 366
 367     sq->ctrl = n;
 368     sq->dma_addr = dma_addr;
 369     sq->sqid = sqid;
 370     sq->size = size;
 371     sq->cqid = cqid;
 372     sq->head = sq->tail = 0;
 373     sq->io_req = g_new(NvmeRequest, sq->size);
 374
 375     QTAILQ_INIT(&sq->req_list);
 376     QTAILQ_INIT(&sq->out_req_list);
 377     for (i = 0; i < sq->size; i++) {
 378         sq->io_req[i].sq = sq;
 379         QTAILQ_INSERT_TAIL(&(sq->req_list), &sq->io_req[i], entry);
 380     }
 381     sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq);
 382
 383     assert(n->cq[cqid]);
 384     cq = n->cq[cqid];
 385     QTAILQ_INSERT_TAIL(&(cq->sq_list), sq, entry);
 386     n->sq[sqid] = sq;
 387 }
 388
 389 static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeCmd *cmd)
 390 {
 391     NvmeSQueue *sq;
 392     NvmeCreateSq *c = (NvmeCreateSq *)cmd;
 393
 394     uint16_t cqid = le16_to_cpu(c->cqid);
 395     uint16_t sqid = le16_to_cpu(c->sqid);
 396     uint16_t qsize = le16_to_cpu(c->qsize);
 397     uint16_t qflags = le16_to_cpu(c->sq_flags);
 398     uint64_t prp1 = le64_to_cpu(c->prp1);
 399
 400     if (!cqid || nvme_check_cqid(n, cqid)) {
 401         return NVME_INVALID_CQID | NVME_DNR;
 402     }
 403     if (!sqid || !nvme_check_sqid(n, sqid)) {
 404         return NVME_INVALID_QID | NVME_DNR;
 405     }
 406     if (!qsize || qsize > NVME_CAP_MQES(n->bar.cap)) {
 407         return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
 408     }
 409     if (!prp1 || prp1 & (n->page_size - 1)) {
 410         return NVME_INVALID_FIELD | NVME_DNR;
 411     }
 412     if (!(NVME_SQ_FLAGS_PC(qflags))) {
 413         return NVME_INVALID_FIELD | NVME_DNR;
 414     }
 415     sq = g_malloc0(sizeof(*sq));
 416     nvme_init_sq(sq, n, prp1, sqid, cqid, qsize + 1);
 417     return NVME_SUCCESS;
 418 }
 419
 420 static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
 421 {
 422     n->cq[cq->cqid] = NULL;
 423     timer_del(cq->timer);
 424     timer_free(cq->timer);
 425     msix_vector_unuse(&n->parent_obj, cq->vector);
 426     if (cq->cqid) {
 427         g_free(cq);
 428     }
 429 }
 430
 431 static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeCmd *cmd)
 432 {
 433     NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
 434     NvmeCQueue *cq;
 435     uint16_t qid = le16_to_cpu(c->qid);
 436
 437     if (!qid || nvme_check_cqid(n, qid)) {
 438         return NVME_INVALID_CQID | NVME_DNR;
 439     }
 440
 441     cq = n->cq[qid];
 442     if (!QTAILQ_EMPTY(&cq->sq_list)) {
 443         return NVME_INVALID_QUEUE_DEL;
 444     }
 445     nvme_free_cq(cq, n);
 446     return NVME_SUCCESS;
 447 }
 448
 449 static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,
 450     uint16_t cqid, uint16_t vector, uint16_t size, uint16_t irq_enabled)
 451 {
 452     cq->ctrl = n;
 453     cq->cqid = cqid;
 454     cq->size = size;
 455     cq->dma_addr = dma_addr;
 456     cq->phase = 1;
 457     cq->irq_enabled = irq_enabled;
 458     cq->vector = vector;
 459     cq->head = cq->tail = 0;
 460     QTAILQ_INIT(&cq->req_list);
 461     QTAILQ_INIT(&cq->sq_list);
 462     msix_vector_use(&n->parent_obj, cq->vector);
 463     n->cq[cqid] = cq;
 464     cq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_post_cqes, cq);
 465 }
 466
 467 static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cmd)
 468 {
 469     NvmeCQueue *cq;
 470     NvmeCreateCq *c = (NvmeCreateCq *)cmd;
 471     uint16_t cqid = le16_to_cpu(c->cqid);
 472     uint16_t vector = le16_to_cpu(c->irq_vector);
 473     uint16_t qsize = le16_to_cpu(c->qsize);
 474     uint16_t qflags = le16_to_cpu(c->cq_flags);
 475     uint64_t prp1 = le64_to_cpu(c->prp1);
 476
 477     if (!cqid || !nvme_check_cqid(n, cqid)) {
 478         return NVME_INVALID_CQID | NVME_DNR;
 479     }
 480     if (!qsize || qsize > NVME_CAP_MQES(n->bar.cap)) {
 481         return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
 482     }
 483     if (!prp1) {
 484         return NVME_INVALID_FIELD | NVME_DNR;
 485     }
 486     if (vector > n->num_queues) {
 487         return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
 488     }
 489     if (!(NVME_CQ_FLAGS_PC(qflags))) {
 490         return NVME_INVALID_FIELD | NVME_DNR;
 491     }
 492
 493     cq = g_malloc0(sizeof(*cq));
 494     nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1,
 495         NVME_CQ_FLAGS_IEN(qflags));
 496     return NVME_SUCCESS;
 497 }
 498
 499 static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeIdentify *c)
 500 {
 501     uint64_t prp1 = le64_to_cpu(c->prp1);
 502     uint64_t prp2 = le64_to_cpu(c->prp2);
 503
 504     return nvme_dma_read_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl),
 505         prp1, prp2);
 506 }
 507
 508 static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdentify *c)
 509 {
 510     NvmeNamespace *ns;
 511     uint32_t nsid = le32_to_cpu(c->nsid);
 512     uint64_t prp1 = le64_to_cpu(c->prp1);
 513     uint64_t prp2 = le64_to_cpu(c->prp2);
 514
 515     if (nsid == 0 || nsid > n->num_namespaces) {
 516         return NVME_INVALID_NSID | NVME_DNR;
 517     }
 518
 519     ns = &n->namespaces[nsid - 1];
 520     return nvme_dma_read_prp(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns),
 521         prp1, prp2);
 522 }
 523
 524 static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c)
 525 {
 526     static const int data_len = 4096;
 527     uint32_t min_nsid = le32_to_cpu(c->nsid);
 528     uint64_t prp1 = le64_to_cpu(c->prp1);
 529     uint64_t prp2 = le64_to_cpu(c->prp2);
 530     uint32_t *list;
 531     uint16_t ret;
 532     int i, j = 0;
 533
 534     list = g_malloc0(data_len);
 535     for (i = 0; i < n->num_namespaces; i++) {
 536         if (i < min_nsid) {
 537             continue;
 538         }
 539         list[j++] = cpu_to_le32(i + 1);
 540         if (j == data_len / sizeof(uint32_t)) {
 541             break;
 542         }
 543     }
 544     ret = nvme_dma_read_prp(n, (uint8_t *)list, data_len, prp1, prp2);
 545     g_free(list);
 546     return ret;
 547 }
 548
 549
 550 static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *cmd)
 551 {
 552     NvmeIdentify *c = (NvmeIdentify *)cmd;
 553
 554     switch (le32_to_cpu(c->cns)) {
 555     case 0x00:
 556         return nvme_identify_ns(n, c);
 557     case 0x01:
 558         return nvme_identify_ctrl(n, c);
 559     case 0x02:
 560         return nvme_identify_nslist(n, c);
 561     default:
 562         return NVME_INVALID_FIELD | NVME_DNR;
 563     }
 564 }
 565
 566 static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 567 {
 568     uint32_t dw10 = le32_to_cpu(cmd->cdw10);
 569     uint32_t result;
 570
 571     switch (dw10) {
 572     case NVME_VOLATILE_WRITE_CACHE:
 573         result = blk_enable_write_cache(n->conf.blk);
 574         break;
 575     case NVME_NUMBER_OF_QUEUES:
 576         result = cpu_to_le32((n->num_queues - 1) | ((n->num_queues - 1) << 16));
 577         break;
 578     default:
 579         return NVME_INVALID_FIELD | NVME_DNR;
 580     }
 581
 582     req->cqe.result = result;
 583     return NVME_SUCCESS;
 584 }
 585
 586 static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 587 {
 588     uint32_t dw10 = le32_to_cpu(cmd->cdw10);
 589     uint32_t dw11 = le32_to_cpu(cmd->cdw11);
 590
 591     switch (dw10) {
 592     case NVME_VOLATILE_WRITE_CACHE:
 593         blk_set_enable_write_cache(n->conf.blk, dw11 & 1);
 594         break;
 595     case NVME_NUMBER_OF_QUEUES:
 596         req->cqe.result =
 597             cpu_to_le32((n->num_queues - 1) | ((n->num_queues - 1) << 16));
 598         break;
 599     default:
 600         return NVME_INVALID_FIELD | NVME_DNR;
 601     }
 602     return NVME_SUCCESS;
 603 }
 604
 605 static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 606 {
 607     switch (cmd->opcode) {
 608     case NVME_ADM_CMD_DELETE_SQ:
 609         return nvme_del_sq(n, cmd);
 610     case NVME_ADM_CMD_CREATE_SQ:
 611         return nvme_create_sq(n, cmd);
 612     case NVME_ADM_CMD_DELETE_CQ:
 613         return nvme_del_cq(n, cmd);
 614     case NVME_ADM_CMD_CREATE_CQ:
 615         return nvme_create_cq(n, cmd);
 616     case NVME_ADM_CMD_IDENTIFY:
 617         return nvme_identify(n, cmd);
 618     case NVME_ADM_CMD_SET_FEATURES:
 619         return nvme_set_feature(n, cmd, req);
 620     case NVME_ADM_CMD_GET_FEATURES:
 621         return nvme_get_feature(n, cmd, req);
 622     default:
 623         return NVME_INVALID_OPCODE | NVME_DNR;
 624     }
 625 }
 626
 627 static void nvme_process_sq(void *opaque)
 628 {
 629     NvmeSQueue *sq = opaque;
 630     NvmeCtrl *n = sq->ctrl;
 631     NvmeCQueue *cq = n->cq[sq->cqid];
 632
 633     uint16_t status;
 634     hwaddr addr;
 635     NvmeCmd cmd;
 636     NvmeRequest *req;
 637
 638     while (!(nvme_sq_empty(sq) || QTAILQ_EMPTY(&sq->req_list))) {
 639         addr = sq->dma_addr + sq->head * n->sqe_size;
 640         pci_dma_read(&n->parent_obj, addr, (void *)&cmd, sizeof(cmd));
 641         nvme_inc_sq_head(sq);
 642
 643         req = QTAILQ_FIRST(&sq->req_list);
 644         QTAILQ_REMOVE(&sq->req_list, req, entry);
 645         QTAILQ_INSERT_TAIL(&sq->out_req_list, req, entry);
 646         memset(&req->cqe, 0, sizeof(req->cqe));
 647         req->cqe.cid = cmd.cid;
 648
 649         status = sq->sqid ? nvme_io_cmd(n, &cmd, req) :
 650             nvme_admin_cmd(n, &cmd, req);
 651         if (status != NVME_NO_COMPLETE) {
 652             req->status = status;
 653             nvme_enqueue_req_completion(cq, req);
 654         }
 655     }
 656 }
 657
 658 static void nvme_clear_ctrl(NvmeCtrl *n)
 659 {
 660     int i;
 661
 662     for (i = 0; i < n->num_queues; i++) {
 663         if (n->sq[i] != NULL) {
 664             nvme_free_sq(n->sq[i], n);
 665         }
 666     }
 667     for (i = 0; i < n->num_queues; i++) {
 668         if (n->cq[i] != NULL) {
 669             nvme_free_cq(n->cq[i], n);
 670         }
 671     }
 672
 673     blk_flush(n->conf.blk);
 674     n->bar.cc = 0;
 675 }
 676
 677 static int nvme_start_ctrl(NvmeCtrl *n)
 678 {
 679     uint32_t page_bits = NVME_CC_MPS(n->bar.cc) + 12;
 680     uint32_t page_size = 1 << page_bits;
 681
 682     if (n->cq[0] || n->sq[0] || !n->bar.asq || !n->bar.acq ||
 683             n->bar.asq & (page_size - 1) || n->bar.acq & (page_size - 1) ||
 684             NVME_CC_MPS(n->bar.cc) < NVME_CAP_MPSMIN(n->bar.cap) ||
 685             NVME_CC_MPS(n->bar.cc) > NVME_CAP_MPSMAX(n->bar.cap) ||
 686             NVME_CC_IOCQES(n->bar.cc) < NVME_CTRL_CQES_MIN(n->id_ctrl.cqes) ||
 687             NVME_CC_IOCQES(n->bar.cc) > NVME_CTRL_CQES_MAX(n->id_ctrl.cqes) ||
 688             NVME_CC_IOSQES(n->bar.cc) < NVME_CTRL_SQES_MIN(n->id_ctrl.sqes) ||
 689             NVME_CC_IOSQES(n->bar.cc) > NVME_CTRL_SQES_MAX(n->id_ctrl.sqes) ||
 690             !NVME_AQA_ASQS(n->bar.aqa) || !NVME_AQA_ACQS(n->bar.aqa)) {
 691         return -1;
 692     }
 693
 694     n->page_bits = page_bits;
 695     n->page_size = page_size;
 696     n->max_prp_ents = n->page_size / sizeof(uint64_t);
 697     n->cqe_size = 1 << NVME_CC_IOCQES(n->bar.cc);
 698     n->sqe_size = 1 << NVME_CC_IOSQES(n->bar.cc);
 699     nvme_init_cq(&n->admin_cq, n, n->bar.acq, 0, 0,
 700         NVME_AQA_ACQS(n->bar.aqa) + 1, 1);
 701     nvme_init_sq(&n->admin_sq, n, n->bar.asq, 0, 0,
 702         NVME_AQA_ASQS(n->bar.aqa) + 1);
 703
 704     return 0;
 705 }
 706
 707 static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
 708     unsigned size)
 709 {
 710     switch (offset) {
 711     case 0xc:
 712         n->bar.intms |= data & 0xffffffff;
 713         n->bar.intmc = n->bar.intms;
 714         break;
 715     case 0x10:
 716         n->bar.intms &= ~(data & 0xffffffff);
 717         n->bar.intmc = n->bar.intms;
 718         break;
 719     case 0x14:
 720         /* Windows first sends data, then sends enable bit */
 721         if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) &&
 722             !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc))
 723         {
 724             n->bar.cc = data;
 725         }
 726
 727         if (NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc)) {
 728             n->bar.cc = data;
 729             if (nvme_start_ctrl(n)) {
 730                 n->bar.csts = NVME_CSTS_FAILED;
 731             } else {
 732                 n->bar.csts = NVME_CSTS_READY;
 733             }
 734         } else if (!NVME_CC_EN(data) && NVME_CC_EN(n->bar.cc)) {
 735             nvme_clear_ctrl(n);
 736             n->bar.csts &= ~NVME_CSTS_READY;
 737         }
 738         if (NVME_CC_SHN(data) && !(NVME_CC_SHN(n->bar.cc))) {
 739                 nvme_clear_ctrl(n);
 740                 n->bar.cc = data;
 741                 n->bar.csts |= NVME_CSTS_SHST_COMPLETE;
 742         } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(n->bar.cc)) {
 743                 n->bar.csts &= ~NVME_CSTS_SHST_COMPLETE;
 744                 n->bar.cc = data;
 745         }
 746         break;
 747     case 0x24:
 748         n->bar.aqa = data & 0xffffffff;
 749         break;
 750     case 0x28:
 751         n->bar.asq = data;
 752         break;
 753     case 0x2c:
 754         n->bar.asq |= data << 32;
 755         break;
 756     case 0x30:
 757         n->bar.acq = data;
 758         break;
 759     case 0x34:
 760         n->bar.acq |= data << 32;
 761         break;
 762     default:
 763         break;
 764     }
 765 }
 766
 767 static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
 768 {
 769     NvmeCtrl *n = (NvmeCtrl *)opaque;
 770     uint8_t *ptr = (uint8_t *)&n->bar;
 771     uint64_t val = 0;
 772
 773     if (addr < sizeof(n->bar)) {
 774         memcpy(&val, ptr + addr, size);
 775     }
 776     return val;
 777 }
 778
 779 static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
 780 {
 781     uint32_t qid;
 782
 783     if (addr & ((1 << 2) - 1)) {
 784         return;
 785     }
 786
 787     if (((addr - 0x1000) >> 2) & 1) {
 788         uint16_t new_head = val & 0xffff;
 789         int start_sqs;
 790         NvmeCQueue *cq;
 791
 792         qid = (addr - (0x1000 + (1 << 2))) >> 3;
 793         if (nvme_check_cqid(n, qid)) {
 794             return;
 795         }
 796
 797         cq = n->cq[qid];
 798         if (new_head >= cq->size) {
 799             return;
 800         }
 801
 802         start_sqs = nvme_cq_full(cq) ? 1 : 0;
 803         cq->head = new_head;
 804         if (start_sqs) {
 805             NvmeSQueue *sq;
 806             QTAILQ_FOREACH(sq, &cq->sq_list, entry) {
 807                 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
 808             }
 809             timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
 810         }
 811
 812         if (cq->tail != cq->head) {
 813             nvme_isr_notify(n, cq);
 814         }
 815     } else {
 816         uint16_t new_tail = val & 0xffff;
 817         NvmeSQueue *sq;
 818
 819         qid = (addr - 0x1000) >> 3;
 820         if (nvme_check_sqid(n, qid)) {
 821             return;
 822         }
 823
 824         sq = n->sq[qid];
 825         if (new_tail >= sq->size) {
 826             return;
 827         }
 828
 829         sq->tail = new_tail;
 830         timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
 831     }
 832 }
 833
 834 static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data,
 835     unsigned size)
 836 {
 837     NvmeCtrl *n = (NvmeCtrl *)opaque;
 838     if (addr < sizeof(n->bar)) {
 839         nvme_write_bar(n, addr, data, size);
 840     } else if (addr >= 0x1000) {
 841         nvme_process_db(n, addr, data);
 842     }
 843 }
 844
 845 static const MemoryRegionOps nvme_mmio_ops = {
 846     .read = nvme_mmio_read,
 847     .write = nvme_mmio_write,
 848     .endianness = DEVICE_LITTLE_ENDIAN,
 849     .impl = {
 850         .min_access_size = 2,
 851         .max_access_size = 8,
 852     },
 853 };
 854
 855 static int nvme_init(PCIDevice *pci_dev)
 856 {
 857     NvmeCtrl *n = NVME(pci_dev);
 858     NvmeIdCtrl *id = &n->id_ctrl;
 859
 860     int i;
 861     int64_t bs_size;
 862     uint8_t *pci_conf;
 863     Error *local_err = NULL;
 864
 865     if (!n->conf.blk) {
 866         return -1;
 867     }
 868
 869     bs_size = blk_getlength(n->conf.blk);
 870     if (bs_size < 0) {
 871         return -1;
 872     }
 873
 874     blkconf_serial(&n->conf, &n->serial);
 875     if (!n->serial) {
 876         return -1;
 877     }
 878     blkconf_blocksizes(&n->conf);
 879     blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.blk),
 880                                   false, &local_err);
 881     if (local_err) {
 882         error_report_err(local_err);
 883         return -1;
 884     }
 885
 886     pci_conf = pci_dev->config;
 887     pci_conf[PCI_INTERRUPT_PIN] = 1;
 888     pci_config_set_prog_interface(pci_dev->config, 0x2);
 889     pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS);
 890     pcie_endpoint_cap_init(&n->parent_obj, 0x80);
 891
 892     n->num_namespaces = 1;
 893     n->num_queues = 64;
 894     n->reg_size = pow2ceil(0x1004 + 2 * (n->num_queues + 1) * 4);
 895     n->ns_size = bs_size / (uint64_t)n->num_namespaces;
 896
 897     n->namespaces = g_new0(NvmeNamespace, n->num_namespaces);
 898     n->sq = g_new0(NvmeSQueue *, n->num_queues);
 899     n->cq = g_new0(NvmeCQueue *, n->num_queues);
 900
 901     memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n,
 902                           "nvme", n->reg_size);
 903     pci_register_bar(&n->parent_obj, 0,
 904         PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64,
 905         &n->iomem);
 906     msix_init_exclusive_bar(&n->parent_obj, n->num_queues, 4, NULL);
 907
 908     id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
 909     id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
 910     strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
 911     strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' ');
 912     strpadcpy((char *)id->sn, sizeof(id->sn), n->serial, ' ');
 913     id->rab = 6;
 914     id->ieee[0] = 0x00;
 915     id->ieee[1] = 0x02;
 916     id->ieee[2] = 0xb3;
 917     id->oacs = cpu_to_le16(0);
 918     id->frmw = 7 << 1;
 919     id->lpa = 1 << 0;
 920     id->sqes = (0x6 << 4) | 0x6;
 921     id->cqes = (0x4 << 4) | 0x4;
 922     id->nn = cpu_to_le32(n->num_namespaces);
 923     id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROS);
 924     id->psd[0].mp = cpu_to_le16(0x9c4);
 925     id->psd[0].enlat = cpu_to_le32(0x10);
 926     id->psd[0].exlat = cpu_to_le32(0x4);
 927     if (blk_enable_write_cache(n->conf.blk)) {
 928         id->vwc = 1;
 929     }
 930
 931     n->bar.cap = 0;
 932     NVME_CAP_SET_MQES(n->bar.cap, 0x7ff);
 933     NVME_CAP_SET_CQR(n->bar.cap, 1);
 934     NVME_CAP_SET_AMS(n->bar.cap, 1);
 935     NVME_CAP_SET_TO(n->bar.cap, 0xf);
 936     NVME_CAP_SET_CSS(n->bar.cap, 1);
 937     NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
 938
 939     n->bar.vs = 0x00010100;
 940     n->bar.intmc = n->bar.intms = 0;
 941
 942     for (i = 0; i < n->num_namespaces; i++) {
 943         NvmeNamespace *ns = &n->namespaces[i];
 944         NvmeIdNs *id_ns = &ns->id_ns;
 945         id_ns->nsfeat = 0;
 946         id_ns->nlbaf = 0;
 947         id_ns->flbas = 0;
 948         id_ns->mc = 0;
 949         id_ns->dpc = 0;
 950         id_ns->dps = 0;
 951         id_ns->lbaf[0].ds = BDRV_SECTOR_BITS;
 952         id_ns->ncap  = id_ns->nuse = id_ns->nsze =
 953             cpu_to_le64(n->ns_size >>
 954                 id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas)].ds);
 955     }
 956     return 0;
 957 }
 958
 959 static void nvme_exit(PCIDevice *pci_dev)
 960 {
 961     NvmeCtrl *n = NVME(pci_dev);
 962
 963     nvme_clear_ctrl(n);
 964     g_free(n->namespaces);
 965     g_free(n->cq);
 966     g_free(n->sq);
 967     msix_uninit_exclusive_bar(pci_dev);
 968 }
 969
 970 static Property nvme_props[] = {
 971     DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf),
 972     DEFINE_PROP_STRING("serial", NvmeCtrl, serial),
 973     DEFINE_PROP_END_OF_LIST(),
 974 };
 975
 976 static const VMStateDescription nvme_vmstate = {
 977     .name = "nvme",
 978     .unmigratable = 1,
 979 };
 980
 981 static void nvme_class_init(ObjectClass *oc, void *data)
 982 {
 983     DeviceClass *dc = DEVICE_CLASS(oc);
 984     PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
 985
 986     pc->init = nvme_init;
 987     pc->exit = nvme_exit;
 988     pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
 989     pc->vendor_id = PCI_VENDOR_ID_INTEL;
 990     pc->device_id = 0x5845;
 991     pc->revision = 2;
 992     pc->is_express = 1;
 993
 994     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 995     dc->desc = "Non-Volatile Memory Express";
 996     dc->props = nvme_props;
 997     dc->vmsd = &nvme_vmstate;
 998 }
 999
1000 static void nvme_instance_init(Object *obj)
1001 {
1002     NvmeCtrl *s = NVME(obj);
1003
1004     device_add_bootindex_property(obj, &s->conf.bootindex,
1005                                   "bootindex", "/namespace@1,0",
1006                                   DEVICE(obj), &error_abort);
1007 }
1008
1009 static const TypeInfo nvme_info = {
1010     .name          = "nvme",
1011     .parent        = TYPE_PCI_DEVICE,
1012     .instance_size = sizeof(NvmeCtrl),
1013     .class_init    = nvme_class_init,
1014     .instance_init = nvme_instance_init,
1015 };
1016
1017 static void nvme_register_types(void)
1018 {
1019     type_register_static(&nvme_info);
1020 }
1021
1022 type_init(nvme_register_types)