2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu/osdep.h"
32 #include "qemu/timer.h"
33 #include "hw/ppc/spapr.h"
34 #include "hw/ppc/spapr_cpu_core.h"
35 #include "hw/ppc/xics.h"
36 #include "hw/ppc/xics_spapr.h"
37 #include "hw/ppc/fdt.h"
38 #include "qapi/visitor.h"
44 static target_ulong
h_cppr(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
45 target_ulong opcode
, target_ulong
*args
)
47 target_ulong cppr
= args
[0];
49 icp_set_cppr(spapr_cpu_state(cpu
)->icp
, cppr
);
53 static target_ulong
h_ipi(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
54 target_ulong opcode
, target_ulong
*args
)
56 target_ulong mfrr
= args
[1];
57 ICPState
*icp
= xics_icp_get(XICS_FABRIC(spapr
), args
[0]);
63 icp_set_mfrr(icp
, mfrr
);
67 static target_ulong
h_xirr(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
68 target_ulong opcode
, target_ulong
*args
)
70 uint32_t xirr
= icp_accept(spapr_cpu_state(cpu
)->icp
);
76 static target_ulong
h_xirr_x(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
77 target_ulong opcode
, target_ulong
*args
)
79 uint32_t xirr
= icp_accept(spapr_cpu_state(cpu
)->icp
);
82 args
[1] = cpu_get_host_ticks();
86 static target_ulong
h_eoi(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
87 target_ulong opcode
, target_ulong
*args
)
89 target_ulong xirr
= args
[0];
91 icp_eoi(spapr_cpu_state(cpu
)->icp
, xirr
);
95 static target_ulong
h_ipoll(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
96 target_ulong opcode
, target_ulong
*args
)
98 ICPState
*icp
= xics_icp_get(XICS_FABRIC(spapr
), args
[0]);
106 xirr
= icp_ipoll(icp
, &mfrr
);
114 static void rtas_set_xive(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
116 uint32_t nargs
, target_ulong args
,
117 uint32_t nret
, target_ulong rets
)
119 ICSState
*ics
= spapr
->ics
;
120 uint32_t nr
, srcno
, server
, priority
;
122 if ((nargs
!= 3) || (nret
!= 1)) {
123 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
127 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
131 nr
= rtas_ld(args
, 0);
132 server
= rtas_ld(args
, 1);
133 priority
= rtas_ld(args
, 2);
135 if (!ics_valid_irq(ics
, nr
) || !xics_icp_get(XICS_FABRIC(spapr
), server
)
136 || (priority
> 0xff)) {
137 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
141 srcno
= nr
- ics
->offset
;
142 ics_simple_write_xive(ics
, srcno
, server
, priority
, priority
);
144 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
147 static void rtas_get_xive(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
149 uint32_t nargs
, target_ulong args
,
150 uint32_t nret
, target_ulong rets
)
152 ICSState
*ics
= spapr
->ics
;
155 if ((nargs
!= 1) || (nret
!= 3)) {
156 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
160 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
164 nr
= rtas_ld(args
, 0);
166 if (!ics_valid_irq(ics
, nr
)) {
167 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
171 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
172 srcno
= nr
- ics
->offset
;
173 rtas_st(rets
, 1, ics
->irqs
[srcno
].server
);
174 rtas_st(rets
, 2, ics
->irqs
[srcno
].priority
);
177 static void rtas_int_off(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
179 uint32_t nargs
, target_ulong args
,
180 uint32_t nret
, target_ulong rets
)
182 ICSState
*ics
= spapr
->ics
;
185 if ((nargs
!= 1) || (nret
!= 1)) {
186 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
190 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
194 nr
= rtas_ld(args
, 0);
196 if (!ics_valid_irq(ics
, nr
)) {
197 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
201 srcno
= nr
- ics
->offset
;
202 ics_simple_write_xive(ics
, srcno
, ics
->irqs
[srcno
].server
, 0xff,
203 ics
->irqs
[srcno
].priority
);
205 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
208 static void rtas_int_on(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
210 uint32_t nargs
, target_ulong args
,
211 uint32_t nret
, target_ulong rets
)
213 ICSState
*ics
= spapr
->ics
;
216 if ((nargs
!= 1) || (nret
!= 1)) {
217 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
221 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
225 nr
= rtas_ld(args
, 0);
227 if (!ics_valid_irq(ics
, nr
)) {
228 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
232 srcno
= nr
- ics
->offset
;
233 ics_simple_write_xive(ics
, srcno
, ics
->irqs
[srcno
].server
,
234 ics
->irqs
[srcno
].saved_priority
,
235 ics
->irqs
[srcno
].saved_priority
);
237 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
240 void xics_spapr_init(SpaprMachineState
*spapr
)
242 /* Registration of global state belongs into realize */
243 spapr_rtas_register(RTAS_IBM_SET_XIVE
, "ibm,set-xive", rtas_set_xive
);
244 spapr_rtas_register(RTAS_IBM_GET_XIVE
, "ibm,get-xive", rtas_get_xive
);
245 spapr_rtas_register(RTAS_IBM_INT_OFF
, "ibm,int-off", rtas_int_off
);
246 spapr_rtas_register(RTAS_IBM_INT_ON
, "ibm,int-on", rtas_int_on
);
248 spapr_register_hypercall(H_CPPR
, h_cppr
);
249 spapr_register_hypercall(H_IPI
, h_ipi
);
250 spapr_register_hypercall(H_XIRR
, h_xirr
);
251 spapr_register_hypercall(H_XIRR_X
, h_xirr_x
);
252 spapr_register_hypercall(H_EOI
, h_eoi
);
253 spapr_register_hypercall(H_IPOLL
, h_ipoll
);
256 void spapr_dt_xics(SpaprMachineState
*spapr
, uint32_t nr_servers
, void *fdt
,
259 uint32_t interrupt_server_ranges_prop
[] = {
260 0, cpu_to_be32(nr_servers
),
264 _FDT(node
= fdt_add_subnode(fdt
, 0, XICS_NODENAME
));
266 _FDT(fdt_setprop_string(fdt
, node
, "device_type",
267 "PowerPC-External-Interrupt-Presentation"));
268 _FDT(fdt_setprop_string(fdt
, node
, "compatible", "IBM,ppc-xicp"));
269 _FDT(fdt_setprop(fdt
, node
, "interrupt-controller", NULL
, 0));
270 _FDT(fdt_setprop(fdt
, node
, "ibm,interrupt-server-ranges",
271 interrupt_server_ranges_prop
,
272 sizeof(interrupt_server_ranges_prop
)));
273 _FDT(fdt_setprop_cell(fdt
, node
, "#interrupt-cells", 2));
274 _FDT(fdt_setprop_cell(fdt
, node
, "linux,phandle", phandle
));
275 _FDT(fdt_setprop_cell(fdt
, node
, "phandle", phandle
));