Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging
[qemu/ar7.git] / exec.c
blob3e78de3b8f8bb1914811a796537790bc4df8ad2f
1 /*
2 * Virtual page mapping
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
24 #include "qemu/cutils.h"
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "exec/target_page.h"
28 #include "tcg.h"
29 #include "hw/qdev-core.h"
30 #include "hw/qdev-properties.h"
31 #if !defined(CONFIG_USER_ONLY)
32 #include "hw/boards.h"
33 #include "hw/xen/xen.h"
34 #endif
35 #include "sysemu/kvm.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "qemu/timer.h"
39 #include "qemu/config-file.h"
40 #include "qemu/error-report.h"
41 #include "qemu/qemu-print.h"
42 #if defined(CONFIG_USER_ONLY)
43 #include "qemu.h"
44 #else /* !CONFIG_USER_ONLY */
45 #include "hw/hw.h"
46 #include "exec/memory.h"
47 #include "exec/ioport.h"
48 #include "sysemu/dma.h"
49 #include "sysemu/numa.h"
50 #include "sysemu/hw_accel.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/xen-mapcache.h"
53 #include "trace-root.h"
55 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
56 #include <linux/falloc.h>
57 #endif
59 #endif
60 #include "qemu/rcu_queue.h"
61 #include "qemu/main-loop.h"
62 #include "translate-all.h"
63 #include "sysemu/replay.h"
65 #include "exec/memory-internal.h"
66 #include "exec/ram_addr.h"
67 #include "exec/log.h"
69 #include "migration/vmstate.h"
71 #include "qemu/range.h"
72 #ifndef _WIN32
73 #include "qemu/mmap-alloc.h"
74 #endif
76 #include "monitor/monitor.h"
78 //#define DEBUG_SUBPAGE
80 #if !defined(CONFIG_USER_ONLY)
81 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
82 * are protected by the ramlist lock.
84 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
86 static MemoryRegion *system_memory;
87 static MemoryRegion *system_io;
89 AddressSpace address_space_io;
90 AddressSpace address_space_memory;
92 MemoryRegion io_mem_rom, io_mem_notdirty;
93 static MemoryRegion io_mem_unassigned;
94 #endif
96 #ifdef TARGET_PAGE_BITS_VARY
97 int target_page_bits;
98 bool target_page_bits_decided;
99 #endif
101 CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
103 /* current CPU in the current thread. It is only valid inside
104 cpu_exec() */
105 __thread CPUState *current_cpu;
106 /* 0 = Do not count executed instructions.
107 1 = Precise instruction counting.
108 2 = Adaptive rate instruction counting. */
109 int use_icount;
111 uintptr_t qemu_host_page_size;
112 intptr_t qemu_host_page_mask;
114 bool set_preferred_target_page_bits(int bits)
116 /* The target page size is the lowest common denominator for all
117 * the CPUs in the system, so we can only make it smaller, never
118 * larger. And we can't make it smaller once we've committed to
119 * a particular size.
121 #ifdef TARGET_PAGE_BITS_VARY
122 assert(bits >= TARGET_PAGE_BITS_MIN);
123 if (target_page_bits == 0 || target_page_bits > bits) {
124 if (target_page_bits_decided) {
125 return false;
127 target_page_bits = bits;
129 #endif
130 return true;
133 #if !defined(CONFIG_USER_ONLY)
135 static void finalize_target_page_bits(void)
137 #ifdef TARGET_PAGE_BITS_VARY
138 if (target_page_bits == 0) {
139 target_page_bits = TARGET_PAGE_BITS_MIN;
141 target_page_bits_decided = true;
142 #endif
145 typedef struct PhysPageEntry PhysPageEntry;
147 struct PhysPageEntry {
148 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
149 uint32_t skip : 6;
150 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
151 uint32_t ptr : 26;
154 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
156 /* Size of the L2 (and L3, etc) page tables. */
157 #define ADDR_SPACE_BITS 64
159 #define P_L2_BITS 9
160 #define P_L2_SIZE (1 << P_L2_BITS)
162 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
164 typedef PhysPageEntry Node[P_L2_SIZE];
166 typedef struct PhysPageMap {
167 struct rcu_head rcu;
169 unsigned sections_nb;
170 unsigned sections_nb_alloc;
171 unsigned nodes_nb;
172 unsigned nodes_nb_alloc;
173 Node *nodes;
174 MemoryRegionSection *sections;
175 } PhysPageMap;
177 struct AddressSpaceDispatch {
178 MemoryRegionSection *mru_section;
179 /* This is a multi-level map on the physical address space.
180 * The bottom level has pointers to MemoryRegionSections.
182 PhysPageEntry phys_map;
183 PhysPageMap map;
186 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
187 typedef struct subpage_t {
188 MemoryRegion iomem;
189 FlatView *fv;
190 hwaddr base;
191 uint16_t sub_section[];
192 } subpage_t;
194 #define PHYS_SECTION_UNASSIGNED 0
195 #define PHYS_SECTION_NOTDIRTY 1
196 #define PHYS_SECTION_ROM 2
197 #define PHYS_SECTION_WATCH 3
199 static void io_mem_init(void);
200 static void memory_map_init(void);
201 static void tcg_commit(MemoryListener *listener);
203 static MemoryRegion io_mem_watch;
206 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
207 * @cpu: the CPU whose AddressSpace this is
208 * @as: the AddressSpace itself
209 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
210 * @tcg_as_listener: listener for tracking changes to the AddressSpace
212 struct CPUAddressSpace {
213 CPUState *cpu;
214 AddressSpace *as;
215 struct AddressSpaceDispatch *memory_dispatch;
216 MemoryListener tcg_as_listener;
219 struct DirtyBitmapSnapshot {
220 ram_addr_t start;
221 ram_addr_t end;
222 unsigned long dirty[];
225 #endif
227 #if !defined(CONFIG_USER_ONLY)
229 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
231 static unsigned alloc_hint = 16;
232 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
233 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
234 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
235 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
236 alloc_hint = map->nodes_nb_alloc;
240 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
242 unsigned i;
243 uint32_t ret;
244 PhysPageEntry e;
245 PhysPageEntry *p;
247 ret = map->nodes_nb++;
248 p = map->nodes[ret];
249 assert(ret != PHYS_MAP_NODE_NIL);
250 assert(ret != map->nodes_nb_alloc);
252 e.skip = leaf ? 0 : 1;
253 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
254 for (i = 0; i < P_L2_SIZE; ++i) {
255 memcpy(&p[i], &e, sizeof(e));
257 return ret;
260 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
261 hwaddr *index, hwaddr *nb, uint16_t leaf,
262 int level)
264 PhysPageEntry *p;
265 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
267 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
268 lp->ptr = phys_map_node_alloc(map, level == 0);
270 p = map->nodes[lp->ptr];
271 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
273 while (*nb && lp < &p[P_L2_SIZE]) {
274 if ((*index & (step - 1)) == 0 && *nb >= step) {
275 lp->skip = 0;
276 lp->ptr = leaf;
277 *index += step;
278 *nb -= step;
279 } else {
280 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
282 ++lp;
286 static void phys_page_set(AddressSpaceDispatch *d,
287 hwaddr index, hwaddr nb,
288 uint16_t leaf)
290 /* Wildly overreserve - it doesn't matter much. */
291 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
293 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
296 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
297 * and update our entry so we can skip it and go directly to the destination.
299 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
301 unsigned valid_ptr = P_L2_SIZE;
302 int valid = 0;
303 PhysPageEntry *p;
304 int i;
306 if (lp->ptr == PHYS_MAP_NODE_NIL) {
307 return;
310 p = nodes[lp->ptr];
311 for (i = 0; i < P_L2_SIZE; i++) {
312 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
313 continue;
316 valid_ptr = i;
317 valid++;
318 if (p[i].skip) {
319 phys_page_compact(&p[i], nodes);
323 /* We can only compress if there's only one child. */
324 if (valid != 1) {
325 return;
328 assert(valid_ptr < P_L2_SIZE);
330 /* Don't compress if it won't fit in the # of bits we have. */
331 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
332 return;
335 lp->ptr = p[valid_ptr].ptr;
336 if (!p[valid_ptr].skip) {
337 /* If our only child is a leaf, make this a leaf. */
338 /* By design, we should have made this node a leaf to begin with so we
339 * should never reach here.
340 * But since it's so simple to handle this, let's do it just in case we
341 * change this rule.
343 lp->skip = 0;
344 } else {
345 lp->skip += p[valid_ptr].skip;
349 void address_space_dispatch_compact(AddressSpaceDispatch *d)
351 if (d->phys_map.skip) {
352 phys_page_compact(&d->phys_map, d->map.nodes);
356 static inline bool section_covers_addr(const MemoryRegionSection *section,
357 hwaddr addr)
359 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
360 * the section must cover the entire address space.
362 return int128_gethi(section->size) ||
363 range_covers_byte(section->offset_within_address_space,
364 int128_getlo(section->size), addr);
367 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
369 PhysPageEntry lp = d->phys_map, *p;
370 Node *nodes = d->map.nodes;
371 MemoryRegionSection *sections = d->map.sections;
372 hwaddr index = addr >> TARGET_PAGE_BITS;
373 int i;
375 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
376 if (lp.ptr == PHYS_MAP_NODE_NIL) {
377 return &sections[PHYS_SECTION_UNASSIGNED];
379 p = nodes[lp.ptr];
380 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
383 if (section_covers_addr(&sections[lp.ptr], addr)) {
384 return &sections[lp.ptr];
385 } else {
386 return &sections[PHYS_SECTION_UNASSIGNED];
390 /* Called from RCU critical section */
391 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
392 hwaddr addr,
393 bool resolve_subpage)
395 MemoryRegionSection *section = atomic_read(&d->mru_section);
396 subpage_t *subpage;
398 if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
399 !section_covers_addr(section, addr)) {
400 section = phys_page_find(d, addr);
401 atomic_set(&d->mru_section, section);
403 if (resolve_subpage && section->mr->subpage) {
404 subpage = container_of(section->mr, subpage_t, iomem);
405 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
407 return section;
410 /* Called from RCU critical section */
411 static MemoryRegionSection *
412 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
413 hwaddr *plen, bool resolve_subpage)
415 MemoryRegionSection *section;
416 MemoryRegion *mr;
417 Int128 diff;
419 section = address_space_lookup_region(d, addr, resolve_subpage);
420 /* Compute offset within MemoryRegionSection */
421 addr -= section->offset_within_address_space;
423 /* Compute offset within MemoryRegion */
424 *xlat = addr + section->offset_within_region;
426 mr = section->mr;
428 /* MMIO registers can be expected to perform full-width accesses based only
429 * on their address, without considering adjacent registers that could
430 * decode to completely different MemoryRegions. When such registers
431 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
432 * regions overlap wildly. For this reason we cannot clamp the accesses
433 * here.
435 * If the length is small (as is the case for address_space_ldl/stl),
436 * everything works fine. If the incoming length is large, however,
437 * the caller really has to do the clamping through memory_access_size.
439 if (memory_region_is_ram(mr)) {
440 diff = int128_sub(section->size, int128_make64(addr));
441 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
443 return section;
447 * address_space_translate_iommu - translate an address through an IOMMU
448 * memory region and then through the target address space.
450 * @iommu_mr: the IOMMU memory region that we start the translation from
451 * @addr: the address to be translated through the MMU
452 * @xlat: the translated address offset within the destination memory region.
453 * It cannot be %NULL.
454 * @plen_out: valid read/write length of the translated address. It
455 * cannot be %NULL.
456 * @page_mask_out: page mask for the translated address. This
457 * should only be meaningful for IOMMU translated
458 * addresses, since there may be huge pages that this bit
459 * would tell. It can be %NULL if we don't care about it.
460 * @is_write: whether the translation operation is for write
461 * @is_mmio: whether this can be MMIO, set true if it can
462 * @target_as: the address space targeted by the IOMMU
463 * @attrs: transaction attributes
465 * This function is called from RCU critical section. It is the common
466 * part of flatview_do_translate and address_space_translate_cached.
468 static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr,
469 hwaddr *xlat,
470 hwaddr *plen_out,
471 hwaddr *page_mask_out,
472 bool is_write,
473 bool is_mmio,
474 AddressSpace **target_as,
475 MemTxAttrs attrs)
477 MemoryRegionSection *section;
478 hwaddr page_mask = (hwaddr)-1;
480 do {
481 hwaddr addr = *xlat;
482 IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
483 int iommu_idx = 0;
484 IOMMUTLBEntry iotlb;
486 if (imrc->attrs_to_index) {
487 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
490 iotlb = imrc->translate(iommu_mr, addr, is_write ?
491 IOMMU_WO : IOMMU_RO, iommu_idx);
493 if (!(iotlb.perm & (1 << is_write))) {
494 goto unassigned;
497 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
498 | (addr & iotlb.addr_mask));
499 page_mask &= iotlb.addr_mask;
500 *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1);
501 *target_as = iotlb.target_as;
503 section = address_space_translate_internal(
504 address_space_to_dispatch(iotlb.target_as), addr, xlat,
505 plen_out, is_mmio);
507 iommu_mr = memory_region_get_iommu(section->mr);
508 } while (unlikely(iommu_mr));
510 if (page_mask_out) {
511 *page_mask_out = page_mask;
513 return *section;
515 unassigned:
516 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
520 * flatview_do_translate - translate an address in FlatView
522 * @fv: the flat view that we want to translate on
523 * @addr: the address to be translated in above address space
524 * @xlat: the translated address offset within memory region. It
525 * cannot be @NULL.
526 * @plen_out: valid read/write length of the translated address. It
527 * can be @NULL when we don't care about it.
528 * @page_mask_out: page mask for the translated address. This
529 * should only be meaningful for IOMMU translated
530 * addresses, since there may be huge pages that this bit
531 * would tell. It can be @NULL if we don't care about it.
532 * @is_write: whether the translation operation is for write
533 * @is_mmio: whether this can be MMIO, set true if it can
534 * @target_as: the address space targeted by the IOMMU
535 * @attrs: memory transaction attributes
537 * This function is called from RCU critical section
539 static MemoryRegionSection flatview_do_translate(FlatView *fv,
540 hwaddr addr,
541 hwaddr *xlat,
542 hwaddr *plen_out,
543 hwaddr *page_mask_out,
544 bool is_write,
545 bool is_mmio,
546 AddressSpace **target_as,
547 MemTxAttrs attrs)
549 MemoryRegionSection *section;
550 IOMMUMemoryRegion *iommu_mr;
551 hwaddr plen = (hwaddr)(-1);
553 if (!plen_out) {
554 plen_out = &plen;
557 section = address_space_translate_internal(
558 flatview_to_dispatch(fv), addr, xlat,
559 plen_out, is_mmio);
561 iommu_mr = memory_region_get_iommu(section->mr);
562 if (unlikely(iommu_mr)) {
563 return address_space_translate_iommu(iommu_mr, xlat,
564 plen_out, page_mask_out,
565 is_write, is_mmio,
566 target_as, attrs);
568 if (page_mask_out) {
569 /* Not behind an IOMMU, use default page size. */
570 *page_mask_out = ~TARGET_PAGE_MASK;
573 return *section;
576 /* Called from RCU critical section */
577 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
578 bool is_write, MemTxAttrs attrs)
580 MemoryRegionSection section;
581 hwaddr xlat, page_mask;
584 * This can never be MMIO, and we don't really care about plen,
585 * but page mask.
587 section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
588 NULL, &page_mask, is_write, false, &as,
589 attrs);
591 /* Illegal translation */
592 if (section.mr == &io_mem_unassigned) {
593 goto iotlb_fail;
596 /* Convert memory region offset into address space offset */
597 xlat += section.offset_within_address_space -
598 section.offset_within_region;
600 return (IOMMUTLBEntry) {
601 .target_as = as,
602 .iova = addr & ~page_mask,
603 .translated_addr = xlat & ~page_mask,
604 .addr_mask = page_mask,
605 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
606 .perm = IOMMU_RW,
609 iotlb_fail:
610 return (IOMMUTLBEntry) {0};
613 /* Called from RCU critical section */
614 MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
615 hwaddr *plen, bool is_write,
616 MemTxAttrs attrs)
618 MemoryRegion *mr;
619 MemoryRegionSection section;
620 AddressSpace *as = NULL;
622 /* This can be MMIO, so setup MMIO bit. */
623 section = flatview_do_translate(fv, addr, xlat, plen, NULL,
624 is_write, true, &as, attrs);
625 mr = section.mr;
627 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
628 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
629 *plen = MIN(page, *plen);
632 return mr;
635 typedef struct TCGIOMMUNotifier {
636 IOMMUNotifier n;
637 MemoryRegion *mr;
638 CPUState *cpu;
639 int iommu_idx;
640 bool active;
641 } TCGIOMMUNotifier;
643 static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb)
645 TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n);
647 if (!notifier->active) {
648 return;
650 tlb_flush(notifier->cpu);
651 notifier->active = false;
652 /* We leave the notifier struct on the list to avoid reallocating it later.
653 * Generally the number of IOMMUs a CPU deals with will be small.
654 * In any case we can't unregister the iommu notifier from a notify
655 * callback.
659 static void tcg_register_iommu_notifier(CPUState *cpu,
660 IOMMUMemoryRegion *iommu_mr,
661 int iommu_idx)
663 /* Make sure this CPU has an IOMMU notifier registered for this
664 * IOMMU/IOMMU index combination, so that we can flush its TLB
665 * when the IOMMU tells us the mappings we've cached have changed.
667 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
668 TCGIOMMUNotifier *notifier;
669 int i;
671 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
672 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
673 if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) {
674 break;
677 if (i == cpu->iommu_notifiers->len) {
678 /* Not found, add a new entry at the end of the array */
679 cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1);
680 notifier = g_new0(TCGIOMMUNotifier, 1);
681 g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i) = notifier;
683 notifier->mr = mr;
684 notifier->iommu_idx = iommu_idx;
685 notifier->cpu = cpu;
686 /* Rather than trying to register interest in the specific part
687 * of the iommu's address space that we've accessed and then
688 * expand it later as subsequent accesses touch more of it, we
689 * just register interest in the whole thing, on the assumption
690 * that iommu reconfiguration will be rare.
692 iommu_notifier_init(&notifier->n,
693 tcg_iommu_unmap_notify,
694 IOMMU_NOTIFIER_UNMAP,
696 HWADDR_MAX,
697 iommu_idx);
698 memory_region_register_iommu_notifier(notifier->mr, &notifier->n);
701 if (!notifier->active) {
702 notifier->active = true;
706 static void tcg_iommu_free_notifier_list(CPUState *cpu)
708 /* Destroy the CPU's notifier list */
709 int i;
710 TCGIOMMUNotifier *notifier;
712 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
713 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
714 memory_region_unregister_iommu_notifier(notifier->mr, &notifier->n);
715 g_free(notifier);
717 g_array_free(cpu->iommu_notifiers, true);
720 /* Called from RCU critical section */
721 MemoryRegionSection *
722 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
723 hwaddr *xlat, hwaddr *plen,
724 MemTxAttrs attrs, int *prot)
726 MemoryRegionSection *section;
727 IOMMUMemoryRegion *iommu_mr;
728 IOMMUMemoryRegionClass *imrc;
729 IOMMUTLBEntry iotlb;
730 int iommu_idx;
731 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
733 for (;;) {
734 section = address_space_translate_internal(d, addr, &addr, plen, false);
736 iommu_mr = memory_region_get_iommu(section->mr);
737 if (!iommu_mr) {
738 break;
741 imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
743 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
744 tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx);
745 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
746 * doesn't short-cut its translation table walk.
748 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx);
749 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
750 | (addr & iotlb.addr_mask));
751 /* Update the caller's prot bits to remove permissions the IOMMU
752 * is giving us a failure response for. If we get down to no
753 * permissions left at all we can give up now.
755 if (!(iotlb.perm & IOMMU_RO)) {
756 *prot &= ~(PAGE_READ | PAGE_EXEC);
758 if (!(iotlb.perm & IOMMU_WO)) {
759 *prot &= ~PAGE_WRITE;
762 if (!*prot) {
763 goto translate_fail;
766 d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as));
769 assert(!memory_region_is_iommu(section->mr));
770 *xlat = addr;
771 return section;
773 translate_fail:
774 return &d->map.sections[PHYS_SECTION_UNASSIGNED];
776 #endif
778 #if !defined(CONFIG_USER_ONLY)
780 static int cpu_common_post_load(void *opaque, int version_id)
782 CPUState *cpu = opaque;
784 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
785 version_id is increased. */
786 cpu->interrupt_request &= ~0x01;
787 tlb_flush(cpu);
789 /* loadvm has just updated the content of RAM, bypassing the
790 * usual mechanisms that ensure we flush TBs for writes to
791 * memory we've translated code from. So we must flush all TBs,
792 * which will now be stale.
794 tb_flush(cpu);
796 return 0;
799 static int cpu_common_pre_load(void *opaque)
801 CPUState *cpu = opaque;
803 cpu->exception_index = -1;
805 return 0;
808 static bool cpu_common_exception_index_needed(void *opaque)
810 CPUState *cpu = opaque;
812 return tcg_enabled() && cpu->exception_index != -1;
815 static const VMStateDescription vmstate_cpu_common_exception_index = {
816 .name = "cpu_common/exception_index",
817 .version_id = 1,
818 .minimum_version_id = 1,
819 .needed = cpu_common_exception_index_needed,
820 .fields = (VMStateField[]) {
821 VMSTATE_INT32(exception_index, CPUState),
822 VMSTATE_END_OF_LIST()
826 static bool cpu_common_crash_occurred_needed(void *opaque)
828 CPUState *cpu = opaque;
830 return cpu->crash_occurred;
833 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
834 .name = "cpu_common/crash_occurred",
835 .version_id = 1,
836 .minimum_version_id = 1,
837 .needed = cpu_common_crash_occurred_needed,
838 .fields = (VMStateField[]) {
839 VMSTATE_BOOL(crash_occurred, CPUState),
840 VMSTATE_END_OF_LIST()
844 const VMStateDescription vmstate_cpu_common = {
845 .name = "cpu_common",
846 .version_id = 1,
847 .minimum_version_id = 1,
848 .pre_load = cpu_common_pre_load,
849 .post_load = cpu_common_post_load,
850 .fields = (VMStateField[]) {
851 VMSTATE_UINT32(halted, CPUState),
852 VMSTATE_UINT32(interrupt_request, CPUState),
853 VMSTATE_END_OF_LIST()
855 .subsections = (const VMStateDescription*[]) {
856 &vmstate_cpu_common_exception_index,
857 &vmstate_cpu_common_crash_occurred,
858 NULL
862 #endif
864 CPUState *qemu_get_cpu(int index)
866 CPUState *cpu;
868 CPU_FOREACH(cpu) {
869 if (cpu->cpu_index == index) {
870 return cpu;
874 return NULL;
877 #if !defined(CONFIG_USER_ONLY)
878 void cpu_address_space_init(CPUState *cpu, int asidx,
879 const char *prefix, MemoryRegion *mr)
881 CPUAddressSpace *newas;
882 AddressSpace *as = g_new0(AddressSpace, 1);
883 char *as_name;
885 assert(mr);
886 as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index);
887 address_space_init(as, mr, as_name);
888 g_free(as_name);
890 /* Target code should have set num_ases before calling us */
891 assert(asidx < cpu->num_ases);
893 if (asidx == 0) {
894 /* address space 0 gets the convenience alias */
895 cpu->as = as;
898 /* KVM cannot currently support multiple address spaces. */
899 assert(asidx == 0 || !kvm_enabled());
901 if (!cpu->cpu_ases) {
902 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
905 newas = &cpu->cpu_ases[asidx];
906 newas->cpu = cpu;
907 newas->as = as;
908 if (tcg_enabled()) {
909 newas->tcg_as_listener.commit = tcg_commit;
910 memory_listener_register(&newas->tcg_as_listener, as);
914 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
916 /* Return the AddressSpace corresponding to the specified index */
917 return cpu->cpu_ases[asidx].as;
919 #endif
921 void cpu_exec_unrealizefn(CPUState *cpu)
923 CPUClass *cc = CPU_GET_CLASS(cpu);
925 cpu_list_remove(cpu);
927 if (cc->vmsd != NULL) {
928 vmstate_unregister(NULL, cc->vmsd, cpu);
930 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
931 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
933 #ifndef CONFIG_USER_ONLY
934 tcg_iommu_free_notifier_list(cpu);
935 #endif
938 Property cpu_common_props[] = {
939 #ifndef CONFIG_USER_ONLY
940 /* Create a memory property for softmmu CPU object,
941 * so users can wire up its memory. (This can't go in qom/cpu.c
942 * because that file is compiled only once for both user-mode
943 * and system builds.) The default if no link is set up is to use
944 * the system address space.
946 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
947 MemoryRegion *),
948 #endif
949 DEFINE_PROP_END_OF_LIST(),
952 void cpu_exec_initfn(CPUState *cpu)
954 cpu->as = NULL;
955 cpu->num_ases = 0;
957 #ifndef CONFIG_USER_ONLY
958 cpu->thread_id = qemu_get_thread_id();
959 cpu->memory = system_memory;
960 object_ref(OBJECT(cpu->memory));
961 #endif
964 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
966 CPUClass *cc = CPU_GET_CLASS(cpu);
967 static bool tcg_target_initialized;
969 cpu_list_add(cpu);
971 if (tcg_enabled() && !tcg_target_initialized) {
972 tcg_target_initialized = true;
973 cc->tcg_initialize();
975 tlb_init(cpu);
977 #ifndef CONFIG_USER_ONLY
978 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
979 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
981 if (cc->vmsd != NULL) {
982 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
985 cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *));
986 #endif
989 const char *parse_cpu_option(const char *cpu_option)
991 ObjectClass *oc;
992 CPUClass *cc;
993 gchar **model_pieces;
994 const char *cpu_type;
996 model_pieces = g_strsplit(cpu_option, ",", 2);
997 if (!model_pieces[0]) {
998 error_report("-cpu option cannot be empty");
999 exit(1);
1002 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
1003 if (oc == NULL) {
1004 error_report("unable to find CPU model '%s'", model_pieces[0]);
1005 g_strfreev(model_pieces);
1006 exit(EXIT_FAILURE);
1009 cpu_type = object_class_get_name(oc);
1010 cc = CPU_CLASS(oc);
1011 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
1012 g_strfreev(model_pieces);
1013 return cpu_type;
1016 #if defined(CONFIG_USER_ONLY)
1017 void tb_invalidate_phys_addr(target_ulong addr)
1019 mmap_lock();
1020 tb_invalidate_phys_page_range(addr, addr + 1, 0);
1021 mmap_unlock();
1024 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
1026 tb_invalidate_phys_addr(pc);
1028 #else
1029 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
1031 ram_addr_t ram_addr;
1032 MemoryRegion *mr;
1033 hwaddr l = 1;
1035 if (!tcg_enabled()) {
1036 return;
1039 rcu_read_lock();
1040 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
1041 if (!(memory_region_is_ram(mr)
1042 || memory_region_is_romd(mr))) {
1043 rcu_read_unlock();
1044 return;
1046 ram_addr = memory_region_get_ram_addr(mr) + addr;
1047 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
1048 rcu_read_unlock();
1051 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
1053 MemTxAttrs attrs;
1054 hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
1055 int asidx = cpu_asidx_from_attrs(cpu, attrs);
1056 if (phys != -1) {
1057 /* Locks grabbed by tb_invalidate_phys_addr */
1058 tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
1059 phys | (pc & ~TARGET_PAGE_MASK), attrs);
1062 #endif
1064 #if defined(CONFIG_USER_ONLY)
1065 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1070 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
1071 int flags)
1073 return -ENOSYS;
1076 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
1080 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1081 int flags, CPUWatchpoint **watchpoint)
1083 return -ENOSYS;
1085 #else
1086 /* Add a watchpoint. */
1087 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1088 int flags, CPUWatchpoint **watchpoint)
1090 CPUWatchpoint *wp;
1092 /* forbid ranges which are empty or run off the end of the address space */
1093 if (len == 0 || (addr + len - 1) < addr) {
1094 error_report("tried to set invalid watchpoint at %"
1095 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
1096 return -EINVAL;
1098 wp = g_malloc(sizeof(*wp));
1100 wp->vaddr = addr;
1101 wp->len = len;
1102 wp->flags = flags;
1104 /* keep all GDB-injected watchpoints in front */
1105 if (flags & BP_GDB) {
1106 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
1107 } else {
1108 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
1111 tlb_flush_page(cpu, addr);
1113 if (watchpoint)
1114 *watchpoint = wp;
1115 return 0;
1118 /* Remove a specific watchpoint. */
1119 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
1120 int flags)
1122 CPUWatchpoint *wp;
1124 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1125 if (addr == wp->vaddr && len == wp->len
1126 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
1127 cpu_watchpoint_remove_by_ref(cpu, wp);
1128 return 0;
1131 return -ENOENT;
1134 /* Remove a specific watchpoint by reference. */
1135 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
1137 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
1139 tlb_flush_page(cpu, watchpoint->vaddr);
1141 g_free(watchpoint);
1144 /* Remove all matching watchpoints. */
1145 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1147 CPUWatchpoint *wp, *next;
1149 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
1150 if (wp->flags & mask) {
1151 cpu_watchpoint_remove_by_ref(cpu, wp);
1156 /* Return true if this watchpoint address matches the specified
1157 * access (ie the address range covered by the watchpoint overlaps
1158 * partially or completely with the address range covered by the
1159 * access).
1161 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
1162 vaddr addr,
1163 vaddr len)
1165 /* We know the lengths are non-zero, but a little caution is
1166 * required to avoid errors in the case where the range ends
1167 * exactly at the top of the address space and so addr + len
1168 * wraps round to zero.
1170 vaddr wpend = wp->vaddr + wp->len - 1;
1171 vaddr addrend = addr + len - 1;
1173 return !(addr > wpend || wp->vaddr > addrend);
1176 #endif
1178 /* Add a breakpoint. */
1179 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1180 CPUBreakpoint **breakpoint)
1182 CPUBreakpoint *bp;
1184 bp = g_malloc(sizeof(*bp));
1186 bp->pc = pc;
1187 bp->flags = flags;
1189 /* keep all GDB-injected breakpoints in front */
1190 if (flags & BP_GDB) {
1191 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
1192 } else {
1193 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
1196 breakpoint_invalidate(cpu, pc);
1198 if (breakpoint) {
1199 *breakpoint = bp;
1201 return 0;
1204 /* Remove a specific breakpoint. */
1205 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
1207 CPUBreakpoint *bp;
1209 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1210 if (bp->pc == pc && bp->flags == flags) {
1211 cpu_breakpoint_remove_by_ref(cpu, bp);
1212 return 0;
1215 return -ENOENT;
1218 /* Remove a specific breakpoint by reference. */
1219 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
1221 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
1223 breakpoint_invalidate(cpu, breakpoint->pc);
1225 g_free(breakpoint);
1228 /* Remove all matching breakpoints. */
1229 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
1231 CPUBreakpoint *bp, *next;
1233 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
1234 if (bp->flags & mask) {
1235 cpu_breakpoint_remove_by_ref(cpu, bp);
1240 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1241 CPU loop after each instruction */
1242 void cpu_single_step(CPUState *cpu, int enabled)
1244 if (cpu->singlestep_enabled != enabled) {
1245 cpu->singlestep_enabled = enabled;
1246 if (kvm_enabled()) {
1247 kvm_update_guest_debug(cpu, 0);
1248 } else {
1249 /* must flush all the translated code to avoid inconsistencies */
1250 /* XXX: only flush what is necessary */
1251 tb_flush(cpu);
1256 void cpu_abort(CPUState *cpu, const char *fmt, ...)
1258 va_list ap;
1259 va_list ap2;
1261 va_start(ap, fmt);
1262 va_copy(ap2, ap);
1263 fprintf(stderr, "qemu: fatal: ");
1264 vfprintf(stderr, fmt, ap);
1265 fprintf(stderr, "\n");
1266 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1267 if (qemu_log_separate()) {
1268 qemu_log_lock();
1269 qemu_log("qemu: fatal: ");
1270 qemu_log_vprintf(fmt, ap2);
1271 qemu_log("\n");
1272 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1273 qemu_log_flush();
1274 qemu_log_unlock();
1275 qemu_log_close();
1277 va_end(ap2);
1278 va_end(ap);
1279 replay_finish();
1280 #if defined(CONFIG_USER_ONLY)
1282 struct sigaction act;
1283 sigfillset(&act.sa_mask);
1284 act.sa_handler = SIG_DFL;
1285 act.sa_flags = 0;
1286 sigaction(SIGABRT, &act, NULL);
1288 #endif
1289 abort();
1292 #if !defined(CONFIG_USER_ONLY)
1293 /* Called from RCU critical section */
1294 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1296 RAMBlock *block;
1298 block = atomic_rcu_read(&ram_list.mru_block);
1299 if (block && addr - block->offset < block->max_length) {
1300 return block;
1302 RAMBLOCK_FOREACH(block) {
1303 if (addr - block->offset < block->max_length) {
1304 goto found;
1308 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1309 abort();
1311 found:
1312 /* It is safe to write mru_block outside the iothread lock. This
1313 * is what happens:
1315 * mru_block = xxx
1316 * rcu_read_unlock()
1317 * xxx removed from list
1318 * rcu_read_lock()
1319 * read mru_block
1320 * mru_block = NULL;
1321 * call_rcu(reclaim_ramblock, xxx);
1322 * rcu_read_unlock()
1324 * atomic_rcu_set is not needed here. The block was already published
1325 * when it was placed into the list. Here we're just making an extra
1326 * copy of the pointer.
1328 ram_list.mru_block = block;
1329 return block;
1332 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1334 CPUState *cpu;
1335 ram_addr_t start1;
1336 RAMBlock *block;
1337 ram_addr_t end;
1339 assert(tcg_enabled());
1340 end = TARGET_PAGE_ALIGN(start + length);
1341 start &= TARGET_PAGE_MASK;
1343 rcu_read_lock();
1344 block = qemu_get_ram_block(start);
1345 assert(block == qemu_get_ram_block(end - 1));
1346 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1347 CPU_FOREACH(cpu) {
1348 tlb_reset_dirty(cpu, start1, length);
1350 rcu_read_unlock();
1353 /* Note: start and end must be within the same ram block. */
1354 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1355 ram_addr_t length,
1356 unsigned client)
1358 DirtyMemoryBlocks *blocks;
1359 unsigned long end, page;
1360 bool dirty = false;
1361 RAMBlock *ramblock;
1362 uint64_t mr_offset, mr_size;
1364 if (length == 0) {
1365 return false;
1368 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1369 page = start >> TARGET_PAGE_BITS;
1371 rcu_read_lock();
1373 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1374 ramblock = qemu_get_ram_block(start);
1375 /* Range sanity check on the ramblock */
1376 assert(start >= ramblock->offset &&
1377 start + length <= ramblock->offset + ramblock->used_length);
1379 while (page < end) {
1380 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1381 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1382 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1384 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1385 offset, num);
1386 page += num;
1389 mr_offset = (ram_addr_t)(page << TARGET_PAGE_BITS) - ramblock->offset;
1390 mr_size = (end - page) << TARGET_PAGE_BITS;
1391 memory_region_clear_dirty_bitmap(ramblock->mr, mr_offset, mr_size);
1393 rcu_read_unlock();
1395 if (dirty && tcg_enabled()) {
1396 tlb_reset_dirty_range_all(start, length);
1399 return dirty;
1402 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1403 (MemoryRegion *mr, hwaddr offset, hwaddr length, unsigned client)
1405 DirtyMemoryBlocks *blocks;
1406 ram_addr_t start = memory_region_get_ram_addr(mr) + offset;
1407 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1408 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1409 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1410 DirtyBitmapSnapshot *snap;
1411 unsigned long page, end, dest;
1413 snap = g_malloc0(sizeof(*snap) +
1414 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1415 snap->start = first;
1416 snap->end = last;
1418 page = first >> TARGET_PAGE_BITS;
1419 end = last >> TARGET_PAGE_BITS;
1420 dest = 0;
1422 rcu_read_lock();
1424 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1426 while (page < end) {
1427 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1428 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1429 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1431 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1432 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1433 offset >>= BITS_PER_LEVEL;
1435 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1436 blocks->blocks[idx] + offset,
1437 num);
1438 page += num;
1439 dest += num >> BITS_PER_LEVEL;
1442 rcu_read_unlock();
1444 if (tcg_enabled()) {
1445 tlb_reset_dirty_range_all(start, length);
1448 memory_region_clear_dirty_bitmap(mr, offset, length);
1450 return snap;
1453 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1454 ram_addr_t start,
1455 ram_addr_t length)
1457 unsigned long page, end;
1459 assert(start >= snap->start);
1460 assert(start + length <= snap->end);
1462 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1463 page = (start - snap->start) >> TARGET_PAGE_BITS;
1465 while (page < end) {
1466 if (test_bit(page, snap->dirty)) {
1467 return true;
1469 page++;
1471 return false;
1474 /* Called from RCU critical section */
1475 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1476 MemoryRegionSection *section,
1477 target_ulong vaddr,
1478 hwaddr paddr, hwaddr xlat,
1479 int prot,
1480 target_ulong *address)
1482 hwaddr iotlb;
1483 CPUWatchpoint *wp;
1485 if (memory_region_is_ram(section->mr)) {
1486 /* Normal RAM. */
1487 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1488 if (!section->readonly) {
1489 iotlb |= PHYS_SECTION_NOTDIRTY;
1490 } else {
1491 iotlb |= PHYS_SECTION_ROM;
1493 } else {
1494 AddressSpaceDispatch *d;
1496 d = flatview_to_dispatch(section->fv);
1497 iotlb = section - d->map.sections;
1498 iotlb += xlat;
1501 /* Make accesses to pages with watchpoints go via the
1502 watchpoint trap routines. */
1503 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1504 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1505 /* Avoid trapping reads of pages with a write breakpoint. */
1506 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1507 iotlb = PHYS_SECTION_WATCH + paddr;
1508 *address |= TLB_MMIO;
1509 break;
1514 return iotlb;
1516 #endif /* defined(CONFIG_USER_ONLY) */
1518 #if !defined(CONFIG_USER_ONLY)
1520 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1521 uint16_t section);
1522 static subpage_t *subpage_init(FlatView *fv, hwaddr base);
1524 static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) =
1525 qemu_anon_ram_alloc;
1528 * Set a custom physical guest memory alloator.
1529 * Accelerators with unusual needs may need this. Hopefully, we can
1530 * get rid of it eventually.
1532 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align, bool shared))
1534 phys_mem_alloc = alloc;
1537 static uint16_t phys_section_add(PhysPageMap *map,
1538 MemoryRegionSection *section)
1540 /* The physical section number is ORed with a page-aligned
1541 * pointer to produce the iotlb entries. Thus it should
1542 * never overflow into the page-aligned value.
1544 assert(map->sections_nb < TARGET_PAGE_SIZE);
1546 if (map->sections_nb == map->sections_nb_alloc) {
1547 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1548 map->sections = g_renew(MemoryRegionSection, map->sections,
1549 map->sections_nb_alloc);
1551 map->sections[map->sections_nb] = *section;
1552 memory_region_ref(section->mr);
1553 return map->sections_nb++;
1556 static void phys_section_destroy(MemoryRegion *mr)
1558 bool have_sub_page = mr->subpage;
1560 memory_region_unref(mr);
1562 if (have_sub_page) {
1563 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1564 object_unref(OBJECT(&subpage->iomem));
1565 g_free(subpage);
1569 static void phys_sections_free(PhysPageMap *map)
1571 while (map->sections_nb > 0) {
1572 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1573 phys_section_destroy(section->mr);
1575 g_free(map->sections);
1576 g_free(map->nodes);
1579 static void register_subpage(FlatView *fv, MemoryRegionSection *section)
1581 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1582 subpage_t *subpage;
1583 hwaddr base = section->offset_within_address_space
1584 & TARGET_PAGE_MASK;
1585 MemoryRegionSection *existing = phys_page_find(d, base);
1586 MemoryRegionSection subsection = {
1587 .offset_within_address_space = base,
1588 .size = int128_make64(TARGET_PAGE_SIZE),
1590 hwaddr start, end;
1592 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1594 if (!(existing->mr->subpage)) {
1595 subpage = subpage_init(fv, base);
1596 subsection.fv = fv;
1597 subsection.mr = &subpage->iomem;
1598 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1599 phys_section_add(&d->map, &subsection));
1600 } else {
1601 subpage = container_of(existing->mr, subpage_t, iomem);
1603 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1604 end = start + int128_get64(section->size) - 1;
1605 subpage_register(subpage, start, end,
1606 phys_section_add(&d->map, section));
1610 static void register_multipage(FlatView *fv,
1611 MemoryRegionSection *section)
1613 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1614 hwaddr start_addr = section->offset_within_address_space;
1615 uint16_t section_index = phys_section_add(&d->map, section);
1616 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1617 TARGET_PAGE_BITS));
1619 assert(num_pages);
1620 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1624 * The range in *section* may look like this:
1626 * |s|PPPPPPP|s|
1628 * where s stands for subpage and P for page.
1630 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section)
1632 MemoryRegionSection remain = *section;
1633 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1635 /* register first subpage */
1636 if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1637 uint64_t left = TARGET_PAGE_ALIGN(remain.offset_within_address_space)
1638 - remain.offset_within_address_space;
1640 MemoryRegionSection now = remain;
1641 now.size = int128_min(int128_make64(left), now.size);
1642 register_subpage(fv, &now);
1643 if (int128_eq(remain.size, now.size)) {
1644 return;
1646 remain.size = int128_sub(remain.size, now.size);
1647 remain.offset_within_address_space += int128_get64(now.size);
1648 remain.offset_within_region += int128_get64(now.size);
1651 /* register whole pages */
1652 if (int128_ge(remain.size, page_size)) {
1653 MemoryRegionSection now = remain;
1654 now.size = int128_and(now.size, int128_neg(page_size));
1655 register_multipage(fv, &now);
1656 if (int128_eq(remain.size, now.size)) {
1657 return;
1659 remain.size = int128_sub(remain.size, now.size);
1660 remain.offset_within_address_space += int128_get64(now.size);
1661 remain.offset_within_region += int128_get64(now.size);
1664 /* register last subpage */
1665 register_subpage(fv, &remain);
1668 void qemu_flush_coalesced_mmio_buffer(void)
1670 if (kvm_enabled())
1671 kvm_flush_coalesced_mmio_buffer();
1674 void qemu_mutex_lock_ramlist(void)
1676 qemu_mutex_lock(&ram_list.mutex);
1679 void qemu_mutex_unlock_ramlist(void)
1681 qemu_mutex_unlock(&ram_list.mutex);
1684 void ram_block_dump(Monitor *mon)
1686 RAMBlock *block;
1687 char *psize;
1689 rcu_read_lock();
1690 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1691 "Block Name", "PSize", "Offset", "Used", "Total");
1692 RAMBLOCK_FOREACH(block) {
1693 psize = size_to_str(block->page_size);
1694 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1695 " 0x%016" PRIx64 "\n", block->idstr, psize,
1696 (uint64_t)block->offset,
1697 (uint64_t)block->used_length,
1698 (uint64_t)block->max_length);
1699 g_free(psize);
1701 rcu_read_unlock();
1704 #ifdef __linux__
1706 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1707 * may or may not name the same files / on the same filesystem now as
1708 * when we actually open and map them. Iterate over the file
1709 * descriptors instead, and use qemu_fd_getpagesize().
1711 static int find_min_backend_pagesize(Object *obj, void *opaque)
1713 long *hpsize_min = opaque;
1715 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1716 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1717 long hpsize = host_memory_backend_pagesize(backend);
1719 if (host_memory_backend_is_mapped(backend) && (hpsize < *hpsize_min)) {
1720 *hpsize_min = hpsize;
1724 return 0;
1727 static int find_max_backend_pagesize(Object *obj, void *opaque)
1729 long *hpsize_max = opaque;
1731 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1732 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1733 long hpsize = host_memory_backend_pagesize(backend);
1735 if (host_memory_backend_is_mapped(backend) && (hpsize > *hpsize_max)) {
1736 *hpsize_max = hpsize;
1740 return 0;
1744 * TODO: We assume right now that all mapped host memory backends are
1745 * used as RAM, however some might be used for different purposes.
1747 long qemu_minrampagesize(void)
1749 long hpsize = LONG_MAX;
1750 long mainrampagesize;
1751 Object *memdev_root;
1753 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1755 /* it's possible we have memory-backend objects with
1756 * hugepage-backed RAM. these may get mapped into system
1757 * address space via -numa parameters or memory hotplug
1758 * hooks. we want to take these into account, but we
1759 * also want to make sure these supported hugepage
1760 * sizes are applicable across the entire range of memory
1761 * we may boot from, so we take the min across all
1762 * backends, and assume normal pages in cases where a
1763 * backend isn't backed by hugepages.
1765 memdev_root = object_resolve_path("/objects", NULL);
1766 if (memdev_root) {
1767 object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize);
1769 if (hpsize == LONG_MAX) {
1770 /* No additional memory regions found ==> Report main RAM page size */
1771 return mainrampagesize;
1774 /* If NUMA is disabled or the NUMA nodes are not backed with a
1775 * memory-backend, then there is at least one node using "normal" RAM,
1776 * so if its page size is smaller we have got to report that size instead.
1778 if (hpsize > mainrampagesize &&
1779 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1780 static bool warned;
1781 if (!warned) {
1782 error_report("Huge page support disabled (n/a for main memory).");
1783 warned = true;
1785 return mainrampagesize;
1788 return hpsize;
1791 long qemu_maxrampagesize(void)
1793 long pagesize = qemu_mempath_getpagesize(mem_path);
1794 Object *memdev_root = object_resolve_path("/objects", NULL);
1796 if (memdev_root) {
1797 object_child_foreach(memdev_root, find_max_backend_pagesize,
1798 &pagesize);
1800 return pagesize;
1802 #else
1803 long qemu_minrampagesize(void)
1805 return getpagesize();
1807 long qemu_maxrampagesize(void)
1809 return getpagesize();
1811 #endif
1813 #ifdef CONFIG_POSIX
1814 static int64_t get_file_size(int fd)
1816 int64_t size = lseek(fd, 0, SEEK_END);
1817 if (size < 0) {
1818 return -errno;
1820 return size;
1823 static int file_ram_open(const char *path,
1824 const char *region_name,
1825 bool *created,
1826 Error **errp)
1828 char *filename;
1829 char *sanitized_name;
1830 char *c;
1831 int fd = -1;
1833 *created = false;
1834 for (;;) {
1835 fd = open(path, O_RDWR);
1836 if (fd >= 0) {
1837 /* @path names an existing file, use it */
1838 break;
1840 if (errno == ENOENT) {
1841 /* @path names a file that doesn't exist, create it */
1842 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1843 if (fd >= 0) {
1844 *created = true;
1845 break;
1847 } else if (errno == EISDIR) {
1848 /* @path names a directory, create a file there */
1849 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1850 sanitized_name = g_strdup(region_name);
1851 for (c = sanitized_name; *c != '\0'; c++) {
1852 if (*c == '/') {
1853 *c = '_';
1857 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1858 sanitized_name);
1859 g_free(sanitized_name);
1861 fd = mkstemp(filename);
1862 if (fd >= 0) {
1863 unlink(filename);
1864 g_free(filename);
1865 break;
1867 g_free(filename);
1869 if (errno != EEXIST && errno != EINTR) {
1870 error_setg_errno(errp, errno,
1871 "can't open backing store %s for guest RAM",
1872 path);
1873 return -1;
1876 * Try again on EINTR and EEXIST. The latter happens when
1877 * something else creates the file between our two open().
1881 return fd;
1884 static void *file_ram_alloc(RAMBlock *block,
1885 ram_addr_t memory,
1886 int fd,
1887 bool truncate,
1888 Error **errp)
1890 MachineState *ms = MACHINE(qdev_get_machine());
1891 void *area;
1893 block->page_size = qemu_fd_getpagesize(fd);
1894 if (block->mr->align % block->page_size) {
1895 error_setg(errp, "alignment 0x%" PRIx64
1896 " must be multiples of page size 0x%zx",
1897 block->mr->align, block->page_size);
1898 return NULL;
1899 } else if (block->mr->align && !is_power_of_2(block->mr->align)) {
1900 error_setg(errp, "alignment 0x%" PRIx64
1901 " must be a power of two", block->mr->align);
1902 return NULL;
1904 block->mr->align = MAX(block->page_size, block->mr->align);
1905 #if defined(__s390x__)
1906 if (kvm_enabled()) {
1907 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1909 #endif
1911 if (memory < block->page_size) {
1912 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1913 "or larger than page size 0x%zx",
1914 memory, block->page_size);
1915 return NULL;
1918 memory = ROUND_UP(memory, block->page_size);
1921 * ftruncate is not supported by hugetlbfs in older
1922 * hosts, so don't bother bailing out on errors.
1923 * If anything goes wrong with it under other filesystems,
1924 * mmap will fail.
1926 * Do not truncate the non-empty backend file to avoid corrupting
1927 * the existing data in the file. Disabling shrinking is not
1928 * enough. For example, the current vNVDIMM implementation stores
1929 * the guest NVDIMM labels at the end of the backend file. If the
1930 * backend file is later extended, QEMU will not be able to find
1931 * those labels. Therefore, extending the non-empty backend file
1932 * is disabled as well.
1934 if (truncate && ftruncate(fd, memory)) {
1935 perror("ftruncate");
1938 area = qemu_ram_mmap(fd, memory, block->mr->align,
1939 block->flags & RAM_SHARED, block->flags & RAM_PMEM);
1940 if (area == MAP_FAILED) {
1941 error_setg_errno(errp, errno,
1942 "unable to map backing store for guest RAM");
1943 return NULL;
1946 if (mem_prealloc) {
1947 os_mem_prealloc(fd, area, memory, ms->smp.cpus, errp);
1948 if (errp && *errp) {
1949 qemu_ram_munmap(fd, area, memory);
1950 return NULL;
1954 block->fd = fd;
1955 return area;
1957 #endif
1959 /* Allocate space within the ram_addr_t space that governs the
1960 * dirty bitmaps.
1961 * Called with the ramlist lock held.
1963 static ram_addr_t find_ram_offset(ram_addr_t size)
1965 RAMBlock *block, *next_block;
1966 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1968 assert(size != 0); /* it would hand out same offset multiple times */
1970 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1971 return 0;
1974 RAMBLOCK_FOREACH(block) {
1975 ram_addr_t candidate, next = RAM_ADDR_MAX;
1977 /* Align blocks to start on a 'long' in the bitmap
1978 * which makes the bitmap sync'ing take the fast path.
1980 candidate = block->offset + block->max_length;
1981 candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS);
1983 /* Search for the closest following block
1984 * and find the gap.
1986 RAMBLOCK_FOREACH(next_block) {
1987 if (next_block->offset >= candidate) {
1988 next = MIN(next, next_block->offset);
1992 /* If it fits remember our place and remember the size
1993 * of gap, but keep going so that we might find a smaller
1994 * gap to fill so avoiding fragmentation.
1996 if (next - candidate >= size && next - candidate < mingap) {
1997 offset = candidate;
1998 mingap = next - candidate;
2001 trace_find_ram_offset_loop(size, candidate, offset, next, mingap);
2004 if (offset == RAM_ADDR_MAX) {
2005 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
2006 (uint64_t)size);
2007 abort();
2010 trace_find_ram_offset(size, offset);
2012 return offset;
2015 static unsigned long last_ram_page(void)
2017 RAMBlock *block;
2018 ram_addr_t last = 0;
2020 rcu_read_lock();
2021 RAMBLOCK_FOREACH(block) {
2022 last = MAX(last, block->offset + block->max_length);
2024 rcu_read_unlock();
2025 return last >> TARGET_PAGE_BITS;
2028 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
2030 int ret;
2032 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
2033 if (!machine_dump_guest_core(current_machine)) {
2034 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
2035 if (ret) {
2036 perror("qemu_madvise");
2037 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
2038 "but dump_guest_core=off specified\n");
2043 const char *qemu_ram_get_idstr(RAMBlock *rb)
2045 return rb->idstr;
2048 void *qemu_ram_get_host_addr(RAMBlock *rb)
2050 return rb->host;
2053 ram_addr_t qemu_ram_get_offset(RAMBlock *rb)
2055 return rb->offset;
2058 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb)
2060 return rb->used_length;
2063 bool qemu_ram_is_shared(RAMBlock *rb)
2065 return rb->flags & RAM_SHARED;
2068 /* Note: Only set at the start of postcopy */
2069 bool qemu_ram_is_uf_zeroable(RAMBlock *rb)
2071 return rb->flags & RAM_UF_ZEROPAGE;
2074 void qemu_ram_set_uf_zeroable(RAMBlock *rb)
2076 rb->flags |= RAM_UF_ZEROPAGE;
2079 bool qemu_ram_is_migratable(RAMBlock *rb)
2081 return rb->flags & RAM_MIGRATABLE;
2084 void qemu_ram_set_migratable(RAMBlock *rb)
2086 rb->flags |= RAM_MIGRATABLE;
2089 void qemu_ram_unset_migratable(RAMBlock *rb)
2091 rb->flags &= ~RAM_MIGRATABLE;
2094 /* Called with iothread lock held. */
2095 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
2097 RAMBlock *block;
2099 assert(new_block);
2100 assert(!new_block->idstr[0]);
2102 if (dev) {
2103 char *id = qdev_get_dev_path(dev);
2104 if (id) {
2105 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
2106 g_free(id);
2109 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
2111 rcu_read_lock();
2112 RAMBLOCK_FOREACH(block) {
2113 if (block != new_block &&
2114 !strcmp(block->idstr, new_block->idstr)) {
2115 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
2116 new_block->idstr);
2117 abort();
2120 rcu_read_unlock();
2123 /* Called with iothread lock held. */
2124 void qemu_ram_unset_idstr(RAMBlock *block)
2126 /* FIXME: arch_init.c assumes that this is not called throughout
2127 * migration. Ignore the problem since hot-unplug during migration
2128 * does not work anyway.
2130 if (block) {
2131 memset(block->idstr, 0, sizeof(block->idstr));
2135 size_t qemu_ram_pagesize(RAMBlock *rb)
2137 return rb->page_size;
2140 /* Returns the largest size of page in use */
2141 size_t qemu_ram_pagesize_largest(void)
2143 RAMBlock *block;
2144 size_t largest = 0;
2146 RAMBLOCK_FOREACH(block) {
2147 largest = MAX(largest, qemu_ram_pagesize(block));
2150 return largest;
2153 static int memory_try_enable_merging(void *addr, size_t len)
2155 if (!machine_mem_merge(current_machine)) {
2156 /* disabled by the user */
2157 return 0;
2160 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
2163 /* Only legal before guest might have detected the memory size: e.g. on
2164 * incoming migration, or right after reset.
2166 * As memory core doesn't know how is memory accessed, it is up to
2167 * resize callback to update device state and/or add assertions to detect
2168 * misuse, if necessary.
2170 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
2172 assert(block);
2174 newsize = HOST_PAGE_ALIGN(newsize);
2176 if (block->used_length == newsize) {
2177 return 0;
2180 if (!(block->flags & RAM_RESIZEABLE)) {
2181 error_setg_errno(errp, EINVAL,
2182 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2183 " in != 0x" RAM_ADDR_FMT, block->idstr,
2184 newsize, block->used_length);
2185 return -EINVAL;
2188 if (block->max_length < newsize) {
2189 error_setg_errno(errp, EINVAL,
2190 "Length too large: %s: 0x" RAM_ADDR_FMT
2191 " > 0x" RAM_ADDR_FMT, block->idstr,
2192 newsize, block->max_length);
2193 return -EINVAL;
2196 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
2197 block->used_length = newsize;
2198 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
2199 DIRTY_CLIENTS_ALL);
2200 memory_region_set_size(block->mr, newsize);
2201 if (block->resized) {
2202 block->resized(block->idstr, newsize, block->host);
2204 return 0;
2207 /* Called with ram_list.mutex held */
2208 static void dirty_memory_extend(ram_addr_t old_ram_size,
2209 ram_addr_t new_ram_size)
2211 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
2212 DIRTY_MEMORY_BLOCK_SIZE);
2213 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
2214 DIRTY_MEMORY_BLOCK_SIZE);
2215 int i;
2217 /* Only need to extend if block count increased */
2218 if (new_num_blocks <= old_num_blocks) {
2219 return;
2222 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
2223 DirtyMemoryBlocks *old_blocks;
2224 DirtyMemoryBlocks *new_blocks;
2225 int j;
2227 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
2228 new_blocks = g_malloc(sizeof(*new_blocks) +
2229 sizeof(new_blocks->blocks[0]) * new_num_blocks);
2231 if (old_num_blocks) {
2232 memcpy(new_blocks->blocks, old_blocks->blocks,
2233 old_num_blocks * sizeof(old_blocks->blocks[0]));
2236 for (j = old_num_blocks; j < new_num_blocks; j++) {
2237 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
2240 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
2242 if (old_blocks) {
2243 g_free_rcu(old_blocks, rcu);
2248 static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared)
2250 RAMBlock *block;
2251 RAMBlock *last_block = NULL;
2252 ram_addr_t old_ram_size, new_ram_size;
2253 Error *err = NULL;
2255 old_ram_size = last_ram_page();
2257 qemu_mutex_lock_ramlist();
2258 new_block->offset = find_ram_offset(new_block->max_length);
2260 if (!new_block->host) {
2261 if (xen_enabled()) {
2262 xen_ram_alloc(new_block->offset, new_block->max_length,
2263 new_block->mr, &err);
2264 if (err) {
2265 error_propagate(errp, err);
2266 qemu_mutex_unlock_ramlist();
2267 return;
2269 } else {
2270 new_block->host = phys_mem_alloc(new_block->max_length,
2271 &new_block->mr->align, shared);
2272 if (!new_block->host) {
2273 error_setg_errno(errp, errno,
2274 "cannot set up guest memory '%s'",
2275 memory_region_name(new_block->mr));
2276 qemu_mutex_unlock_ramlist();
2277 return;
2279 memory_try_enable_merging(new_block->host, new_block->max_length);
2283 new_ram_size = MAX(old_ram_size,
2284 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
2285 if (new_ram_size > old_ram_size) {
2286 dirty_memory_extend(old_ram_size, new_ram_size);
2288 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2289 * QLIST (which has an RCU-friendly variant) does not have insertion at
2290 * tail, so save the last element in last_block.
2292 RAMBLOCK_FOREACH(block) {
2293 last_block = block;
2294 if (block->max_length < new_block->max_length) {
2295 break;
2298 if (block) {
2299 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
2300 } else if (last_block) {
2301 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
2302 } else { /* list is empty */
2303 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
2305 ram_list.mru_block = NULL;
2307 /* Write list before version */
2308 smp_wmb();
2309 ram_list.version++;
2310 qemu_mutex_unlock_ramlist();
2312 cpu_physical_memory_set_dirty_range(new_block->offset,
2313 new_block->used_length,
2314 DIRTY_CLIENTS_ALL);
2316 if (new_block->host) {
2317 qemu_ram_setup_dump(new_block->host, new_block->max_length);
2318 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
2319 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2320 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
2321 ram_block_notify_add(new_block->host, new_block->max_length);
2325 #ifdef CONFIG_POSIX
2326 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
2327 uint32_t ram_flags, int fd,
2328 Error **errp)
2330 RAMBlock *new_block;
2331 Error *local_err = NULL;
2332 int64_t file_size;
2334 /* Just support these ram flags by now. */
2335 assert((ram_flags & ~(RAM_SHARED | RAM_PMEM)) == 0);
2337 if (xen_enabled()) {
2338 error_setg(errp, "-mem-path not supported with Xen");
2339 return NULL;
2342 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2343 error_setg(errp,
2344 "host lacks kvm mmu notifiers, -mem-path unsupported");
2345 return NULL;
2348 if (phys_mem_alloc != qemu_anon_ram_alloc) {
2350 * file_ram_alloc() needs to allocate just like
2351 * phys_mem_alloc, but we haven't bothered to provide
2352 * a hook there.
2354 error_setg(errp,
2355 "-mem-path not supported with this accelerator");
2356 return NULL;
2359 size = HOST_PAGE_ALIGN(size);
2360 file_size = get_file_size(fd);
2361 if (file_size > 0 && file_size < size) {
2362 error_setg(errp, "backing store %s size 0x%" PRIx64
2363 " does not match 'size' option 0x" RAM_ADDR_FMT,
2364 mem_path, file_size, size);
2365 return NULL;
2368 new_block = g_malloc0(sizeof(*new_block));
2369 new_block->mr = mr;
2370 new_block->used_length = size;
2371 new_block->max_length = size;
2372 new_block->flags = ram_flags;
2373 new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp);
2374 if (!new_block->host) {
2375 g_free(new_block);
2376 return NULL;
2379 ram_block_add(new_block, &local_err, ram_flags & RAM_SHARED);
2380 if (local_err) {
2381 g_free(new_block);
2382 error_propagate(errp, local_err);
2383 return NULL;
2385 return new_block;
2390 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
2391 uint32_t ram_flags, const char *mem_path,
2392 Error **errp)
2394 int fd;
2395 bool created;
2396 RAMBlock *block;
2398 fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp);
2399 if (fd < 0) {
2400 return NULL;
2403 block = qemu_ram_alloc_from_fd(size, mr, ram_flags, fd, errp);
2404 if (!block) {
2405 if (created) {
2406 unlink(mem_path);
2408 close(fd);
2409 return NULL;
2412 return block;
2414 #endif
2416 static
2417 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2418 void (*resized)(const char*,
2419 uint64_t length,
2420 void *host),
2421 void *host, bool resizeable, bool share,
2422 MemoryRegion *mr, Error **errp)
2424 RAMBlock *new_block;
2425 Error *local_err = NULL;
2427 size = HOST_PAGE_ALIGN(size);
2428 max_size = HOST_PAGE_ALIGN(max_size);
2429 new_block = g_malloc0(sizeof(*new_block));
2430 new_block->mr = mr;
2431 new_block->resized = resized;
2432 new_block->used_length = size;
2433 new_block->max_length = max_size;
2434 assert(max_size >= size);
2435 new_block->fd = -1;
2436 new_block->page_size = getpagesize();
2437 new_block->host = host;
2438 if (host) {
2439 new_block->flags |= RAM_PREALLOC;
2441 if (resizeable) {
2442 new_block->flags |= RAM_RESIZEABLE;
2444 ram_block_add(new_block, &local_err, share);
2445 if (local_err) {
2446 g_free(new_block);
2447 error_propagate(errp, local_err);
2448 return NULL;
2450 return new_block;
2453 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2454 MemoryRegion *mr, Error **errp)
2456 return qemu_ram_alloc_internal(size, size, NULL, host, false,
2457 false, mr, errp);
2460 RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share,
2461 MemoryRegion *mr, Error **errp)
2463 return qemu_ram_alloc_internal(size, size, NULL, NULL, false,
2464 share, mr, errp);
2467 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2468 void (*resized)(const char*,
2469 uint64_t length,
2470 void *host),
2471 MemoryRegion *mr, Error **errp)
2473 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true,
2474 false, mr, errp);
2477 static void reclaim_ramblock(RAMBlock *block)
2479 if (block->flags & RAM_PREALLOC) {
2481 } else if (xen_enabled()) {
2482 xen_invalidate_map_cache_entry(block->host);
2483 #ifndef _WIN32
2484 } else if (block->fd >= 0) {
2485 qemu_ram_munmap(block->fd, block->host, block->max_length);
2486 close(block->fd);
2487 #endif
2488 } else {
2489 qemu_anon_ram_free(block->host, block->max_length);
2491 g_free(block);
2494 void qemu_ram_free(RAMBlock *block)
2496 if (!block) {
2497 return;
2500 if (block->host) {
2501 ram_block_notify_remove(block->host, block->max_length);
2504 qemu_mutex_lock_ramlist();
2505 QLIST_REMOVE_RCU(block, next);
2506 ram_list.mru_block = NULL;
2507 /* Write list before version */
2508 smp_wmb();
2509 ram_list.version++;
2510 call_rcu(block, reclaim_ramblock, rcu);
2511 qemu_mutex_unlock_ramlist();
2514 #ifndef _WIN32
2515 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2517 RAMBlock *block;
2518 ram_addr_t offset;
2519 int flags;
2520 void *area, *vaddr;
2522 RAMBLOCK_FOREACH(block) {
2523 offset = addr - block->offset;
2524 if (offset < block->max_length) {
2525 vaddr = ramblock_ptr(block, offset);
2526 if (block->flags & RAM_PREALLOC) {
2528 } else if (xen_enabled()) {
2529 abort();
2530 } else {
2531 flags = MAP_FIXED;
2532 if (block->fd >= 0) {
2533 flags |= (block->flags & RAM_SHARED ?
2534 MAP_SHARED : MAP_PRIVATE);
2535 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2536 flags, block->fd, offset);
2537 } else {
2539 * Remap needs to match alloc. Accelerators that
2540 * set phys_mem_alloc never remap. If they did,
2541 * we'd need a remap hook here.
2543 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2545 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2546 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2547 flags, -1, 0);
2549 if (area != vaddr) {
2550 error_report("Could not remap addr: "
2551 RAM_ADDR_FMT "@" RAM_ADDR_FMT "",
2552 length, addr);
2553 exit(1);
2555 memory_try_enable_merging(vaddr, length);
2556 qemu_ram_setup_dump(vaddr, length);
2561 #endif /* !_WIN32 */
2563 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2564 * This should not be used for general purpose DMA. Use address_space_map
2565 * or address_space_rw instead. For local memory (e.g. video ram) that the
2566 * device owns, use memory_region_get_ram_ptr.
2568 * Called within RCU critical section.
2570 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2572 RAMBlock *block = ram_block;
2574 if (block == NULL) {
2575 block = qemu_get_ram_block(addr);
2576 addr -= block->offset;
2579 if (xen_enabled() && block->host == NULL) {
2580 /* We need to check if the requested address is in the RAM
2581 * because we don't want to map the entire memory in QEMU.
2582 * In that case just map until the end of the page.
2584 if (block->offset == 0) {
2585 return xen_map_cache(addr, 0, 0, false);
2588 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2590 return ramblock_ptr(block, addr);
2593 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2594 * but takes a size argument.
2596 * Called within RCU critical section.
2598 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2599 hwaddr *size, bool lock)
2601 RAMBlock *block = ram_block;
2602 if (*size == 0) {
2603 return NULL;
2606 if (block == NULL) {
2607 block = qemu_get_ram_block(addr);
2608 addr -= block->offset;
2610 *size = MIN(*size, block->max_length - addr);
2612 if (xen_enabled() && block->host == NULL) {
2613 /* We need to check if the requested address is in the RAM
2614 * because we don't want to map the entire memory in QEMU.
2615 * In that case just map the requested area.
2617 if (block->offset == 0) {
2618 return xen_map_cache(addr, *size, lock, lock);
2621 block->host = xen_map_cache(block->offset, block->max_length, 1, lock);
2624 return ramblock_ptr(block, addr);
2627 /* Return the offset of a hostpointer within a ramblock */
2628 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host)
2630 ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host;
2631 assert((uintptr_t)host >= (uintptr_t)rb->host);
2632 assert(res < rb->max_length);
2634 return res;
2638 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2639 * in that RAMBlock.
2641 * ptr: Host pointer to look up
2642 * round_offset: If true round the result offset down to a page boundary
2643 * *ram_addr: set to result ram_addr
2644 * *offset: set to result offset within the RAMBlock
2646 * Returns: RAMBlock (or NULL if not found)
2648 * By the time this function returns, the returned pointer is not protected
2649 * by RCU anymore. If the caller is not within an RCU critical section and
2650 * does not hold the iothread lock, it must have other means of protecting the
2651 * pointer, such as a reference to the region that includes the incoming
2652 * ram_addr_t.
2654 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2655 ram_addr_t *offset)
2657 RAMBlock *block;
2658 uint8_t *host = ptr;
2660 if (xen_enabled()) {
2661 ram_addr_t ram_addr;
2662 rcu_read_lock();
2663 ram_addr = xen_ram_addr_from_mapcache(ptr);
2664 block = qemu_get_ram_block(ram_addr);
2665 if (block) {
2666 *offset = ram_addr - block->offset;
2668 rcu_read_unlock();
2669 return block;
2672 rcu_read_lock();
2673 block = atomic_rcu_read(&ram_list.mru_block);
2674 if (block && block->host && host - block->host < block->max_length) {
2675 goto found;
2678 RAMBLOCK_FOREACH(block) {
2679 /* This case append when the block is not mapped. */
2680 if (block->host == NULL) {
2681 continue;
2683 if (host - block->host < block->max_length) {
2684 goto found;
2688 rcu_read_unlock();
2689 return NULL;
2691 found:
2692 *offset = (host - block->host);
2693 if (round_offset) {
2694 *offset &= TARGET_PAGE_MASK;
2696 rcu_read_unlock();
2697 return block;
2701 * Finds the named RAMBlock
2703 * name: The name of RAMBlock to find
2705 * Returns: RAMBlock (or NULL if not found)
2707 RAMBlock *qemu_ram_block_by_name(const char *name)
2709 RAMBlock *block;
2711 RAMBLOCK_FOREACH(block) {
2712 if (!strcmp(name, block->idstr)) {
2713 return block;
2717 return NULL;
2720 /* Some of the softmmu routines need to translate from a host pointer
2721 (typically a TLB entry) back to a ram offset. */
2722 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2724 RAMBlock *block;
2725 ram_addr_t offset;
2727 block = qemu_ram_block_from_host(ptr, false, &offset);
2728 if (!block) {
2729 return RAM_ADDR_INVALID;
2732 return block->offset + offset;
2735 /* Called within RCU critical section. */
2736 void memory_notdirty_write_prepare(NotDirtyInfo *ndi,
2737 CPUState *cpu,
2738 vaddr mem_vaddr,
2739 ram_addr_t ram_addr,
2740 unsigned size)
2742 ndi->cpu = cpu;
2743 ndi->ram_addr = ram_addr;
2744 ndi->mem_vaddr = mem_vaddr;
2745 ndi->size = size;
2746 ndi->pages = NULL;
2748 assert(tcg_enabled());
2749 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2750 ndi->pages = page_collection_lock(ram_addr, ram_addr + size);
2751 tb_invalidate_phys_page_fast(ndi->pages, ram_addr, size);
2755 /* Called within RCU critical section. */
2756 void memory_notdirty_write_complete(NotDirtyInfo *ndi)
2758 if (ndi->pages) {
2759 assert(tcg_enabled());
2760 page_collection_unlock(ndi->pages);
2761 ndi->pages = NULL;
2764 /* Set both VGA and migration bits for simplicity and to remove
2765 * the notdirty callback faster.
2767 cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size,
2768 DIRTY_CLIENTS_NOCODE);
2769 /* we remove the notdirty callback only if the code has been
2770 flushed */
2771 if (!cpu_physical_memory_is_clean(ndi->ram_addr)) {
2772 tlb_set_dirty(ndi->cpu, ndi->mem_vaddr);
2776 /* Called within RCU critical section. */
2777 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2778 uint64_t val, unsigned size)
2780 NotDirtyInfo ndi;
2782 memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr,
2783 ram_addr, size);
2785 stn_p(qemu_map_ram_ptr(NULL, ram_addr), size, val);
2786 memory_notdirty_write_complete(&ndi);
2789 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2790 unsigned size, bool is_write,
2791 MemTxAttrs attrs)
2793 return is_write;
2796 static const MemoryRegionOps notdirty_mem_ops = {
2797 .write = notdirty_mem_write,
2798 .valid.accepts = notdirty_mem_accepts,
2799 .endianness = DEVICE_NATIVE_ENDIAN,
2800 .valid = {
2801 .min_access_size = 1,
2802 .max_access_size = 8,
2803 .unaligned = false,
2805 .impl = {
2806 .min_access_size = 1,
2807 .max_access_size = 8,
2808 .unaligned = false,
2812 /* Generate a debug exception if a watchpoint has been hit. */
2813 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2815 CPUState *cpu = current_cpu;
2816 CPUClass *cc = CPU_GET_CLASS(cpu);
2817 target_ulong vaddr;
2818 CPUWatchpoint *wp;
2820 assert(tcg_enabled());
2821 if (cpu->watchpoint_hit) {
2822 /* We re-entered the check after replacing the TB. Now raise
2823 * the debug interrupt so that is will trigger after the
2824 * current instruction. */
2825 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2826 return;
2828 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2829 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2830 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2831 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2832 && (wp->flags & flags)) {
2833 if (flags == BP_MEM_READ) {
2834 wp->flags |= BP_WATCHPOINT_HIT_READ;
2835 } else {
2836 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2838 wp->hitaddr = vaddr;
2839 wp->hitattrs = attrs;
2840 if (!cpu->watchpoint_hit) {
2841 if (wp->flags & BP_CPU &&
2842 !cc->debug_check_watchpoint(cpu, wp)) {
2843 wp->flags &= ~BP_WATCHPOINT_HIT;
2844 continue;
2846 cpu->watchpoint_hit = wp;
2848 mmap_lock();
2849 tb_check_watchpoint(cpu);
2850 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2851 cpu->exception_index = EXCP_DEBUG;
2852 mmap_unlock();
2853 cpu_loop_exit(cpu);
2854 } else {
2855 /* Force execution of one insn next time. */
2856 cpu->cflags_next_tb = 1 | curr_cflags();
2857 mmap_unlock();
2858 cpu_loop_exit_noexc(cpu);
2861 } else {
2862 wp->flags &= ~BP_WATCHPOINT_HIT;
2867 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2868 so these check for a hit then pass through to the normal out-of-line
2869 phys routines. */
2870 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2871 unsigned size, MemTxAttrs attrs)
2873 MemTxResult res;
2874 uint64_t data;
2875 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2876 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2878 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2879 switch (size) {
2880 case 1:
2881 data = address_space_ldub(as, addr, attrs, &res);
2882 break;
2883 case 2:
2884 data = address_space_lduw(as, addr, attrs, &res);
2885 break;
2886 case 4:
2887 data = address_space_ldl(as, addr, attrs, &res);
2888 break;
2889 case 8:
2890 data = address_space_ldq(as, addr, attrs, &res);
2891 break;
2892 default: abort();
2894 *pdata = data;
2895 return res;
2898 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2899 uint64_t val, unsigned size,
2900 MemTxAttrs attrs)
2902 MemTxResult res;
2903 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2904 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2906 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2907 switch (size) {
2908 case 1:
2909 address_space_stb(as, addr, val, attrs, &res);
2910 break;
2911 case 2:
2912 address_space_stw(as, addr, val, attrs, &res);
2913 break;
2914 case 4:
2915 address_space_stl(as, addr, val, attrs, &res);
2916 break;
2917 case 8:
2918 address_space_stq(as, addr, val, attrs, &res);
2919 break;
2920 default: abort();
2922 return res;
2925 static const MemoryRegionOps watch_mem_ops = {
2926 .read_with_attrs = watch_mem_read,
2927 .write_with_attrs = watch_mem_write,
2928 .endianness = DEVICE_NATIVE_ENDIAN,
2929 .valid = {
2930 .min_access_size = 1,
2931 .max_access_size = 8,
2932 .unaligned = false,
2934 .impl = {
2935 .min_access_size = 1,
2936 .max_access_size = 8,
2937 .unaligned = false,
2941 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
2942 MemTxAttrs attrs, uint8_t *buf, hwaddr len);
2943 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
2944 const uint8_t *buf, hwaddr len);
2945 static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,
2946 bool is_write, MemTxAttrs attrs);
2948 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2949 unsigned len, MemTxAttrs attrs)
2951 subpage_t *subpage = opaque;
2952 uint8_t buf[8];
2953 MemTxResult res;
2955 #if defined(DEBUG_SUBPAGE)
2956 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2957 subpage, len, addr);
2958 #endif
2959 res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
2960 if (res) {
2961 return res;
2963 *data = ldn_p(buf, len);
2964 return MEMTX_OK;
2967 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2968 uint64_t value, unsigned len, MemTxAttrs attrs)
2970 subpage_t *subpage = opaque;
2971 uint8_t buf[8];
2973 #if defined(DEBUG_SUBPAGE)
2974 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2975 " value %"PRIx64"\n",
2976 __func__, subpage, len, addr, value);
2977 #endif
2978 stn_p(buf, len, value);
2979 return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);
2982 static bool subpage_accepts(void *opaque, hwaddr addr,
2983 unsigned len, bool is_write,
2984 MemTxAttrs attrs)
2986 subpage_t *subpage = opaque;
2987 #if defined(DEBUG_SUBPAGE)
2988 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2989 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2990 #endif
2992 return flatview_access_valid(subpage->fv, addr + subpage->base,
2993 len, is_write, attrs);
2996 static const MemoryRegionOps subpage_ops = {
2997 .read_with_attrs = subpage_read,
2998 .write_with_attrs = subpage_write,
2999 .impl.min_access_size = 1,
3000 .impl.max_access_size = 8,
3001 .valid.min_access_size = 1,
3002 .valid.max_access_size = 8,
3003 .valid.accepts = subpage_accepts,
3004 .endianness = DEVICE_NATIVE_ENDIAN,
3007 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
3008 uint16_t section)
3010 int idx, eidx;
3012 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
3013 return -1;
3014 idx = SUBPAGE_IDX(start);
3015 eidx = SUBPAGE_IDX(end);
3016 #if defined(DEBUG_SUBPAGE)
3017 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
3018 __func__, mmio, start, end, idx, eidx, section);
3019 #endif
3020 for (; idx <= eidx; idx++) {
3021 mmio->sub_section[idx] = section;
3024 return 0;
3027 static subpage_t *subpage_init(FlatView *fv, hwaddr base)
3029 subpage_t *mmio;
3031 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
3032 mmio->fv = fv;
3033 mmio->base = base;
3034 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
3035 NULL, TARGET_PAGE_SIZE);
3036 mmio->iomem.subpage = true;
3037 #if defined(DEBUG_SUBPAGE)
3038 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
3039 mmio, base, TARGET_PAGE_SIZE);
3040 #endif
3041 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
3043 return mmio;
3046 static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr)
3048 assert(fv);
3049 MemoryRegionSection section = {
3050 .fv = fv,
3051 .mr = mr,
3052 .offset_within_address_space = 0,
3053 .offset_within_region = 0,
3054 .size = int128_2_64(),
3057 return phys_section_add(map, &section);
3060 static void readonly_mem_write(void *opaque, hwaddr addr,
3061 uint64_t val, unsigned size)
3063 /* Ignore any write to ROM. */
3066 static bool readonly_mem_accepts(void *opaque, hwaddr addr,
3067 unsigned size, bool is_write,
3068 MemTxAttrs attrs)
3070 return is_write;
3073 /* This will only be used for writes, because reads are special cased
3074 * to directly access the underlying host ram.
3076 static const MemoryRegionOps readonly_mem_ops = {
3077 .write = readonly_mem_write,
3078 .valid.accepts = readonly_mem_accepts,
3079 .endianness = DEVICE_NATIVE_ENDIAN,
3080 .valid = {
3081 .min_access_size = 1,
3082 .max_access_size = 8,
3083 .unaligned = false,
3085 .impl = {
3086 .min_access_size = 1,
3087 .max_access_size = 8,
3088 .unaligned = false,
3092 MemoryRegionSection *iotlb_to_section(CPUState *cpu,
3093 hwaddr index, MemTxAttrs attrs)
3095 int asidx = cpu_asidx_from_attrs(cpu, attrs);
3096 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
3097 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
3098 MemoryRegionSection *sections = d->map.sections;
3100 return &sections[index & ~TARGET_PAGE_MASK];
3103 static void io_mem_init(void)
3105 memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops,
3106 NULL, NULL, UINT64_MAX);
3107 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
3108 NULL, UINT64_MAX);
3110 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3111 * which can be called without the iothread mutex.
3113 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
3114 NULL, UINT64_MAX);
3115 memory_region_clear_global_locking(&io_mem_notdirty);
3117 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
3118 NULL, UINT64_MAX);
3121 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv)
3123 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
3124 uint16_t n;
3126 n = dummy_section(&d->map, fv, &io_mem_unassigned);
3127 assert(n == PHYS_SECTION_UNASSIGNED);
3128 n = dummy_section(&d->map, fv, &io_mem_notdirty);
3129 assert(n == PHYS_SECTION_NOTDIRTY);
3130 n = dummy_section(&d->map, fv, &io_mem_rom);
3131 assert(n == PHYS_SECTION_ROM);
3132 n = dummy_section(&d->map, fv, &io_mem_watch);
3133 assert(n == PHYS_SECTION_WATCH);
3135 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
3137 return d;
3140 void address_space_dispatch_free(AddressSpaceDispatch *d)
3142 phys_sections_free(&d->map);
3143 g_free(d);
3146 static void tcg_commit(MemoryListener *listener)
3148 CPUAddressSpace *cpuas;
3149 AddressSpaceDispatch *d;
3151 assert(tcg_enabled());
3152 /* since each CPU stores ram addresses in its TLB cache, we must
3153 reset the modified entries */
3154 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
3155 cpu_reloading_memory_map();
3156 /* The CPU and TLB are protected by the iothread lock.
3157 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3158 * may have split the RCU critical section.
3160 d = address_space_to_dispatch(cpuas->as);
3161 atomic_rcu_set(&cpuas->memory_dispatch, d);
3162 tlb_flush(cpuas->cpu);
3165 static void memory_map_init(void)
3167 system_memory = g_malloc(sizeof(*system_memory));
3169 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
3170 address_space_init(&address_space_memory, system_memory, "memory");
3172 system_io = g_malloc(sizeof(*system_io));
3173 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
3174 65536);
3175 address_space_init(&address_space_io, system_io, "I/O");
3178 MemoryRegion *get_system_memory(void)
3180 return system_memory;
3183 MemoryRegion *get_system_io(void)
3185 return system_io;
3188 #endif /* !defined(CONFIG_USER_ONLY) */
3190 /* physical memory access (slow version, mainly for debug) */
3191 #if defined(CONFIG_USER_ONLY)
3192 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3193 uint8_t *buf, target_ulong len, int is_write)
3195 int flags;
3196 target_ulong l, page;
3197 void * p;
3199 while (len > 0) {
3200 page = addr & TARGET_PAGE_MASK;
3201 l = (page + TARGET_PAGE_SIZE) - addr;
3202 if (l > len)
3203 l = len;
3204 flags = page_get_flags(page);
3205 if (!(flags & PAGE_VALID))
3206 return -1;
3207 if (is_write) {
3208 if (!(flags & PAGE_WRITE))
3209 return -1;
3210 /* XXX: this code should not depend on lock_user */
3211 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
3212 return -1;
3213 memcpy(p, buf, l);
3214 unlock_user(p, addr, l);
3215 } else {
3216 if (!(flags & PAGE_READ))
3217 return -1;
3218 /* XXX: this code should not depend on lock_user */
3219 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
3220 return -1;
3221 memcpy(buf, p, l);
3222 unlock_user(p, addr, 0);
3224 len -= l;
3225 buf += l;
3226 addr += l;
3228 return 0;
3231 #else
3233 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
3234 hwaddr length)
3236 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
3237 addr += memory_region_get_ram_addr(mr);
3239 /* No early return if dirty_log_mask is or becomes 0, because
3240 * cpu_physical_memory_set_dirty_range will still call
3241 * xen_modified_memory.
3243 if (dirty_log_mask) {
3244 dirty_log_mask =
3245 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
3247 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
3248 assert(tcg_enabled());
3249 tb_invalidate_phys_range(addr, addr + length);
3250 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
3252 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
3255 void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr size)
3258 * In principle this function would work on other memory region types too,
3259 * but the ROM device use case is the only one where this operation is
3260 * necessary. Other memory regions should use the
3261 * address_space_read/write() APIs.
3263 assert(memory_region_is_romd(mr));
3265 invalidate_and_set_dirty(mr, addr, size);
3268 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
3270 unsigned access_size_max = mr->ops->valid.max_access_size;
3272 /* Regions are assumed to support 1-4 byte accesses unless
3273 otherwise specified. */
3274 if (access_size_max == 0) {
3275 access_size_max = 4;
3278 /* Bound the maximum access by the alignment of the address. */
3279 if (!mr->ops->impl.unaligned) {
3280 unsigned align_size_max = addr & -addr;
3281 if (align_size_max != 0 && align_size_max < access_size_max) {
3282 access_size_max = align_size_max;
3286 /* Don't attempt accesses larger than the maximum. */
3287 if (l > access_size_max) {
3288 l = access_size_max;
3290 l = pow2floor(l);
3292 return l;
3295 static bool prepare_mmio_access(MemoryRegion *mr)
3297 bool unlocked = !qemu_mutex_iothread_locked();
3298 bool release_lock = false;
3300 if (unlocked && mr->global_locking) {
3301 qemu_mutex_lock_iothread();
3302 unlocked = false;
3303 release_lock = true;
3305 if (mr->flush_coalesced_mmio) {
3306 if (unlocked) {
3307 qemu_mutex_lock_iothread();
3309 qemu_flush_coalesced_mmio_buffer();
3310 if (unlocked) {
3311 qemu_mutex_unlock_iothread();
3315 return release_lock;
3318 /* Called within RCU critical section. */
3319 static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
3320 MemTxAttrs attrs,
3321 const uint8_t *buf,
3322 hwaddr len, hwaddr addr1,
3323 hwaddr l, MemoryRegion *mr)
3325 uint8_t *ptr;
3326 uint64_t val;
3327 MemTxResult result = MEMTX_OK;
3328 bool release_lock = false;
3330 for (;;) {
3331 if (!memory_access_is_direct(mr, true)) {
3332 release_lock |= prepare_mmio_access(mr);
3333 l = memory_access_size(mr, l, addr1);
3334 /* XXX: could force current_cpu to NULL to avoid
3335 potential bugs */
3336 val = ldn_p(buf, l);
3337 result |= memory_region_dispatch_write(mr, addr1, val, l, attrs);
3338 } else {
3339 /* RAM case */
3340 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3341 memcpy(ptr, buf, l);
3342 invalidate_and_set_dirty(mr, addr1, l);
3345 if (release_lock) {
3346 qemu_mutex_unlock_iothread();
3347 release_lock = false;
3350 len -= l;
3351 buf += l;
3352 addr += l;
3354 if (!len) {
3355 break;
3358 l = len;
3359 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3362 return result;
3365 /* Called from RCU critical section. */
3366 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
3367 const uint8_t *buf, hwaddr len)
3369 hwaddr l;
3370 hwaddr addr1;
3371 MemoryRegion *mr;
3372 MemTxResult result = MEMTX_OK;
3374 l = len;
3375 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3376 result = flatview_write_continue(fv, addr, attrs, buf, len,
3377 addr1, l, mr);
3379 return result;
3382 /* Called within RCU critical section. */
3383 MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
3384 MemTxAttrs attrs, uint8_t *buf,
3385 hwaddr len, hwaddr addr1, hwaddr l,
3386 MemoryRegion *mr)
3388 uint8_t *ptr;
3389 uint64_t val;
3390 MemTxResult result = MEMTX_OK;
3391 bool release_lock = false;
3393 for (;;) {
3394 if (!memory_access_is_direct(mr, false)) {
3395 /* I/O case */
3396 release_lock |= prepare_mmio_access(mr);
3397 l = memory_access_size(mr, l, addr1);
3398 result |= memory_region_dispatch_read(mr, addr1, &val, l, attrs);
3399 stn_p(buf, l, val);
3400 } else {
3401 /* RAM case */
3402 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3403 memcpy(buf, ptr, l);
3406 if (release_lock) {
3407 qemu_mutex_unlock_iothread();
3408 release_lock = false;
3411 len -= l;
3412 buf += l;
3413 addr += l;
3415 if (!len) {
3416 break;
3419 l = len;
3420 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3423 return result;
3426 /* Called from RCU critical section. */
3427 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
3428 MemTxAttrs attrs, uint8_t *buf, hwaddr len)
3430 hwaddr l;
3431 hwaddr addr1;
3432 MemoryRegion *mr;
3434 l = len;
3435 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3436 return flatview_read_continue(fv, addr, attrs, buf, len,
3437 addr1, l, mr);
3440 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3441 MemTxAttrs attrs, uint8_t *buf, hwaddr len)
3443 MemTxResult result = MEMTX_OK;
3444 FlatView *fv;
3446 if (len > 0) {
3447 rcu_read_lock();
3448 fv = address_space_to_flatview(as);
3449 result = flatview_read(fv, addr, attrs, buf, len);
3450 rcu_read_unlock();
3453 return result;
3456 MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
3457 MemTxAttrs attrs,
3458 const uint8_t *buf, hwaddr len)
3460 MemTxResult result = MEMTX_OK;
3461 FlatView *fv;
3463 if (len > 0) {
3464 rcu_read_lock();
3465 fv = address_space_to_flatview(as);
3466 result = flatview_write(fv, addr, attrs, buf, len);
3467 rcu_read_unlock();
3470 return result;
3473 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3474 uint8_t *buf, hwaddr len, bool is_write)
3476 if (is_write) {
3477 return address_space_write(as, addr, attrs, buf, len);
3478 } else {
3479 return address_space_read_full(as, addr, attrs, buf, len);
3483 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
3484 hwaddr len, int is_write)
3486 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3487 buf, len, is_write);
3490 enum write_rom_type {
3491 WRITE_DATA,
3492 FLUSH_CACHE,
3495 static inline MemTxResult address_space_write_rom_internal(AddressSpace *as,
3496 hwaddr addr,
3497 MemTxAttrs attrs,
3498 const uint8_t *buf,
3499 hwaddr len,
3500 enum write_rom_type type)
3502 hwaddr l;
3503 uint8_t *ptr;
3504 hwaddr addr1;
3505 MemoryRegion *mr;
3507 rcu_read_lock();
3508 while (len > 0) {
3509 l = len;
3510 mr = address_space_translate(as, addr, &addr1, &l, true, attrs);
3512 if (!(memory_region_is_ram(mr) ||
3513 memory_region_is_romd(mr))) {
3514 l = memory_access_size(mr, l, addr1);
3515 } else {
3516 /* ROM/RAM case */
3517 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3518 switch (type) {
3519 case WRITE_DATA:
3520 memcpy(ptr, buf, l);
3521 invalidate_and_set_dirty(mr, addr1, l);
3522 break;
3523 case FLUSH_CACHE:
3524 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
3525 break;
3528 len -= l;
3529 buf += l;
3530 addr += l;
3532 rcu_read_unlock();
3533 return MEMTX_OK;
3536 /* used for ROM loading : can write in RAM and ROM */
3537 MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr,
3538 MemTxAttrs attrs,
3539 const uint8_t *buf, hwaddr len)
3541 return address_space_write_rom_internal(as, addr, attrs,
3542 buf, len, WRITE_DATA);
3545 void cpu_flush_icache_range(hwaddr start, hwaddr len)
3548 * This function should do the same thing as an icache flush that was
3549 * triggered from within the guest. For TCG we are always cache coherent,
3550 * so there is no need to flush anything. For KVM / Xen we need to flush
3551 * the host's instruction cache at least.
3553 if (tcg_enabled()) {
3554 return;
3557 address_space_write_rom_internal(&address_space_memory,
3558 start, MEMTXATTRS_UNSPECIFIED,
3559 NULL, len, FLUSH_CACHE);
3562 typedef struct {
3563 MemoryRegion *mr;
3564 void *buffer;
3565 hwaddr addr;
3566 hwaddr len;
3567 bool in_use;
3568 } BounceBuffer;
3570 static BounceBuffer bounce;
3572 typedef struct MapClient {
3573 QEMUBH *bh;
3574 QLIST_ENTRY(MapClient) link;
3575 } MapClient;
3577 QemuMutex map_client_list_lock;
3578 static QLIST_HEAD(, MapClient) map_client_list
3579 = QLIST_HEAD_INITIALIZER(map_client_list);
3581 static void cpu_unregister_map_client_do(MapClient *client)
3583 QLIST_REMOVE(client, link);
3584 g_free(client);
3587 static void cpu_notify_map_clients_locked(void)
3589 MapClient *client;
3591 while (!QLIST_EMPTY(&map_client_list)) {
3592 client = QLIST_FIRST(&map_client_list);
3593 qemu_bh_schedule(client->bh);
3594 cpu_unregister_map_client_do(client);
3598 void cpu_register_map_client(QEMUBH *bh)
3600 MapClient *client = g_malloc(sizeof(*client));
3602 qemu_mutex_lock(&map_client_list_lock);
3603 client->bh = bh;
3604 QLIST_INSERT_HEAD(&map_client_list, client, link);
3605 if (!atomic_read(&bounce.in_use)) {
3606 cpu_notify_map_clients_locked();
3608 qemu_mutex_unlock(&map_client_list_lock);
3611 void cpu_exec_init_all(void)
3613 qemu_mutex_init(&ram_list.mutex);
3614 /* The data structures we set up here depend on knowing the page size,
3615 * so no more changes can be made after this point.
3616 * In an ideal world, nothing we did before we had finished the
3617 * machine setup would care about the target page size, and we could
3618 * do this much later, rather than requiring board models to state
3619 * up front what their requirements are.
3621 finalize_target_page_bits();
3622 io_mem_init();
3623 memory_map_init();
3624 qemu_mutex_init(&map_client_list_lock);
3627 void cpu_unregister_map_client(QEMUBH *bh)
3629 MapClient *client;
3631 qemu_mutex_lock(&map_client_list_lock);
3632 QLIST_FOREACH(client, &map_client_list, link) {
3633 if (client->bh == bh) {
3634 cpu_unregister_map_client_do(client);
3635 break;
3638 qemu_mutex_unlock(&map_client_list_lock);
3641 static void cpu_notify_map_clients(void)
3643 qemu_mutex_lock(&map_client_list_lock);
3644 cpu_notify_map_clients_locked();
3645 qemu_mutex_unlock(&map_client_list_lock);
3648 static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,
3649 bool is_write, MemTxAttrs attrs)
3651 MemoryRegion *mr;
3652 hwaddr l, xlat;
3654 while (len > 0) {
3655 l = len;
3656 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3657 if (!memory_access_is_direct(mr, is_write)) {
3658 l = memory_access_size(mr, l, addr);
3659 if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
3660 return false;
3664 len -= l;
3665 addr += l;
3667 return true;
3670 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
3671 hwaddr len, bool is_write,
3672 MemTxAttrs attrs)
3674 FlatView *fv;
3675 bool result;
3677 rcu_read_lock();
3678 fv = address_space_to_flatview(as);
3679 result = flatview_access_valid(fv, addr, len, is_write, attrs);
3680 rcu_read_unlock();
3681 return result;
3684 static hwaddr
3685 flatview_extend_translation(FlatView *fv, hwaddr addr,
3686 hwaddr target_len,
3687 MemoryRegion *mr, hwaddr base, hwaddr len,
3688 bool is_write, MemTxAttrs attrs)
3690 hwaddr done = 0;
3691 hwaddr xlat;
3692 MemoryRegion *this_mr;
3694 for (;;) {
3695 target_len -= len;
3696 addr += len;
3697 done += len;
3698 if (target_len == 0) {
3699 return done;
3702 len = target_len;
3703 this_mr = flatview_translate(fv, addr, &xlat,
3704 &len, is_write, attrs);
3705 if (this_mr != mr || xlat != base + done) {
3706 return done;
3711 /* Map a physical memory region into a host virtual address.
3712 * May map a subset of the requested range, given by and returned in *plen.
3713 * May return NULL if resources needed to perform the mapping are exhausted.
3714 * Use only for reads OR writes - not for read-modify-write operations.
3715 * Use cpu_register_map_client() to know when retrying the map operation is
3716 * likely to succeed.
3718 void *address_space_map(AddressSpace *as,
3719 hwaddr addr,
3720 hwaddr *plen,
3721 bool is_write,
3722 MemTxAttrs attrs)
3724 hwaddr len = *plen;
3725 hwaddr l, xlat;
3726 MemoryRegion *mr;
3727 void *ptr;
3728 FlatView *fv;
3730 if (len == 0) {
3731 return NULL;
3734 l = len;
3735 rcu_read_lock();
3736 fv = address_space_to_flatview(as);
3737 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3739 if (!memory_access_is_direct(mr, is_write)) {
3740 if (atomic_xchg(&bounce.in_use, true)) {
3741 rcu_read_unlock();
3742 return NULL;
3744 /* Avoid unbounded allocations */
3745 l = MIN(l, TARGET_PAGE_SIZE);
3746 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3747 bounce.addr = addr;
3748 bounce.len = l;
3750 memory_region_ref(mr);
3751 bounce.mr = mr;
3752 if (!is_write) {
3753 flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED,
3754 bounce.buffer, l);
3757 rcu_read_unlock();
3758 *plen = l;
3759 return bounce.buffer;
3763 memory_region_ref(mr);
3764 *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
3765 l, is_write, attrs);
3766 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
3767 rcu_read_unlock();
3769 return ptr;
3772 /* Unmaps a memory region previously mapped by address_space_map().
3773 * Will also mark the memory as dirty if is_write == 1. access_len gives
3774 * the amount of memory that was actually read or written by the caller.
3776 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3777 int is_write, hwaddr access_len)
3779 if (buffer != bounce.buffer) {
3780 MemoryRegion *mr;
3781 ram_addr_t addr1;
3783 mr = memory_region_from_host(buffer, &addr1);
3784 assert(mr != NULL);
3785 if (is_write) {
3786 invalidate_and_set_dirty(mr, addr1, access_len);
3788 if (xen_enabled()) {
3789 xen_invalidate_map_cache_entry(buffer);
3791 memory_region_unref(mr);
3792 return;
3794 if (is_write) {
3795 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3796 bounce.buffer, access_len);
3798 qemu_vfree(bounce.buffer);
3799 bounce.buffer = NULL;
3800 memory_region_unref(bounce.mr);
3801 atomic_mb_set(&bounce.in_use, false);
3802 cpu_notify_map_clients();
3805 void *cpu_physical_memory_map(hwaddr addr,
3806 hwaddr *plen,
3807 int is_write)
3809 return address_space_map(&address_space_memory, addr, plen, is_write,
3810 MEMTXATTRS_UNSPECIFIED);
3813 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3814 int is_write, hwaddr access_len)
3816 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3819 #define ARG1_DECL AddressSpace *as
3820 #define ARG1 as
3821 #define SUFFIX
3822 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3823 #define RCU_READ_LOCK(...) rcu_read_lock()
3824 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3825 #include "memory_ldst.inc.c"
3827 int64_t address_space_cache_init(MemoryRegionCache *cache,
3828 AddressSpace *as,
3829 hwaddr addr,
3830 hwaddr len,
3831 bool is_write)
3833 AddressSpaceDispatch *d;
3834 hwaddr l;
3835 MemoryRegion *mr;
3837 assert(len > 0);
3839 l = len;
3840 cache->fv = address_space_get_flatview(as);
3841 d = flatview_to_dispatch(cache->fv);
3842 cache->mrs = *address_space_translate_internal(d, addr, &cache->xlat, &l, true);
3844 mr = cache->mrs.mr;
3845 memory_region_ref(mr);
3846 if (memory_access_is_direct(mr, is_write)) {
3847 /* We don't care about the memory attributes here as we're only
3848 * doing this if we found actual RAM, which behaves the same
3849 * regardless of attributes; so UNSPECIFIED is fine.
3851 l = flatview_extend_translation(cache->fv, addr, len, mr,
3852 cache->xlat, l, is_write,
3853 MEMTXATTRS_UNSPECIFIED);
3854 cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
3855 } else {
3856 cache->ptr = NULL;
3859 cache->len = l;
3860 cache->is_write = is_write;
3861 return l;
3864 void address_space_cache_invalidate(MemoryRegionCache *cache,
3865 hwaddr addr,
3866 hwaddr access_len)
3868 assert(cache->is_write);
3869 if (likely(cache->ptr)) {
3870 invalidate_and_set_dirty(cache->mrs.mr, addr + cache->xlat, access_len);
3874 void address_space_cache_destroy(MemoryRegionCache *cache)
3876 if (!cache->mrs.mr) {
3877 return;
3880 if (xen_enabled()) {
3881 xen_invalidate_map_cache_entry(cache->ptr);
3883 memory_region_unref(cache->mrs.mr);
3884 flatview_unref(cache->fv);
3885 cache->mrs.mr = NULL;
3886 cache->fv = NULL;
3889 /* Called from RCU critical section. This function has the same
3890 * semantics as address_space_translate, but it only works on a
3891 * predefined range of a MemoryRegion that was mapped with
3892 * address_space_cache_init.
3894 static inline MemoryRegion *address_space_translate_cached(
3895 MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
3896 hwaddr *plen, bool is_write, MemTxAttrs attrs)
3898 MemoryRegionSection section;
3899 MemoryRegion *mr;
3900 IOMMUMemoryRegion *iommu_mr;
3901 AddressSpace *target_as;
3903 assert(!cache->ptr);
3904 *xlat = addr + cache->xlat;
3906 mr = cache->mrs.mr;
3907 iommu_mr = memory_region_get_iommu(mr);
3908 if (!iommu_mr) {
3909 /* MMIO region. */
3910 return mr;
3913 section = address_space_translate_iommu(iommu_mr, xlat, plen,
3914 NULL, is_write, true,
3915 &target_as, attrs);
3916 return section.mr;
3919 /* Called from RCU critical section. address_space_read_cached uses this
3920 * out of line function when the target is an MMIO or IOMMU region.
3922 void
3923 address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
3924 void *buf, hwaddr len)
3926 hwaddr addr1, l;
3927 MemoryRegion *mr;
3929 l = len;
3930 mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
3931 MEMTXATTRS_UNSPECIFIED);
3932 flatview_read_continue(cache->fv,
3933 addr, MEMTXATTRS_UNSPECIFIED, buf, len,
3934 addr1, l, mr);
3937 /* Called from RCU critical section. address_space_write_cached uses this
3938 * out of line function when the target is an MMIO or IOMMU region.
3940 void
3941 address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
3942 const void *buf, hwaddr len)
3944 hwaddr addr1, l;
3945 MemoryRegion *mr;
3947 l = len;
3948 mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
3949 MEMTXATTRS_UNSPECIFIED);
3950 flatview_write_continue(cache->fv,
3951 addr, MEMTXATTRS_UNSPECIFIED, buf, len,
3952 addr1, l, mr);
3955 #define ARG1_DECL MemoryRegionCache *cache
3956 #define ARG1 cache
3957 #define SUFFIX _cached_slow
3958 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3959 #define RCU_READ_LOCK() ((void)0)
3960 #define RCU_READ_UNLOCK() ((void)0)
3961 #include "memory_ldst.inc.c"
3963 /* virtual memory access for debug (includes writing to ROM) */
3964 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3965 uint8_t *buf, target_ulong len, int is_write)
3967 hwaddr phys_addr;
3968 target_ulong l, page;
3970 cpu_synchronize_state(cpu);
3971 while (len > 0) {
3972 int asidx;
3973 MemTxAttrs attrs;
3975 page = addr & TARGET_PAGE_MASK;
3976 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3977 asidx = cpu_asidx_from_attrs(cpu, attrs);
3978 /* if no physical page mapped, return an error */
3979 if (phys_addr == -1)
3980 return -1;
3981 l = (page + TARGET_PAGE_SIZE) - addr;
3982 if (l > len)
3983 l = len;
3984 phys_addr += (addr & ~TARGET_PAGE_MASK);
3985 if (is_write) {
3986 address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr,
3987 attrs, buf, l);
3988 } else {
3989 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3990 attrs, buf, l, 0);
3992 len -= l;
3993 buf += l;
3994 addr += l;
3996 return 0;
4000 * Allows code that needs to deal with migration bitmaps etc to still be built
4001 * target independent.
4003 size_t qemu_target_page_size(void)
4005 return TARGET_PAGE_SIZE;
4008 int qemu_target_page_bits(void)
4010 return TARGET_PAGE_BITS;
4013 int qemu_target_page_bits_min(void)
4015 return TARGET_PAGE_BITS_MIN;
4017 #endif
4019 bool target_words_bigendian(void)
4021 #if defined(TARGET_WORDS_BIGENDIAN)
4022 return true;
4023 #else
4024 return false;
4025 #endif
4028 #ifndef CONFIG_USER_ONLY
4029 bool cpu_physical_memory_is_io(hwaddr phys_addr)
4031 MemoryRegion*mr;
4032 hwaddr l = 1;
4033 bool res;
4035 rcu_read_lock();
4036 mr = address_space_translate(&address_space_memory,
4037 phys_addr, &phys_addr, &l, false,
4038 MEMTXATTRS_UNSPECIFIED);
4040 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
4041 rcu_read_unlock();
4042 return res;
4045 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
4047 RAMBlock *block;
4048 int ret = 0;
4050 rcu_read_lock();
4051 RAMBLOCK_FOREACH(block) {
4052 ret = func(block, opaque);
4053 if (ret) {
4054 break;
4057 rcu_read_unlock();
4058 return ret;
4062 * Unmap pages of memory from start to start+length such that
4063 * they a) read as 0, b) Trigger whatever fault mechanism
4064 * the OS provides for postcopy.
4065 * The pages must be unmapped by the end of the function.
4066 * Returns: 0 on success, none-0 on failure
4069 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
4071 int ret = -1;
4073 uint8_t *host_startaddr = rb->host + start;
4075 if ((uintptr_t)host_startaddr & (rb->page_size - 1)) {
4076 error_report("ram_block_discard_range: Unaligned start address: %p",
4077 host_startaddr);
4078 goto err;
4081 if ((start + length) <= rb->used_length) {
4082 bool need_madvise, need_fallocate;
4083 uint8_t *host_endaddr = host_startaddr + length;
4084 if ((uintptr_t)host_endaddr & (rb->page_size - 1)) {
4085 error_report("ram_block_discard_range: Unaligned end address: %p",
4086 host_endaddr);
4087 goto err;
4090 errno = ENOTSUP; /* If we are missing MADVISE etc */
4092 /* The logic here is messy;
4093 * madvise DONTNEED fails for hugepages
4094 * fallocate works on hugepages and shmem
4096 need_madvise = (rb->page_size == qemu_host_page_size);
4097 need_fallocate = rb->fd != -1;
4098 if (need_fallocate) {
4099 /* For a file, this causes the area of the file to be zero'd
4100 * if read, and for hugetlbfs also causes it to be unmapped
4101 * so a userfault will trigger.
4103 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
4104 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
4105 start, length);
4106 if (ret) {
4107 ret = -errno;
4108 error_report("ram_block_discard_range: Failed to fallocate "
4109 "%s:%" PRIx64 " +%zx (%d)",
4110 rb->idstr, start, length, ret);
4111 goto err;
4113 #else
4114 ret = -ENOSYS;
4115 error_report("ram_block_discard_range: fallocate not available/file"
4116 "%s:%" PRIx64 " +%zx (%d)",
4117 rb->idstr, start, length, ret);
4118 goto err;
4119 #endif
4121 if (need_madvise) {
4122 /* For normal RAM this causes it to be unmapped,
4123 * for shared memory it causes the local mapping to disappear
4124 * and to fall back on the file contents (which we just
4125 * fallocate'd away).
4127 #if defined(CONFIG_MADVISE)
4128 ret = madvise(host_startaddr, length, MADV_DONTNEED);
4129 if (ret) {
4130 ret = -errno;
4131 error_report("ram_block_discard_range: Failed to discard range "
4132 "%s:%" PRIx64 " +%zx (%d)",
4133 rb->idstr, start, length, ret);
4134 goto err;
4136 #else
4137 ret = -ENOSYS;
4138 error_report("ram_block_discard_range: MADVISE not available"
4139 "%s:%" PRIx64 " +%zx (%d)",
4140 rb->idstr, start, length, ret);
4141 goto err;
4142 #endif
4144 trace_ram_block_discard_range(rb->idstr, host_startaddr, length,
4145 need_madvise, need_fallocate, ret);
4146 } else {
4147 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
4148 "/%zx/" RAM_ADDR_FMT")",
4149 rb->idstr, start, length, rb->used_length);
4152 err:
4153 return ret;
4156 bool ramblock_is_pmem(RAMBlock *rb)
4158 return rb->flags & RAM_PMEM;
4161 #endif
4163 void page_size_init(void)
4165 /* NOTE: we can always suppose that qemu_host_page_size >=
4166 TARGET_PAGE_SIZE */
4167 if (qemu_host_page_size == 0) {
4168 qemu_host_page_size = qemu_real_host_page_size;
4170 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
4171 qemu_host_page_size = TARGET_PAGE_SIZE;
4173 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
4176 #if !defined(CONFIG_USER_ONLY)
4178 static void mtree_print_phys_entries(int start, int end, int skip, int ptr)
4180 if (start == end - 1) {
4181 qemu_printf("\t%3d ", start);
4182 } else {
4183 qemu_printf("\t%3d..%-3d ", start, end - 1);
4185 qemu_printf(" skip=%d ", skip);
4186 if (ptr == PHYS_MAP_NODE_NIL) {
4187 qemu_printf(" ptr=NIL");
4188 } else if (!skip) {
4189 qemu_printf(" ptr=#%d", ptr);
4190 } else {
4191 qemu_printf(" ptr=[%d]", ptr);
4193 qemu_printf("\n");
4196 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4197 int128_sub((size), int128_one())) : 0)
4199 void mtree_print_dispatch(AddressSpaceDispatch *d, MemoryRegion *root)
4201 int i;
4203 qemu_printf(" Dispatch\n");
4204 qemu_printf(" Physical sections\n");
4206 for (i = 0; i < d->map.sections_nb; ++i) {
4207 MemoryRegionSection *s = d->map.sections + i;
4208 const char *names[] = { " [unassigned]", " [not dirty]",
4209 " [ROM]", " [watch]" };
4211 qemu_printf(" #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx
4212 " %s%s%s%s%s",
4214 s->offset_within_address_space,
4215 s->offset_within_address_space + MR_SIZE(s->mr->size),
4216 s->mr->name ? s->mr->name : "(noname)",
4217 i < ARRAY_SIZE(names) ? names[i] : "",
4218 s->mr == root ? " [ROOT]" : "",
4219 s == d->mru_section ? " [MRU]" : "",
4220 s->mr->is_iommu ? " [iommu]" : "");
4222 if (s->mr->alias) {
4223 qemu_printf(" alias=%s", s->mr->alias->name ?
4224 s->mr->alias->name : "noname");
4226 qemu_printf("\n");
4229 qemu_printf(" Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4230 P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip);
4231 for (i = 0; i < d->map.nodes_nb; ++i) {
4232 int j, jprev;
4233 PhysPageEntry prev;
4234 Node *n = d->map.nodes + i;
4236 qemu_printf(" [%d]\n", i);
4238 for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) {
4239 PhysPageEntry *pe = *n + j;
4241 if (pe->ptr == prev.ptr && pe->skip == prev.skip) {
4242 continue;
4245 mtree_print_phys_entries(jprev, j, prev.skip, prev.ptr);
4247 jprev = j;
4248 prev = *pe;
4251 if (jprev != ARRAY_SIZE(*n)) {
4252 mtree_print_phys_entries(jprev, j, prev.skip, prev.ptr);
4257 #endif