target/microblaze/cpu.c

   1 /*
   2  * QEMU MicroBlaze CPU
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias
   5  * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  * Copyright (c) 2012 SUSE LINUX Products GmbH
   7  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "cpu.h"
  27 #include "qemu/module.h"
  28 #include "hw/qdev-properties.h"
  29 #include "migration/vmstate.h"
  30 #include "exec/exec-all.h"
  31 #include "fpu/softfloat-helpers.h"
  32
  33 static const struct {
  34     const char *name;
  35     uint8_t version_id;
  36 } mb_cpu_lookup[] = {
  37     /* These key value are as per MBV field in PVR0 */
  38     {"5.00.a", 0x01},
  39     {"5.00.b", 0x02},
  40     {"5.00.c", 0x03},
  41     {"6.00.a", 0x04},
  42     {"6.00.b", 0x06},
  43     {"7.00.a", 0x05},
  44     {"7.00.b", 0x07},
  45     {"7.10.a", 0x08},
  46     {"7.10.b", 0x09},
  47     {"7.10.c", 0x0a},
  48     {"7.10.d", 0x0b},
  49     {"7.20.a", 0x0c},
  50     {"7.20.b", 0x0d},
  51     {"7.20.c", 0x0e},
  52     {"7.20.d", 0x0f},
  53     {"7.30.a", 0x10},
  54     {"7.30.b", 0x11},
  55     {"8.00.a", 0x12},
  56     {"8.00.b", 0x13},
  57     {"8.10.a", 0x14},
  58     {"8.20.a", 0x15},
  59     {"8.20.b", 0x16},
  60     {"8.30.a", 0x17},
  61     {"8.40.a", 0x18},
  62     {"8.40.b", 0x19},
  63     {"8.50.a", 0x1A},
  64     {"9.0", 0x1B},
  65     {"9.1", 0x1D},
  66     {"9.2", 0x1F},
  67     {"9.3", 0x20},
  68     {"9.4", 0x21},
  69     {"9.5", 0x22},
  70     {"9.6", 0x23},
  71     {"10.0", 0x24},
  72     {NULL, 0},
  73 };
  74
  75 /* If no specific version gets selected, default to the following.  */
  76 #define DEFAULT_CPU_VERSION "10.0"
  77
  78 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
  79 {
  80     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  81
  82     cpu->env.pc = value;
  83     /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
  84     cpu->env.iflags = 0;
  85 }
  86
  87 static void mb_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  88 {
  89     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  90
  91     cpu->env.pc = tb->pc;
  92     cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
  93 }
  94
  95 static bool mb_cpu_has_work(CPUState *cs)
  96 {
  97     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  98 }
  99
 100 #ifndef CONFIG_USER_ONLY
 101 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
 102 {
 103     MicroBlazeCPU *cpu = opaque;
 104     CPUState *cs = CPU(cpu);
 105     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
 106
 107     if (level) {
 108         cpu_interrupt(cs, type);
 109     } else {
 110         cpu_reset_interrupt(cs, type);
 111     }
 112 }
 113 #endif
 114
 115 static void mb_cpu_reset(DeviceState *dev)
 116 {
 117     CPUState *s = CPU(dev);
 118     MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
 119     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
 120     CPUMBState *env = &cpu->env;
 121
 122     mcc->parent_reset(dev);
 123
 124     memset(env, 0, offsetof(CPUMBState, end_reset_fields));
 125     env->res_addr = RES_ADDR_NONE;
 126
 127     /* Disable stack protector.  */
 128     env->shr = ~0;
 129
 130     env->pc = cpu->cfg.base_vectors;
 131
 132 #if defined(CONFIG_USER_ONLY)
 133     /* start in user mode with interrupts enabled.  */
 134     mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
 135 #else
 136     mb_cpu_write_msr(env, 0);
 137     mmu_init(&env->mmu);
 138     env->mmu.c_mmu = 3;
 139     env->mmu.c_mmu_tlb_access = 3;
 140     env->mmu.c_mmu_zones = 16;
 141     env->mmu.c_addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
 142 #endif
 143 }
 144
 145 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
 146 {
 147     info->mach = bfd_arch_microblaze;
 148     info->print_insn = print_insn_microblaze;
 149 }
 150
 151 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 152 {
 153     CPUState *cs = CPU(dev);
 154     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
 155     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 156     CPUMBState *env = &cpu->env;
 157     uint8_t version_code = 0;
 158     const char *version;
 159     int i = 0;
 160     Error *local_err = NULL;
 161
 162     cpu_exec_realizefn(cs, &local_err);
 163     if (local_err != NULL) {
 164         error_propagate(errp, local_err);
 165         return;
 166     }
 167
 168     if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
 169         error_setg(errp, "addr-size %d is out of range (32 - 64)",
 170                    cpu->cfg.addr_size);
 171         return;
 172     }
 173
 174     qemu_init_vcpu(cs);
 175
 176     env->pvr.regs[0] = PVR0_USE_EXC_MASK
 177                        | PVR0_USE_ICACHE_MASK
 178                        | PVR0_USE_DCACHE_MASK;
 179     env->pvr.regs[2] = PVR2_D_OPB_MASK
 180                         | PVR2_D_LMB_MASK
 181                         | PVR2_I_OPB_MASK
 182                         | PVR2_I_LMB_MASK
 183                         | PVR2_FPU_EXC_MASK
 184                         | 0;
 185
 186     version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
 187     for (i = 0; mb_cpu_lookup[i].name && version; i++) {
 188         if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
 189             version_code = mb_cpu_lookup[i].version_id;
 190             break;
 191         }
 192     }
 193
 194     if (!version_code) {
 195         qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
 196     }
 197
 198     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
 199                         (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
 200                         (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
 201                         (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
 202                         (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
 203                         (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
 204                         (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
 205                         (version_code << PVR0_VERSION_SHIFT) |
 206                         (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
 207                         cpu->cfg.pvr_user1;
 208
 209     env->pvr.regs[1] = cpu->cfg.pvr_user2;
 210     env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
 211                         (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
 212                         (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
 213                         (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
 214                         (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
 215                         (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
 216                         (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
 217                         (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
 218                         (cpu->cfg.dopb_bus_exception ?
 219                                                  PVR2_DOPB_BUS_EXC_MASK : 0) |
 220                         (cpu->cfg.iopb_bus_exception ?
 221                                                  PVR2_IOPB_BUS_EXC_MASK : 0) |
 222                         (cpu->cfg.div_zero_exception ?
 223                                                  PVR2_DIV_ZERO_EXC_MASK : 0) |
 224                         (cpu->cfg.illegal_opcode_exception ?
 225                                                 PVR2_ILL_OPCODE_EXC_MASK : 0) |
 226                         (cpu->cfg.unaligned_exceptions ?
 227                                                 PVR2_UNALIGNED_EXC_MASK : 0) |
 228                         (cpu->cfg.opcode_0_illegal ?
 229                                                  PVR2_OPCODE_0x0_ILL_MASK : 0);
 230
 231     env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
 232                                         PVR5_DCACHE_WRITEBACK_MASK : 0;
 233
 234     env->pvr.regs[10] = 0x0c000000 | /* Default to spartan 3a dsp family.  */
 235                         (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT;
 236     env->pvr.regs[11] = (cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
 237                         16 << 17;
 238
 239     mcc->parent_realize(dev, errp);
 240 }
 241
 242 static void mb_cpu_initfn(Object *obj)
 243 {
 244     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
 245     CPUMBState *env = &cpu->env;
 246
 247     cpu_set_cpustate_pointers(cpu);
 248
 249     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 250
 251 #ifndef CONFIG_USER_ONLY
 252     /* Inbound IRQ and FIR lines */
 253     qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
 254 #endif
 255 }
 256
 257 static const VMStateDescription vmstate_mb_cpu = {
 258     .name = "cpu",
 259     .unmigratable = 1,
 260 };
 261
 262 static Property mb_properties[] = {
 263     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
 264     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
 265                      false),
 266     /*
 267      * This is the C_ADDR_SIZE synth-time configuration option of the
 268      * MicroBlaze cores. Supported values range between 32 and 64.
 269      *
 270      * When set to > 32, 32bit MicroBlaze can emit load/stores
 271      * with extended addressing.
 272      */
 273     DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
 274     /* If use-fpu > 0 - FPU is enabled
 275      * If use-fpu = 2 - Floating point conversion and square root instructions
 276      *                  are enabled
 277      */
 278     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
 279     /* If use-hw-mul > 0 - Multiplier is enabled
 280      * If use-hw-mul = 2 - 64-bit multiplier is enabled
 281      */
 282     DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
 283     DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
 284     DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
 285     DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
 286     DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
 287     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
 288     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
 289                      false),
 290     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
 291     /* Enables bus exceptions on failed data accesses (load/stores).  */
 292     DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
 293                      cfg.dopb_bus_exception, false),
 294     /* Enables bus exceptions on failed instruction fetches.  */
 295     DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
 296                      cfg.iopb_bus_exception, false),
 297     DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
 298                      cfg.illegal_opcode_exception, false),
 299     DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
 300                      cfg.div_zero_exception, false),
 301     DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
 302                      cfg.unaligned_exceptions, false),
 303     DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
 304                      cfg.opcode_0_illegal, false),
 305     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
 306     DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
 307     DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
 308     DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
 309     DEFINE_PROP_END_OF_LIST(),
 310 };
 311
 312 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
 313 {
 314     return object_class_by_name(TYPE_MICROBLAZE_CPU);
 315 }
 316
 317 static void mb_cpu_class_init(ObjectClass *oc, void *data)
 318 {
 319     DeviceClass *dc = DEVICE_CLASS(oc);
 320     CPUClass *cc = CPU_CLASS(oc);
 321     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
 322
 323     device_class_set_parent_realize(dc, mb_cpu_realizefn,
 324                                     &mcc->parent_realize);
 325     device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset);
 326
 327     cc->class_by_name = mb_cpu_class_by_name;
 328     cc->has_work = mb_cpu_has_work;
 329     cc->do_interrupt = mb_cpu_do_interrupt;
 330     cc->do_unaligned_access = mb_cpu_do_unaligned_access;
 331     cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
 332     cc->dump_state = mb_cpu_dump_state;
 333     cc->set_pc = mb_cpu_set_pc;
 334     cc->synchronize_from_tb = mb_cpu_synchronize_from_tb;
 335     cc->gdb_read_register = mb_cpu_gdb_read_register;
 336     cc->gdb_write_register = mb_cpu_gdb_write_register;
 337     cc->tlb_fill = mb_cpu_tlb_fill;
 338 #ifndef CONFIG_USER_ONLY
 339     cc->do_transaction_failed = mb_cpu_transaction_failed;
 340     cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
 341 #endif
 342     dc->vmsd = &vmstate_mb_cpu;
 343     device_class_set_props(dc, mb_properties);
 344     cc->gdb_num_core_regs = 32 + 27;
 345
 346     cc->disas_set_info = mb_disas_set_info;
 347     cc->tcg_initialize = mb_tcg_init;
 348 }
 349
 350 static const TypeInfo mb_cpu_type_info = {
 351     .name = TYPE_MICROBLAZE_CPU,
 352     .parent = TYPE_CPU,
 353     .instance_size = sizeof(MicroBlazeCPU),
 354     .instance_init = mb_cpu_initfn,
 355     .class_size = sizeof(MicroBlazeCPUClass),
 356     .class_init = mb_cpu_class_init,
 357 };
 358
 359 static void mb_cpu_register_types(void)
 360 {
 361     type_register_static(&mb_cpu_type_info);
 362 }
 363
 364 type_init(mb_cpu_register_types)