2 * RISC-V CPU helpers for qemu.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
26 #define RISCV_DEBUG_INTERRUPT 0
28 int riscv_cpu_mmu_index(CPURISCVState
*env
, bool ifetch
)
30 #ifdef CONFIG_USER_ONLY
37 #ifndef CONFIG_USER_ONLY
38 static int riscv_cpu_local_irq_pending(CPURISCVState
*env
)
40 target_ulong mstatus_mie
= get_field(env
->mstatus
, MSTATUS_MIE
);
41 target_ulong mstatus_sie
= get_field(env
->mstatus
, MSTATUS_SIE
);
42 target_ulong pending
= atomic_read(&env
->mip
) & env
->mie
;
43 target_ulong mie
= env
->priv
< PRV_M
|| (env
->priv
== PRV_M
&& mstatus_mie
);
44 target_ulong sie
= env
->priv
< PRV_S
|| (env
->priv
== PRV_S
&& mstatus_sie
);
45 target_ulong irqs
= (pending
& ~env
->mideleg
& -mie
) |
46 (pending
& env
->mideleg
& -sie
);
49 return ctz64(irqs
); /* since non-zero */
51 return EXCP_NONE
; /* indicates no pending interrupt */
56 bool riscv_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
58 #if !defined(CONFIG_USER_ONLY)
59 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
60 RISCVCPU
*cpu
= RISCV_CPU(cs
);
61 CPURISCVState
*env
= &cpu
->env
;
62 int interruptno
= riscv_cpu_local_irq_pending(env
);
63 if (interruptno
>= 0) {
64 cs
->exception_index
= RISCV_EXCP_INT_FLAG
| interruptno
;
65 riscv_cpu_do_interrupt(cs
);
73 #if !defined(CONFIG_USER_ONLY)
75 /* iothread_mutex must be held */
76 uint32_t riscv_cpu_update_mip(RISCVCPU
*cpu
, uint32_t mask
, uint32_t value
)
78 CPURISCVState
*env
= &cpu
->env
;
79 uint32_t old
, new, cmp
= atomic_read(&env
->mip
);
83 new = (old
& ~mask
) | (value
& mask
);
84 cmp
= atomic_cmpxchg(&env
->mip
, old
, new);
88 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_HARD
);
89 } else if (!new && old
) {
90 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_HARD
);
96 void riscv_cpu_set_mode(CPURISCVState
*env
, target_ulong newpriv
)
98 if (newpriv
> PRV_M
) {
99 g_assert_not_reached();
101 if (newpriv
== PRV_H
) {
104 /* tlb_flush is unnecessary as mode is contained in mmu_idx */
108 /* get_physical_address - get the physical address for this virtual address
110 * Do a page table walk to obtain the physical address corresponding to a
111 * virtual address. Returns 0 if the translation was successful
113 * Adapted from Spike's mmu_t::translate and mmu_t::walk
116 static int get_physical_address(CPURISCVState
*env
, hwaddr
*physical
,
117 int *prot
, target_ulong addr
,
118 int access_type
, int mmu_idx
)
120 /* NOTE: the env->pc value visible here will not be
121 * correct, but the value visible to the exception handler
122 * (riscv_cpu_do_interrupt) is correct */
126 if (mode
== PRV_M
&& access_type
!= MMU_INST_FETCH
) {
127 if (get_field(env
->mstatus
, MSTATUS_MPRV
)) {
128 mode
= get_field(env
->mstatus
, MSTATUS_MPP
);
132 if (mode
== PRV_M
|| !riscv_feature(env
, RISCV_FEATURE_MMU
)) {
134 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
135 return TRANSLATE_SUCCESS
;
141 int levels
, ptidxbits
, ptesize
, vm
, sum
;
142 int mxr
= get_field(env
->mstatus
, MSTATUS_MXR
);
144 if (env
->priv_ver
>= PRIV_VERSION_1_10_0
) {
145 base
= get_field(env
->satp
, SATP_PPN
) << PGSHIFT
;
146 sum
= get_field(env
->mstatus
, MSTATUS_SUM
);
147 vm
= get_field(env
->satp
, SATP_MODE
);
150 levels
= 2; ptidxbits
= 10; ptesize
= 4; break;
152 levels
= 3; ptidxbits
= 9; ptesize
= 8; break;
154 levels
= 4; ptidxbits
= 9; ptesize
= 8; break;
156 levels
= 5; ptidxbits
= 9; ptesize
= 8; break;
159 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
160 return TRANSLATE_SUCCESS
;
162 g_assert_not_reached();
165 base
= env
->sptbr
<< PGSHIFT
;
166 sum
= !get_field(env
->mstatus
, MSTATUS_PUM
);
167 vm
= get_field(env
->mstatus
, MSTATUS_VM
);
170 levels
= 2; ptidxbits
= 10; ptesize
= 4; break;
172 levels
= 3; ptidxbits
= 9; ptesize
= 8; break;
174 levels
= 4; ptidxbits
= 9; ptesize
= 8; break;
177 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
178 return TRANSLATE_SUCCESS
;
180 g_assert_not_reached();
184 CPUState
*cs
= CPU(riscv_env_get_cpu(env
));
185 int va_bits
= PGSHIFT
+ levels
* ptidxbits
;
186 target_ulong mask
= (1L << (TARGET_LONG_BITS
- (va_bits
- 1))) - 1;
187 target_ulong masked_msbs
= (addr
>> (va_bits
- 1)) & mask
;
188 if (masked_msbs
!= 0 && masked_msbs
!= mask
) {
189 return TRANSLATE_FAIL
;
192 int ptshift
= (levels
- 1) * ptidxbits
;
195 #if !TCG_OVERSIZED_GUEST
198 for (i
= 0; i
< levels
; i
++, ptshift
-= ptidxbits
) {
199 target_ulong idx
= (addr
>> (PGSHIFT
+ ptshift
)) &
200 ((1 << ptidxbits
) - 1);
202 /* check that physical address of PTE is legal */
203 target_ulong pte_addr
= base
+ idx
* ptesize
;
204 #if defined(TARGET_RISCV32)
205 target_ulong pte
= ldl_phys(cs
->as
, pte_addr
);
206 #elif defined(TARGET_RISCV64)
207 target_ulong pte
= ldq_phys(cs
->as
, pte_addr
);
209 target_ulong ppn
= pte
>> PTE_PPN_SHIFT
;
211 if (!(pte
& PTE_V
)) {
213 return TRANSLATE_FAIL
;
214 } else if (!(pte
& (PTE_R
| PTE_W
| PTE_X
))) {
215 /* Inner PTE, continue walking */
216 base
= ppn
<< PGSHIFT
;
217 } else if ((pte
& (PTE_R
| PTE_W
| PTE_X
)) == PTE_W
) {
218 /* Reserved leaf PTE flags: PTE_W */
219 return TRANSLATE_FAIL
;
220 } else if ((pte
& (PTE_R
| PTE_W
| PTE_X
)) == (PTE_W
| PTE_X
)) {
221 /* Reserved leaf PTE flags: PTE_W + PTE_X */
222 return TRANSLATE_FAIL
;
223 } else if ((pte
& PTE_U
) && ((mode
!= PRV_U
) &&
224 (!sum
|| access_type
== MMU_INST_FETCH
))) {
225 /* User PTE flags when not U mode and mstatus.SUM is not set,
226 or the access type is an instruction fetch */
227 return TRANSLATE_FAIL
;
228 } else if (!(pte
& PTE_U
) && (mode
!= PRV_S
)) {
229 /* Supervisor PTE flags when not S mode */
230 return TRANSLATE_FAIL
;
231 } else if (ppn
& ((1ULL << ptshift
) - 1)) {
233 return TRANSLATE_FAIL
;
234 } else if (access_type
== MMU_DATA_LOAD
&& !((pte
& PTE_R
) ||
235 ((pte
& PTE_X
) && mxr
))) {
236 /* Read access check failed */
237 return TRANSLATE_FAIL
;
238 } else if (access_type
== MMU_DATA_STORE
&& !(pte
& PTE_W
)) {
239 /* Write access check failed */
240 return TRANSLATE_FAIL
;
241 } else if (access_type
== MMU_INST_FETCH
&& !(pte
& PTE_X
)) {
242 /* Fetch access check failed */
243 return TRANSLATE_FAIL
;
245 /* if necessary, set accessed and dirty bits. */
246 target_ulong updated_pte
= pte
| PTE_A
|
247 (access_type
== MMU_DATA_STORE
? PTE_D
: 0);
249 /* Page table updates need to be atomic with MTTCG enabled */
250 if (updated_pte
!= pte
) {
252 * - if accessed or dirty bits need updating, and the PTE is
253 * in RAM, then we do so atomically with a compare and swap.
254 * - if the PTE is in IO space or ROM, then it can't be updated
255 * and we return TRANSLATE_FAIL.
256 * - if the PTE changed by the time we went to update it, then
257 * it is no longer valid and we must re-walk the page table.
260 hwaddr l
= sizeof(target_ulong
), addr1
;
261 mr
= address_space_translate(cs
->as
, pte_addr
,
262 &addr1
, &l
, false, MEMTXATTRS_UNSPECIFIED
);
263 if (memory_region_is_ram(mr
)) {
264 target_ulong
*pte_pa
=
265 qemu_map_ram_ptr(mr
->ram_block
, addr1
);
266 #if TCG_OVERSIZED_GUEST
267 /* MTTCG is not enabled on oversized TCG guests so
268 * page table updates do not need to be atomic */
269 *pte_pa
= pte
= updated_pte
;
271 target_ulong old_pte
=
272 atomic_cmpxchg(pte_pa
, pte
, updated_pte
);
273 if (old_pte
!= pte
) {
280 /* misconfigured PTE in ROM (AD bits are not preset) or
281 * PTE is in IO space and can't be updated atomically */
282 return TRANSLATE_FAIL
;
286 /* for superpage mappings, make a fake leaf PTE for the TLB's
288 target_ulong vpn
= addr
>> PGSHIFT
;
289 *physical
= (ppn
| (vpn
& ((1L << ptshift
) - 1))) << PGSHIFT
;
291 /* set permissions on the TLB entry */
292 if ((pte
& PTE_R
) || ((pte
& PTE_X
) && mxr
)) {
298 /* add write permission on stores or if the page is already dirty,
299 so that we TLB miss on later writes to update the dirty bit */
301 (access_type
== MMU_DATA_STORE
|| (pte
& PTE_D
))) {
304 return TRANSLATE_SUCCESS
;
307 return TRANSLATE_FAIL
;
310 static void raise_mmu_exception(CPURISCVState
*env
, target_ulong address
,
311 MMUAccessType access_type
)
313 CPUState
*cs
= CPU(riscv_env_get_cpu(env
));
314 int page_fault_exceptions
=
315 (env
->priv_ver
>= PRIV_VERSION_1_10_0
) &&
316 get_field(env
->satp
, SATP_MODE
) != VM_1_10_MBARE
;
317 switch (access_type
) {
319 cs
->exception_index
= page_fault_exceptions
?
320 RISCV_EXCP_INST_PAGE_FAULT
: RISCV_EXCP_INST_ACCESS_FAULT
;
323 cs
->exception_index
= page_fault_exceptions
?
324 RISCV_EXCP_LOAD_PAGE_FAULT
: RISCV_EXCP_LOAD_ACCESS_FAULT
;
327 cs
->exception_index
= page_fault_exceptions
?
328 RISCV_EXCP_STORE_PAGE_FAULT
: RISCV_EXCP_STORE_AMO_ACCESS_FAULT
;
331 g_assert_not_reached();
333 env
->badaddr
= address
;
336 hwaddr
riscv_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
338 RISCVCPU
*cpu
= RISCV_CPU(cs
);
341 int mmu_idx
= cpu_mmu_index(&cpu
->env
, false);
343 if (get_physical_address(&cpu
->env
, &phys_addr
, &prot
, addr
, 0, mmu_idx
)) {
349 void riscv_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
350 MMUAccessType access_type
, int mmu_idx
,
353 RISCVCPU
*cpu
= RISCV_CPU(cs
);
354 CPURISCVState
*env
= &cpu
->env
;
355 switch (access_type
) {
357 cs
->exception_index
= RISCV_EXCP_INST_ADDR_MIS
;
360 cs
->exception_index
= RISCV_EXCP_LOAD_ADDR_MIS
;
363 cs
->exception_index
= RISCV_EXCP_STORE_AMO_ADDR_MIS
;
366 g_assert_not_reached();
369 riscv_raise_exception(env
, cs
->exception_index
, retaddr
);
372 /* called by qemu's softmmu to fill the qemu tlb */
373 void tlb_fill(CPUState
*cs
, target_ulong addr
, int size
,
374 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
377 ret
= riscv_cpu_handle_mmu_fault(cs
, addr
, size
, access_type
, mmu_idx
);
378 if (ret
== TRANSLATE_FAIL
) {
379 RISCVCPU
*cpu
= RISCV_CPU(cs
);
380 CPURISCVState
*env
= &cpu
->env
;
381 riscv_raise_exception(env
, cs
->exception_index
, retaddr
);
387 int riscv_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int size
,
390 RISCVCPU
*cpu
= RISCV_CPU(cs
);
391 CPURISCVState
*env
= &cpu
->env
;
392 #if !defined(CONFIG_USER_ONLY)
396 int ret
= TRANSLATE_FAIL
;
398 qemu_log_mask(CPU_LOG_MMU
,
399 "%s pc " TARGET_FMT_lx
" ad %" VADDR_PRIx
" rw %d mmu_idx \
400 %d\n", __func__
, env
->pc
, address
, rw
, mmu_idx
);
402 #if !defined(CONFIG_USER_ONLY)
403 ret
= get_physical_address(env
, &pa
, &prot
, address
, rw
, mmu_idx
);
404 qemu_log_mask(CPU_LOG_MMU
,
405 "%s address=%" VADDR_PRIx
" ret %d physical " TARGET_FMT_plx
406 " prot %d\n", __func__
, address
, ret
, pa
, prot
);
407 if (riscv_feature(env
, RISCV_FEATURE_PMP
) &&
408 !pmp_hart_has_privs(env
, pa
, TARGET_PAGE_SIZE
, 1 << rw
)) {
409 ret
= TRANSLATE_FAIL
;
411 if (ret
== TRANSLATE_SUCCESS
) {
412 tlb_set_page(cs
, address
& TARGET_PAGE_MASK
, pa
& TARGET_PAGE_MASK
,
413 prot
, mmu_idx
, TARGET_PAGE_SIZE
);
414 } else if (ret
== TRANSLATE_FAIL
) {
415 raise_mmu_exception(env
, address
, rw
);
420 cs
->exception_index
= RISCV_EXCP_INST_PAGE_FAULT
;
423 cs
->exception_index
= RISCV_EXCP_LOAD_PAGE_FAULT
;
426 cs
->exception_index
= RISCV_EXCP_STORE_PAGE_FAULT
;
436 * Adapted from Spike's processor_t::take_trap.
439 void riscv_cpu_do_interrupt(CPUState
*cs
)
441 #if !defined(CONFIG_USER_ONLY)
443 RISCVCPU
*cpu
= RISCV_CPU(cs
);
444 CPURISCVState
*env
= &cpu
->env
;
446 if (RISCV_DEBUG_INTERRUPT
) {
447 int log_cause
= cs
->exception_index
& RISCV_EXCP_INT_MASK
;
448 if (cs
->exception_index
& RISCV_EXCP_INT_FLAG
) {
449 qemu_log_mask(LOG_TRACE
, "core "
450 TARGET_FMT_ld
": trap %s, epc 0x" TARGET_FMT_lx
"\n",
451 env
->mhartid
, riscv_intr_names
[log_cause
], env
->pc
);
453 qemu_log_mask(LOG_TRACE
, "core "
454 TARGET_FMT_ld
": intr %s, epc 0x" TARGET_FMT_lx
"\n",
455 env
->mhartid
, riscv_excp_names
[log_cause
], env
->pc
);
459 target_ulong fixed_cause
= 0;
460 if (cs
->exception_index
& (RISCV_EXCP_INT_FLAG
)) {
461 /* hacky for now. the MSB (bit 63) indicates interrupt but cs->exception
462 index is only 32 bits wide */
463 fixed_cause
= cs
->exception_index
& RISCV_EXCP_INT_MASK
;
464 fixed_cause
|= ((target_ulong
)1) << (TARGET_LONG_BITS
- 1);
466 /* fixup User ECALL -> correct priv ECALL */
467 if (cs
->exception_index
== RISCV_EXCP_U_ECALL
) {
470 fixed_cause
= RISCV_EXCP_U_ECALL
;
473 fixed_cause
= RISCV_EXCP_S_ECALL
;
476 fixed_cause
= RISCV_EXCP_H_ECALL
;
479 fixed_cause
= RISCV_EXCP_M_ECALL
;
483 fixed_cause
= cs
->exception_index
;
487 target_ulong backup_epc
= env
->pc
;
489 target_ulong bit
= fixed_cause
;
490 target_ulong deleg
= env
->medeleg
;
493 (fixed_cause
== RISCV_EXCP_INST_ADDR_MIS
) ||
494 (fixed_cause
== RISCV_EXCP_INST_ACCESS_FAULT
) ||
495 (fixed_cause
== RISCV_EXCP_LOAD_ADDR_MIS
) ||
496 (fixed_cause
== RISCV_EXCP_STORE_AMO_ADDR_MIS
) ||
497 (fixed_cause
== RISCV_EXCP_LOAD_ACCESS_FAULT
) ||
498 (fixed_cause
== RISCV_EXCP_STORE_AMO_ACCESS_FAULT
) ||
499 (fixed_cause
== RISCV_EXCP_INST_PAGE_FAULT
) ||
500 (fixed_cause
== RISCV_EXCP_LOAD_PAGE_FAULT
) ||
501 (fixed_cause
== RISCV_EXCP_STORE_PAGE_FAULT
);
503 if (bit
& ((target_ulong
)1 << (TARGET_LONG_BITS
- 1))) {
504 deleg
= env
->mideleg
;
505 bit
&= ~((target_ulong
)1 << (TARGET_LONG_BITS
- 1));
508 if (env
->priv
<= PRV_S
&& bit
< 64 && ((deleg
>> bit
) & 1)) {
509 /* handle the trap in S-mode */
510 /* No need to check STVEC for misaligned - lower 2 bits cannot be set */
511 env
->pc
= env
->stvec
;
512 env
->scause
= fixed_cause
;
513 env
->sepc
= backup_epc
;
516 if (RISCV_DEBUG_INTERRUPT
) {
517 qemu_log_mask(LOG_TRACE
, "core " TARGET_FMT_ld
": badaddr 0x"
518 TARGET_FMT_lx
"\n", env
->mhartid
, env
->badaddr
);
520 env
->sbadaddr
= env
->badaddr
;
522 /* otherwise we must clear sbadaddr/stval
523 * todo: support populating stval on illegal instructions */
527 target_ulong s
= env
->mstatus
;
528 s
= set_field(s
, MSTATUS_SPIE
, env
->priv_ver
>= PRIV_VERSION_1_10_0
?
529 get_field(s
, MSTATUS_SIE
) : get_field(s
, MSTATUS_UIE
<< env
->priv
));
530 s
= set_field(s
, MSTATUS_SPP
, env
->priv
);
531 s
= set_field(s
, MSTATUS_SIE
, 0);
533 riscv_cpu_set_mode(env
, PRV_S
);
535 /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
536 env
->pc
= env
->mtvec
;
537 env
->mepc
= backup_epc
;
538 env
->mcause
= fixed_cause
;
541 if (RISCV_DEBUG_INTERRUPT
) {
542 qemu_log_mask(LOG_TRACE
, "core " TARGET_FMT_ld
": badaddr 0x"
543 TARGET_FMT_lx
"\n", env
->mhartid
, env
->badaddr
);
545 env
->mbadaddr
= env
->badaddr
;
547 /* otherwise we must clear mbadaddr/mtval
548 * todo: support populating mtval on illegal instructions */
552 target_ulong s
= env
->mstatus
;
553 s
= set_field(s
, MSTATUS_MPIE
, env
->priv_ver
>= PRIV_VERSION_1_10_0
?
554 get_field(s
, MSTATUS_MIE
) : get_field(s
, MSTATUS_UIE
<< env
->priv
));
555 s
= set_field(s
, MSTATUS_MPP
, env
->priv
);
556 s
= set_field(s
, MSTATUS_MIE
, 0);
558 riscv_cpu_set_mode(env
, PRV_M
);
560 /* TODO yield load reservation */
562 cs
->exception_index
= EXCP_NONE
; /* mark handled to qemu */