2 * MIPS internal definitions and helpers
4 * This work is licensed under the terms of the GNU GPL, version 2 or later.
5 * See the COPYING file in the top-level directory.
8 #ifndef MIPS_INTERNAL_H
9 #define MIPS_INTERNAL_H
11 #include "exec/memattrs.h"
14 * MMU types, the first four entries have the same layout as the
19 MMU_TYPE_R4000
= 1, /* Standard TLB */
20 MMU_TYPE_BAT
= 2, /* Block Address Translation */
21 MMU_TYPE_FMT
= 3, /* Fixed Mapping */
22 MMU_TYPE_DVF
= 4, /* Dual VTLB and FTLB */
36 int32_t CP0_Config4_rw_bitmask
;
38 int32_t CP0_Config5_rw_bitmask
;
40 int32_t CP0_Config6_rw_bitmask
;
42 int32_t CP0_Config7_rw_bitmask
;
43 target_ulong CP0_LLAddr_rw_bitmask
;
47 int32_t CP0_Status_rw_bitmask
;
48 int32_t CP0_TCStatus_rw_bitmask
;
51 int32_t CP1_fcr31_rw_bitmask
;
56 int32_t CP0_SRSConf0_rw_bitmask
;
58 int32_t CP0_SRSConf1_rw_bitmask
;
60 int32_t CP0_SRSConf2_rw_bitmask
;
62 int32_t CP0_SRSConf3_rw_bitmask
;
64 int32_t CP0_SRSConf4_rw_bitmask
;
66 int32_t CP0_PageGrain_rw_bitmask
;
67 int32_t CP0_PageGrain
;
68 target_ulong CP0_EBaseWG_rw_bitmask
;
70 enum mips_mmu_types mmu_type
;
74 extern const char regnames
[32][4];
75 extern const char fregnames
[32][4];
77 extern const struct mips_def_t mips_defs
[];
78 extern const int mips_defs_number
;
80 void mips_cpu_do_interrupt(CPUState
*cpu
);
81 bool mips_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
82 void mips_cpu_dump_state(CPUState
*cpu
, FILE *f
, int flags
);
83 hwaddr
mips_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
84 int mips_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
85 int mips_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
86 void mips_cpu_do_unaligned_access(CPUState
*cpu
, vaddr addr
,
87 MMUAccessType access_type
,
88 int mmu_idx
, uintptr_t retaddr
);
90 #if !defined(CONFIG_USER_ONLY)
92 typedef struct r4k_tlb_t r4k_tlb_t
;
109 unsigned int EHINV
:1;
113 struct CPUMIPSTLBContext
{
116 int (*map_address
)(struct CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
117 target_ulong address
, MMUAccessType access_type
);
118 void (*helper_tlbwi
)(struct CPUMIPSState
*env
);
119 void (*helper_tlbwr
)(struct CPUMIPSState
*env
);
120 void (*helper_tlbp
)(struct CPUMIPSState
*env
);
121 void (*helper_tlbr
)(struct CPUMIPSState
*env
);
122 void (*helper_tlbinv
)(struct CPUMIPSState
*env
);
123 void (*helper_tlbinvf
)(struct CPUMIPSState
*env
);
126 r4k_tlb_t tlb
[MIPS_TLB_MAX
];
131 int no_mmu_map_address(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
132 target_ulong address
, MMUAccessType access_type
);
133 int fixed_mmu_map_address(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
134 target_ulong address
, MMUAccessType access_type
);
135 int r4k_map_address(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
136 target_ulong address
, MMUAccessType access_type
);
137 void r4k_helper_tlbwi(CPUMIPSState
*env
);
138 void r4k_helper_tlbwr(CPUMIPSState
*env
);
139 void r4k_helper_tlbp(CPUMIPSState
*env
);
140 void r4k_helper_tlbr(CPUMIPSState
*env
);
141 void r4k_helper_tlbinv(CPUMIPSState
*env
);
142 void r4k_helper_tlbinvf(CPUMIPSState
*env
);
143 void r4k_invalidate_tlb(CPUMIPSState
*env
, int idx
, int use_extra
);
144 uint32_t cpu_mips_get_random(CPUMIPSState
*env
);
146 void mips_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
147 vaddr addr
, unsigned size
,
148 MMUAccessType access_type
,
149 int mmu_idx
, MemTxAttrs attrs
,
150 MemTxResult response
, uintptr_t retaddr
);
151 hwaddr
cpu_mips_translate_address(CPUMIPSState
*env
, target_ulong address
,
152 MMUAccessType access_type
);
155 #define cpu_signal_handler cpu_mips_signal_handler
157 #ifndef CONFIG_USER_ONLY
158 extern const VMStateDescription vmstate_mips_cpu
;
161 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState
*env
)
163 return (env
->CP0_Status
& (1 << CP0St_IE
)) &&
164 !(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
165 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
166 !(env
->hflags
& MIPS_HFLAG_DM
) &&
168 * Note that the TCStatus IXMT field is initialized to zero,
169 * and only MT capable cores can set it to one. So we don't
170 * need to check for MT capabilities here.
172 !(env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_IXMT
));
175 /* Check if there is pending and not masked out interrupt */
176 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState
*env
)
182 pending
= env
->CP0_Cause
& CP0Ca_IP_mask
;
183 status
= env
->CP0_Status
& CP0Ca_IP_mask
;
185 if (env
->CP0_Config3
& (1 << CP0C3_VEIC
)) {
187 * A MIPS configured with a vectorizing external interrupt controller
188 * will feed a vector into the Cause pending lines. The core treats
189 * the status lines as a vector level, not as individual masks.
191 r
= pending
> status
;
194 * A MIPS configured with compatibility or VInt (Vectored Interrupts)
195 * treats the pending lines as individual interrupt lines, the status
196 * lines are individual masks.
198 r
= (pending
& status
) != 0;
203 void mips_tcg_init(void);
205 void msa_reset(CPUMIPSState
*env
);
208 uint32_t cpu_mips_get_count(CPUMIPSState
*env
);
209 void cpu_mips_store_count(CPUMIPSState
*env
, uint32_t value
);
210 void cpu_mips_store_compare(CPUMIPSState
*env
, uint32_t value
);
211 void cpu_mips_start_count(CPUMIPSState
*env
);
212 void cpu_mips_stop_count(CPUMIPSState
*env
);
215 void mmu_init(CPUMIPSState
*env
, const mips_def_t
*def
);
216 bool mips_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
217 MMUAccessType access_type
, int mmu_idx
,
218 bool probe
, uintptr_t retaddr
);
221 void update_pagemask(CPUMIPSState
*env
, target_ulong arg1
, int32_t *pagemask
);
223 static inline void restore_pamask(CPUMIPSState
*env
)
225 if (env
->hflags
& MIPS_HFLAG_ELPA
) {
226 env
->PAMask
= (1ULL << env
->PABITS
) - 1;
228 env
->PAMask
= PAMASK_BASE
;
232 static inline int mips_vpe_active(CPUMIPSState
*env
)
236 /* Check that the VPE is enabled. */
237 if (!(env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_EVP
))) {
240 /* Check that the VPE is activated. */
241 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))) {
246 * Now verify that there are active thread contexts in the VPE.
248 * This assumes the CPU model will internally reschedule threads
249 * if the active one goes to sleep. If there are no threads available
250 * the active one will be in a sleeping state, and we can turn off
253 if (!(env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_A
))) {
254 /* TC is not activated. */
257 if (env
->active_tc
.CP0_TCHalt
& 1) {
258 /* TC is in halt state. */
265 static inline int mips_vp_active(CPUMIPSState
*env
)
267 CPUState
*other_cs
= first_cpu
;
269 /* Check if the VP disabled other VPs (which means the VP is enabled) */
270 if ((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1) {
274 /* Check if the virtual processor is disabled due to a DVP */
275 CPU_FOREACH(other_cs
) {
276 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
277 if ((&other_cpu
->env
!= env
) &&
278 ((other_cpu
->env
.CP0_VPControl
>> CP0VPCtl_DIS
) & 1)) {
285 static inline void compute_hflags(CPUMIPSState
*env
)
287 env
->hflags
&= ~(MIPS_HFLAG_COP1X
| MIPS_HFLAG_64
| MIPS_HFLAG_CP0
|
288 MIPS_HFLAG_F64
| MIPS_HFLAG_FPU
| MIPS_HFLAG_KSU
|
289 MIPS_HFLAG_AWRAP
| MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
|
290 MIPS_HFLAG_DSP_R3
| MIPS_HFLAG_SBRI
| MIPS_HFLAG_MSA
|
291 MIPS_HFLAG_FRE
| MIPS_HFLAG_ELPA
| MIPS_HFLAG_ERL
);
292 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
293 env
->hflags
|= MIPS_HFLAG_ERL
;
295 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
296 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
297 !(env
->hflags
& MIPS_HFLAG_DM
)) {
298 env
->hflags
|= (env
->CP0_Status
>> CP0St_KSU
) &
301 #if defined(TARGET_MIPS64)
302 if ((env
->insn_flags
& ISA_MIPS3
) &&
303 (((env
->hflags
& MIPS_HFLAG_KSU
) != MIPS_HFLAG_UM
) ||
304 (env
->CP0_Status
& (1 << CP0St_PX
)) ||
305 (env
->CP0_Status
& (1 << CP0St_UX
)))) {
306 env
->hflags
|= MIPS_HFLAG_64
;
309 if (!(env
->insn_flags
& ISA_MIPS3
)) {
310 env
->hflags
|= MIPS_HFLAG_AWRAP
;
311 } else if (((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
312 !(env
->CP0_Status
& (1 << CP0St_UX
))) {
313 env
->hflags
|= MIPS_HFLAG_AWRAP
;
314 } else if (env
->insn_flags
& ISA_MIPS_R6
) {
315 /* Address wrapping for Supervisor and Kernel is specified in R6 */
316 if ((((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_SM
) &&
317 !(env
->CP0_Status
& (1 << CP0St_SX
))) ||
318 (((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_KM
) &&
319 !(env
->CP0_Status
& (1 << CP0St_KX
)))) {
320 env
->hflags
|= MIPS_HFLAG_AWRAP
;
324 if (((env
->CP0_Status
& (1 << CP0St_CU0
)) &&
325 !(env
->insn_flags
& ISA_MIPS_R6
)) ||
326 !(env
->hflags
& MIPS_HFLAG_KSU
)) {
327 env
->hflags
|= MIPS_HFLAG_CP0
;
329 if (env
->CP0_Status
& (1 << CP0St_CU1
)) {
330 env
->hflags
|= MIPS_HFLAG_FPU
;
332 if (env
->CP0_Status
& (1 << CP0St_FR
)) {
333 env
->hflags
|= MIPS_HFLAG_F64
;
335 if (((env
->hflags
& MIPS_HFLAG_KSU
) != MIPS_HFLAG_KM
) &&
336 (env
->CP0_Config5
& (1 << CP0C5_SBRI
))) {
337 env
->hflags
|= MIPS_HFLAG_SBRI
;
339 if (env
->insn_flags
& ASE_DSP_R3
) {
341 * Our cpu supports DSP R3 ASE, so enable
342 * access to DSP R3 resources.
344 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
345 env
->hflags
|= MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
|
348 } else if (env
->insn_flags
& ASE_DSP_R2
) {
350 * Our cpu supports DSP R2 ASE, so enable
351 * access to DSP R2 resources.
353 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
354 env
->hflags
|= MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
;
357 } else if (env
->insn_flags
& ASE_DSP
) {
359 * Our cpu supports DSP ASE, so enable
360 * access to DSP resources.
362 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
363 env
->hflags
|= MIPS_HFLAG_DSP
;
367 if (env
->insn_flags
& ISA_MIPS_R2
) {
368 if (env
->active_fpu
.fcr0
& (1 << FCR0_F64
)) {
369 env
->hflags
|= MIPS_HFLAG_COP1X
;
371 } else if (env
->insn_flags
& ISA_MIPS_R1
) {
372 if (env
->hflags
& MIPS_HFLAG_64
) {
373 env
->hflags
|= MIPS_HFLAG_COP1X
;
375 } else if (env
->insn_flags
& ISA_MIPS4
) {
377 * All supported MIPS IV CPUs use the XX (CU3) to enable
378 * and disable the MIPS IV extensions to the MIPS III ISA.
379 * Some other MIPS IV CPUs ignore the bit, so the check here
380 * would be too restrictive for them.
382 if (env
->CP0_Status
& (1U << CP0St_CU3
)) {
383 env
->hflags
|= MIPS_HFLAG_COP1X
;
386 if (ase_msa_available(env
)) {
387 if (env
->CP0_Config5
& (1 << CP0C5_MSAEn
)) {
388 env
->hflags
|= MIPS_HFLAG_MSA
;
391 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
392 if (env
->CP0_Config5
& (1 << CP0C5_FRE
)) {
393 env
->hflags
|= MIPS_HFLAG_FRE
;
396 if (env
->CP0_Config3
& (1 << CP0C3_LPA
)) {
397 if (env
->CP0_PageGrain
& (1 << CP0PG_ELPA
)) {
398 env
->hflags
|= MIPS_HFLAG_ELPA
;
403 void cpu_mips_tlb_flush(CPUMIPSState
*env
);
404 void sync_c0_status(CPUMIPSState
*env
, CPUMIPSState
*cpu
, int tc
);
405 void cpu_mips_store_status(CPUMIPSState
*env
, target_ulong val
);
406 void cpu_mips_store_cause(CPUMIPSState
*env
, target_ulong val
);
408 const char *mips_exception_name(int32_t exception
);
410 void QEMU_NORETURN
do_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
411 int error_code
, uintptr_t pc
);
413 static inline void QEMU_NORETURN
do_raise_exception(CPUMIPSState
*env
,
417 do_raise_exception_err(env
, exception
, 0, pc
);