2 * i386 virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "sysemu/tcg.h"
25 #include "kvm/hyperv-proto.h"
26 #include "exec/cpu-defs.h"
27 #include "qapi/qapi-types-common.h"
28 #include "qemu/cpu-float.h"
29 #include "qemu/timer.h"
31 #define XEN_NR_VIRQS 24
33 /* The x86 has a strong memory model with some store-after-load re-ordering */
34 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
36 #define KVM_HAVE_MCE_INJECTION 1
38 /* support for self modifying code even if the modified instruction is
39 close to the modifying instruction */
40 #define TARGET_HAS_PRECISE_SMC
43 #define I386_ELF_MACHINE EM_X86_64
44 #define ELF_MACHINE_UNAME "x86_64"
46 #define I386_ELF_MACHINE EM_386
47 #define ELF_MACHINE_UNAME "i686"
89 /* segment descriptor fields */
90 #define DESC_G_SHIFT 23
91 #define DESC_G_MASK (1 << DESC_G_SHIFT)
92 #define DESC_B_SHIFT 22
93 #define DESC_B_MASK (1 << DESC_B_SHIFT)
94 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
95 #define DESC_L_MASK (1 << DESC_L_SHIFT)
96 #define DESC_AVL_SHIFT 20
97 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
98 #define DESC_P_SHIFT 15
99 #define DESC_P_MASK (1 << DESC_P_SHIFT)
100 #define DESC_DPL_SHIFT 13
101 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
102 #define DESC_S_SHIFT 12
103 #define DESC_S_MASK (1 << DESC_S_SHIFT)
104 #define DESC_TYPE_SHIFT 8
105 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
106 #define DESC_A_MASK (1 << 8)
108 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
109 #define DESC_C_MASK (1 << 10) /* code: conforming */
110 #define DESC_R_MASK (1 << 9) /* code: readable */
112 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
113 #define DESC_W_MASK (1 << 9) /* data: writable */
115 #define DESC_TSS_BUSY_MASK (1 << 9)
126 #define IOPL_SHIFT 12
129 #define TF_MASK 0x00000100
130 #define IF_MASK 0x00000200
131 #define DF_MASK 0x00000400
132 #define IOPL_MASK 0x00003000
133 #define NT_MASK 0x00004000
134 #define RF_MASK 0x00010000
135 #define VM_MASK 0x00020000
136 #define AC_MASK 0x00040000
137 #define VIF_MASK 0x00080000
138 #define VIP_MASK 0x00100000
139 #define ID_MASK 0x00200000
141 /* hidden flags - used internally by qemu to represent additional cpu
142 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
143 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
144 positions to ease oring with eflags. */
146 #define HF_CPL_SHIFT 0
147 /* true if hardware interrupts must be disabled for next instruction */
148 #define HF_INHIBIT_IRQ_SHIFT 3
149 /* 16 or 32 segments */
150 #define HF_CS32_SHIFT 4
151 #define HF_SS32_SHIFT 5
152 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
153 #define HF_ADDSEG_SHIFT 6
154 /* copy of CR0.PE (protected mode) */
155 #define HF_PE_SHIFT 7
156 #define HF_TF_SHIFT 8 /* must be same as eflags */
157 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
158 #define HF_EM_SHIFT 10
159 #define HF_TS_SHIFT 11
160 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
161 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
162 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
163 #define HF_RF_SHIFT 16 /* must be same as eflags */
164 #define HF_VM_SHIFT 17 /* must be same as eflags */
165 #define HF_AC_SHIFT 18 /* must be same as eflags */
166 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
167 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
168 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */
169 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
170 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
171 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */
172 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
173 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */
174 #define HF_UMIP_SHIFT 27 /* CR4.UMIP */
175 #define HF_AVX_EN_SHIFT 28 /* AVX Enabled (CR4+XCR0) */
177 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
178 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
179 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
180 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
181 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
182 #define HF_PE_MASK (1 << HF_PE_SHIFT)
183 #define HF_TF_MASK (1 << HF_TF_SHIFT)
184 #define HF_MP_MASK (1 << HF_MP_SHIFT)
185 #define HF_EM_MASK (1 << HF_EM_SHIFT)
186 #define HF_TS_MASK (1 << HF_TS_SHIFT)
187 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
188 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
189 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
190 #define HF_RF_MASK (1 << HF_RF_SHIFT)
191 #define HF_VM_MASK (1 << HF_VM_SHIFT)
192 #define HF_AC_MASK (1 << HF_AC_SHIFT)
193 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
194 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
195 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
196 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
197 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
198 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
199 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
200 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
201 #define HF_UMIP_MASK (1 << HF_UMIP_SHIFT)
202 #define HF_AVX_EN_MASK (1 << HF_AVX_EN_SHIFT)
206 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
207 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
208 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
209 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
210 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
211 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
212 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */
213 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */
214 #define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/
216 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
217 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
218 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
219 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
220 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
221 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
222 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
223 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
224 #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT)
226 #define CR0_PE_SHIFT 0
227 #define CR0_MP_SHIFT 1
229 #define CR0_PE_MASK (1U << 0)
230 #define CR0_MP_MASK (1U << 1)
231 #define CR0_EM_MASK (1U << 2)
232 #define CR0_TS_MASK (1U << 3)
233 #define CR0_ET_MASK (1U << 4)
234 #define CR0_NE_MASK (1U << 5)
235 #define CR0_WP_MASK (1U << 16)
236 #define CR0_AM_MASK (1U << 18)
237 #define CR0_NW_MASK (1U << 29)
238 #define CR0_CD_MASK (1U << 30)
239 #define CR0_PG_MASK (1U << 31)
241 #define CR4_VME_MASK (1U << 0)
242 #define CR4_PVI_MASK (1U << 1)
243 #define CR4_TSD_MASK (1U << 2)
244 #define CR4_DE_MASK (1U << 3)
245 #define CR4_PSE_MASK (1U << 4)
246 #define CR4_PAE_MASK (1U << 5)
247 #define CR4_MCE_MASK (1U << 6)
248 #define CR4_PGE_MASK (1U << 7)
249 #define CR4_PCE_MASK (1U << 8)
250 #define CR4_OSFXSR_SHIFT 9
251 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
252 #define CR4_OSXMMEXCPT_MASK (1U << 10)
253 #define CR4_UMIP_MASK (1U << 11)
254 #define CR4_LA57_MASK (1U << 12)
255 #define CR4_VMXE_MASK (1U << 13)
256 #define CR4_SMXE_MASK (1U << 14)
257 #define CR4_FSGSBASE_MASK (1U << 16)
258 #define CR4_PCIDE_MASK (1U << 17)
259 #define CR4_OSXSAVE_MASK (1U << 18)
260 #define CR4_SMEP_MASK (1U << 20)
261 #define CR4_SMAP_MASK (1U << 21)
262 #define CR4_PKE_MASK (1U << 22)
263 #define CR4_PKS_MASK (1U << 24)
265 #define CR4_RESERVED_MASK \
266 (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \
267 | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
268 | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \
269 | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \
271 | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
272 | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK))
274 #define DR6_BD (1 << 13)
275 #define DR6_BS (1 << 14)
276 #define DR6_BT (1 << 15)
277 #define DR6_FIXED_1 0xffff0ff0
279 #define DR7_GD (1 << 13)
280 #define DR7_TYPE_SHIFT 16
281 #define DR7_LEN_SHIFT 18
282 #define DR7_FIXED_1 0x00000400
283 #define DR7_GLOBAL_BP_MASK 0xaa
284 #define DR7_LOCAL_BP_MASK 0x55
286 #define DR7_TYPE_BP_INST 0x0
287 #define DR7_TYPE_DATA_WR 0x1
288 #define DR7_TYPE_IO_RW 0x2
289 #define DR7_TYPE_DATA_RW 0x3
291 #define DR_RESERVED_MASK 0xffffffff00000000ULL
293 #define PG_PRESENT_BIT 0
295 #define PG_USER_BIT 2
298 #define PG_ACCESSED_BIT 5
299 #define PG_DIRTY_BIT 6
301 #define PG_GLOBAL_BIT 8
302 #define PG_PSE_PAT_BIT 12
303 #define PG_PKRU_BIT 59
306 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
307 #define PG_RW_MASK (1 << PG_RW_BIT)
308 #define PG_USER_MASK (1 << PG_USER_BIT)
309 #define PG_PWT_MASK (1 << PG_PWT_BIT)
310 #define PG_PCD_MASK (1 << PG_PCD_BIT)
311 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
312 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
313 #define PG_PSE_MASK (1 << PG_PSE_BIT)
314 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
315 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
316 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
317 #define PG_HI_USER_MASK 0x7ff0000000000000LL
318 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
319 #define PG_NX_MASK (1ULL << PG_NX_BIT)
321 #define PG_ERROR_W_BIT 1
323 #define PG_ERROR_P_MASK 0x01
324 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
325 #define PG_ERROR_U_MASK 0x04
326 #define PG_ERROR_RSVD_MASK 0x08
327 #define PG_ERROR_I_D_MASK 0x10
328 #define PG_ERROR_PK_MASK 0x20
330 #define PG_MODE_PAE (1 << 0)
331 #define PG_MODE_LMA (1 << 1)
332 #define PG_MODE_NXE (1 << 2)
333 #define PG_MODE_PSE (1 << 3)
334 #define PG_MODE_LA57 (1 << 4)
335 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
337 /* Bits of CR4 that do not affect the NPT page format. */
338 #define PG_MODE_WP (1 << 16)
339 #define PG_MODE_PKE (1 << 17)
340 #define PG_MODE_PKS (1 << 18)
341 #define PG_MODE_SMEP (1 << 19)
343 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
344 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
345 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */
347 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
348 #define MCE_BANKS_DEF 10
350 #define MCG_CAP_BANKS_MASK 0xff
352 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
353 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
354 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
355 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */
357 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
359 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
360 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
361 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
362 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
363 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
364 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
365 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
366 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
367 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
369 /* MISC register defines */
370 #define MCM_ADDR_SEGOFF 0 /* segment offset */
371 #define MCM_ADDR_LINEAR 1 /* linear address */
372 #define MCM_ADDR_PHYS 2 /* physical address */
373 #define MCM_ADDR_MEM 3 /* memory address */
374 #define MCM_ADDR_GENERIC 7 /* generic */
376 #define MSR_IA32_TSC 0x10
377 #define MSR_IA32_APICBASE 0x1b
378 #define MSR_IA32_APICBASE_BSP (1<<8)
379 #define MSR_IA32_APICBASE_ENABLE (1<<11)
380 #define MSR_IA32_APICBASE_EXTD (1 << 10)
381 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
382 #define MSR_IA32_APICBASE_RESERVED \
383 (~(uint64_t)(MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE \
384 | MSR_IA32_APICBASE_EXTD | MSR_IA32_APICBASE_BASE))
386 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
387 #define MSR_TSC_ADJUST 0x0000003b
388 #define MSR_IA32_SPEC_CTRL 0x48
389 #define MSR_VIRT_SSBD 0xc001011f
390 #define MSR_IA32_PRED_CMD 0x49
391 #define MSR_IA32_UCODE_REV 0x8b
392 #define MSR_IA32_CORE_CAPABILITY 0xcf
394 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
395 #define ARCH_CAP_TSX_CTRL_MSR (1<<7)
397 #define MSR_IA32_PERF_CAPABILITIES 0x345
398 #define PERF_CAP_LBR_FMT 0x3f
400 #define MSR_IA32_TSX_CTRL 0x122
401 #define MSR_IA32_TSCDEADLINE 0x6e0
402 #define MSR_IA32_PKRS 0x6e1
403 #define MSR_ARCH_LBR_CTL 0x000014ce
404 #define MSR_ARCH_LBR_DEPTH 0x000014cf
405 #define MSR_ARCH_LBR_FROM_0 0x00001500
406 #define MSR_ARCH_LBR_TO_0 0x00001600
407 #define MSR_ARCH_LBR_INFO_0 0x00001200
409 #define FEATURE_CONTROL_LOCKED (1<<0)
410 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1)
411 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
412 #define FEATURE_CONTROL_SGX_LC (1ULL << 17)
413 #define FEATURE_CONTROL_SGX (1ULL << 18)
414 #define FEATURE_CONTROL_LMCE (1<<20)
416 #define MSR_IA32_SGXLEPUBKEYHASH0 0x8c
417 #define MSR_IA32_SGXLEPUBKEYHASH1 0x8d
418 #define MSR_IA32_SGXLEPUBKEYHASH2 0x8e
419 #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f
421 #define MSR_P6_PERFCTR0 0xc1
423 #define MSR_IA32_SMBASE 0x9e
424 #define MSR_SMI_COUNT 0x34
425 #define MSR_CORE_THREAD_COUNT 0x35
426 #define MSR_MTRRcap 0xfe
427 #define MSR_MTRRcap_VCNT 8
428 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
429 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
431 #define MSR_IA32_SYSENTER_CS 0x174
432 #define MSR_IA32_SYSENTER_ESP 0x175
433 #define MSR_IA32_SYSENTER_EIP 0x176
435 #define MSR_MCG_CAP 0x179
436 #define MSR_MCG_STATUS 0x17a
437 #define MSR_MCG_CTL 0x17b
438 #define MSR_MCG_EXT_CTL 0x4d0
440 #define MSR_P6_EVNTSEL0 0x186
442 #define MSR_IA32_PERF_STATUS 0x198
444 #define MSR_IA32_MISC_ENABLE 0x1a0
445 /* Indicates good rep/movs microcode on some processors: */
446 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
447 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
449 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
450 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
452 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
454 #define MSR_MTRRfix64K_00000 0x250
455 #define MSR_MTRRfix16K_80000 0x258
456 #define MSR_MTRRfix16K_A0000 0x259
457 #define MSR_MTRRfix4K_C0000 0x268
458 #define MSR_MTRRfix4K_C8000 0x269
459 #define MSR_MTRRfix4K_D0000 0x26a
460 #define MSR_MTRRfix4K_D8000 0x26b
461 #define MSR_MTRRfix4K_E0000 0x26c
462 #define MSR_MTRRfix4K_E8000 0x26d
463 #define MSR_MTRRfix4K_F0000 0x26e
464 #define MSR_MTRRfix4K_F8000 0x26f
466 #define MSR_PAT 0x277
468 #define MSR_MTRRdefType 0x2ff
470 #define MSR_CORE_PERF_FIXED_CTR0 0x309
471 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
472 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
473 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
474 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
475 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
476 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
478 #define MSR_MC0_CTL 0x400
479 #define MSR_MC0_STATUS 0x401
480 #define MSR_MC0_ADDR 0x402
481 #define MSR_MC0_MISC 0x403
483 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560
484 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561
485 #define MSR_IA32_RTIT_CTL 0x570
486 #define MSR_IA32_RTIT_STATUS 0x571
487 #define MSR_IA32_RTIT_CR3_MATCH 0x572
488 #define MSR_IA32_RTIT_ADDR0_A 0x580
489 #define MSR_IA32_RTIT_ADDR0_B 0x581
490 #define MSR_IA32_RTIT_ADDR1_A 0x582
491 #define MSR_IA32_RTIT_ADDR1_B 0x583
492 #define MSR_IA32_RTIT_ADDR2_A 0x584
493 #define MSR_IA32_RTIT_ADDR2_B 0x585
494 #define MSR_IA32_RTIT_ADDR3_A 0x586
495 #define MSR_IA32_RTIT_ADDR3_B 0x587
496 #define MAX_RTIT_ADDRS 8
498 #define MSR_EFER 0xc0000080
500 #define MSR_EFER_SCE (1 << 0)
501 #define MSR_EFER_LME (1 << 8)
502 #define MSR_EFER_LMA (1 << 10)
503 #define MSR_EFER_NXE (1 << 11)
504 #define MSR_EFER_SVME (1 << 12)
505 #define MSR_EFER_FFXSR (1 << 14)
507 #define MSR_EFER_RESERVED\
508 (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\
509 | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\
512 #define MSR_STAR 0xc0000081
513 #define MSR_LSTAR 0xc0000082
514 #define MSR_CSTAR 0xc0000083
515 #define MSR_FMASK 0xc0000084
516 #define MSR_FSBASE 0xc0000100
517 #define MSR_GSBASE 0xc0000101
518 #define MSR_KERNELGSBASE 0xc0000102
519 #define MSR_TSC_AUX 0xc0000103
520 #define MSR_AMD64_TSC_RATIO 0xc0000104
522 #define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL
524 #define MSR_VM_HSAVE_PA 0xc0010117
526 #define MSR_IA32_XFD 0x000001c4
527 #define MSR_IA32_XFD_ERR 0x000001c5
529 #define MSR_IA32_BNDCFGS 0x00000d90
530 #define MSR_IA32_XSS 0x00000da0
531 #define MSR_IA32_UMWAIT_CONTROL 0xe1
533 #define MSR_IA32_VMX_BASIC 0x00000480
534 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
535 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
536 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
537 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
538 #define MSR_IA32_VMX_MISC 0x00000485
539 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
540 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
541 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
542 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
543 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
544 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
545 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
546 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
547 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
548 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
549 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
550 #define MSR_IA32_VMX_VMFUNC 0x00000491
552 #define MSR_APIC_START 0x00000800
553 #define MSR_APIC_END 0x000008ff
555 #define XSTATE_FP_BIT 0
556 #define XSTATE_SSE_BIT 1
557 #define XSTATE_YMM_BIT 2
558 #define XSTATE_BNDREGS_BIT 3
559 #define XSTATE_BNDCSR_BIT 4
560 #define XSTATE_OPMASK_BIT 5
561 #define XSTATE_ZMM_Hi256_BIT 6
562 #define XSTATE_Hi16_ZMM_BIT 7
563 #define XSTATE_PKRU_BIT 9
564 #define XSTATE_ARCH_LBR_BIT 15
565 #define XSTATE_XTILE_CFG_BIT 17
566 #define XSTATE_XTILE_DATA_BIT 18
568 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
569 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
570 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
571 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
572 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
573 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
574 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
575 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
576 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
577 #define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT)
578 #define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT)
579 #define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT)
581 #define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK)
583 #define ESA_FEATURE_ALIGN64_BIT 1
584 #define ESA_FEATURE_XFD_BIT 2
586 #define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT)
587 #define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT)
590 /* CPUID feature bits available in XCR0 */
591 #define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \
592 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \
593 XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \
594 XSTATE_ZMM_Hi256_MASK | \
595 XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
596 XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK)
598 /* CPUID feature words */
599 typedef enum FeatureWord
{
600 FEAT_1_EDX
, /* CPUID[1].EDX */
601 FEAT_1_ECX
, /* CPUID[1].ECX */
602 FEAT_7_0_EBX
, /* CPUID[EAX=7,ECX=0].EBX */
603 FEAT_7_0_ECX
, /* CPUID[EAX=7,ECX=0].ECX */
604 FEAT_7_0_EDX
, /* CPUID[EAX=7,ECX=0].EDX */
605 FEAT_7_1_EAX
, /* CPUID[EAX=7,ECX=1].EAX */
606 FEAT_8000_0001_EDX
, /* CPUID[8000_0001].EDX */
607 FEAT_8000_0001_ECX
, /* CPUID[8000_0001].ECX */
608 FEAT_8000_0007_EDX
, /* CPUID[8000_0007].EDX */
609 FEAT_8000_0008_EBX
, /* CPUID[8000_0008].EBX */
610 FEAT_8000_0021_EAX
, /* CPUID[8000_0021].EAX */
611 FEAT_C000_0001_EDX
, /* CPUID[C000_0001].EDX */
612 FEAT_KVM
, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
613 FEAT_KVM_HINTS
, /* CPUID[4000_0001].EDX */
614 FEAT_SVM
, /* CPUID[8000_000A].EDX */
615 FEAT_XSAVE
, /* CPUID[EAX=0xd,ECX=1].EAX */
616 FEAT_6_EAX
, /* CPUID[6].EAX */
617 FEAT_XSAVE_XCR0_LO
, /* CPUID[EAX=0xd,ECX=0].EAX */
618 FEAT_XSAVE_XCR0_HI
, /* CPUID[EAX=0xd,ECX=0].EDX */
619 FEAT_ARCH_CAPABILITIES
,
620 FEAT_CORE_CAPABILITY
,
621 FEAT_PERF_CAPABILITIES
,
622 FEAT_VMX_PROCBASED_CTLS
,
623 FEAT_VMX_SECONDARY_CTLS
,
624 FEAT_VMX_PINBASED_CTLS
,
628 FEAT_VMX_EPT_VPID_CAPS
,
632 FEAT_SGX_12_0_EAX
, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
633 FEAT_SGX_12_0_EBX
, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
634 FEAT_SGX_12_1_EAX
, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
635 FEAT_XSAVE_XSS_LO
, /* CPUID[EAX=0xd,ECX=1].ECX */
636 FEAT_XSAVE_XSS_HI
, /* CPUID[EAX=0xd,ECX=1].EDX */
637 FEAT_7_1_EDX
, /* CPUID[EAX=7,ECX=1].EDX */
638 FEAT_7_2_EDX
, /* CPUID[EAX=7,ECX=2].EDX */
642 typedef uint64_t FeatureWordArray
[FEATURE_WORDS
];
643 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w
,
644 bool migratable_only
);
646 /* cpuid_features bits */
647 #define CPUID_FP87 (1U << 0)
648 #define CPUID_VME (1U << 1)
649 #define CPUID_DE (1U << 2)
650 #define CPUID_PSE (1U << 3)
651 #define CPUID_TSC (1U << 4)
652 #define CPUID_MSR (1U << 5)
653 #define CPUID_PAE (1U << 6)
654 #define CPUID_MCE (1U << 7)
655 #define CPUID_CX8 (1U << 8)
656 #define CPUID_APIC (1U << 9)
657 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
658 #define CPUID_MTRR (1U << 12)
659 #define CPUID_PGE (1U << 13)
660 #define CPUID_MCA (1U << 14)
661 #define CPUID_CMOV (1U << 15)
662 #define CPUID_PAT (1U << 16)
663 #define CPUID_PSE36 (1U << 17)
664 #define CPUID_PN (1U << 18)
665 #define CPUID_CLFLUSH (1U << 19)
666 #define CPUID_DTS (1U << 21)
667 #define CPUID_ACPI (1U << 22)
668 #define CPUID_MMX (1U << 23)
669 #define CPUID_FXSR (1U << 24)
670 #define CPUID_SSE (1U << 25)
671 #define CPUID_SSE2 (1U << 26)
672 #define CPUID_SS (1U << 27)
673 #define CPUID_HT (1U << 28)
674 #define CPUID_TM (1U << 29)
675 #define CPUID_IA64 (1U << 30)
676 #define CPUID_PBE (1U << 31)
678 #define CPUID_EXT_SSE3 (1U << 0)
679 #define CPUID_EXT_PCLMULQDQ (1U << 1)
680 #define CPUID_EXT_DTES64 (1U << 2)
681 #define CPUID_EXT_MONITOR (1U << 3)
682 #define CPUID_EXT_DSCPL (1U << 4)
683 #define CPUID_EXT_VMX (1U << 5)
684 #define CPUID_EXT_SMX (1U << 6)
685 #define CPUID_EXT_EST (1U << 7)
686 #define CPUID_EXT_TM2 (1U << 8)
687 #define CPUID_EXT_SSSE3 (1U << 9)
688 #define CPUID_EXT_CID (1U << 10)
689 #define CPUID_EXT_FMA (1U << 12)
690 #define CPUID_EXT_CX16 (1U << 13)
691 #define CPUID_EXT_XTPR (1U << 14)
692 #define CPUID_EXT_PDCM (1U << 15)
693 #define CPUID_EXT_PCID (1U << 17)
694 #define CPUID_EXT_DCA (1U << 18)
695 #define CPUID_EXT_SSE41 (1U << 19)
696 #define CPUID_EXT_SSE42 (1U << 20)
697 #define CPUID_EXT_X2APIC (1U << 21)
698 #define CPUID_EXT_MOVBE (1U << 22)
699 #define CPUID_EXT_POPCNT (1U << 23)
700 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
701 #define CPUID_EXT_AES (1U << 25)
702 #define CPUID_EXT_XSAVE (1U << 26)
703 #define CPUID_EXT_OSXSAVE (1U << 27)
704 #define CPUID_EXT_AVX (1U << 28)
705 #define CPUID_EXT_F16C (1U << 29)
706 #define CPUID_EXT_RDRAND (1U << 30)
707 #define CPUID_EXT_HYPERVISOR (1U << 31)
709 #define CPUID_EXT2_FPU (1U << 0)
710 #define CPUID_EXT2_VME (1U << 1)
711 #define CPUID_EXT2_DE (1U << 2)
712 #define CPUID_EXT2_PSE (1U << 3)
713 #define CPUID_EXT2_TSC (1U << 4)
714 #define CPUID_EXT2_MSR (1U << 5)
715 #define CPUID_EXT2_PAE (1U << 6)
716 #define CPUID_EXT2_MCE (1U << 7)
717 #define CPUID_EXT2_CX8 (1U << 8)
718 #define CPUID_EXT2_APIC (1U << 9)
719 #define CPUID_EXT2_SYSCALL (1U << 11)
720 #define CPUID_EXT2_MTRR (1U << 12)
721 #define CPUID_EXT2_PGE (1U << 13)
722 #define CPUID_EXT2_MCA (1U << 14)
723 #define CPUID_EXT2_CMOV (1U << 15)
724 #define CPUID_EXT2_PAT (1U << 16)
725 #define CPUID_EXT2_PSE36 (1U << 17)
726 #define CPUID_EXT2_MP (1U << 19)
727 #define CPUID_EXT2_NX (1U << 20)
728 #define CPUID_EXT2_MMXEXT (1U << 22)
729 #define CPUID_EXT2_MMX (1U << 23)
730 #define CPUID_EXT2_FXSR (1U << 24)
731 #define CPUID_EXT2_FFXSR (1U << 25)
732 #define CPUID_EXT2_PDPE1GB (1U << 26)
733 #define CPUID_EXT2_RDTSCP (1U << 27)
734 #define CPUID_EXT2_LM (1U << 29)
735 #define CPUID_EXT2_3DNOWEXT (1U << 30)
736 #define CPUID_EXT2_3DNOW (1U << 31)
738 /* CPUID[8000_0001].EDX bits that are aliases of CPUID[1].EDX bits on AMD CPUs */
739 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
740 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
741 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
742 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
743 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
744 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
745 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
746 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
747 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
749 #define CPUID_EXT3_LAHF_LM (1U << 0)
750 #define CPUID_EXT3_CMP_LEG (1U << 1)
751 #define CPUID_EXT3_SVM (1U << 2)
752 #define CPUID_EXT3_EXTAPIC (1U << 3)
753 #define CPUID_EXT3_CR8LEG (1U << 4)
754 #define CPUID_EXT3_ABM (1U << 5)
755 #define CPUID_EXT3_SSE4A (1U << 6)
756 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
757 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
758 #define CPUID_EXT3_OSVW (1U << 9)
759 #define CPUID_EXT3_IBS (1U << 10)
760 #define CPUID_EXT3_XOP (1U << 11)
761 #define CPUID_EXT3_SKINIT (1U << 12)
762 #define CPUID_EXT3_WDT (1U << 13)
763 #define CPUID_EXT3_LWP (1U << 15)
764 #define CPUID_EXT3_FMA4 (1U << 16)
765 #define CPUID_EXT3_TCE (1U << 17)
766 #define CPUID_EXT3_NODEID (1U << 19)
767 #define CPUID_EXT3_TBM (1U << 21)
768 #define CPUID_EXT3_TOPOEXT (1U << 22)
769 #define CPUID_EXT3_PERFCORE (1U << 23)
770 #define CPUID_EXT3_PERFNB (1U << 24)
772 #define CPUID_SVM_NPT (1U << 0)
773 #define CPUID_SVM_LBRV (1U << 1)
774 #define CPUID_SVM_SVMLOCK (1U << 2)
775 #define CPUID_SVM_NRIPSAVE (1U << 3)
776 #define CPUID_SVM_TSCSCALE (1U << 4)
777 #define CPUID_SVM_VMCBCLEAN (1U << 5)
778 #define CPUID_SVM_FLUSHASID (1U << 6)
779 #define CPUID_SVM_DECODEASSIST (1U << 7)
780 #define CPUID_SVM_PAUSEFILTER (1U << 10)
781 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
782 #define CPUID_SVM_AVIC (1U << 13)
783 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
784 #define CPUID_SVM_VGIF (1U << 16)
785 #define CPUID_SVM_VNMI (1U << 25)
786 #define CPUID_SVM_SVME_ADDR_CHK (1U << 28)
788 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
789 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
791 #define CPUID_7_0_EBX_SGX (1U << 2)
792 /* 1st Group of Advanced Bit Manipulation Extensions */
793 #define CPUID_7_0_EBX_BMI1 (1U << 3)
794 /* Hardware Lock Elision */
795 #define CPUID_7_0_EBX_HLE (1U << 4)
796 /* Intel Advanced Vector Extensions 2 */
797 #define CPUID_7_0_EBX_AVX2 (1U << 5)
798 /* Supervisor-mode Execution Prevention */
799 #define CPUID_7_0_EBX_SMEP (1U << 7)
800 /* 2nd Group of Advanced Bit Manipulation Extensions */
801 #define CPUID_7_0_EBX_BMI2 (1U << 8)
802 /* Enhanced REP MOVSB/STOSB */
803 #define CPUID_7_0_EBX_ERMS (1U << 9)
804 /* Invalidate Process-Context Identifier */
805 #define CPUID_7_0_EBX_INVPCID (1U << 10)
806 /* Restricted Transactional Memory */
807 #define CPUID_7_0_EBX_RTM (1U << 11)
808 /* Memory Protection Extension */
809 #define CPUID_7_0_EBX_MPX (1U << 14)
810 /* AVX-512 Foundation */
811 #define CPUID_7_0_EBX_AVX512F (1U << 16)
812 /* AVX-512 Doubleword & Quadword Instruction */
813 #define CPUID_7_0_EBX_AVX512DQ (1U << 17)
814 /* Read Random SEED */
815 #define CPUID_7_0_EBX_RDSEED (1U << 18)
816 /* ADCX and ADOX instructions */
817 #define CPUID_7_0_EBX_ADX (1U << 19)
818 /* Supervisor Mode Access Prevention */
819 #define CPUID_7_0_EBX_SMAP (1U << 20)
820 /* AVX-512 Integer Fused Multiply Add */
821 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
822 /* Persistent Commit */
823 #define CPUID_7_0_EBX_PCOMMIT (1U << 22)
824 /* Flush a Cache Line Optimized */
825 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
826 /* Cache Line Write Back */
827 #define CPUID_7_0_EBX_CLWB (1U << 24)
828 /* Intel Processor Trace */
829 #define CPUID_7_0_EBX_INTEL_PT (1U << 25)
830 /* AVX-512 Prefetch */
831 #define CPUID_7_0_EBX_AVX512PF (1U << 26)
832 /* AVX-512 Exponential and Reciprocal */
833 #define CPUID_7_0_EBX_AVX512ER (1U << 27)
834 /* AVX-512 Conflict Detection */
835 #define CPUID_7_0_EBX_AVX512CD (1U << 28)
836 /* SHA1/SHA256 Instruction Extensions */
837 #define CPUID_7_0_EBX_SHA_NI (1U << 29)
838 /* AVX-512 Byte and Word Instructions */
839 #define CPUID_7_0_EBX_AVX512BW (1U << 30)
840 /* AVX-512 Vector Length Extensions */
841 #define CPUID_7_0_EBX_AVX512VL (1U << 31)
843 /* AVX-512 Vector Byte Manipulation Instruction */
844 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
845 /* User-Mode Instruction Prevention */
846 #define CPUID_7_0_ECX_UMIP (1U << 2)
847 /* Protection Keys for User-mode Pages */
848 #define CPUID_7_0_ECX_PKU (1U << 3)
849 /* OS Enable Protection Keys */
850 #define CPUID_7_0_ECX_OSPKE (1U << 4)
851 /* UMONITOR/UMWAIT/TPAUSE Instructions */
852 #define CPUID_7_0_ECX_WAITPKG (1U << 5)
853 /* Additional AVX-512 Vector Byte Manipulation Instruction */
854 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
855 /* Galois Field New Instructions */
856 #define CPUID_7_0_ECX_GFNI (1U << 8)
857 /* Vector AES Instructions */
858 #define CPUID_7_0_ECX_VAES (1U << 9)
859 /* Carry-Less Multiplication Quadword */
860 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
861 /* Vector Neural Network Instructions */
862 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
863 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
864 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
865 /* POPCNT for vectors of DW/QW */
866 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
867 /* 5-level Page Tables */
868 #define CPUID_7_0_ECX_LA57 (1U << 16)
869 /* Read Processor ID */
870 #define CPUID_7_0_ECX_RDPID (1U << 22)
871 /* Bus Lock Debug Exception */
872 #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24)
873 /* Cache Line Demote Instruction */
874 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
875 /* Move Doubleword as Direct Store Instruction */
876 #define CPUID_7_0_ECX_MOVDIRI (1U << 27)
877 /* Move 64 Bytes as Direct Store Instruction */
878 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
879 /* Support SGX Launch Control */
880 #define CPUID_7_0_ECX_SGX_LC (1U << 30)
881 /* Protection Keys for Supervisor-mode Pages */
882 #define CPUID_7_0_ECX_PKS (1U << 31)
884 /* AVX512 Neural Network Instructions */
885 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
886 /* AVX512 Multiply Accumulation Single Precision */
887 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
888 /* Fast Short Rep Mov */
889 #define CPUID_7_0_EDX_FSRM (1U << 4)
890 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
891 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
892 /* SERIALIZE instruction */
893 #define CPUID_7_0_EDX_SERIALIZE (1U << 14)
894 /* TSX Suspend Load Address Tracking instruction */
895 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
896 /* Architectural LBRs */
897 #define CPUID_7_0_EDX_ARCH_LBR (1U << 19)
898 /* AMX_BF16 instruction */
899 #define CPUID_7_0_EDX_AMX_BF16 (1U << 22)
900 /* AVX512_FP16 instruction */
901 #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
902 /* AMX tile (two-dimensional register) */
903 #define CPUID_7_0_EDX_AMX_TILE (1U << 24)
904 /* AMX_INT8 instruction */
905 #define CPUID_7_0_EDX_AMX_INT8 (1U << 25)
906 /* Speculation Control */
907 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
908 /* Single Thread Indirect Branch Predictors */
909 #define CPUID_7_0_EDX_STIBP (1U << 27)
910 /* Flush L1D cache */
911 #define CPUID_7_0_EDX_FLUSH_L1D (1U << 28)
912 /* Arch Capabilities */
913 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
914 /* Core Capability */
915 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
916 /* Speculative Store Bypass Disable */
917 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
919 /* AVX VNNI Instruction */
920 #define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
921 /* AVX512 BFloat16 Instruction */
922 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
923 /* CMPCCXADD Instructions */
924 #define CPUID_7_1_EAX_CMPCCXADD (1U << 7)
925 /* Fast Zero REP MOVS */
926 #define CPUID_7_1_EAX_FZRM (1U << 10)
927 /* Fast Short REP STOS */
928 #define CPUID_7_1_EAX_FSRS (1U << 11)
929 /* Fast Short REP CMPS/SCAS */
930 #define CPUID_7_1_EAX_FSRC (1U << 12)
931 /* Support Tile Computational Operations on FP16 Numbers */
932 #define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
933 /* Support for VPMADD52[H,L]UQ */
934 #define CPUID_7_1_EAX_AVX_IFMA (1U << 23)
936 /* Support for VPDPB[SU,UU,SS]D[,S] */
937 #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4)
938 /* AVX NE CONVERT Instructions */
939 #define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5)
940 /* AMX COMPLEX Instructions */
941 #define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8)
942 /* PREFETCHIT0/1 Instructions */
943 #define CPUID_7_1_EDX_PREFETCHITI (1U << 14)
945 /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
946 #define CPUID_7_2_EDX_MCDT_NO (1U << 5)
948 /* XFD Extend Feature Disabled */
949 #define CPUID_D_1_EAX_XFD (1U << 4)
951 /* Packets which contain IP payload have LIP values */
952 #define CPUID_14_0_ECX_LIP (1U << 31)
954 /* CLZERO instruction */
955 #define CPUID_8000_0008_EBX_CLZERO (1U << 0)
956 /* Always save/restore FP error pointers */
957 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
958 /* Write back and do not invalidate cache */
959 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
960 /* Indirect Branch Prediction Barrier */
961 #define CPUID_8000_0008_EBX_IBPB (1U << 12)
962 /* Indirect Branch Restricted Speculation */
963 #define CPUID_8000_0008_EBX_IBRS (1U << 14)
964 /* Single Thread Indirect Branch Predictors */
965 #define CPUID_8000_0008_EBX_STIBP (1U << 15)
966 /* STIBP mode has enhanced performance and may be left always on */
967 #define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON (1U << 17)
968 /* Speculative Store Bypass Disable */
969 #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)
970 /* Predictive Store Forwarding Disable */
971 #define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28)
973 /* Processor ignores nested data breakpoints */
974 #define CPUID_8000_0021_EAX_No_NESTED_DATA_BP (1U << 0)
975 /* LFENCE is always serializing */
976 #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2)
977 /* Null Selector Clears Base */
978 #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6)
980 #define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8)
982 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
983 #define CPUID_XSAVE_XSAVEC (1U << 1)
984 #define CPUID_XSAVE_XGETBV1 (1U << 2)
985 #define CPUID_XSAVE_XSAVES (1U << 3)
987 #define CPUID_6_EAX_ARAT (1U << 2)
989 /* CPUID[0x80000007].EDX flags: */
990 #define CPUID_APM_INVTSC (1U << 8)
992 #define CPUID_VENDOR_SZ 12
994 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
995 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
996 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
997 #define CPUID_VENDOR_INTEL "GenuineIntel"
999 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
1000 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
1001 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
1002 #define CPUID_VENDOR_AMD "AuthenticAMD"
1004 #define CPUID_VENDOR_VIA "CentaurHauls"
1006 #define CPUID_VENDOR_HYGON "HygonGenuine"
1008 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
1009 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
1010 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
1011 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
1012 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
1013 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
1015 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
1016 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
1018 /* CPUID[0xB].ECX level types */
1019 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
1020 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
1021 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
1022 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
1024 /* MSR Feature Bits */
1025 #define MSR_ARCH_CAP_RDCL_NO (1U << 0)
1026 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
1027 #define MSR_ARCH_CAP_RSBA (1U << 2)
1028 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
1029 #define MSR_ARCH_CAP_SSB_NO (1U << 4)
1030 #define MSR_ARCH_CAP_MDS_NO (1U << 5)
1031 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
1032 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
1033 #define MSR_ARCH_CAP_TAA_NO (1U << 8)
1034 #define MSR_ARCH_CAP_SBDR_SSDP_NO (1U << 13)
1035 #define MSR_ARCH_CAP_FBSDP_NO (1U << 14)
1036 #define MSR_ARCH_CAP_PSDP_NO (1U << 15)
1037 #define MSR_ARCH_CAP_FB_CLEAR (1U << 17)
1038 #define MSR_ARCH_CAP_PBRSB_NO (1U << 24)
1040 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
1042 /* VMX MSR features */
1043 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
1044 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
1045 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
1046 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
1047 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
1048 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
1049 #define MSR_VMX_BASIC_ANY_ERRCODE (1ULL << 56)
1051 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
1052 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
1053 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
1054 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
1055 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
1056 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
1057 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
1058 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
1060 #define MSR_VMX_EPT_EXECONLY (1ULL << 0)
1061 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
1062 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
1063 #define MSR_VMX_EPT_UC (1ULL << 8)
1064 #define MSR_VMX_EPT_WB (1ULL << 14)
1065 #define MSR_VMX_EPT_2MB (1ULL << 16)
1066 #define MSR_VMX_EPT_1GB (1ULL << 17)
1067 #define MSR_VMX_EPT_INVEPT (1ULL << 20)
1068 #define MSR_VMX_EPT_AD_BITS (1ULL << 21)
1069 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
1070 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
1071 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
1072 #define MSR_VMX_EPT_INVVPID (1ULL << 32)
1073 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
1074 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
1075 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
1076 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
1078 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
1082 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
1083 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
1084 #define VMX_CPU_BASED_HLT_EXITING 0x00000080
1085 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
1086 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
1087 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
1088 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
1089 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
1090 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
1091 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
1092 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
1093 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000
1094 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
1095 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
1096 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
1097 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
1098 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
1099 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
1100 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
1101 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
1102 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
1104 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
1105 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
1106 #define VMX_SECONDARY_EXEC_DESC 0x00000004
1107 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
1108 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
1109 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
1110 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
1111 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
1112 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
1113 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
1114 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
1115 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
1116 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
1117 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
1118 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
1119 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
1120 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
1121 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
1122 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000
1123 #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000
1124 #define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE 0x04000000
1126 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
1127 #define VMX_PIN_BASED_NMI_EXITING 0x00000008
1128 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
1129 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
1130 #define VMX_PIN_BASED_POSTED_INTR 0x00000080
1132 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
1133 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
1134 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
1135 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
1136 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
1137 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
1138 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
1139 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
1140 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
1141 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
1142 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
1143 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
1144 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000
1146 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
1147 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200
1148 #define VMX_VM_ENTRY_SMM 0x00000400
1149 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
1150 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
1151 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
1152 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
1153 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
1154 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
1155 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
1156 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000
1158 /* Supported Hyper-V Enlightenments */
1159 #define HYPERV_FEAT_RELAXED 0
1160 #define HYPERV_FEAT_VAPIC 1
1161 #define HYPERV_FEAT_TIME 2
1162 #define HYPERV_FEAT_CRASH 3
1163 #define HYPERV_FEAT_RESET 4
1164 #define HYPERV_FEAT_VPINDEX 5
1165 #define HYPERV_FEAT_RUNTIME 6
1166 #define HYPERV_FEAT_SYNIC 7
1167 #define HYPERV_FEAT_STIMER 8
1168 #define HYPERV_FEAT_FREQUENCIES 9
1169 #define HYPERV_FEAT_REENLIGHTENMENT 10
1170 #define HYPERV_FEAT_TLBFLUSH 11
1171 #define HYPERV_FEAT_EVMCS 12
1172 #define HYPERV_FEAT_IPI 13
1173 #define HYPERV_FEAT_STIMER_DIRECT 14
1174 #define HYPERV_FEAT_AVIC 15
1175 #define HYPERV_FEAT_SYNDBG 16
1176 #define HYPERV_FEAT_MSR_BITMAP 17
1177 #define HYPERV_FEAT_XMM_INPUT 18
1178 #define HYPERV_FEAT_TLBFLUSH_EXT 19
1179 #define HYPERV_FEAT_TLBFLUSH_DIRECT 20
1181 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
1182 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
1185 #define EXCP00_DIVZ 0
1187 #define EXCP02_NMI 2
1188 #define EXCP03_INT3 3
1189 #define EXCP04_INTO 4
1190 #define EXCP05_BOUND 5
1191 #define EXCP06_ILLOP 6
1192 #define EXCP07_PREX 7
1193 #define EXCP08_DBLE 8
1194 #define EXCP09_XERR 9
1195 #define EXCP0A_TSS 10
1196 #define EXCP0B_NOSEG 11
1197 #define EXCP0C_STACK 12
1198 #define EXCP0D_GPF 13
1199 #define EXCP0E_PAGE 14
1200 #define EXCP10_COPR 16
1201 #define EXCP11_ALGN 17
1202 #define EXCP12_MCHK 18
1204 #define EXCP_VMEXIT 0x100 /* only for system emulation */
1205 #define EXCP_SYSCALL 0x101 /* only for user emulation */
1206 #define EXCP_VSYSCALL 0x102 /* only for user emulation */
1208 /* i386-specific interrupt pending bits. */
1209 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
1210 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
1211 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
1212 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
1213 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
1214 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
1215 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
1217 /* Use a clearer name for this. */
1218 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
1220 /* Instead of computing the condition codes after each x86 instruction,
1221 * QEMU just stores one operand (called CC_SRC), the result
1222 * (called CC_DST) and the type of operation (called CC_OP). When the
1223 * condition codes are needed, the condition codes can be calculated
1224 * using this information. Condition codes are not generated if they
1225 * are only needed for conditional branches.
1228 CC_OP_DYNAMIC
, /* must use dynamic code to get cc_op */
1229 CC_OP_EFLAGS
, /* all cc are explicitly computed, CC_SRC = flags */
1231 CC_OP_MULB
, /* modify all flags, C, O = (CC_SRC != 0) */
1236 CC_OP_ADDB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1241 CC_OP_ADCB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1246 CC_OP_SUBB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1251 CC_OP_SBBB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1256 CC_OP_LOGICB
, /* modify all flags, CC_DST = res */
1261 CC_OP_INCB
, /* modify all flags except, CC_DST = res, CC_SRC = C */
1266 CC_OP_DECB
, /* modify all flags except, CC_DST = res, CC_SRC = C */
1271 CC_OP_SHLB
, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
1276 CC_OP_SARB
, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
1281 CC_OP_BMILGB
, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1286 CC_OP_ADCX
, /* CC_DST = C, CC_SRC = rest. */
1287 CC_OP_ADOX
, /* CC_DST = O, CC_SRC = rest. */
1288 CC_OP_ADCOX
, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
1290 CC_OP_CLR
, /* Z set, all other flags clear. */
1291 CC_OP_POPCNT
, /* Z via CC_SRC, all other flags clear. */
1295 QEMU_BUILD_BUG_ON(CC_OP_NB
>= 128);
1297 typedef struct SegmentCache
{
1304 typedef union MMXReg
{
1305 uint8_t _b_MMXReg
[64 / 8];
1306 uint16_t _w_MMXReg
[64 / 16];
1307 uint32_t _l_MMXReg
[64 / 32];
1308 uint64_t _q_MMXReg
[64 / 64];
1309 float32 _s_MMXReg
[64 / 32];
1310 float64 _d_MMXReg
[64 / 64];
1313 typedef union XMMReg
{
1314 uint64_t _q_XMMReg
[128 / 64];
1317 typedef union YMMReg
{
1318 uint64_t _q_YMMReg
[256 / 64];
1319 XMMReg _x_YMMReg
[256 / 128];
1322 typedef union ZMMReg
{
1323 uint8_t _b_ZMMReg
[512 / 8];
1324 uint16_t _w_ZMMReg
[512 / 16];
1325 uint32_t _l_ZMMReg
[512 / 32];
1326 uint64_t _q_ZMMReg
[512 / 64];
1327 float16 _h_ZMMReg
[512 / 16];
1328 float32 _s_ZMMReg
[512 / 32];
1329 float64 _d_ZMMReg
[512 / 64];
1330 XMMReg _x_ZMMReg
[512 / 128];
1331 YMMReg _y_ZMMReg
[512 / 256];
1334 typedef struct BNDReg
{
1339 typedef struct BNDCSReg
{
1344 #define BNDCFG_ENABLE 1ULL
1345 #define BNDCFG_BNDPRESERVE 2ULL
1346 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
1349 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
1350 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
1351 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
1352 #define ZMM_H(n) _h_ZMMReg[31 - (n)]
1353 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
1354 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1355 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
1356 #define ZMM_X(n) _x_ZMMReg[3 - (n)]
1357 #define ZMM_Y(n) _y_ZMMReg[1 - (n)]
1359 #define XMM_Q(n) _q_XMMReg[1 - (n)]
1361 #define YMM_Q(n) _q_YMMReg[3 - (n)]
1362 #define YMM_X(n) _x_YMMReg[1 - (n)]
1364 #define MMX_B(n) _b_MMXReg[7 - (n)]
1365 #define MMX_W(n) _w_MMXReg[3 - (n)]
1366 #define MMX_L(n) _l_MMXReg[1 - (n)]
1367 #define MMX_S(n) _s_MMXReg[1 - (n)]
1369 #define ZMM_B(n) _b_ZMMReg[n]
1370 #define ZMM_W(n) _w_ZMMReg[n]
1371 #define ZMM_L(n) _l_ZMMReg[n]
1372 #define ZMM_H(n) _h_ZMMReg[n]
1373 #define ZMM_S(n) _s_ZMMReg[n]
1374 #define ZMM_Q(n) _q_ZMMReg[n]
1375 #define ZMM_D(n) _d_ZMMReg[n]
1376 #define ZMM_X(n) _x_ZMMReg[n]
1377 #define ZMM_Y(n) _y_ZMMReg[n]
1379 #define XMM_Q(n) _q_XMMReg[n]
1381 #define YMM_Q(n) _q_YMMReg[n]
1382 #define YMM_X(n) _x_YMMReg[n]
1384 #define MMX_B(n) _b_MMXReg[n]
1385 #define MMX_W(n) _w_MMXReg[n]
1386 #define MMX_L(n) _l_MMXReg[n]
1387 #define MMX_S(n) _s_MMXReg[n]
1389 #define MMX_Q(n) _q_MMXReg[n]
1392 floatx80 d
__attribute__((aligned(16)));
1401 #define CPU_NB_REGS64 16
1402 #define CPU_NB_REGS32 8
1404 #ifdef TARGET_X86_64
1405 #define CPU_NB_REGS CPU_NB_REGS64
1407 #define CPU_NB_REGS CPU_NB_REGS32
1410 #define MAX_FIXED_COUNTERS 3
1411 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1413 #define TARGET_INSN_START_EXTRA_WORDS 1
1415 #define NB_OPMASK_REGS 8
1417 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1418 * that APIC ID hasn't been set yet
1420 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1422 typedef union X86LegacyXSaveArea
{
1432 uint32_t mxcsr_mask
;
1434 uint8_t xmm_regs
[16][16];
1437 } X86LegacyXSaveArea
;
1439 typedef struct X86XSaveHeader
{
1443 uint8_t reserved
[40];
1446 /* Ext. save area 2: AVX State */
1447 typedef struct XSaveAVX
{
1448 uint8_t ymmh
[16][16];
1451 /* Ext. save area 3: BNDREG */
1452 typedef struct XSaveBNDREG
{
1456 /* Ext. save area 4: BNDCSR */
1457 typedef union XSaveBNDCSR
{
1462 /* Ext. save area 5: Opmask */
1463 typedef struct XSaveOpmask
{
1464 uint64_t opmask_regs
[NB_OPMASK_REGS
];
1467 /* Ext. save area 6: ZMM_Hi256 */
1468 typedef struct XSaveZMM_Hi256
{
1469 uint8_t zmm_hi256
[16][32];
1472 /* Ext. save area 7: Hi16_ZMM */
1473 typedef struct XSaveHi16_ZMM
{
1474 uint8_t hi16_zmm
[16][64];
1477 /* Ext. save area 9: PKRU state */
1478 typedef struct XSavePKRU
{
1483 /* Ext. save area 17: AMX XTILECFG state */
1484 typedef struct XSaveXTILECFG
{
1485 uint8_t xtilecfg
[64];
1488 /* Ext. save area 18: AMX XTILEDATA state */
1489 typedef struct XSaveXTILEDATA
{
1490 uint8_t xtiledata
[8][1024];
1499 #define ARCH_LBR_NR_ENTRIES 32
1501 /* Ext. save area 19: Supervisor mode Arch LBR state */
1502 typedef struct XSavesArchLBR
{
1508 LBREntry lbr_records
[ARCH_LBR_NR_ENTRIES
];
1511 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX
) != 0x100);
1512 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG
) != 0x40);
1513 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR
) != 0x40);
1514 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask
) != 0x40);
1515 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256
) != 0x200);
1516 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM
) != 0x400);
1517 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU
) != 0x8);
1518 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG
) != 0x40);
1519 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA
) != 0x2000);
1520 QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR
) != 0x328);
1522 typedef struct ExtSaveArea
{
1523 uint32_t feature
, bits
;
1524 uint32_t offset
, size
;
1528 #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
1530 extern ExtSaveArea x86_ext_save_areas
[XSAVE_STATE_AREA_COUNT
];
1532 typedef enum TPRAccess
{
1537 /* Cache information data structures: */
1545 typedef struct CPUCacheInfo
{
1546 enum CacheType type
;
1550 /* Line size, in bytes */
1554 * Note: representation of fully-associative caches is not implemented
1556 uint8_t associativity
;
1557 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1559 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1563 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1564 * (Is this synonym to @partitions?)
1566 uint8_t lines_per_tag
;
1568 /* Self-initializing cache */
1571 * WBINVD/INVD is not guaranteed to act upon lower level caches of
1572 * non-originating threads sharing this cache.
1573 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1575 bool no_invd_sharing
;
1577 * Cache is inclusive of lower cache levels.
1578 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1582 * A complex function is used to index the cache, potentially using all
1583 * address bits. CPUID[4].EDX[bit 2].
1585 bool complex_indexing
;
1589 typedef struct CPUCaches
{
1590 CPUCacheInfo
*l1d_cache
;
1591 CPUCacheInfo
*l1i_cache
;
1592 CPUCacheInfo
*l2_cache
;
1593 CPUCacheInfo
*l3_cache
;
1596 typedef struct HVFX86LazyFlags
{
1597 target_ulong result
;
1598 target_ulong auxbits
;
1601 typedef struct CPUArchState
{
1602 /* standard registers */
1603 target_ulong regs
[CPU_NB_REGS
];
1605 target_ulong eflags
; /* eflags register. During CPU emulation, CC
1606 flags and DF are set to zero because they are
1609 /* emulator internal eflags handling */
1610 target_ulong cc_dst
;
1611 target_ulong cc_src
;
1612 target_ulong cc_src2
;
1614 int32_t df
; /* D flag : 1 if D = 0, -1 if D = 1 */
1615 uint32_t hflags
; /* TB flags, see HF_xxx constants. These flags
1616 are known at translation time. */
1617 uint32_t hflags2
; /* various other flags, see HF2_xxx constants. */
1620 SegmentCache segs
[6]; /* selector values */
1623 SegmentCache gdt
; /* only base and limit are used */
1624 SegmentCache idt
; /* only base and limit are used */
1626 target_ulong cr
[5]; /* NOTE: cr1 is unused */
1633 BNDCSReg bndcs_regs
;
1634 uint64_t msr_bndcfgs
;
1637 /* Beginning of state preserved by INIT (dummy marker). */
1638 struct {} start_init_save
;
1641 unsigned int fpstt
; /* top of stack index */
1644 uint8_t fptags
[8]; /* 0 = valid, 1 = empty */
1646 /* KVM-only so far */
1653 /* emulator internal variables */
1654 float_status fp_status
;
1657 float_status mmx_status
; /* for 3DNow! float ops */
1658 float_status sse_status
;
1660 ZMMReg xmm_regs
[CPU_NB_REGS
== 8 ? 8 : 32] QEMU_ALIGNED(16);
1661 ZMMReg xmm_t0
QEMU_ALIGNED(16);
1664 uint64_t opmask_regs
[NB_OPMASK_REGS
];
1665 #ifdef TARGET_X86_64
1666 uint8_t xtilecfg
[64];
1667 uint8_t xtiledata
[8192];
1670 /* sysenter registers */
1671 uint32_t sysenter_cs
;
1672 target_ulong sysenter_esp
;
1673 target_ulong sysenter_eip
;
1678 #ifdef TARGET_X86_64
1682 target_ulong kernelgsbase
;
1685 uint64_t tsc_adjust
;
1686 uint64_t tsc_deadline
;
1691 uint64_t mcg_status
;
1692 uint64_t msr_ia32_misc_enable
;
1693 uint64_t msr_ia32_feature_control
;
1694 uint64_t msr_ia32_sgxlepubkeyhash
[4];
1696 uint64_t msr_fixed_ctr_ctrl
;
1697 uint64_t msr_global_ctrl
;
1698 uint64_t msr_global_status
;
1699 uint64_t msr_global_ovf_ctrl
;
1700 uint64_t msr_fixed_counters
[MAX_FIXED_COUNTERS
];
1701 uint64_t msr_gp_counters
[MAX_GP_COUNTERS
];
1702 uint64_t msr_gp_evtsel
[MAX_GP_COUNTERS
];
1706 uint64_t msr_smi_count
;
1713 uint64_t amd_tsc_scale_msr
;
1716 /* End of state preserved by INIT (dummy marker). */
1717 struct {} end_init_save
;
1719 uint64_t system_time_msr
;
1720 uint64_t wall_clock_msr
;
1721 uint64_t steal_time_msr
;
1722 uint64_t async_pf_en_msr
;
1723 uint64_t async_pf_int_msr
;
1724 uint64_t pv_eoi_en_msr
;
1725 uint64_t poll_control_msr
;
1727 /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1728 uint64_t msr_hv_hypercall
;
1729 uint64_t msr_hv_guest_os_id
;
1730 uint64_t msr_hv_tsc
;
1731 uint64_t msr_hv_syndbg_control
;
1732 uint64_t msr_hv_syndbg_status
;
1733 uint64_t msr_hv_syndbg_send_page
;
1734 uint64_t msr_hv_syndbg_recv_page
;
1735 uint64_t msr_hv_syndbg_pending_page
;
1736 uint64_t msr_hv_syndbg_options
;
1738 /* Per-VCPU HV MSRs */
1739 uint64_t msr_hv_vapic
;
1740 uint64_t msr_hv_crash_params
[HV_CRASH_PARAMS
];
1741 uint64_t msr_hv_runtime
;
1742 uint64_t msr_hv_synic_control
;
1743 uint64_t msr_hv_synic_evt_page
;
1744 uint64_t msr_hv_synic_msg_page
;
1745 uint64_t msr_hv_synic_sint
[HV_SINT_COUNT
];
1746 uint64_t msr_hv_stimer_config
[HV_STIMER_COUNT
];
1747 uint64_t msr_hv_stimer_count
[HV_STIMER_COUNT
];
1748 uint64_t msr_hv_reenlightenment_control
;
1749 uint64_t msr_hv_tsc_emulation_control
;
1750 uint64_t msr_hv_tsc_emulation_status
;
1752 uint64_t msr_rtit_ctrl
;
1753 uint64_t msr_rtit_status
;
1754 uint64_t msr_rtit_output_base
;
1755 uint64_t msr_rtit_output_mask
;
1756 uint64_t msr_rtit_cr3_match
;
1757 uint64_t msr_rtit_addrs
[MAX_RTIT_ADDRS
];
1759 /* Per-VCPU XFD MSRs */
1761 uint64_t msr_xfd_err
;
1763 /* Per-VCPU Arch LBR MSRs */
1764 uint64_t msr_lbr_ctl
;
1765 uint64_t msr_lbr_depth
;
1766 LBREntry lbr_records
[ARCH_LBR_NR_ENTRIES
];
1768 /* exception/interrupt handling */
1770 int exception_is_int
;
1771 target_ulong exception_next_eip
;
1772 target_ulong dr
[8]; /* debug registers; note dr4 and dr5 are unused */
1774 struct CPUBreakpoint
*cpu_breakpoint
[4];
1775 struct CPUWatchpoint
*cpu_watchpoint
[4];
1776 }; /* break/watchpoints for dr[0..3] */
1777 int old_exception
; /* exception in flight */
1780 uint64_t tsc_offset
;
1782 uint16_t intercept_cr_read
;
1783 uint16_t intercept_cr_write
;
1784 uint16_t intercept_dr_read
;
1785 uint16_t intercept_dr_write
;
1786 uint32_t intercept_exceptions
;
1787 uint64_t nested_cr3
;
1788 uint32_t nested_pg_mode
;
1792 /* KVM states, automatically cleared on reset */
1793 uint8_t nmi_injected
;
1794 uint8_t nmi_pending
;
1798 /* Fields up to this point are cleared by a CPU reset */
1799 struct {} end_reset_fields
;
1801 /* Fields after this point are preserved across CPU reset. */
1803 /* processor features (e.g. for CPUID insn) */
1804 /* Minimum cpuid leaf 7 value */
1805 uint32_t cpuid_level_func7
;
1806 /* Actual cpuid leaf 7 value */
1807 uint32_t cpuid_min_level_func7
;
1808 /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1809 uint32_t cpuid_min_level
, cpuid_min_xlevel
, cpuid_min_xlevel2
;
1810 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1811 uint32_t cpuid_max_level
, cpuid_max_xlevel
, cpuid_max_xlevel2
;
1812 /* Actual level/xlevel/xlevel2 value: */
1813 uint32_t cpuid_level
, cpuid_xlevel
, cpuid_xlevel2
;
1814 uint32_t cpuid_vendor1
;
1815 uint32_t cpuid_vendor2
;
1816 uint32_t cpuid_vendor3
;
1817 uint32_t cpuid_version
;
1818 FeatureWordArray features
;
1819 /* Features that were explicitly enabled/disabled */
1820 FeatureWordArray user_features
;
1821 uint32_t cpuid_model
[12];
1822 /* Cache information for CPUID. When legacy-cache=on, the cache data
1823 * on each CPUID leaf will be different, because we keep compatibility
1824 * with old QEMU versions.
1826 CPUCaches cache_info_cpuid2
, cache_info_cpuid4
, cache_info_amd
;
1829 uint64_t mtrr_fixed
[11];
1830 uint64_t mtrr_deftype
;
1831 MTRRVar mtrr_var
[MSR_MTRRcap_VCNT
];
1835 int32_t exception_nr
;
1836 int32_t interrupt_injected
;
1837 uint8_t soft_interrupt
;
1838 uint8_t exception_pending
;
1839 uint8_t exception_injected
;
1840 uint8_t has_error_code
;
1841 uint8_t exception_has_payload
;
1842 uint64_t exception_payload
;
1843 uint8_t triple_fault_pending
;
1845 uint32_t sipi_vector
;
1848 int64_t user_tsc_khz
; /* for sanity check only */
1849 uint64_t apic_bus_freq
;
1851 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1853 uint32_t xsave_buf_len
;
1855 #if defined(CONFIG_KVM)
1856 struct kvm_nested_state
*nested_state
;
1857 MemoryRegion
*xen_vcpu_info_mr
;
1858 void *xen_vcpu_info_hva
;
1859 uint64_t xen_vcpu_info_gpa
;
1860 uint64_t xen_vcpu_info_default_gpa
;
1861 uint64_t xen_vcpu_time_info_gpa
;
1862 uint64_t xen_vcpu_runstate_gpa
;
1863 uint8_t xen_vcpu_callback_vector
;
1864 bool xen_callback_asserted
;
1865 uint16_t xen_virq
[XEN_NR_VIRQS
];
1866 uint64_t xen_singleshot_timer_ns
;
1867 QEMUTimer
*xen_singleshot_timer
;
1868 uint64_t xen_periodic_timer_period
;
1869 QEMUTimer
*xen_periodic_timer
;
1870 QemuMutex xen_timers_lock
;
1872 #if defined(CONFIG_HVF)
1873 HVFX86LazyFlags hvf_lflags
;
1879 uint64_t mcg_ext_ctl
;
1880 uint64_t mce_banks
[MCE_BANKS_DEF
*4];
1884 uint16_t fpus_vmstate
;
1885 uint16_t fptag_vmstate
;
1886 uint16_t fpregs_format_vmstate
;
1891 TPRAccess tpr_access_type
;
1893 /* Number of dies within this CPU package. */
1901 * @env: #CPUX86State
1902 * @migratable: If set, only migratable flags will be accepted when "enforce"
1903 * mode is used, and only migratable flags will be included in the "host"
1909 CPUState parent_obj
;
1912 VMChangeStateEntry
*vmsentry
;
1916 uint32_t hyperv_spinlock_attempts
;
1917 char *hyperv_vendor
;
1918 bool hyperv_synic_kvm_only
;
1919 uint64_t hyperv_features
;
1920 bool hyperv_passthrough
;
1921 OnOffAuto hyperv_no_nonarch_cs
;
1922 uint32_t hyperv_vendor_id
[3];
1923 uint32_t hyperv_interface_id
[4];
1924 uint32_t hyperv_limits
[3];
1925 bool hyperv_enforce_cpuid
;
1926 uint32_t hyperv_ver_id_build
;
1927 uint16_t hyperv_ver_id_major
;
1928 uint16_t hyperv_ver_id_minor
;
1929 uint32_t hyperv_ver_id_sp
;
1930 uint8_t hyperv_ver_id_sb
;
1931 uint32_t hyperv_ver_id_sn
;
1936 * Force features to be enabled even if the host doesn't support them.
1937 * This is dangerous and should be done only for testing CPUID
1940 bool force_features
;
1944 bool migrate_smi_count
;
1945 bool max_features
; /* Enable all supported features automatically */
1948 /* Enables publishing of TSC increment and Local APIC bus frequencies to
1949 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
1950 bool vmware_cpuid_freq
;
1952 /* if true the CPUID code directly forward host cache leaves to the guest */
1953 bool cache_info_passthrough
;
1955 /* if true the CPUID code directly forwards
1956 * host monitor/mwait leaves to the guest */
1964 /* Features that were filtered out because of missing host capabilities */
1965 FeatureWordArray filtered_features
;
1967 /* Enable PMU CPUID bits. This can't be enabled by default yet because
1968 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
1969 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
1970 * capabilities) directly to the guest.
1975 * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR.
1976 * This can't be initialized with a default because it doesn't have
1977 * stable ABI support yet. It is only allowed to pass all LBR_FMT bits
1978 * returned by kvm_arch_get_supported_msr_feature()(which depends on both
1979 * host CPU and kernel capabilities) to the guest.
1983 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
1984 * disabled by default to avoid breaking migration between QEMU with
1985 * different LMCE configurations.
1989 /* Compatibility bits for old machine types.
1990 * If true present virtual l3 cache for VM, the vcpus in the same virtual
1991 * socket share an virtual l3 cache.
1993 bool enable_l3_cache
;
1995 /* Compatibility bits for old machine types.
1996 * If true present the old cache topology information
2000 /* Compatibility bits for old machine types: */
2001 bool enable_cpuid_0xb
;
2003 /* Enable auto level-increase for all CPUID leaves */
2004 bool full_cpuid_auto_level
;
2006 /* Only advertise CPUID leaves defined by the vendor */
2007 bool vendor_cpuid_only
;
2009 /* Enable auto level-increase for Intel Processor Trace leave */
2010 bool intel_pt_auto_level
;
2012 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
2013 bool fill_mtrr_mask
;
2015 /* if true override the phys_bits value with a value read from the host */
2016 bool host_phys_bits
;
2018 /* if set, limit maximum value for phys_bits when host_phys_bits is true */
2019 uint8_t host_phys_bits_limit
;
2021 /* Stop SMI delivery for migration compatibility with old machines */
2022 bool kvm_no_smi_migration
;
2024 /* Forcefully disable KVM PV features not exposed in guest CPUIDs */
2025 bool kvm_pv_enforce_cpuid
;
2027 /* Number of physical address bits supported */
2030 /* in order to simplify APIC support, we leave this pointer to the
2032 struct DeviceState
*apic_state
;
2033 struct MemoryRegion
*cpu_as_root
, *cpu_as_mem
, *smram
;
2034 Notifier machine_done
;
2036 struct kvm_msrs
*kvm_msr_buf
;
2038 int32_t node_id
; /* NUMA node this CPU belongs to */
2049 typedef struct X86CPUModel X86CPUModel
;
2053 * @cpu_def: CPU model definition
2054 * @host_cpuid_required: Whether CPU model requires cpuid from host.
2055 * @ordering: Ordering on the "-cpu help" CPU model list.
2056 * @migration_safe: See CpuDefinitionInfo::migration_safe
2057 * @static_model: See CpuDefinitionInfo::static
2058 * @parent_realize: The parent class' realize handler.
2059 * @parent_phases: The parent class' reset phase handlers.
2061 * An x86 CPU model or family.
2063 struct X86CPUClass
{
2064 CPUClass parent_class
;
2067 * CPU definition, automatically loaded by instance_init if not NULL.
2068 * Should be eventually replaced by subclass-specific property defaults.
2072 bool host_cpuid_required
;
2074 bool migration_safe
;
2078 * Optional description of CPU model.
2079 * If unavailable, cpu_def->model_id is used.
2081 const char *model_description
;
2083 DeviceRealize parent_realize
;
2084 DeviceUnrealize parent_unrealize
;
2085 ResettablePhases parent_phases
;
2088 #ifndef CONFIG_USER_ONLY
2089 extern const VMStateDescription vmstate_x86_cpu
;
2092 int x86_cpu_pending_interrupt(CPUState
*cs
, int interrupt_request
);
2094 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
2095 int cpuid
, DumpState
*s
);
2096 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
2097 int cpuid
, DumpState
*s
);
2098 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
2100 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
2103 bool x86_cpu_get_memory_mapping(CPUState
*cpu
, MemoryMappingList
*list
,
2106 void x86_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
);
2108 int x86_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
2109 int x86_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
2111 void x86_cpu_list(void);
2112 int cpu_x86_support_mca_broadcast(CPUX86State
*env
);
2114 #ifndef CONFIG_USER_ONLY
2115 hwaddr
x86_cpu_get_phys_page_attrs_debug(CPUState
*cpu
, vaddr addr
,
2117 int cpu_get_pic_interrupt(CPUX86State
*s
);
2119 /* MS-DOS compatibility mode FPU exception support */
2120 void x86_register_ferr_irq(qemu_irq irq
);
2121 void fpu_check_raise_ferr_irq(CPUX86State
*s
);
2122 void cpu_set_ignne(void);
2123 void cpu_clear_ignne(void);
2127 void cpu_sync_bndcs_hflags(CPUX86State
*env
);
2129 /* this function must always be used to load data in the segment
2130 cache: it synchronizes the hflags with the segment cache values */
2131 static inline void cpu_x86_load_seg_cache(CPUX86State
*env
,
2132 X86Seg seg_reg
, unsigned int selector
,
2138 unsigned int new_hflags
;
2140 sc
= &env
->segs
[seg_reg
];
2141 sc
->selector
= selector
;
2146 /* update the hidden flags */
2148 if (seg_reg
== R_CS
) {
2149 #ifdef TARGET_X86_64
2150 if ((env
->hflags
& HF_LMA_MASK
) && (flags
& DESC_L_MASK
)) {
2152 env
->hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
2153 env
->hflags
&= ~(HF_ADDSEG_MASK
);
2157 /* legacy / compatibility case */
2158 new_hflags
= (env
->segs
[R_CS
].flags
& DESC_B_MASK
)
2159 >> (DESC_B_SHIFT
- HF_CS32_SHIFT
);
2160 env
->hflags
= (env
->hflags
& ~(HF_CS32_MASK
| HF_CS64_MASK
)) |
2164 if (seg_reg
== R_SS
) {
2165 int cpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
2166 #if HF_CPL_MASK != 3
2167 #error HF_CPL_MASK is hardcoded
2169 env
->hflags
= (env
->hflags
& ~HF_CPL_MASK
) | cpl
;
2170 /* Possibly switch between BNDCFGS and BNDCFGU */
2171 cpu_sync_bndcs_hflags(env
);
2173 new_hflags
= (env
->segs
[R_SS
].flags
& DESC_B_MASK
)
2174 >> (DESC_B_SHIFT
- HF_SS32_SHIFT
);
2175 if (env
->hflags
& HF_CS64_MASK
) {
2176 /* zero base assumed for DS, ES and SS in long mode */
2177 } else if (!(env
->cr
[0] & CR0_PE_MASK
) ||
2178 (env
->eflags
& VM_MASK
) ||
2179 !(env
->hflags
& HF_CS32_MASK
)) {
2180 /* XXX: try to avoid this test. The problem comes from the
2181 fact that is real mode or vm86 mode we only modify the
2182 'base' and 'selector' fields of the segment cache to go
2183 faster. A solution may be to force addseg to one in
2184 translate-i386.c. */
2185 new_hflags
|= HF_ADDSEG_MASK
;
2187 new_hflags
|= ((env
->segs
[R_DS
].base
|
2188 env
->segs
[R_ES
].base
|
2189 env
->segs
[R_SS
].base
) != 0) <<
2192 env
->hflags
= (env
->hflags
&
2193 ~(HF_SS32_MASK
| HF_ADDSEG_MASK
)) | new_hflags
;
2197 static inline void cpu_x86_load_seg_cache_sipi(X86CPU
*cpu
,
2198 uint8_t sipi_vector
)
2200 CPUState
*cs
= CPU(cpu
);
2201 CPUX86State
*env
= &cpu
->env
;
2204 cpu_x86_load_seg_cache(env
, R_CS
, sipi_vector
<< 8,
2206 env
->segs
[R_CS
].limit
,
2207 env
->segs
[R_CS
].flags
);
2211 int cpu_x86_get_descr_debug(CPUX86State
*env
, unsigned int selector
,
2212 target_ulong
*base
, unsigned int *limit
,
2213 unsigned int *flags
);
2216 /* used for debug or cpu save/restore */
2219 /* the following helpers are only usable in user mode simulation as
2220 they can trigger unexpected exceptions */
2221 void cpu_x86_load_seg(CPUX86State
*s
, X86Seg seg_reg
, int selector
);
2222 void cpu_x86_fsave(CPUX86State
*s
, target_ulong ptr
, int data32
);
2223 void cpu_x86_frstor(CPUX86State
*s
, target_ulong ptr
, int data32
);
2224 void cpu_x86_fxsave(CPUX86State
*s
, target_ulong ptr
);
2225 void cpu_x86_fxrstor(CPUX86State
*s
, target_ulong ptr
);
2226 void cpu_x86_xsave(CPUX86State
*s
, target_ulong ptr
);
2227 void cpu_x86_xrstor(CPUX86State
*s
, target_ulong ptr
);
2230 void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
2231 uint32_t vendor2
, uint32_t vendor3
);
2232 typedef struct PropValue
{
2233 const char *prop
, *value
;
2235 void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
);
2237 void x86_cpu_after_reset(X86CPU
*cpu
);
2239 uint32_t cpu_x86_virtual_addr_width(CPUX86State
*env
);
2241 /* cpu.c other functions (cpuid) */
2242 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
2243 uint32_t *eax
, uint32_t *ebx
,
2244 uint32_t *ecx
, uint32_t *edx
);
2245 void cpu_clear_apic_feature(CPUX86State
*env
);
2246 void cpu_set_apic_feature(CPUX86State
*env
);
2247 void host_cpuid(uint32_t function
, uint32_t count
,
2248 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
);
2249 bool cpu_has_x2apic_feature(CPUX86State
*env
);
2252 void x86_cpu_set_a20(X86CPU
*cpu
, int a20_state
);
2253 void cpu_sync_avx_hflag(CPUX86State
*env
);
2255 #ifndef CONFIG_USER_ONLY
2256 static inline int x86_asidx_from_attrs(CPUState
*cs
, MemTxAttrs attrs
)
2258 return !!attrs
.secure
;
2261 static inline AddressSpace
*cpu_addressspace(CPUState
*cs
, MemTxAttrs attrs
)
2263 return cpu_get_address_space(cs
, cpu_asidx_from_attrs(cs
, attrs
));
2267 * load efer and update the corresponding hflags. XXX: do consistency
2268 * checks with cpuid bits?
2270 void cpu_load_efer(CPUX86State
*env
, uint64_t val
);
2271 uint8_t x86_ldub_phys(CPUState
*cs
, hwaddr addr
);
2272 uint32_t x86_lduw_phys(CPUState
*cs
, hwaddr addr
);
2273 uint32_t x86_ldl_phys(CPUState
*cs
, hwaddr addr
);
2274 uint64_t x86_ldq_phys(CPUState
*cs
, hwaddr addr
);
2275 void x86_stb_phys(CPUState
*cs
, hwaddr addr
, uint8_t val
);
2276 void x86_stl_phys_notdirty(CPUState
*cs
, hwaddr addr
, uint32_t val
);
2277 void x86_stw_phys(CPUState
*cs
, hwaddr addr
, uint32_t val
);
2278 void x86_stl_phys(CPUState
*cs
, hwaddr addr
, uint32_t val
);
2279 void x86_stq_phys(CPUState
*cs
, hwaddr addr
, uint64_t val
);
2282 /* will be suppressed */
2283 void cpu_x86_update_cr0(CPUX86State
*env
, uint32_t new_cr0
);
2284 void cpu_x86_update_cr3(CPUX86State
*env
, target_ulong new_cr3
);
2285 void cpu_x86_update_cr4(CPUX86State
*env
, uint32_t new_cr4
);
2286 void cpu_x86_update_dr7(CPUX86State
*env
, uint32_t new_dr7
);
2289 uint64_t cpu_get_tsc(CPUX86State
*env
);
2291 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
2293 #ifdef TARGET_X86_64
2294 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
2296 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
2299 #define cpu_list x86_cpu_list
2301 /* MMU modes definitions */
2302 #define MMU_KSMAP64_IDX 0
2303 #define MMU_KSMAP32_IDX 1
2304 #define MMU_USER64_IDX 2
2305 #define MMU_USER32_IDX 3
2306 #define MMU_KNOSMAP64_IDX 4
2307 #define MMU_KNOSMAP32_IDX 5
2308 #define MMU_PHYS_IDX 6
2309 #define MMU_NESTED_IDX 7
2311 #ifdef CONFIG_USER_ONLY
2312 #ifdef TARGET_X86_64
2313 #define MMU_USER_IDX MMU_USER64_IDX
2315 #define MMU_USER_IDX MMU_USER32_IDX
2319 static inline bool is_mmu_index_smap(int mmu_index
)
2321 return (mmu_index
& ~1) == MMU_KSMAP64_IDX
;
2324 static inline bool is_mmu_index_user(int mmu_index
)
2326 return (mmu_index
& ~1) == MMU_USER64_IDX
;
2329 static inline bool is_mmu_index_32(int mmu_index
)
2331 assert(mmu_index
< MMU_PHYS_IDX
);
2332 return mmu_index
& 1;
2335 static inline int cpu_mmu_index_kernel(CPUX86State
*env
)
2337 int mmu_index_32
= (env
->hflags
& HF_LMA_MASK
) ? 1 : 0;
2338 int mmu_index_base
=
2339 !(env
->hflags
& HF_SMAP_MASK
) ? MMU_KNOSMAP64_IDX
:
2340 ((env
->hflags
& HF_CPL_MASK
) < 3 && (env
->eflags
& AC_MASK
)) ? MMU_KNOSMAP64_IDX
: MMU_KSMAP64_IDX
;
2342 return mmu_index_base
+ mmu_index_32
;
2345 #define CC_DST (env->cc_dst)
2346 #define CC_SRC (env->cc_src)
2347 #define CC_SRC2 (env->cc_src2)
2348 #define CC_OP (env->cc_op)
2350 #include "exec/cpu-all.h"
2353 #if !defined(CONFIG_USER_ONLY)
2354 #include "hw/i386/apic.h"
2357 static inline void cpu_get_tb_cpu_state(CPUX86State
*env
, vaddr
*pc
,
2358 uint64_t *cs_base
, uint32_t *flags
)
2360 *flags
= env
->hflags
|
2361 (env
->eflags
& (IOPL_MASK
| TF_MASK
| RF_MASK
| VM_MASK
| AC_MASK
));
2362 if (env
->hflags
& HF_CS64_MASK
) {
2366 *cs_base
= env
->segs
[R_CS
].base
;
2367 *pc
= (uint32_t)(*cs_base
+ env
->eip
);
2371 void do_cpu_init(X86CPU
*cpu
);
2373 #define MCE_INJECT_BROADCAST 1
2374 #define MCE_INJECT_UNCOND_AO 2
2376 void cpu_x86_inject_mce(Monitor
*mon
, X86CPU
*cpu
, int bank
,
2377 uint64_t status
, uint64_t mcg_status
, uint64_t addr
,
2378 uint64_t misc
, int flags
);
2380 uint32_t cpu_cc_compute_all(CPUX86State
*env1
);
2382 static inline uint32_t cpu_compute_eflags(CPUX86State
*env
)
2384 uint32_t eflags
= env
->eflags
;
2385 if (tcg_enabled()) {
2386 eflags
|= cpu_cc_compute_all(env
) | (env
->df
& DF_MASK
);
2391 static inline MemTxAttrs
cpu_get_mem_attrs(CPUX86State
*env
)
2393 return ((MemTxAttrs
) { .secure
= (env
->hflags
& HF_SMM_MASK
) != 0 });
2396 static inline int32_t x86_get_a20_mask(CPUX86State
*env
)
2398 if (env
->hflags
& HF_SMM_MASK
) {
2401 return env
->a20_mask
;
2405 static inline bool cpu_has_vmx(CPUX86State
*env
)
2407 return env
->features
[FEAT_1_ECX
] & CPUID_EXT_VMX
;
2410 static inline bool cpu_has_svm(CPUX86State
*env
)
2412 return env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
;
2416 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set.
2417 * Since it was set, CR4.VMXE must remain set as long as vCPU is in
2418 * VMX operation. This is because CR4.VMXE is one of the bits set
2419 * in MSR_IA32_VMX_CR4_FIXED1.
2421 * There is one exception to above statement when vCPU enters SMM mode.
2422 * When a vCPU enters SMM mode, it temporarily exit VMX operation and
2423 * may also reset CR4.VMXE during execution in SMM mode.
2424 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation
2425 * and CR4.VMXE is restored to it's original value of being set.
2427 * Therefore, when vCPU is not in SMM mode, we can infer whether
2428 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot
2431 static inline bool cpu_vmx_maybe_enabled(CPUX86State
*env
)
2433 return cpu_has_vmx(env
) &&
2434 ((env
->cr
[4] & CR4_VMXE_MASK
) || (env
->hflags
& HF_SMM_MASK
));
2438 int get_pg_mode(CPUX86State
*env
);
2441 void update_fp_status(CPUX86State
*env
);
2442 void update_mxcsr_status(CPUX86State
*env
);
2443 void update_mxcsr_from_sse_status(CPUX86State
*env
);
2445 static inline void cpu_set_mxcsr(CPUX86State
*env
, uint32_t mxcsr
)
2448 if (tcg_enabled()) {
2449 update_mxcsr_status(env
);
2453 static inline void cpu_set_fpuc(CPUX86State
*env
, uint16_t fpuc
)
2456 if (tcg_enabled()) {
2457 update_fp_status(env
);
2462 #ifdef CONFIG_USER_ONLY
2464 cpu_svm_check_intercept_param(CPUX86State
*env1
, uint32_t type
,
2465 uint64_t param
, uintptr_t retaddr
)
2468 cpu_svm_has_intercept(CPUX86State
*env
, uint32_t type
)
2471 void cpu_svm_check_intercept_param(CPUX86State
*env1
, uint32_t type
,
2472 uint64_t param
, uintptr_t retaddr
);
2473 bool cpu_svm_has_intercept(CPUX86State
*env
, uint32_t type
);
2477 void cpu_report_tpr_access(CPUX86State
*env
, TPRAccess access
);
2478 void apic_handle_tpr_access_report(DeviceState
*d
, target_ulong ip
,
2481 /* Special values for X86CPUVersion: */
2483 /* Resolve to latest CPU version */
2484 #define CPU_VERSION_LATEST -1
2487 * Resolve to version defined by current machine type.
2488 * See x86_cpu_set_default_version()
2490 #define CPU_VERSION_AUTO -2
2492 /* Don't resolve to any versioned CPU models, like old QEMU versions */
2493 #define CPU_VERSION_LEGACY 0
2495 typedef int X86CPUVersion
;
2498 * Set default CPU model version for CPU models having
2499 * version == CPU_VERSION_AUTO.
2501 void x86_cpu_set_default_version(X86CPUVersion version
);
2503 #ifndef CONFIG_USER_ONLY
2505 void do_cpu_sipi(X86CPU
*cpu
);
2507 #define APIC_DEFAULT_ADDRESS 0xfee00000
2508 #define APIC_SPACE_SIZE 0x100000
2511 void x86_cpu_dump_local_apic_state(CPUState
*cs
, int flags
);
2516 bool cpu_is_bsp(X86CPU
*cpu
);
2518 void x86_cpu_xrstor_all_areas(X86CPU
*cpu
, const void *buf
, uint32_t buflen
);
2519 void x86_cpu_xsave_all_areas(X86CPU
*cpu
, void *buf
, uint32_t buflen
);
2520 uint32_t xsave_area_size(uint64_t mask
, bool compacted
);
2521 void x86_update_hflags(CPUX86State
* env
);
2523 static inline bool hyperv_feat_enabled(X86CPU
*cpu
, int feat
)
2525 return !!(cpu
->hyperv_features
& BIT(feat
));
2528 static inline uint64_t cr4_reserved_bits(CPUX86State
*env
)
2530 uint64_t reserved_bits
= CR4_RESERVED_MASK
;
2531 if (!env
->features
[FEAT_XSAVE
]) {
2532 reserved_bits
|= CR4_OSXSAVE_MASK
;
2534 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_SMEP
)) {
2535 reserved_bits
|= CR4_SMEP_MASK
;
2537 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_SMAP
)) {
2538 reserved_bits
|= CR4_SMAP_MASK
;
2540 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
)) {
2541 reserved_bits
|= CR4_FSGSBASE_MASK
;
2543 if (!(env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_PKU
)) {
2544 reserved_bits
|= CR4_PKE_MASK
;
2546 if (!(env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_LA57
)) {
2547 reserved_bits
|= CR4_LA57_MASK
;
2549 if (!(env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_UMIP
)) {
2550 reserved_bits
|= CR4_UMIP_MASK
;
2552 if (!(env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_PKS
)) {
2553 reserved_bits
|= CR4_PKS_MASK
;
2555 return reserved_bits
;
2558 static inline bool ctl_has_irq(CPUX86State
*env
)
2563 int_prio
= (env
->int_ctl
& V_INTR_PRIO_MASK
) >> V_INTR_PRIO_SHIFT
;
2564 tpr
= env
->int_ctl
& V_TPR_MASK
;
2566 if (env
->int_ctl
& V_IGN_TPR_MASK
) {
2567 return (env
->int_ctl
& V_IRQ_MASK
);
2570 return (env
->int_ctl
& V_IRQ_MASK
) && (int_prio
>= tpr
);
2573 #if defined(TARGET_X86_64) && \
2574 defined(CONFIG_USER_ONLY) && \
2575 defined(CONFIG_LINUX)
2576 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20)
2579 #endif /* I386_CPU_H */