2 * QEMU generic PowerPC hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
25 #include "qemu-common.h"
28 #include "hw/ppc/ppc.h"
29 #include "hw/ppc/ppc_e500.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/cpus.h"
33 #include "hw/timer/m48t59.h"
35 #include "qemu/error-report.h"
36 #include "qapi/error.h"
37 #include "hw/loader.h"
38 #include "sysemu/kvm.h"
42 //#define PPC_DEBUG_IRQ
43 //#define PPC_DEBUG_TB
46 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
48 # define LOG_IRQ(...) do { } while (0)
53 # define LOG_TB(...) qemu_log(__VA_ARGS__)
55 # define LOG_TB(...) do { } while (0)
58 static void cpu_ppc_tb_stop (CPUPPCState
*env
);
59 static void cpu_ppc_tb_start (CPUPPCState
*env
);
61 void ppc_set_irq(PowerPCCPU
*cpu
, int n_IRQ
, int level
)
63 CPUState
*cs
= CPU(cpu
);
64 CPUPPCState
*env
= &cpu
->env
;
65 unsigned int old_pending
= env
->pending_interrupts
;
68 env
->pending_interrupts
|= 1 << n_IRQ
;
69 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
71 env
->pending_interrupts
&= ~(1 << n_IRQ
);
72 if (env
->pending_interrupts
== 0) {
73 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
77 if (old_pending
!= env
->pending_interrupts
) {
79 kvmppc_set_interrupt(cpu
, n_IRQ
, level
);
83 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
84 "req %08x\n", __func__
, env
, n_IRQ
, level
,
85 env
->pending_interrupts
, CPU(cpu
)->interrupt_request
);
88 /* PowerPC 6xx / 7xx internal IRQ controller */
89 static void ppc6xx_set_irq(void *opaque
, int pin
, int level
)
91 PowerPCCPU
*cpu
= opaque
;
92 CPUPPCState
*env
= &cpu
->env
;
95 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
97 cur_level
= (env
->irq_input_state
>> pin
) & 1;
98 /* Don't generate spurious events */
99 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
100 CPUState
*cs
= CPU(cpu
);
103 case PPC6xx_INPUT_TBEN
:
104 /* Level sensitive - active high */
105 LOG_IRQ("%s: %s the time base\n",
106 __func__
, level
? "start" : "stop");
108 cpu_ppc_tb_start(env
);
110 cpu_ppc_tb_stop(env
);
112 case PPC6xx_INPUT_INT
:
113 /* Level sensitive - active high */
114 LOG_IRQ("%s: set the external IRQ state to %d\n",
116 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
118 case PPC6xx_INPUT_SMI
:
119 /* Level sensitive - active high */
120 LOG_IRQ("%s: set the SMI IRQ state to %d\n",
122 ppc_set_irq(cpu
, PPC_INTERRUPT_SMI
, level
);
124 case PPC6xx_INPUT_MCP
:
125 /* Negative edge sensitive */
126 /* XXX: TODO: actual reaction may depends on HID0 status
127 * 603/604/740/750: check HID0[EMCP]
129 if (cur_level
== 1 && level
== 0) {
130 LOG_IRQ("%s: raise machine check state\n",
132 ppc_set_irq(cpu
, PPC_INTERRUPT_MCK
, 1);
135 case PPC6xx_INPUT_CKSTP_IN
:
136 /* Level sensitive - active low */
137 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
138 /* XXX: Note that the only way to restart the CPU is to reset it */
140 LOG_IRQ("%s: stop the CPU\n", __func__
);
144 case PPC6xx_INPUT_HRESET
:
145 /* Level sensitive - active low */
147 LOG_IRQ("%s: reset the CPU\n", __func__
);
148 cpu_interrupt(cs
, CPU_INTERRUPT_RESET
);
151 case PPC6xx_INPUT_SRESET
:
152 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
154 ppc_set_irq(cpu
, PPC_INTERRUPT_RESET
, level
);
157 /* Unknown pin - do nothing */
158 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
162 env
->irq_input_state
|= 1 << pin
;
164 env
->irq_input_state
&= ~(1 << pin
);
168 void ppc6xx_irq_init(PowerPCCPU
*cpu
)
170 CPUPPCState
*env
= &cpu
->env
;
172 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppc6xx_set_irq
, cpu
,
176 #if defined(TARGET_PPC64)
177 /* PowerPC 970 internal IRQ controller */
178 static void ppc970_set_irq(void *opaque
, int pin
, int level
)
180 PowerPCCPU
*cpu
= opaque
;
181 CPUPPCState
*env
= &cpu
->env
;
184 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
186 cur_level
= (env
->irq_input_state
>> pin
) & 1;
187 /* Don't generate spurious events */
188 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
189 CPUState
*cs
= CPU(cpu
);
192 case PPC970_INPUT_INT
:
193 /* Level sensitive - active high */
194 LOG_IRQ("%s: set the external IRQ state to %d\n",
196 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
198 case PPC970_INPUT_THINT
:
199 /* Level sensitive - active high */
200 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__
,
202 ppc_set_irq(cpu
, PPC_INTERRUPT_THERM
, level
);
204 case PPC970_INPUT_MCP
:
205 /* Negative edge sensitive */
206 /* XXX: TODO: actual reaction may depends on HID0 status
207 * 603/604/740/750: check HID0[EMCP]
209 if (cur_level
== 1 && level
== 0) {
210 LOG_IRQ("%s: raise machine check state\n",
212 ppc_set_irq(cpu
, PPC_INTERRUPT_MCK
, 1);
215 case PPC970_INPUT_CKSTP
:
216 /* Level sensitive - active low */
217 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
219 LOG_IRQ("%s: stop the CPU\n", __func__
);
222 LOG_IRQ("%s: restart the CPU\n", __func__
);
227 case PPC970_INPUT_HRESET
:
228 /* Level sensitive - active low */
230 cpu_interrupt(cs
, CPU_INTERRUPT_RESET
);
233 case PPC970_INPUT_SRESET
:
234 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
236 ppc_set_irq(cpu
, PPC_INTERRUPT_RESET
, level
);
238 case PPC970_INPUT_TBEN
:
239 LOG_IRQ("%s: set the TBEN state to %d\n", __func__
,
244 /* Unknown pin - do nothing */
245 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
249 env
->irq_input_state
|= 1 << pin
;
251 env
->irq_input_state
&= ~(1 << pin
);
255 void ppc970_irq_init(PowerPCCPU
*cpu
)
257 CPUPPCState
*env
= &cpu
->env
;
259 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppc970_set_irq
, cpu
,
263 /* POWER7 internal IRQ controller */
264 static void power7_set_irq(void *opaque
, int pin
, int level
)
266 PowerPCCPU
*cpu
= opaque
;
267 CPUPPCState
*env
= &cpu
->env
;
269 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
273 case POWER7_INPUT_INT
:
274 /* Level sensitive - active high */
275 LOG_IRQ("%s: set the external IRQ state to %d\n",
277 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
280 /* Unknown pin - do nothing */
281 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
285 env
->irq_input_state
|= 1 << pin
;
287 env
->irq_input_state
&= ~(1 << pin
);
291 void ppcPOWER7_irq_init(PowerPCCPU
*cpu
)
293 CPUPPCState
*env
= &cpu
->env
;
295 env
->irq_inputs
= (void **)qemu_allocate_irqs(&power7_set_irq
, cpu
,
298 #endif /* defined(TARGET_PPC64) */
300 /* PowerPC 40x internal IRQ controller */
301 static void ppc40x_set_irq(void *opaque
, int pin
, int level
)
303 PowerPCCPU
*cpu
= opaque
;
304 CPUPPCState
*env
= &cpu
->env
;
307 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
309 cur_level
= (env
->irq_input_state
>> pin
) & 1;
310 /* Don't generate spurious events */
311 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
312 CPUState
*cs
= CPU(cpu
);
315 case PPC40x_INPUT_RESET_SYS
:
317 LOG_IRQ("%s: reset the PowerPC system\n",
319 ppc40x_system_reset(cpu
);
322 case PPC40x_INPUT_RESET_CHIP
:
324 LOG_IRQ("%s: reset the PowerPC chip\n", __func__
);
325 ppc40x_chip_reset(cpu
);
328 case PPC40x_INPUT_RESET_CORE
:
329 /* XXX: TODO: update DBSR[MRR] */
331 LOG_IRQ("%s: reset the PowerPC core\n", __func__
);
332 ppc40x_core_reset(cpu
);
335 case PPC40x_INPUT_CINT
:
336 /* Level sensitive - active high */
337 LOG_IRQ("%s: set the critical IRQ state to %d\n",
339 ppc_set_irq(cpu
, PPC_INTERRUPT_CEXT
, level
);
341 case PPC40x_INPUT_INT
:
342 /* Level sensitive - active high */
343 LOG_IRQ("%s: set the external IRQ state to %d\n",
345 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
347 case PPC40x_INPUT_HALT
:
348 /* Level sensitive - active low */
350 LOG_IRQ("%s: stop the CPU\n", __func__
);
353 LOG_IRQ("%s: restart the CPU\n", __func__
);
358 case PPC40x_INPUT_DEBUG
:
359 /* Level sensitive - active high */
360 LOG_IRQ("%s: set the debug pin state to %d\n",
362 ppc_set_irq(cpu
, PPC_INTERRUPT_DEBUG
, level
);
365 /* Unknown pin - do nothing */
366 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
370 env
->irq_input_state
|= 1 << pin
;
372 env
->irq_input_state
&= ~(1 << pin
);
376 void ppc40x_irq_init(PowerPCCPU
*cpu
)
378 CPUPPCState
*env
= &cpu
->env
;
380 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppc40x_set_irq
,
381 cpu
, PPC40x_INPUT_NB
);
384 /* PowerPC E500 internal IRQ controller */
385 static void ppce500_set_irq(void *opaque
, int pin
, int level
)
387 PowerPCCPU
*cpu
= opaque
;
388 CPUPPCState
*env
= &cpu
->env
;
391 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
393 cur_level
= (env
->irq_input_state
>> pin
) & 1;
394 /* Don't generate spurious events */
395 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
397 case PPCE500_INPUT_MCK
:
399 LOG_IRQ("%s: reset the PowerPC system\n",
401 qemu_system_reset_request();
404 case PPCE500_INPUT_RESET_CORE
:
406 LOG_IRQ("%s: reset the PowerPC core\n", __func__
);
407 ppc_set_irq(cpu
, PPC_INTERRUPT_MCK
, level
);
410 case PPCE500_INPUT_CINT
:
411 /* Level sensitive - active high */
412 LOG_IRQ("%s: set the critical IRQ state to %d\n",
414 ppc_set_irq(cpu
, PPC_INTERRUPT_CEXT
, level
);
416 case PPCE500_INPUT_INT
:
417 /* Level sensitive - active high */
418 LOG_IRQ("%s: set the core IRQ state to %d\n",
420 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
422 case PPCE500_INPUT_DEBUG
:
423 /* Level sensitive - active high */
424 LOG_IRQ("%s: set the debug pin state to %d\n",
426 ppc_set_irq(cpu
, PPC_INTERRUPT_DEBUG
, level
);
429 /* Unknown pin - do nothing */
430 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
434 env
->irq_input_state
|= 1 << pin
;
436 env
->irq_input_state
&= ~(1 << pin
);
440 void ppce500_irq_init(PowerPCCPU
*cpu
)
442 CPUPPCState
*env
= &cpu
->env
;
444 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppce500_set_irq
,
445 cpu
, PPCE500_INPUT_NB
);
448 /* Enable or Disable the E500 EPR capability */
449 void ppce500_set_mpic_proxy(bool enabled
)
454 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
456 cpu
->env
.mpic_proxy
= enabled
;
458 kvmppc_set_mpic_proxy(cpu
, enabled
);
463 /*****************************************************************************/
464 /* PowerPC time base and decrementer emulation */
466 uint64_t cpu_ppc_get_tb(ppc_tb_t
*tb_env
, uint64_t vmclk
, int64_t tb_offset
)
468 /* TB time in tb periods */
469 return muldiv64(vmclk
, tb_env
->tb_freq
, NANOSECONDS_PER_SECOND
) + tb_offset
;
472 uint64_t cpu_ppc_load_tbl (CPUPPCState
*env
)
474 ppc_tb_t
*tb_env
= env
->tb_env
;
478 return env
->spr
[SPR_TBL
];
481 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->tb_offset
);
482 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
487 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState
*env
)
489 ppc_tb_t
*tb_env
= env
->tb_env
;
492 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->tb_offset
);
493 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
498 uint32_t cpu_ppc_load_tbu (CPUPPCState
*env
)
501 return env
->spr
[SPR_TBU
];
504 return _cpu_ppc_load_tbu(env
);
507 static inline void cpu_ppc_store_tb(ppc_tb_t
*tb_env
, uint64_t vmclk
,
508 int64_t *tb_offsetp
, uint64_t value
)
510 *tb_offsetp
= value
-
511 muldiv64(vmclk
, tb_env
->tb_freq
, NANOSECONDS_PER_SECOND
);
513 LOG_TB("%s: tb %016" PRIx64
" offset %08" PRIx64
"\n",
514 __func__
, value
, *tb_offsetp
);
517 void cpu_ppc_store_tbl (CPUPPCState
*env
, uint32_t value
)
519 ppc_tb_t
*tb_env
= env
->tb_env
;
522 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->tb_offset
);
523 tb
&= 0xFFFFFFFF00000000ULL
;
524 cpu_ppc_store_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
525 &tb_env
->tb_offset
, tb
| (uint64_t)value
);
528 static inline void _cpu_ppc_store_tbu(CPUPPCState
*env
, uint32_t value
)
530 ppc_tb_t
*tb_env
= env
->tb_env
;
533 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->tb_offset
);
534 tb
&= 0x00000000FFFFFFFFULL
;
535 cpu_ppc_store_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
536 &tb_env
->tb_offset
, ((uint64_t)value
<< 32) | tb
);
539 void cpu_ppc_store_tbu (CPUPPCState
*env
, uint32_t value
)
541 _cpu_ppc_store_tbu(env
, value
);
544 uint64_t cpu_ppc_load_atbl (CPUPPCState
*env
)
546 ppc_tb_t
*tb_env
= env
->tb_env
;
549 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->atb_offset
);
550 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
555 uint32_t cpu_ppc_load_atbu (CPUPPCState
*env
)
557 ppc_tb_t
*tb_env
= env
->tb_env
;
560 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->atb_offset
);
561 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
566 void cpu_ppc_store_atbl (CPUPPCState
*env
, uint32_t value
)
568 ppc_tb_t
*tb_env
= env
->tb_env
;
571 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->atb_offset
);
572 tb
&= 0xFFFFFFFF00000000ULL
;
573 cpu_ppc_store_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
574 &tb_env
->atb_offset
, tb
| (uint64_t)value
);
577 void cpu_ppc_store_atbu (CPUPPCState
*env
, uint32_t value
)
579 ppc_tb_t
*tb_env
= env
->tb_env
;
582 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->atb_offset
);
583 tb
&= 0x00000000FFFFFFFFULL
;
584 cpu_ppc_store_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
585 &tb_env
->atb_offset
, ((uint64_t)value
<< 32) | tb
);
588 static void cpu_ppc_tb_stop (CPUPPCState
*env
)
590 ppc_tb_t
*tb_env
= env
->tb_env
;
591 uint64_t tb
, atb
, vmclk
;
593 /* If the time base is already frozen, do nothing */
594 if (tb_env
->tb_freq
!= 0) {
595 vmclk
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
596 /* Get the time base */
597 tb
= cpu_ppc_get_tb(tb_env
, vmclk
, tb_env
->tb_offset
);
598 /* Get the alternate time base */
599 atb
= cpu_ppc_get_tb(tb_env
, vmclk
, tb_env
->atb_offset
);
600 /* Store the time base value (ie compute the current offset) */
601 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->tb_offset
, tb
);
602 /* Store the alternate time base value (compute the current offset) */
603 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->atb_offset
, atb
);
604 /* Set the time base frequency to zero */
606 /* Now, the time bases are frozen to tb_offset / atb_offset value */
610 static void cpu_ppc_tb_start (CPUPPCState
*env
)
612 ppc_tb_t
*tb_env
= env
->tb_env
;
613 uint64_t tb
, atb
, vmclk
;
615 /* If the time base is not frozen, do nothing */
616 if (tb_env
->tb_freq
== 0) {
617 vmclk
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
618 /* Get the time base from tb_offset */
619 tb
= tb_env
->tb_offset
;
620 /* Get the alternate time base from atb_offset */
621 atb
= tb_env
->atb_offset
;
622 /* Restore the tb frequency from the decrementer frequency */
623 tb_env
->tb_freq
= tb_env
->decr_freq
;
624 /* Store the time base value */
625 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->tb_offset
, tb
);
626 /* Store the alternate time base value */
627 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->atb_offset
, atb
);
631 bool ppc_decr_clear_on_delivery(CPUPPCState
*env
)
633 ppc_tb_t
*tb_env
= env
->tb_env
;
634 int flags
= PPC_DECR_UNDERFLOW_TRIGGERED
| PPC_DECR_UNDERFLOW_LEVEL
;
635 return ((tb_env
->flags
& flags
) == PPC_DECR_UNDERFLOW_TRIGGERED
);
638 static inline uint32_t _cpu_ppc_load_decr(CPUPPCState
*env
, uint64_t next
)
640 ppc_tb_t
*tb_env
= env
->tb_env
;
644 diff
= next
- qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
646 decr
= muldiv64(diff
, tb_env
->decr_freq
, NANOSECONDS_PER_SECOND
);
647 } else if (tb_env
->flags
& PPC_TIMER_BOOKE
) {
650 decr
= -muldiv64(-diff
, tb_env
->decr_freq
, NANOSECONDS_PER_SECOND
);
652 LOG_TB("%s: %08" PRIx32
"\n", __func__
, decr
);
657 uint32_t cpu_ppc_load_decr (CPUPPCState
*env
)
659 ppc_tb_t
*tb_env
= env
->tb_env
;
662 return env
->spr
[SPR_DECR
];
665 return _cpu_ppc_load_decr(env
, tb_env
->decr_next
);
668 uint32_t cpu_ppc_load_hdecr (CPUPPCState
*env
)
670 ppc_tb_t
*tb_env
= env
->tb_env
;
672 return _cpu_ppc_load_decr(env
, tb_env
->hdecr_next
);
675 uint64_t cpu_ppc_load_purr (CPUPPCState
*env
)
677 ppc_tb_t
*tb_env
= env
->tb_env
;
680 diff
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - tb_env
->purr_start
;
682 return tb_env
->purr_load
+
683 muldiv64(diff
, tb_env
->tb_freq
, NANOSECONDS_PER_SECOND
);
686 /* When decrementer expires,
687 * all we need to do is generate or queue a CPU exception
689 static inline void cpu_ppc_decr_excp(PowerPCCPU
*cpu
)
692 LOG_TB("raise decrementer exception\n");
693 ppc_set_irq(cpu
, PPC_INTERRUPT_DECR
, 1);
696 static inline void cpu_ppc_decr_lower(PowerPCCPU
*cpu
)
698 ppc_set_irq(cpu
, PPC_INTERRUPT_DECR
, 0);
701 static inline void cpu_ppc_hdecr_excp(PowerPCCPU
*cpu
)
703 CPUPPCState
*env
= &cpu
->env
;
706 LOG_TB("raise hv decrementer exception\n");
708 /* The architecture specifies that we don't deliver HDEC
709 * interrupts in a PM state. Not only they don't cause a
710 * wakeup but they also get effectively discarded.
712 if (!env
->in_pm_state
) {
713 ppc_set_irq(cpu
, PPC_INTERRUPT_HDECR
, 1);
717 static inline void cpu_ppc_hdecr_lower(PowerPCCPU
*cpu
)
719 ppc_set_irq(cpu
, PPC_INTERRUPT_HDECR
, 0);
722 static void __cpu_ppc_store_decr(PowerPCCPU
*cpu
, uint64_t *nextp
,
724 void (*raise_excp
)(void *),
725 void (*lower_excp
)(PowerPCCPU
*),
726 uint32_t decr
, uint32_t value
)
728 CPUPPCState
*env
= &cpu
->env
;
729 ppc_tb_t
*tb_env
= env
->tb_env
;
732 LOG_TB("%s: %08" PRIx32
" => %08" PRIx32
"\n", __func__
,
736 /* KVM handles decrementer exceptions, we don't need our own timer */
741 * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC
744 * If we get a really small DEC value, we can assume that by the time we
745 * handled it we should inject an interrupt already.
747 * On MSB level based DEC implementations the MSB always means the interrupt
748 * is pending, so raise it on those.
750 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers
751 * an edge interrupt, so raise it here too.
754 ((tb_env
->flags
& PPC_DECR_UNDERFLOW_LEVEL
) && (value
& 0x80000000)) ||
755 ((tb_env
->flags
& PPC_DECR_UNDERFLOW_TRIGGERED
) && (value
& 0x80000000)
756 && !(decr
& 0x80000000))) {
761 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */
762 if (!(value
& 0x80000000) && (tb_env
->flags
& PPC_DECR_UNDERFLOW_LEVEL
)) {
766 /* Calculate the next timer event */
767 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
768 next
= now
+ muldiv64(value
, NANOSECONDS_PER_SECOND
, tb_env
->decr_freq
);
772 timer_mod(timer
, next
);
775 static inline void _cpu_ppc_store_decr(PowerPCCPU
*cpu
, uint32_t decr
,
778 ppc_tb_t
*tb_env
= cpu
->env
.tb_env
;
780 __cpu_ppc_store_decr(cpu
, &tb_env
->decr_next
, tb_env
->decr_timer
,
781 tb_env
->decr_timer
->cb
, &cpu_ppc_decr_lower
, decr
,
785 void cpu_ppc_store_decr (CPUPPCState
*env
, uint32_t value
)
787 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
789 _cpu_ppc_store_decr(cpu
, cpu_ppc_load_decr(env
), value
);
792 static void cpu_ppc_decr_cb(void *opaque
)
794 PowerPCCPU
*cpu
= opaque
;
796 cpu_ppc_decr_excp(cpu
);
799 static inline void _cpu_ppc_store_hdecr(PowerPCCPU
*cpu
, uint32_t hdecr
,
802 ppc_tb_t
*tb_env
= cpu
->env
.tb_env
;
804 if (tb_env
->hdecr_timer
!= NULL
) {
805 __cpu_ppc_store_decr(cpu
, &tb_env
->hdecr_next
, tb_env
->hdecr_timer
,
806 tb_env
->hdecr_timer
->cb
, &cpu_ppc_hdecr_lower
,
811 void cpu_ppc_store_hdecr (CPUPPCState
*env
, uint32_t value
)
813 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
815 _cpu_ppc_store_hdecr(cpu
, cpu_ppc_load_hdecr(env
), value
);
818 static void cpu_ppc_hdecr_cb(void *opaque
)
820 PowerPCCPU
*cpu
= opaque
;
822 cpu_ppc_hdecr_excp(cpu
);
825 static void cpu_ppc_store_purr(PowerPCCPU
*cpu
, uint64_t value
)
827 ppc_tb_t
*tb_env
= cpu
->env
.tb_env
;
829 tb_env
->purr_load
= value
;
830 tb_env
->purr_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
833 static void cpu_ppc_set_tb_clk (void *opaque
, uint32_t freq
)
835 CPUPPCState
*env
= opaque
;
836 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
837 ppc_tb_t
*tb_env
= env
->tb_env
;
839 tb_env
->tb_freq
= freq
;
840 tb_env
->decr_freq
= freq
;
841 /* There is a bug in Linux 2.4 kernels:
842 * if a decrementer exception is pending when it enables msr_ee at startup,
843 * it's not ready to handle it...
845 _cpu_ppc_store_decr(cpu
, 0xFFFFFFFF, 0xFFFFFFFF);
846 _cpu_ppc_store_hdecr(cpu
, 0xFFFFFFFF, 0xFFFFFFFF);
847 cpu_ppc_store_purr(cpu
, 0x0000000000000000ULL
);
850 static void timebase_save(PPCTimebase
*tb
)
852 uint64_t ticks
= cpu_get_host_ticks();
853 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
855 if (!first_ppc_cpu
->env
.tb_env
) {
856 error_report("No timebase object");
860 /* not used anymore, we keep it for compatibility */
861 tb
->time_of_the_day_ns
= qemu_clock_get_ns(QEMU_CLOCK_HOST
);
863 * tb_offset is only expected to be changed by QEMU so
864 * there is no need to update it from KVM here
866 tb
->guest_timebase
= ticks
+ first_ppc_cpu
->env
.tb_env
->tb_offset
;
869 static void timebase_load(PPCTimebase
*tb
)
872 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
873 int64_t tb_off_adj
, tb_off
;
876 if (!first_ppc_cpu
->env
.tb_env
) {
877 error_report("No timebase object");
881 freq
= first_ppc_cpu
->env
.tb_env
->tb_freq
;
883 tb_off_adj
= tb
->guest_timebase
- cpu_get_host_ticks();
885 tb_off
= first_ppc_cpu
->env
.tb_env
->tb_offset
;
886 trace_ppc_tb_adjust(tb_off
, tb_off_adj
, tb_off_adj
- tb_off
,
887 (tb_off_adj
- tb_off
) / freq
);
889 /* Set new offset to all CPUs */
891 PowerPCCPU
*pcpu
= POWERPC_CPU(cpu
);
892 pcpu
->env
.tb_env
->tb_offset
= tb_off_adj
;
893 #if defined(CONFIG_KVM)
894 kvm_set_one_reg(cpu
, KVM_REG_PPC_TB_OFFSET
,
895 &pcpu
->env
.tb_env
->tb_offset
);
900 void cpu_ppc_clock_vm_state_change(void *opaque
, int running
,
903 PPCTimebase
*tb
= opaque
;
913 * When migrating, read the clock just before migration,
914 * so that the guest clock counts during the events
921 * This reduces clock difference on migration from 5s
922 * to 0.1s (when max_downtime == 5s), because sending the
923 * final pages of memory (which happens between vm_stop()
924 * and pre_save()) takes max_downtime.
926 static void timebase_pre_save(void *opaque
)
928 PPCTimebase
*tb
= opaque
;
933 const VMStateDescription vmstate_ppc_timebase
= {
936 .minimum_version_id
= 1,
937 .minimum_version_id_old
= 1,
938 .pre_save
= timebase_pre_save
,
939 .fields
= (VMStateField
[]) {
940 VMSTATE_UINT64(guest_timebase
, PPCTimebase
),
941 VMSTATE_INT64(time_of_the_day_ns
, PPCTimebase
),
942 VMSTATE_END_OF_LIST()
946 /* Set up (once) timebase frequency (in Hz) */
947 clk_setup_cb
cpu_ppc_tb_init (CPUPPCState
*env
, uint32_t freq
)
949 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
952 tb_env
= g_malloc0(sizeof(ppc_tb_t
));
953 env
->tb_env
= tb_env
;
954 tb_env
->flags
= PPC_DECR_UNDERFLOW_TRIGGERED
;
955 if (env
->insns_flags
& PPC_SEGMENT_64B
) {
956 /* All Book3S 64bit CPUs implement level based DEC logic */
957 tb_env
->flags
|= PPC_DECR_UNDERFLOW_LEVEL
;
959 /* Create new timer */
960 tb_env
->decr_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &cpu_ppc_decr_cb
, cpu
);
961 if (env
->has_hv_mode
) {
962 tb_env
->hdecr_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &cpu_ppc_hdecr_cb
,
965 tb_env
->hdecr_timer
= NULL
;
967 cpu_ppc_set_tb_clk(env
, freq
);
969 return &cpu_ppc_set_tb_clk
;
972 /* Specific helpers for POWER & PowerPC 601 RTC */
973 void cpu_ppc601_store_rtcu (CPUPPCState
*env
, uint32_t value
)
975 _cpu_ppc_store_tbu(env
, value
);
978 uint32_t cpu_ppc601_load_rtcu (CPUPPCState
*env
)
980 return _cpu_ppc_load_tbu(env
);
983 void cpu_ppc601_store_rtcl (CPUPPCState
*env
, uint32_t value
)
985 cpu_ppc_store_tbl(env
, value
& 0x3FFFFF80);
988 uint32_t cpu_ppc601_load_rtcl (CPUPPCState
*env
)
990 return cpu_ppc_load_tbl(env
) & 0x3FFFFF80;
993 /*****************************************************************************/
994 /* PowerPC 40x timers */
997 typedef struct ppc40x_timer_t ppc40x_timer_t
;
998 struct ppc40x_timer_t
{
999 uint64_t pit_reload
; /* PIT auto-reload value */
1000 uint64_t fit_next
; /* Tick for next FIT interrupt */
1001 QEMUTimer
*fit_timer
;
1002 uint64_t wdt_next
; /* Tick for next WDT interrupt */
1003 QEMUTimer
*wdt_timer
;
1005 /* 405 have the PIT, 440 have a DECR. */
1006 unsigned int decr_excp
;
1009 /* Fixed interval timer */
1010 static void cpu_4xx_fit_cb (void *opaque
)
1015 ppc40x_timer_t
*ppc40x_timer
;
1019 cpu
= ppc_env_get_cpu(env
);
1020 tb_env
= env
->tb_env
;
1021 ppc40x_timer
= tb_env
->opaque
;
1022 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1023 switch ((env
->spr
[SPR_40x_TCR
] >> 24) & 0x3) {
1037 /* Cannot occur, but makes gcc happy */
1040 next
= now
+ muldiv64(next
, NANOSECONDS_PER_SECOND
, tb_env
->tb_freq
);
1043 timer_mod(ppc40x_timer
->fit_timer
, next
);
1044 env
->spr
[SPR_40x_TSR
] |= 1 << 26;
1045 if ((env
->spr
[SPR_40x_TCR
] >> 23) & 0x1) {
1046 ppc_set_irq(cpu
, PPC_INTERRUPT_FIT
, 1);
1048 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
"\n", __func__
,
1049 (int)((env
->spr
[SPR_40x_TCR
] >> 23) & 0x1),
1050 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
]);
1053 /* Programmable interval timer */
1054 static void start_stop_pit (CPUPPCState
*env
, ppc_tb_t
*tb_env
, int is_excp
)
1056 ppc40x_timer_t
*ppc40x_timer
;
1059 ppc40x_timer
= tb_env
->opaque
;
1060 if (ppc40x_timer
->pit_reload
<= 1 ||
1061 !((env
->spr
[SPR_40x_TCR
] >> 26) & 0x1) ||
1062 (is_excp
&& !((env
->spr
[SPR_40x_TCR
] >> 22) & 0x1))) {
1064 LOG_TB("%s: stop PIT\n", __func__
);
1065 timer_del(tb_env
->decr_timer
);
1067 LOG_TB("%s: start PIT %016" PRIx64
"\n",
1068 __func__
, ppc40x_timer
->pit_reload
);
1069 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1070 next
= now
+ muldiv64(ppc40x_timer
->pit_reload
,
1071 NANOSECONDS_PER_SECOND
, tb_env
->decr_freq
);
1073 next
+= tb_env
->decr_next
- now
;
1076 timer_mod(tb_env
->decr_timer
, next
);
1077 tb_env
->decr_next
= next
;
1081 static void cpu_4xx_pit_cb (void *opaque
)
1086 ppc40x_timer_t
*ppc40x_timer
;
1089 cpu
= ppc_env_get_cpu(env
);
1090 tb_env
= env
->tb_env
;
1091 ppc40x_timer
= tb_env
->opaque
;
1092 env
->spr
[SPR_40x_TSR
] |= 1 << 27;
1093 if ((env
->spr
[SPR_40x_TCR
] >> 26) & 0x1) {
1094 ppc_set_irq(cpu
, ppc40x_timer
->decr_excp
, 1);
1096 start_stop_pit(env
, tb_env
, 1);
1097 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
" "
1098 "%016" PRIx64
"\n", __func__
,
1099 (int)((env
->spr
[SPR_40x_TCR
] >> 22) & 0x1),
1100 (int)((env
->spr
[SPR_40x_TCR
] >> 26) & 0x1),
1101 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
],
1102 ppc40x_timer
->pit_reload
);
1105 /* Watchdog timer */
1106 static void cpu_4xx_wdt_cb (void *opaque
)
1111 ppc40x_timer_t
*ppc40x_timer
;
1115 cpu
= ppc_env_get_cpu(env
);
1116 tb_env
= env
->tb_env
;
1117 ppc40x_timer
= tb_env
->opaque
;
1118 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1119 switch ((env
->spr
[SPR_40x_TCR
] >> 30) & 0x3) {
1133 /* Cannot occur, but makes gcc happy */
1136 next
= now
+ muldiv64(next
, NANOSECONDS_PER_SECOND
, tb_env
->decr_freq
);
1139 LOG_TB("%s: TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
"\n", __func__
,
1140 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
]);
1141 switch ((env
->spr
[SPR_40x_TSR
] >> 30) & 0x3) {
1144 timer_mod(ppc40x_timer
->wdt_timer
, next
);
1145 ppc40x_timer
->wdt_next
= next
;
1146 env
->spr
[SPR_40x_TSR
] |= 1U << 31;
1149 timer_mod(ppc40x_timer
->wdt_timer
, next
);
1150 ppc40x_timer
->wdt_next
= next
;
1151 env
->spr
[SPR_40x_TSR
] |= 1 << 30;
1152 if ((env
->spr
[SPR_40x_TCR
] >> 27) & 0x1) {
1153 ppc_set_irq(cpu
, PPC_INTERRUPT_WDT
, 1);
1157 env
->spr
[SPR_40x_TSR
] &= ~0x30000000;
1158 env
->spr
[SPR_40x_TSR
] |= env
->spr
[SPR_40x_TCR
] & 0x30000000;
1159 switch ((env
->spr
[SPR_40x_TCR
] >> 28) & 0x3) {
1163 case 0x1: /* Core reset */
1164 ppc40x_core_reset(cpu
);
1166 case 0x2: /* Chip reset */
1167 ppc40x_chip_reset(cpu
);
1169 case 0x3: /* System reset */
1170 ppc40x_system_reset(cpu
);
1176 void store_40x_pit (CPUPPCState
*env
, target_ulong val
)
1179 ppc40x_timer_t
*ppc40x_timer
;
1181 tb_env
= env
->tb_env
;
1182 ppc40x_timer
= tb_env
->opaque
;
1183 LOG_TB("%s val" TARGET_FMT_lx
"\n", __func__
, val
);
1184 ppc40x_timer
->pit_reload
= val
;
1185 start_stop_pit(env
, tb_env
, 0);
1188 target_ulong
load_40x_pit (CPUPPCState
*env
)
1190 return cpu_ppc_load_decr(env
);
1193 static void ppc_40x_set_tb_clk (void *opaque
, uint32_t freq
)
1195 CPUPPCState
*env
= opaque
;
1196 ppc_tb_t
*tb_env
= env
->tb_env
;
1198 LOG_TB("%s set new frequency to %" PRIu32
"\n", __func__
,
1200 tb_env
->tb_freq
= freq
;
1201 tb_env
->decr_freq
= freq
;
1202 /* XXX: we should also update all timers */
1205 clk_setup_cb
ppc_40x_timers_init (CPUPPCState
*env
, uint32_t freq
,
1206 unsigned int decr_excp
)
1209 ppc40x_timer_t
*ppc40x_timer
;
1211 tb_env
= g_malloc0(sizeof(ppc_tb_t
));
1212 env
->tb_env
= tb_env
;
1213 tb_env
->flags
= PPC_DECR_UNDERFLOW_TRIGGERED
;
1214 ppc40x_timer
= g_malloc0(sizeof(ppc40x_timer_t
));
1215 tb_env
->tb_freq
= freq
;
1216 tb_env
->decr_freq
= freq
;
1217 tb_env
->opaque
= ppc40x_timer
;
1218 LOG_TB("%s freq %" PRIu32
"\n", __func__
, freq
);
1219 if (ppc40x_timer
!= NULL
) {
1220 /* We use decr timer for PIT */
1221 tb_env
->decr_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &cpu_4xx_pit_cb
, env
);
1222 ppc40x_timer
->fit_timer
=
1223 timer_new_ns(QEMU_CLOCK_VIRTUAL
, &cpu_4xx_fit_cb
, env
);
1224 ppc40x_timer
->wdt_timer
=
1225 timer_new_ns(QEMU_CLOCK_VIRTUAL
, &cpu_4xx_wdt_cb
, env
);
1226 ppc40x_timer
->decr_excp
= decr_excp
;
1229 return &ppc_40x_set_tb_clk
;
1232 /*****************************************************************************/
1233 /* Embedded PowerPC Device Control Registers */
1234 typedef struct ppc_dcrn_t ppc_dcrn_t
;
1236 dcr_read_cb dcr_read
;
1237 dcr_write_cb dcr_write
;
1241 /* XXX: on 460, DCR addresses are 32 bits wide,
1242 * using DCRIPR to get the 22 upper bits of the DCR address
1244 #define DCRN_NB 1024
1246 ppc_dcrn_t dcrn
[DCRN_NB
];
1247 int (*read_error
)(int dcrn
);
1248 int (*write_error
)(int dcrn
);
1251 int ppc_dcr_read (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t *valp
)
1255 if (dcrn
< 0 || dcrn
>= DCRN_NB
)
1257 dcr
= &dcr_env
->dcrn
[dcrn
];
1258 if (dcr
->dcr_read
== NULL
)
1260 *valp
= (*dcr
->dcr_read
)(dcr
->opaque
, dcrn
);
1265 if (dcr_env
->read_error
!= NULL
)
1266 return (*dcr_env
->read_error
)(dcrn
);
1271 int ppc_dcr_write (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t val
)
1275 if (dcrn
< 0 || dcrn
>= DCRN_NB
)
1277 dcr
= &dcr_env
->dcrn
[dcrn
];
1278 if (dcr
->dcr_write
== NULL
)
1280 (*dcr
->dcr_write
)(dcr
->opaque
, dcrn
, val
);
1285 if (dcr_env
->write_error
!= NULL
)
1286 return (*dcr_env
->write_error
)(dcrn
);
1291 int ppc_dcr_register (CPUPPCState
*env
, int dcrn
, void *opaque
,
1292 dcr_read_cb dcr_read
, dcr_write_cb dcr_write
)
1297 dcr_env
= env
->dcr_env
;
1298 if (dcr_env
== NULL
)
1300 if (dcrn
< 0 || dcrn
>= DCRN_NB
)
1302 dcr
= &dcr_env
->dcrn
[dcrn
];
1303 if (dcr
->opaque
!= NULL
||
1304 dcr
->dcr_read
!= NULL
||
1305 dcr
->dcr_write
!= NULL
)
1307 dcr
->opaque
= opaque
;
1308 dcr
->dcr_read
= dcr_read
;
1309 dcr
->dcr_write
= dcr_write
;
1314 int ppc_dcr_init (CPUPPCState
*env
, int (*read_error
)(int dcrn
),
1315 int (*write_error
)(int dcrn
))
1319 dcr_env
= g_malloc0(sizeof(ppc_dcr_t
));
1320 dcr_env
->read_error
= read_error
;
1321 dcr_env
->write_error
= write_error
;
1322 env
->dcr_env
= dcr_env
;
1327 /*****************************************************************************/
1329 void PPC_debug_write (void *opaque
, uint32_t addr
, uint32_t val
)
1341 printf("Set loglevel to %04" PRIx32
"\n", val
);
1342 qemu_set_log(val
| 0x100);
1347 /* CPU device-tree ID helpers */
1348 int ppc_get_vcpu_dt_id(PowerPCCPU
*cpu
)
1350 return cpu
->cpu_dt_id
;
1353 PowerPCCPU
*ppc_get_vcpu_by_dt_id(int cpu_dt_id
)
1358 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1360 if (cpu
->cpu_dt_id
== cpu_dt_id
) {
1368 void ppc_cpu_parse_features(const char *cpu_model
)
1372 const char *typename
;
1373 gchar
**model_pieces
;
1375 model_pieces
= g_strsplit(cpu_model
, ",", 2);
1376 if (!model_pieces
[0]) {
1377 error_report("Invalid/empty CPU model name");
1381 oc
= cpu_class_by_name(TYPE_POWERPC_CPU
, model_pieces
[0]);
1383 error_report("Unable to find CPU definition: %s", model_pieces
[0]);
1387 typename
= object_class_get_name(oc
);
1389 cc
->parse_features(typename
, model_pieces
[1], &error_fatal
);
1390 g_strfreev(model_pieces
);