spapr: Expose the name of the interrupt controller node
[qemu/ar7.git] / include / hw / acpi / tco.h
blob52ad767ddda319c0da00aa0ca9f1ea7c99db7e29
1 /*
2 * QEMU ICH9 TCO emulation
4 * Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
9 #ifndef HW_ACPI_TCO_H
10 #define HW_ACPI_TCO_H
12 #include "qemu-common.h"
14 /* As per ICH9 spec, the internal timer has an error of ~0.6s on every tick */
15 #define TCO_TICK_NSEC 600000000LL
17 /* TCO I/O register offsets */
18 enum {
19 TCO_RLD = 0x00,
20 TCO_DAT_IN = 0x02,
21 TCO_DAT_OUT = 0x03,
22 TCO1_STS = 0x04,
23 TCO2_STS = 0x06,
24 TCO1_CNT = 0x08,
25 TCO2_CNT = 0x0a,
26 TCO_MESSAGE1 = 0x0c,
27 TCO_MESSAGE2 = 0x0d,
28 TCO_WDCNT = 0x0e,
29 SW_IRQ_GEN = 0x10,
30 TCO_TMR = 0x12,
33 /* TCO I/O register control/status bits */
34 enum {
35 SW_TCO_SMI = 1 << 1,
36 TCO_INT_STS = 1 << 2,
37 TCO_LOCK = 1 << 12,
38 TCO_TMR_HLT = 1 << 11,
39 TCO_TIMEOUT = 1 << 3,
40 TCO_SECOND_TO_STS = 1 << 1,
41 TCO_BOOT_STS = 1 << 2,
44 /* TCO I/O registers mask bits */
45 enum {
46 TCO_RLD_MASK = 0x3ff,
47 TCO1_STS_MASK = 0xe870,
48 TCO2_STS_MASK = 0xfff8,
49 TCO1_CNT_MASK = 0xfeff,
50 TCO_TMR_MASK = 0x3ff,
53 typedef struct TCOIORegs {
54 struct {
55 uint16_t rld;
56 uint8_t din;
57 uint8_t dout;
58 uint16_t sts1;
59 uint16_t sts2;
60 uint16_t cnt1;
61 uint16_t cnt2;
62 uint8_t msg1;
63 uint8_t msg2;
64 uint8_t wdcnt;
65 uint16_t tmr;
66 } tco;
67 uint8_t sw_irq_gen;
69 QEMUTimer *tco_timer;
70 int64_t expire_time;
71 uint8_t timeouts_no;
73 MemoryRegion io;
74 } TCOIORegs;
76 /* tco.c */
77 void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent);
79 extern const VMStateDescription vmstate_tco_io_sts;
81 #endif /* HW_ACPI_TCO_H */