2 * QEMU generic PowerPC hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu-timer.h"
34 //#define PPC_DEBUG_IRQ
35 //#define PPC_DEBUG_TB
38 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
40 # define LOG_IRQ(...) do { } while (0)
45 # define LOG_TB(...) qemu_log(__VA_ARGS__)
47 # define LOG_TB(...) do { } while (0)
50 static void cpu_ppc_tb_stop (CPUPPCState
*env
);
51 static void cpu_ppc_tb_start (CPUPPCState
*env
);
53 void ppc_set_irq(CPUPPCState
*env
, int n_IRQ
, int level
)
55 unsigned int old_pending
= env
->pending_interrupts
;
58 env
->pending_interrupts
|= 1 << n_IRQ
;
59 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
61 env
->pending_interrupts
&= ~(1 << n_IRQ
);
62 if (env
->pending_interrupts
== 0)
63 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
66 if (old_pending
!= env
->pending_interrupts
) {
68 kvmppc_set_interrupt(env
, n_IRQ
, level
);
72 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
73 "req %08x\n", __func__
, env
, n_IRQ
, level
,
74 env
->pending_interrupts
, env
->interrupt_request
);
77 /* PowerPC 6xx / 7xx internal IRQ controller */
78 static void ppc6xx_set_irq(void *opaque
, int pin
, int level
)
80 PowerPCCPU
*cpu
= opaque
;
81 CPUPPCState
*env
= &cpu
->env
;
84 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
86 cur_level
= (env
->irq_input_state
>> pin
) & 1;
87 /* Don't generate spurious events */
88 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
90 case PPC6xx_INPUT_TBEN
:
91 /* Level sensitive - active high */
92 LOG_IRQ("%s: %s the time base\n",
93 __func__
, level
? "start" : "stop");
95 cpu_ppc_tb_start(env
);
99 case PPC6xx_INPUT_INT
:
100 /* Level sensitive - active high */
101 LOG_IRQ("%s: set the external IRQ state to %d\n",
103 ppc_set_irq(env
, PPC_INTERRUPT_EXT
, level
);
105 case PPC6xx_INPUT_SMI
:
106 /* Level sensitive - active high */
107 LOG_IRQ("%s: set the SMI IRQ state to %d\n",
109 ppc_set_irq(env
, PPC_INTERRUPT_SMI
, level
);
111 case PPC6xx_INPUT_MCP
:
112 /* Negative edge sensitive */
113 /* XXX: TODO: actual reaction may depends on HID0 status
114 * 603/604/740/750: check HID0[EMCP]
116 if (cur_level
== 1 && level
== 0) {
117 LOG_IRQ("%s: raise machine check state\n",
119 ppc_set_irq(env
, PPC_INTERRUPT_MCK
, 1);
122 case PPC6xx_INPUT_CKSTP_IN
:
123 /* Level sensitive - active low */
124 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
125 /* XXX: Note that the only way to restart the CPU is to reset it */
127 LOG_IRQ("%s: stop the CPU\n", __func__
);
131 case PPC6xx_INPUT_HRESET
:
132 /* Level sensitive - active low */
134 LOG_IRQ("%s: reset the CPU\n", __func__
);
135 cpu_interrupt(env
, CPU_INTERRUPT_RESET
);
138 case PPC6xx_INPUT_SRESET
:
139 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
141 ppc_set_irq(env
, PPC_INTERRUPT_RESET
, level
);
144 /* Unknown pin - do nothing */
145 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
149 env
->irq_input_state
|= 1 << pin
;
151 env
->irq_input_state
&= ~(1 << pin
);
155 void ppc6xx_irq_init(CPUPPCState
*env
)
157 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
159 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppc6xx_set_irq
, cpu
,
163 #if defined(TARGET_PPC64)
164 /* PowerPC 970 internal IRQ controller */
165 static void ppc970_set_irq(void *opaque
, int pin
, int level
)
167 PowerPCCPU
*cpu
= opaque
;
168 CPUPPCState
*env
= &cpu
->env
;
171 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
173 cur_level
= (env
->irq_input_state
>> pin
) & 1;
174 /* Don't generate spurious events */
175 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
177 case PPC970_INPUT_INT
:
178 /* Level sensitive - active high */
179 LOG_IRQ("%s: set the external IRQ state to %d\n",
181 ppc_set_irq(env
, PPC_INTERRUPT_EXT
, level
);
183 case PPC970_INPUT_THINT
:
184 /* Level sensitive - active high */
185 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__
,
187 ppc_set_irq(env
, PPC_INTERRUPT_THERM
, level
);
189 case PPC970_INPUT_MCP
:
190 /* Negative edge sensitive */
191 /* XXX: TODO: actual reaction may depends on HID0 status
192 * 603/604/740/750: check HID0[EMCP]
194 if (cur_level
== 1 && level
== 0) {
195 LOG_IRQ("%s: raise machine check state\n",
197 ppc_set_irq(env
, PPC_INTERRUPT_MCK
, 1);
200 case PPC970_INPUT_CKSTP
:
201 /* Level sensitive - active low */
202 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
204 LOG_IRQ("%s: stop the CPU\n", __func__
);
207 LOG_IRQ("%s: restart the CPU\n", __func__
);
209 qemu_cpu_kick(CPU(cpu
));
212 case PPC970_INPUT_HRESET
:
213 /* Level sensitive - active low */
215 cpu_interrupt(env
, CPU_INTERRUPT_RESET
);
218 case PPC970_INPUT_SRESET
:
219 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
221 ppc_set_irq(env
, PPC_INTERRUPT_RESET
, level
);
223 case PPC970_INPUT_TBEN
:
224 LOG_IRQ("%s: set the TBEN state to %d\n", __func__
,
229 /* Unknown pin - do nothing */
230 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
234 env
->irq_input_state
|= 1 << pin
;
236 env
->irq_input_state
&= ~(1 << pin
);
240 void ppc970_irq_init(CPUPPCState
*env
)
242 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
244 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppc970_set_irq
, cpu
,
248 /* POWER7 internal IRQ controller */
249 static void power7_set_irq(void *opaque
, int pin
, int level
)
251 PowerPCCPU
*cpu
= opaque
;
252 CPUPPCState
*env
= &cpu
->env
;
254 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
258 case POWER7_INPUT_INT
:
259 /* Level sensitive - active high */
260 LOG_IRQ("%s: set the external IRQ state to %d\n",
262 ppc_set_irq(env
, PPC_INTERRUPT_EXT
, level
);
265 /* Unknown pin - do nothing */
266 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
270 env
->irq_input_state
|= 1 << pin
;
272 env
->irq_input_state
&= ~(1 << pin
);
276 void ppcPOWER7_irq_init(CPUPPCState
*env
)
278 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
280 env
->irq_inputs
= (void **)qemu_allocate_irqs(&power7_set_irq
, cpu
,
283 #endif /* defined(TARGET_PPC64) */
285 /* PowerPC 40x internal IRQ controller */
286 static void ppc40x_set_irq(void *opaque
, int pin
, int level
)
288 PowerPCCPU
*cpu
= opaque
;
289 CPUPPCState
*env
= &cpu
->env
;
292 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
294 cur_level
= (env
->irq_input_state
>> pin
) & 1;
295 /* Don't generate spurious events */
296 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
298 case PPC40x_INPUT_RESET_SYS
:
300 LOG_IRQ("%s: reset the PowerPC system\n",
302 ppc40x_system_reset(env
);
305 case PPC40x_INPUT_RESET_CHIP
:
307 LOG_IRQ("%s: reset the PowerPC chip\n", __func__
);
308 ppc40x_chip_reset(env
);
311 case PPC40x_INPUT_RESET_CORE
:
312 /* XXX: TODO: update DBSR[MRR] */
314 LOG_IRQ("%s: reset the PowerPC core\n", __func__
);
315 ppc40x_core_reset(env
);
318 case PPC40x_INPUT_CINT
:
319 /* Level sensitive - active high */
320 LOG_IRQ("%s: set the critical IRQ state to %d\n",
322 ppc_set_irq(env
, PPC_INTERRUPT_CEXT
, level
);
324 case PPC40x_INPUT_INT
:
325 /* Level sensitive - active high */
326 LOG_IRQ("%s: set the external IRQ state to %d\n",
328 ppc_set_irq(env
, PPC_INTERRUPT_EXT
, level
);
330 case PPC40x_INPUT_HALT
:
331 /* Level sensitive - active low */
333 LOG_IRQ("%s: stop the CPU\n", __func__
);
336 LOG_IRQ("%s: restart the CPU\n", __func__
);
338 qemu_cpu_kick(CPU(cpu
));
341 case PPC40x_INPUT_DEBUG
:
342 /* Level sensitive - active high */
343 LOG_IRQ("%s: set the debug pin state to %d\n",
345 ppc_set_irq(env
, PPC_INTERRUPT_DEBUG
, level
);
348 /* Unknown pin - do nothing */
349 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
353 env
->irq_input_state
|= 1 << pin
;
355 env
->irq_input_state
&= ~(1 << pin
);
359 void ppc40x_irq_init(CPUPPCState
*env
)
361 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
363 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppc40x_set_irq
,
364 cpu
, PPC40x_INPUT_NB
);
367 /* PowerPC E500 internal IRQ controller */
368 static void ppce500_set_irq(void *opaque
, int pin
, int level
)
370 PowerPCCPU
*cpu
= opaque
;
371 CPUPPCState
*env
= &cpu
->env
;
374 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
376 cur_level
= (env
->irq_input_state
>> pin
) & 1;
377 /* Don't generate spurious events */
378 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
380 case PPCE500_INPUT_MCK
:
382 LOG_IRQ("%s: reset the PowerPC system\n",
384 qemu_system_reset_request();
387 case PPCE500_INPUT_RESET_CORE
:
389 LOG_IRQ("%s: reset the PowerPC core\n", __func__
);
390 ppc_set_irq(env
, PPC_INTERRUPT_MCK
, level
);
393 case PPCE500_INPUT_CINT
:
394 /* Level sensitive - active high */
395 LOG_IRQ("%s: set the critical IRQ state to %d\n",
397 ppc_set_irq(env
, PPC_INTERRUPT_CEXT
, level
);
399 case PPCE500_INPUT_INT
:
400 /* Level sensitive - active high */
401 LOG_IRQ("%s: set the core IRQ state to %d\n",
403 ppc_set_irq(env
, PPC_INTERRUPT_EXT
, level
);
405 case PPCE500_INPUT_DEBUG
:
406 /* Level sensitive - active high */
407 LOG_IRQ("%s: set the debug pin state to %d\n",
409 ppc_set_irq(env
, PPC_INTERRUPT_DEBUG
, level
);
412 /* Unknown pin - do nothing */
413 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
417 env
->irq_input_state
|= 1 << pin
;
419 env
->irq_input_state
&= ~(1 << pin
);
423 void ppce500_irq_init(CPUPPCState
*env
)
425 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
427 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppce500_set_irq
,
428 cpu
, PPCE500_INPUT_NB
);
430 /*****************************************************************************/
431 /* PowerPC time base and decrementer emulation */
433 uint64_t cpu_ppc_get_tb(ppc_tb_t
*tb_env
, uint64_t vmclk
, int64_t tb_offset
)
435 /* TB time in tb periods */
436 return muldiv64(vmclk
, tb_env
->tb_freq
, get_ticks_per_sec()) + tb_offset
;
439 uint64_t cpu_ppc_load_tbl (CPUPPCState
*env
)
441 ppc_tb_t
*tb_env
= env
->tb_env
;
445 return env
->spr
[SPR_TBL
];
448 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->tb_offset
);
449 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
454 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState
*env
)
456 ppc_tb_t
*tb_env
= env
->tb_env
;
459 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->tb_offset
);
460 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
465 uint32_t cpu_ppc_load_tbu (CPUPPCState
*env
)
468 return env
->spr
[SPR_TBU
];
471 return _cpu_ppc_load_tbu(env
);
474 static inline void cpu_ppc_store_tb(ppc_tb_t
*tb_env
, uint64_t vmclk
,
475 int64_t *tb_offsetp
, uint64_t value
)
477 *tb_offsetp
= value
- muldiv64(vmclk
, tb_env
->tb_freq
, get_ticks_per_sec());
478 LOG_TB("%s: tb %016" PRIx64
" offset %08" PRIx64
"\n",
479 __func__
, value
, *tb_offsetp
);
482 void cpu_ppc_store_tbl (CPUPPCState
*env
, uint32_t value
)
484 ppc_tb_t
*tb_env
= env
->tb_env
;
487 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->tb_offset
);
488 tb
&= 0xFFFFFFFF00000000ULL
;
489 cpu_ppc_store_tb(tb_env
, qemu_get_clock_ns(vm_clock
),
490 &tb_env
->tb_offset
, tb
| (uint64_t)value
);
493 static inline void _cpu_ppc_store_tbu(CPUPPCState
*env
, uint32_t value
)
495 ppc_tb_t
*tb_env
= env
->tb_env
;
498 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->tb_offset
);
499 tb
&= 0x00000000FFFFFFFFULL
;
500 cpu_ppc_store_tb(tb_env
, qemu_get_clock_ns(vm_clock
),
501 &tb_env
->tb_offset
, ((uint64_t)value
<< 32) | tb
);
504 void cpu_ppc_store_tbu (CPUPPCState
*env
, uint32_t value
)
506 _cpu_ppc_store_tbu(env
, value
);
509 uint64_t cpu_ppc_load_atbl (CPUPPCState
*env
)
511 ppc_tb_t
*tb_env
= env
->tb_env
;
514 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->atb_offset
);
515 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
520 uint32_t cpu_ppc_load_atbu (CPUPPCState
*env
)
522 ppc_tb_t
*tb_env
= env
->tb_env
;
525 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->atb_offset
);
526 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
531 void cpu_ppc_store_atbl (CPUPPCState
*env
, uint32_t value
)
533 ppc_tb_t
*tb_env
= env
->tb_env
;
536 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->atb_offset
);
537 tb
&= 0xFFFFFFFF00000000ULL
;
538 cpu_ppc_store_tb(tb_env
, qemu_get_clock_ns(vm_clock
),
539 &tb_env
->atb_offset
, tb
| (uint64_t)value
);
542 void cpu_ppc_store_atbu (CPUPPCState
*env
, uint32_t value
)
544 ppc_tb_t
*tb_env
= env
->tb_env
;
547 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->atb_offset
);
548 tb
&= 0x00000000FFFFFFFFULL
;
549 cpu_ppc_store_tb(tb_env
, qemu_get_clock_ns(vm_clock
),
550 &tb_env
->atb_offset
, ((uint64_t)value
<< 32) | tb
);
553 static void cpu_ppc_tb_stop (CPUPPCState
*env
)
555 ppc_tb_t
*tb_env
= env
->tb_env
;
556 uint64_t tb
, atb
, vmclk
;
558 /* If the time base is already frozen, do nothing */
559 if (tb_env
->tb_freq
!= 0) {
560 vmclk
= qemu_get_clock_ns(vm_clock
);
561 /* Get the time base */
562 tb
= cpu_ppc_get_tb(tb_env
, vmclk
, tb_env
->tb_offset
);
563 /* Get the alternate time base */
564 atb
= cpu_ppc_get_tb(tb_env
, vmclk
, tb_env
->atb_offset
);
565 /* Store the time base value (ie compute the current offset) */
566 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->tb_offset
, tb
);
567 /* Store the alternate time base value (compute the current offset) */
568 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->atb_offset
, atb
);
569 /* Set the time base frequency to zero */
571 /* Now, the time bases are frozen to tb_offset / atb_offset value */
575 static void cpu_ppc_tb_start (CPUPPCState
*env
)
577 ppc_tb_t
*tb_env
= env
->tb_env
;
578 uint64_t tb
, atb
, vmclk
;
580 /* If the time base is not frozen, do nothing */
581 if (tb_env
->tb_freq
== 0) {
582 vmclk
= qemu_get_clock_ns(vm_clock
);
583 /* Get the time base from tb_offset */
584 tb
= tb_env
->tb_offset
;
585 /* Get the alternate time base from atb_offset */
586 atb
= tb_env
->atb_offset
;
587 /* Restore the tb frequency from the decrementer frequency */
588 tb_env
->tb_freq
= tb_env
->decr_freq
;
589 /* Store the time base value */
590 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->tb_offset
, tb
);
591 /* Store the alternate time base value */
592 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->atb_offset
, atb
);
596 static inline uint32_t _cpu_ppc_load_decr(CPUPPCState
*env
, uint64_t next
)
598 ppc_tb_t
*tb_env
= env
->tb_env
;
602 diff
= next
- qemu_get_clock_ns(vm_clock
);
604 decr
= muldiv64(diff
, tb_env
->decr_freq
, get_ticks_per_sec());
605 } else if (tb_env
->flags
& PPC_TIMER_BOOKE
) {
608 decr
= -muldiv64(-diff
, tb_env
->decr_freq
, get_ticks_per_sec());
610 LOG_TB("%s: %08" PRIx32
"\n", __func__
, decr
);
615 uint32_t cpu_ppc_load_decr (CPUPPCState
*env
)
617 ppc_tb_t
*tb_env
= env
->tb_env
;
620 return env
->spr
[SPR_DECR
];
623 return _cpu_ppc_load_decr(env
, tb_env
->decr_next
);
626 uint32_t cpu_ppc_load_hdecr (CPUPPCState
*env
)
628 ppc_tb_t
*tb_env
= env
->tb_env
;
630 return _cpu_ppc_load_decr(env
, tb_env
->hdecr_next
);
633 uint64_t cpu_ppc_load_purr (CPUPPCState
*env
)
635 ppc_tb_t
*tb_env
= env
->tb_env
;
638 diff
= qemu_get_clock_ns(vm_clock
) - tb_env
->purr_start
;
640 return tb_env
->purr_load
+ muldiv64(diff
, tb_env
->tb_freq
, get_ticks_per_sec());
643 /* When decrementer expires,
644 * all we need to do is generate or queue a CPU exception
646 static inline void cpu_ppc_decr_excp(CPUPPCState
*env
)
649 LOG_TB("raise decrementer exception\n");
650 ppc_set_irq(env
, PPC_INTERRUPT_DECR
, 1);
653 static inline void cpu_ppc_hdecr_excp(CPUPPCState
*env
)
656 LOG_TB("raise decrementer exception\n");
657 ppc_set_irq(env
, PPC_INTERRUPT_HDECR
, 1);
660 static void __cpu_ppc_store_decr (CPUPPCState
*env
, uint64_t *nextp
,
661 struct QEMUTimer
*timer
,
662 void (*raise_excp
)(CPUPPCState
*),
663 uint32_t decr
, uint32_t value
,
666 ppc_tb_t
*tb_env
= env
->tb_env
;
669 LOG_TB("%s: %08" PRIx32
" => %08" PRIx32
"\n", __func__
,
673 /* KVM handles decrementer exceptions, we don't need our own timer */
677 now
= qemu_get_clock_ns(vm_clock
);
678 next
= now
+ muldiv64(value
, get_ticks_per_sec(), tb_env
->decr_freq
);
680 next
+= *nextp
- now
;
687 qemu_mod_timer(timer
, next
);
689 /* If we set a negative value and the decrementer was positive, raise an
692 if ((tb_env
->flags
& PPC_DECR_UNDERFLOW_TRIGGERED
)
693 && (value
& 0x80000000)
694 && !(decr
& 0x80000000)) {
699 static inline void _cpu_ppc_store_decr(CPUPPCState
*env
, uint32_t decr
,
700 uint32_t value
, int is_excp
)
702 ppc_tb_t
*tb_env
= env
->tb_env
;
704 __cpu_ppc_store_decr(env
, &tb_env
->decr_next
, tb_env
->decr_timer
,
705 &cpu_ppc_decr_excp
, decr
, value
, is_excp
);
708 void cpu_ppc_store_decr (CPUPPCState
*env
, uint32_t value
)
710 _cpu_ppc_store_decr(env
, cpu_ppc_load_decr(env
), value
, 0);
713 static void cpu_ppc_decr_cb (void *opaque
)
715 _cpu_ppc_store_decr(opaque
, 0x00000000, 0xFFFFFFFF, 1);
718 static inline void _cpu_ppc_store_hdecr(CPUPPCState
*env
, uint32_t hdecr
,
719 uint32_t value
, int is_excp
)
721 ppc_tb_t
*tb_env
= env
->tb_env
;
723 if (tb_env
->hdecr_timer
!= NULL
) {
724 __cpu_ppc_store_decr(env
, &tb_env
->hdecr_next
, tb_env
->hdecr_timer
,
725 &cpu_ppc_hdecr_excp
, hdecr
, value
, is_excp
);
729 void cpu_ppc_store_hdecr (CPUPPCState
*env
, uint32_t value
)
731 _cpu_ppc_store_hdecr(env
, cpu_ppc_load_hdecr(env
), value
, 0);
734 static void cpu_ppc_hdecr_cb (void *opaque
)
736 _cpu_ppc_store_hdecr(opaque
, 0x00000000, 0xFFFFFFFF, 1);
739 static void cpu_ppc_store_purr(CPUPPCState
*env
, uint64_t value
)
741 ppc_tb_t
*tb_env
= env
->tb_env
;
743 tb_env
->purr_load
= value
;
744 tb_env
->purr_start
= qemu_get_clock_ns(vm_clock
);
747 static void cpu_ppc_set_tb_clk (void *opaque
, uint32_t freq
)
749 CPUPPCState
*env
= opaque
;
750 ppc_tb_t
*tb_env
= env
->tb_env
;
752 tb_env
->tb_freq
= freq
;
753 tb_env
->decr_freq
= freq
;
754 /* There is a bug in Linux 2.4 kernels:
755 * if a decrementer exception is pending when it enables msr_ee at startup,
756 * it's not ready to handle it...
758 _cpu_ppc_store_decr(env
, 0xFFFFFFFF, 0xFFFFFFFF, 0);
759 _cpu_ppc_store_hdecr(env
, 0xFFFFFFFF, 0xFFFFFFFF, 0);
760 cpu_ppc_store_purr(env
, 0x0000000000000000ULL
);
763 /* Set up (once) timebase frequency (in Hz) */
764 clk_setup_cb
cpu_ppc_tb_init (CPUPPCState
*env
, uint32_t freq
)
768 tb_env
= g_malloc0(sizeof(ppc_tb_t
));
769 env
->tb_env
= tb_env
;
770 tb_env
->flags
= PPC_DECR_UNDERFLOW_TRIGGERED
;
771 /* Create new timer */
772 tb_env
->decr_timer
= qemu_new_timer_ns(vm_clock
, &cpu_ppc_decr_cb
, env
);
774 /* XXX: find a suitable condition to enable the hypervisor decrementer
776 tb_env
->hdecr_timer
= qemu_new_timer_ns(vm_clock
, &cpu_ppc_hdecr_cb
, env
);
778 tb_env
->hdecr_timer
= NULL
;
780 cpu_ppc_set_tb_clk(env
, freq
);
782 return &cpu_ppc_set_tb_clk
;
785 /* Specific helpers for POWER & PowerPC 601 RTC */
787 static clk_setup_cb
cpu_ppc601_rtc_init (CPUPPCState
*env
)
789 return cpu_ppc_tb_init(env
, 7812500);
793 void cpu_ppc601_store_rtcu (CPUPPCState
*env
, uint32_t value
)
795 _cpu_ppc_store_tbu(env
, value
);
798 uint32_t cpu_ppc601_load_rtcu (CPUPPCState
*env
)
800 return _cpu_ppc_load_tbu(env
);
803 void cpu_ppc601_store_rtcl (CPUPPCState
*env
, uint32_t value
)
805 cpu_ppc_store_tbl(env
, value
& 0x3FFFFF80);
808 uint32_t cpu_ppc601_load_rtcl (CPUPPCState
*env
)
810 return cpu_ppc_load_tbl(env
) & 0x3FFFFF80;
813 /*****************************************************************************/
814 /* PowerPC 40x timers */
817 typedef struct ppc40x_timer_t ppc40x_timer_t
;
818 struct ppc40x_timer_t
{
819 uint64_t pit_reload
; /* PIT auto-reload value */
820 uint64_t fit_next
; /* Tick for next FIT interrupt */
821 struct QEMUTimer
*fit_timer
;
822 uint64_t wdt_next
; /* Tick for next WDT interrupt */
823 struct QEMUTimer
*wdt_timer
;
825 /* 405 have the PIT, 440 have a DECR. */
826 unsigned int decr_excp
;
829 /* Fixed interval timer */
830 static void cpu_4xx_fit_cb (void *opaque
)
834 ppc40x_timer_t
*ppc40x_timer
;
838 tb_env
= env
->tb_env
;
839 ppc40x_timer
= tb_env
->opaque
;
840 now
= qemu_get_clock_ns(vm_clock
);
841 switch ((env
->spr
[SPR_40x_TCR
] >> 24) & 0x3) {
855 /* Cannot occur, but makes gcc happy */
858 next
= now
+ muldiv64(next
, get_ticks_per_sec(), tb_env
->tb_freq
);
861 qemu_mod_timer(ppc40x_timer
->fit_timer
, next
);
862 env
->spr
[SPR_40x_TSR
] |= 1 << 26;
863 if ((env
->spr
[SPR_40x_TCR
] >> 23) & 0x1)
864 ppc_set_irq(env
, PPC_INTERRUPT_FIT
, 1);
865 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
"\n", __func__
,
866 (int)((env
->spr
[SPR_40x_TCR
] >> 23) & 0x1),
867 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
]);
870 /* Programmable interval timer */
871 static void start_stop_pit (CPUPPCState
*env
, ppc_tb_t
*tb_env
, int is_excp
)
873 ppc40x_timer_t
*ppc40x_timer
;
876 ppc40x_timer
= tb_env
->opaque
;
877 if (ppc40x_timer
->pit_reload
<= 1 ||
878 !((env
->spr
[SPR_40x_TCR
] >> 26) & 0x1) ||
879 (is_excp
&& !((env
->spr
[SPR_40x_TCR
] >> 22) & 0x1))) {
881 LOG_TB("%s: stop PIT\n", __func__
);
882 qemu_del_timer(tb_env
->decr_timer
);
884 LOG_TB("%s: start PIT %016" PRIx64
"\n",
885 __func__
, ppc40x_timer
->pit_reload
);
886 now
= qemu_get_clock_ns(vm_clock
);
887 next
= now
+ muldiv64(ppc40x_timer
->pit_reload
,
888 get_ticks_per_sec(), tb_env
->decr_freq
);
890 next
+= tb_env
->decr_next
- now
;
893 qemu_mod_timer(tb_env
->decr_timer
, next
);
894 tb_env
->decr_next
= next
;
898 static void cpu_4xx_pit_cb (void *opaque
)
902 ppc40x_timer_t
*ppc40x_timer
;
905 tb_env
= env
->tb_env
;
906 ppc40x_timer
= tb_env
->opaque
;
907 env
->spr
[SPR_40x_TSR
] |= 1 << 27;
908 if ((env
->spr
[SPR_40x_TCR
] >> 26) & 0x1)
909 ppc_set_irq(env
, ppc40x_timer
->decr_excp
, 1);
910 start_stop_pit(env
, tb_env
, 1);
911 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
" "
912 "%016" PRIx64
"\n", __func__
,
913 (int)((env
->spr
[SPR_40x_TCR
] >> 22) & 0x1),
914 (int)((env
->spr
[SPR_40x_TCR
] >> 26) & 0x1),
915 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
],
916 ppc40x_timer
->pit_reload
);
920 static void cpu_4xx_wdt_cb (void *opaque
)
924 ppc40x_timer_t
*ppc40x_timer
;
928 tb_env
= env
->tb_env
;
929 ppc40x_timer
= tb_env
->opaque
;
930 now
= qemu_get_clock_ns(vm_clock
);
931 switch ((env
->spr
[SPR_40x_TCR
] >> 30) & 0x3) {
945 /* Cannot occur, but makes gcc happy */
948 next
= now
+ muldiv64(next
, get_ticks_per_sec(), tb_env
->decr_freq
);
951 LOG_TB("%s: TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
"\n", __func__
,
952 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
]);
953 switch ((env
->spr
[SPR_40x_TSR
] >> 30) & 0x3) {
956 qemu_mod_timer(ppc40x_timer
->wdt_timer
, next
);
957 ppc40x_timer
->wdt_next
= next
;
958 env
->spr
[SPR_40x_TSR
] |= 1 << 31;
961 qemu_mod_timer(ppc40x_timer
->wdt_timer
, next
);
962 ppc40x_timer
->wdt_next
= next
;
963 env
->spr
[SPR_40x_TSR
] |= 1 << 30;
964 if ((env
->spr
[SPR_40x_TCR
] >> 27) & 0x1)
965 ppc_set_irq(env
, PPC_INTERRUPT_WDT
, 1);
968 env
->spr
[SPR_40x_TSR
] &= ~0x30000000;
969 env
->spr
[SPR_40x_TSR
] |= env
->spr
[SPR_40x_TCR
] & 0x30000000;
970 switch ((env
->spr
[SPR_40x_TCR
] >> 28) & 0x3) {
974 case 0x1: /* Core reset */
975 ppc40x_core_reset(env
);
977 case 0x2: /* Chip reset */
978 ppc40x_chip_reset(env
);
980 case 0x3: /* System reset */
981 ppc40x_system_reset(env
);
987 void store_40x_pit (CPUPPCState
*env
, target_ulong val
)
990 ppc40x_timer_t
*ppc40x_timer
;
992 tb_env
= env
->tb_env
;
993 ppc40x_timer
= tb_env
->opaque
;
994 LOG_TB("%s val" TARGET_FMT_lx
"\n", __func__
, val
);
995 ppc40x_timer
->pit_reload
= val
;
996 start_stop_pit(env
, tb_env
, 0);
999 target_ulong
load_40x_pit (CPUPPCState
*env
)
1001 return cpu_ppc_load_decr(env
);
1004 static void ppc_40x_set_tb_clk (void *opaque
, uint32_t freq
)
1006 CPUPPCState
*env
= opaque
;
1007 ppc_tb_t
*tb_env
= env
->tb_env
;
1009 LOG_TB("%s set new frequency to %" PRIu32
"\n", __func__
,
1011 tb_env
->tb_freq
= freq
;
1012 tb_env
->decr_freq
= freq
;
1013 /* XXX: we should also update all timers */
1016 clk_setup_cb
ppc_40x_timers_init (CPUPPCState
*env
, uint32_t freq
,
1017 unsigned int decr_excp
)
1020 ppc40x_timer_t
*ppc40x_timer
;
1022 tb_env
= g_malloc0(sizeof(ppc_tb_t
));
1023 env
->tb_env
= tb_env
;
1024 tb_env
->flags
= PPC_DECR_UNDERFLOW_TRIGGERED
;
1025 ppc40x_timer
= g_malloc0(sizeof(ppc40x_timer_t
));
1026 tb_env
->tb_freq
= freq
;
1027 tb_env
->decr_freq
= freq
;
1028 tb_env
->opaque
= ppc40x_timer
;
1029 LOG_TB("%s freq %" PRIu32
"\n", __func__
, freq
);
1030 if (ppc40x_timer
!= NULL
) {
1031 /* We use decr timer for PIT */
1032 tb_env
->decr_timer
= qemu_new_timer_ns(vm_clock
, &cpu_4xx_pit_cb
, env
);
1033 ppc40x_timer
->fit_timer
=
1034 qemu_new_timer_ns(vm_clock
, &cpu_4xx_fit_cb
, env
);
1035 ppc40x_timer
->wdt_timer
=
1036 qemu_new_timer_ns(vm_clock
, &cpu_4xx_wdt_cb
, env
);
1037 ppc40x_timer
->decr_excp
= decr_excp
;
1040 return &ppc_40x_set_tb_clk
;
1043 /*****************************************************************************/
1044 /* Embedded PowerPC Device Control Registers */
1045 typedef struct ppc_dcrn_t ppc_dcrn_t
;
1047 dcr_read_cb dcr_read
;
1048 dcr_write_cb dcr_write
;
1052 /* XXX: on 460, DCR addresses are 32 bits wide,
1053 * using DCRIPR to get the 22 upper bits of the DCR address
1055 #define DCRN_NB 1024
1057 ppc_dcrn_t dcrn
[DCRN_NB
];
1058 int (*read_error
)(int dcrn
);
1059 int (*write_error
)(int dcrn
);
1062 int ppc_dcr_read (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t *valp
)
1066 if (dcrn
< 0 || dcrn
>= DCRN_NB
)
1068 dcr
= &dcr_env
->dcrn
[dcrn
];
1069 if (dcr
->dcr_read
== NULL
)
1071 *valp
= (*dcr
->dcr_read
)(dcr
->opaque
, dcrn
);
1076 if (dcr_env
->read_error
!= NULL
)
1077 return (*dcr_env
->read_error
)(dcrn
);
1082 int ppc_dcr_write (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t val
)
1086 if (dcrn
< 0 || dcrn
>= DCRN_NB
)
1088 dcr
= &dcr_env
->dcrn
[dcrn
];
1089 if (dcr
->dcr_write
== NULL
)
1091 (*dcr
->dcr_write
)(dcr
->opaque
, dcrn
, val
);
1096 if (dcr_env
->write_error
!= NULL
)
1097 return (*dcr_env
->write_error
)(dcrn
);
1102 int ppc_dcr_register (CPUPPCState
*env
, int dcrn
, void *opaque
,
1103 dcr_read_cb dcr_read
, dcr_write_cb dcr_write
)
1108 dcr_env
= env
->dcr_env
;
1109 if (dcr_env
== NULL
)
1111 if (dcrn
< 0 || dcrn
>= DCRN_NB
)
1113 dcr
= &dcr_env
->dcrn
[dcrn
];
1114 if (dcr
->opaque
!= NULL
||
1115 dcr
->dcr_read
!= NULL
||
1116 dcr
->dcr_write
!= NULL
)
1118 dcr
->opaque
= opaque
;
1119 dcr
->dcr_read
= dcr_read
;
1120 dcr
->dcr_write
= dcr_write
;
1125 int ppc_dcr_init (CPUPPCState
*env
, int (*read_error
)(int dcrn
),
1126 int (*write_error
)(int dcrn
))
1130 dcr_env
= g_malloc0(sizeof(ppc_dcr_t
));
1131 dcr_env
->read_error
= read_error
;
1132 dcr_env
->write_error
= write_error
;
1133 env
->dcr_env
= dcr_env
;
1138 /*****************************************************************************/
1140 void PPC_debug_write (void *opaque
, uint32_t addr
, uint32_t val
)
1152 printf("Set loglevel to %04" PRIx32
"\n", val
);
1153 cpu_set_log(val
| 0x100);
1158 /*****************************************************************************/
1160 static inline uint32_t nvram_read (nvram_t
*nvram
, uint32_t addr
)
1162 return (*nvram
->read_fn
)(nvram
->opaque
, addr
);
1165 static inline void nvram_write (nvram_t
*nvram
, uint32_t addr
, uint32_t val
)
1167 (*nvram
->write_fn
)(nvram
->opaque
, addr
, val
);
1170 static void NVRAM_set_byte(nvram_t
*nvram
, uint32_t addr
, uint8_t value
)
1172 nvram_write(nvram
, addr
, value
);
1175 static uint8_t NVRAM_get_byte(nvram_t
*nvram
, uint32_t addr
)
1177 return nvram_read(nvram
, addr
);
1180 static void NVRAM_set_word(nvram_t
*nvram
, uint32_t addr
, uint16_t value
)
1182 nvram_write(nvram
, addr
, value
>> 8);
1183 nvram_write(nvram
, addr
+ 1, value
& 0xFF);
1186 static uint16_t NVRAM_get_word(nvram_t
*nvram
, uint32_t addr
)
1190 tmp
= nvram_read(nvram
, addr
) << 8;
1191 tmp
|= nvram_read(nvram
, addr
+ 1);
1196 static void NVRAM_set_lword(nvram_t
*nvram
, uint32_t addr
, uint32_t value
)
1198 nvram_write(nvram
, addr
, value
>> 24);
1199 nvram_write(nvram
, addr
+ 1, (value
>> 16) & 0xFF);
1200 nvram_write(nvram
, addr
+ 2, (value
>> 8) & 0xFF);
1201 nvram_write(nvram
, addr
+ 3, value
& 0xFF);
1204 uint32_t NVRAM_get_lword (nvram_t
*nvram
, uint32_t addr
)
1208 tmp
= nvram_read(nvram
, addr
) << 24;
1209 tmp
|= nvram_read(nvram
, addr
+ 1) << 16;
1210 tmp
|= nvram_read(nvram
, addr
+ 2) << 8;
1211 tmp
|= nvram_read(nvram
, addr
+ 3);
1216 static void NVRAM_set_string(nvram_t
*nvram
, uint32_t addr
, const char *str
,
1221 for (i
= 0; i
< max
&& str
[i
] != '\0'; i
++) {
1222 nvram_write(nvram
, addr
+ i
, str
[i
]);
1224 nvram_write(nvram
, addr
+ i
, str
[i
]);
1225 nvram_write(nvram
, addr
+ max
- 1, '\0');
1228 int NVRAM_get_string (nvram_t
*nvram
, uint8_t *dst
, uint16_t addr
, int max
)
1232 memset(dst
, 0, max
);
1233 for (i
= 0; i
< max
; i
++) {
1234 dst
[i
] = NVRAM_get_byte(nvram
, addr
+ i
);
1242 static uint16_t NVRAM_crc_update (uint16_t prev
, uint16_t value
)
1245 uint16_t pd
, pd1
, pd2
;
1250 pd2
= ((pd
>> 4) & 0x000F) ^ pd1
;
1251 tmp
^= (pd1
<< 3) | (pd1
<< 8);
1252 tmp
^= pd2
| (pd2
<< 7) | (pd2
<< 12);
1257 static uint16_t NVRAM_compute_crc (nvram_t
*nvram
, uint32_t start
, uint32_t count
)
1260 uint16_t crc
= 0xFFFF;
1265 for (i
= 0; i
!= count
; i
++) {
1266 crc
= NVRAM_crc_update(crc
, NVRAM_get_word(nvram
, start
+ i
));
1269 crc
= NVRAM_crc_update(crc
, NVRAM_get_byte(nvram
, start
+ i
) << 8);
1275 #define CMDLINE_ADDR 0x017ff000
1277 int PPC_NVRAM_set_params (nvram_t
*nvram
, uint16_t NVRAM_size
,
1279 uint32_t RAM_size
, int boot_device
,
1280 uint32_t kernel_image
, uint32_t kernel_size
,
1281 const char *cmdline
,
1282 uint32_t initrd_image
, uint32_t initrd_size
,
1283 uint32_t NVRAM_image
,
1284 int width
, int height
, int depth
)
1288 /* Set parameters for Open Hack'Ware BIOS */
1289 NVRAM_set_string(nvram
, 0x00, "QEMU_BIOS", 16);
1290 NVRAM_set_lword(nvram
, 0x10, 0x00000002); /* structure v2 */
1291 NVRAM_set_word(nvram
, 0x14, NVRAM_size
);
1292 NVRAM_set_string(nvram
, 0x20, arch
, 16);
1293 NVRAM_set_lword(nvram
, 0x30, RAM_size
);
1294 NVRAM_set_byte(nvram
, 0x34, boot_device
);
1295 NVRAM_set_lword(nvram
, 0x38, kernel_image
);
1296 NVRAM_set_lword(nvram
, 0x3C, kernel_size
);
1298 /* XXX: put the cmdline in NVRAM too ? */
1299 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, RAM_size
- CMDLINE_ADDR
, cmdline
);
1300 NVRAM_set_lword(nvram
, 0x40, CMDLINE_ADDR
);
1301 NVRAM_set_lword(nvram
, 0x44, strlen(cmdline
));
1303 NVRAM_set_lword(nvram
, 0x40, 0);
1304 NVRAM_set_lword(nvram
, 0x44, 0);
1306 NVRAM_set_lword(nvram
, 0x48, initrd_image
);
1307 NVRAM_set_lword(nvram
, 0x4C, initrd_size
);
1308 NVRAM_set_lword(nvram
, 0x50, NVRAM_image
);
1310 NVRAM_set_word(nvram
, 0x54, width
);
1311 NVRAM_set_word(nvram
, 0x56, height
);
1312 NVRAM_set_word(nvram
, 0x58, depth
);
1313 crc
= NVRAM_compute_crc(nvram
, 0x00, 0xF8);
1314 NVRAM_set_word(nvram
, 0xFC, crc
);