hw/arm/smmuv3.c

   1 /*
   2  * Copyright (C) 2014-2016 Broadcom Corporation
   3  * Copyright (c) 2017 Red Hat, Inc.
   4  * Written by Prem Mallappa, Eric Auger
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "hw/boards.h"
  21 #include "sysemu/sysemu.h"
  22 #include "hw/sysbus.h"
  23 #include "hw/qdev-core.h"
  24 #include "hw/pci/pci.h"
  25 #include "exec/address-spaces.h"
  26 #include "trace.h"
  27 #include "qemu/log.h"
  28 #include "qemu/error-report.h"
  29 #include "qapi/error.h"
  30
  31 #include "hw/arm/smmuv3.h"
  32 #include "smmuv3-internal.h"
  33
  34 /**
  35  * smmuv3_trigger_irq - pulse @irq if enabled and update
  36  * GERROR register in case of GERROR interrupt
  37  *
  38  * @irq: irq type
  39  * @gerror_mask: mask of gerrors to toggle (relevant if @irq is GERROR)
  40  */
  41 void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask)
  42 {
  43
  44     bool pulse = false;
  45
  46     switch (irq) {
  47     case SMMU_IRQ_EVTQ:
  48         pulse = smmuv3_eventq_irq_enabled(s);
  49         break;
  50     case SMMU_IRQ_PRIQ:
  51         qemu_log_mask(LOG_UNIMP, "PRI not yet supported\n");
  52         break;
  53     case SMMU_IRQ_CMD_SYNC:
  54         pulse = true;
  55         break;
  56     case SMMU_IRQ_GERROR:
  57     {
  58         uint32_t pending = s->gerror ^ s->gerrorn;
  59         uint32_t new_gerrors = ~pending & gerror_mask;
  60
  61         if (!new_gerrors) {
  62             /* only toggle non pending errors */
  63             return;
  64         }
  65         s->gerror ^= new_gerrors;
  66         trace_smmuv3_write_gerror(new_gerrors, s->gerror);
  67
  68         pulse = smmuv3_gerror_irq_enabled(s);
  69         break;
  70     }
  71     }
  72     if (pulse) {
  73             trace_smmuv3_trigger_irq(irq);
  74             qemu_irq_pulse(s->irq[irq]);
  75     }
  76 }
  77
  78 void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
  79 {
  80     uint32_t pending = s->gerror ^ s->gerrorn;
  81     uint32_t toggled = s->gerrorn ^ new_gerrorn;
  82
  83     if (toggled & ~pending) {
  84         qemu_log_mask(LOG_GUEST_ERROR,
  85                       "guest toggles non pending errors = 0x%x\n",
  86                       toggled & ~pending);
  87     }
  88
  89     /*
  90      * We do not raise any error in case guest toggles bits corresponding
  91      * to not active IRQs (CONSTRAINED UNPREDICTABLE)
  92      */
  93     s->gerrorn = new_gerrorn;
  94
  95     trace_smmuv3_write_gerrorn(toggled & pending, s->gerrorn);
  96 }
  97
  98 static void smmuv3_init_regs(SMMUv3State *s)
  99 {
 100     /**
 101      * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID,
 102      *       multi-level stream table
 103      */
 104     s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1); /* stage 1 supported */
 105     s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only */
 106     s->idr[0] = FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */
 107     s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */
 108     s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endian */
 109     s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall */
 110     /* terminated transaction will always be aborted/error returned */
 111     s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TERM_MODEL, 1);
 112     /* 2-level stream table supported */
 113     s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STLEVEL, 1);
 114
 115     s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SIDSIZE, SMMU_IDR1_SIDSIZE);
 116     s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS);
 117     s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS,   SMMU_CMDQS);
 118
 119    /* 4K and 64K granule support */
 120     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
 121     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
 122     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
 123
 124     s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS);
 125     s->cmdq.prod = 0;
 126     s->cmdq.cons = 0;
 127     s->cmdq.entry_size = sizeof(struct Cmd);
 128     s->eventq.base = deposit64(s->eventq.base, 0, 5, SMMU_EVENTQS);
 129     s->eventq.prod = 0;
 130     s->eventq.cons = 0;
 131     s->eventq.entry_size = sizeof(struct Evt);
 132
 133     s->features = 0;
 134     s->sid_split = 0;
 135 }
 136
 137 static MemTxResult smmu_write_mmio(void *opaque, hwaddr offset, uint64_t data,
 138                                    unsigned size, MemTxAttrs attrs)
 139 {
 140     /* not yet implemented */
 141     return MEMTX_ERROR;
 142 }
 143
 144 static MemTxResult smmu_readll(SMMUv3State *s, hwaddr offset,
 145                                uint64_t *data, MemTxAttrs attrs)
 146 {
 147     switch (offset) {
 148     case A_GERROR_IRQ_CFG0:
 149         *data = s->gerror_irq_cfg0;
 150         return MEMTX_OK;
 151     case A_STRTAB_BASE:
 152         *data = s->strtab_base;
 153         return MEMTX_OK;
 154     case A_CMDQ_BASE:
 155         *data = s->cmdq.base;
 156         return MEMTX_OK;
 157     case A_EVENTQ_BASE:
 158         *data = s->eventq.base;
 159         return MEMTX_OK;
 160     default:
 161         *data = 0;
 162         qemu_log_mask(LOG_UNIMP,
 163                       "%s Unexpected 64-bit access to 0x%"PRIx64" (RAZ)\n",
 164                       __func__, offset);
 165         return MEMTX_OK;
 166     }
 167 }
 168
 169 static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
 170                               uint64_t *data, MemTxAttrs attrs)
 171 {
 172     switch (offset) {
 173     case A_IDREGS ... A_IDREGS + 0x1f:
 174         *data = smmuv3_idreg(offset - A_IDREGS);
 175         return MEMTX_OK;
 176     case A_IDR0 ... A_IDR5:
 177         *data = s->idr[(offset - A_IDR0) / 4];
 178         return MEMTX_OK;
 179     case A_IIDR:
 180         *data = s->iidr;
 181         return MEMTX_OK;
 182     case A_CR0:
 183         *data = s->cr[0];
 184         return MEMTX_OK;
 185     case A_CR0ACK:
 186         *data = s->cr0ack;
 187         return MEMTX_OK;
 188     case A_CR1:
 189         *data = s->cr[1];
 190         return MEMTX_OK;
 191     case A_CR2:
 192         *data = s->cr[2];
 193         return MEMTX_OK;
 194     case A_STATUSR:
 195         *data = s->statusr;
 196         return MEMTX_OK;
 197     case A_IRQ_CTRL:
 198     case A_IRQ_CTRL_ACK:
 199         *data = s->irq_ctrl;
 200         return MEMTX_OK;
 201     case A_GERROR:
 202         *data = s->gerror;
 203         return MEMTX_OK;
 204     case A_GERRORN:
 205         *data = s->gerrorn;
 206         return MEMTX_OK;
 207     case A_GERROR_IRQ_CFG0: /* 64b */
 208         *data = extract64(s->gerror_irq_cfg0, 0, 32);
 209         return MEMTX_OK;
 210     case A_GERROR_IRQ_CFG0 + 4:
 211         *data = extract64(s->gerror_irq_cfg0, 32, 32);
 212         return MEMTX_OK;
 213     case A_GERROR_IRQ_CFG1:
 214         *data = s->gerror_irq_cfg1;
 215         return MEMTX_OK;
 216     case A_GERROR_IRQ_CFG2:
 217         *data = s->gerror_irq_cfg2;
 218         return MEMTX_OK;
 219     case A_STRTAB_BASE: /* 64b */
 220         *data = extract64(s->strtab_base, 0, 32);
 221         return MEMTX_OK;
 222     case A_STRTAB_BASE + 4: /* 64b */
 223         *data = extract64(s->strtab_base, 32, 32);
 224         return MEMTX_OK;
 225     case A_STRTAB_BASE_CFG:
 226         *data = s->strtab_base_cfg;
 227         return MEMTX_OK;
 228     case A_CMDQ_BASE: /* 64b */
 229         *data = extract64(s->cmdq.base, 0, 32);
 230         return MEMTX_OK;
 231     case A_CMDQ_BASE + 4:
 232         *data = extract64(s->cmdq.base, 32, 32);
 233         return MEMTX_OK;
 234     case A_CMDQ_PROD:
 235         *data = s->cmdq.prod;
 236         return MEMTX_OK;
 237     case A_CMDQ_CONS:
 238         *data = s->cmdq.cons;
 239         return MEMTX_OK;
 240     case A_EVENTQ_BASE: /* 64b */
 241         *data = extract64(s->eventq.base, 0, 32);
 242         return MEMTX_OK;
 243     case A_EVENTQ_BASE + 4: /* 64b */
 244         *data = extract64(s->eventq.base, 32, 32);
 245         return MEMTX_OK;
 246     case A_EVENTQ_PROD:
 247         *data = s->eventq.prod;
 248         return MEMTX_OK;
 249     case A_EVENTQ_CONS:
 250         *data = s->eventq.cons;
 251         return MEMTX_OK;
 252     default:
 253         *data = 0;
 254         qemu_log_mask(LOG_UNIMP,
 255                       "%s unhandled 32-bit access at 0x%"PRIx64" (RAZ)\n",
 256                       __func__, offset);
 257         return MEMTX_OK;
 258     }
 259 }
 260
 261 static MemTxResult smmu_read_mmio(void *opaque, hwaddr offset, uint64_t *data,
 262                                   unsigned size, MemTxAttrs attrs)
 263 {
 264     SMMUState *sys = opaque;
 265     SMMUv3State *s = ARM_SMMUV3(sys);
 266     MemTxResult r;
 267
 268     /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
 269     offset &= ~0x10000;
 270
 271     switch (size) {
 272     case 8:
 273         r = smmu_readll(s, offset, data, attrs);
 274         break;
 275     case 4:
 276         r = smmu_readl(s, offset, data, attrs);
 277         break;
 278     default:
 279         r = MEMTX_ERROR;
 280         break;
 281     }
 282
 283     trace_smmuv3_read_mmio(offset, *data, size, r);
 284     return r;
 285 }
 286
 287 static const MemoryRegionOps smmu_mem_ops = {
 288     .read_with_attrs = smmu_read_mmio,
 289     .write_with_attrs = smmu_write_mmio,
 290     .endianness = DEVICE_LITTLE_ENDIAN,
 291     .valid = {
 292         .min_access_size = 4,
 293         .max_access_size = 8,
 294     },
 295     .impl = {
 296         .min_access_size = 4,
 297         .max_access_size = 8,
 298     },
 299 };
 300
 301 static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev)
 302 {
 303     int i;
 304
 305     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
 306         sysbus_init_irq(dev, &s->irq[i]);
 307     }
 308 }
 309
 310 static void smmu_reset(DeviceState *dev)
 311 {
 312     SMMUv3State *s = ARM_SMMUV3(dev);
 313     SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
 314
 315     c->parent_reset(dev);
 316
 317     smmuv3_init_regs(s);
 318 }
 319
 320 static void smmu_realize(DeviceState *d, Error **errp)
 321 {
 322     SMMUState *sys = ARM_SMMU(d);
 323     SMMUv3State *s = ARM_SMMUV3(sys);
 324     SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
 325     SysBusDevice *dev = SYS_BUS_DEVICE(d);
 326     Error *local_err = NULL;
 327
 328     c->parent_realize(d, &local_err);
 329     if (local_err) {
 330         error_propagate(errp, local_err);
 331         return;
 332     }
 333
 334     memory_region_init_io(&sys->iomem, OBJECT(s),
 335                           &smmu_mem_ops, sys, TYPE_ARM_SMMUV3, 0x20000);
 336
 337     sys->mrtypename = TYPE_SMMUV3_IOMMU_MEMORY_REGION;
 338
 339     sysbus_init_mmio(dev, &sys->iomem);
 340
 341     smmu_init_irq(s, dev);
 342 }
 343
 344 static const VMStateDescription vmstate_smmuv3_queue = {
 345     .name = "smmuv3_queue",
 346     .version_id = 1,
 347     .minimum_version_id = 1,
 348     .fields = (VMStateField[]) {
 349         VMSTATE_UINT64(base, SMMUQueue),
 350         VMSTATE_UINT32(prod, SMMUQueue),
 351         VMSTATE_UINT32(cons, SMMUQueue),
 352         VMSTATE_UINT8(log2size, SMMUQueue),
 353     },
 354 };
 355
 356 static const VMStateDescription vmstate_smmuv3 = {
 357     .name = "smmuv3",
 358     .version_id = 1,
 359     .minimum_version_id = 1,
 360     .fields = (VMStateField[]) {
 361         VMSTATE_UINT32(features, SMMUv3State),
 362         VMSTATE_UINT8(sid_size, SMMUv3State),
 363         VMSTATE_UINT8(sid_split, SMMUv3State),
 364
 365         VMSTATE_UINT32_ARRAY(cr, SMMUv3State, 3),
 366         VMSTATE_UINT32(cr0ack, SMMUv3State),
 367         VMSTATE_UINT32(statusr, SMMUv3State),
 368         VMSTATE_UINT32(irq_ctrl, SMMUv3State),
 369         VMSTATE_UINT32(gerror, SMMUv3State),
 370         VMSTATE_UINT32(gerrorn, SMMUv3State),
 371         VMSTATE_UINT64(gerror_irq_cfg0, SMMUv3State),
 372         VMSTATE_UINT32(gerror_irq_cfg1, SMMUv3State),
 373         VMSTATE_UINT32(gerror_irq_cfg2, SMMUv3State),
 374         VMSTATE_UINT64(strtab_base, SMMUv3State),
 375         VMSTATE_UINT32(strtab_base_cfg, SMMUv3State),
 376         VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State),
 377         VMSTATE_UINT32(eventq_irq_cfg1, SMMUv3State),
 378         VMSTATE_UINT32(eventq_irq_cfg2, SMMUv3State),
 379
 380         VMSTATE_STRUCT(cmdq, SMMUv3State, 0, vmstate_smmuv3_queue, SMMUQueue),
 381         VMSTATE_STRUCT(eventq, SMMUv3State, 0, vmstate_smmuv3_queue, SMMUQueue),
 382
 383         VMSTATE_END_OF_LIST(),
 384     },
 385 };
 386
 387 static void smmuv3_instance_init(Object *obj)
 388 {
 389     /* Nothing much to do here as of now */
 390 }
 391
 392 static void smmuv3_class_init(ObjectClass *klass, void *data)
 393 {
 394     DeviceClass *dc = DEVICE_CLASS(klass);
 395     SMMUv3Class *c = ARM_SMMUV3_CLASS(klass);
 396
 397     dc->vmsd = &vmstate_smmuv3;
 398     device_class_set_parent_reset(dc, smmu_reset, &c->parent_reset);
 399     c->parent_realize = dc->realize;
 400     dc->realize = smmu_realize;
 401 }
 402
 403 static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass,
 404                                                   void *data)
 405 {
 406 }
 407
 408 static const TypeInfo smmuv3_type_info = {
 409     .name          = TYPE_ARM_SMMUV3,
 410     .parent        = TYPE_ARM_SMMU,
 411     .instance_size = sizeof(SMMUv3State),
 412     .instance_init = smmuv3_instance_init,
 413     .class_size    = sizeof(SMMUv3Class),
 414     .class_init    = smmuv3_class_init,
 415 };
 416
 417 static const TypeInfo smmuv3_iommu_memory_region_info = {
 418     .parent = TYPE_IOMMU_MEMORY_REGION,
 419     .name = TYPE_SMMUV3_IOMMU_MEMORY_REGION,
 420     .class_init = smmuv3_iommu_memory_region_class_init,
 421 };
 422
 423 static void smmuv3_register_types(void)
 424 {
 425     type_register(&smmuv3_type_info);
 426     type_register(&smmuv3_iommu_memory_region_info);
 427 }
 428
 429 type_init(smmuv3_register_types)
 430