4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
22 #include "internals.h"
23 #include "qemu-common.h"
24 #include "hw/qdev-properties.h"
25 #if !defined(CONFIG_USER_ONLY)
26 #include "hw/loader.h"
28 #include "hw/arm/arm.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/kvm.h"
33 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
35 ARMCPU
*cpu
= ARM_CPU(cs
);
37 cpu
->env
.regs
[15] = value
;
40 static bool arm_cpu_has_work(CPUState
*cs
)
42 ARMCPU
*cpu
= ARM_CPU(cs
);
44 return !cpu
->powered_off
45 && cs
->interrupt_request
&
46 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
47 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
48 | CPU_INTERRUPT_EXITTB
);
51 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
53 /* Reset a single ARMCPRegInfo register */
54 ARMCPRegInfo
*ri
= value
;
57 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
62 ri
->resetfn(&cpu
->env
, ri
);
66 /* A zero offset is never possible as it would be regs[0]
67 * so we use it to indicate that reset is being handled elsewhere.
68 * This is basically only used for fields in non-core coprocessors
69 * (like the pxa2xx ones).
71 if (!ri
->fieldoffset
) {
75 if (cpreg_field_is_64bit(ri
)) {
76 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
78 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
82 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
84 /* Purely an assertion check: we've already done reset once,
85 * so now check that running the reset for the cpreg doesn't
86 * change its value. This traps bugs where two different cpregs
87 * both try to reset the same state field but to different values.
89 ARMCPRegInfo
*ri
= value
;
91 uint64_t oldvalue
, newvalue
;
93 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
97 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
98 cp_reg_reset(key
, value
, opaque
);
99 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
100 assert(oldvalue
== newvalue
);
103 /* CPUClass::reset() */
104 static void arm_cpu_reset(CPUState
*s
)
106 ARMCPU
*cpu
= ARM_CPU(s
);
107 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
108 CPUARMState
*env
= &cpu
->env
;
110 acc
->parent_reset(s
);
112 memset(env
, 0, offsetof(CPUARMState
, features
));
113 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
114 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
116 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
117 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
118 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
119 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->mvfr2
;
121 cpu
->powered_off
= cpu
->start_powered_off
;
122 s
->halted
= cpu
->start_powered_off
;
124 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
125 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
128 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
129 /* 64 bit CPUs always start in 64 bit mode */
131 #if defined(CONFIG_USER_ONLY)
132 env
->pstate
= PSTATE_MODE_EL0t
;
133 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
134 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
135 /* and to the FP/Neon instructions */
136 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
138 /* Reset into the highest available EL */
139 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
140 env
->pstate
= PSTATE_MODE_EL3h
;
141 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
142 env
->pstate
= PSTATE_MODE_EL2h
;
144 env
->pstate
= PSTATE_MODE_EL1h
;
146 env
->pc
= cpu
->rvbar
;
149 #if defined(CONFIG_USER_ONLY)
150 /* Userspace expects access to cp10 and cp11 for FP/Neon */
151 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
155 #if defined(CONFIG_USER_ONLY)
156 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
157 /* For user mode we must enable access to coprocessors */
158 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
159 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
160 env
->cp15
.c15_cpar
= 3;
161 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
162 env
->cp15
.c15_cpar
= 1;
165 /* SVC mode with interrupts disabled. */
166 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
167 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
168 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
169 * clear at reset. Initial SP and PC are loaded from ROM.
172 uint32_t initial_msp
; /* Loaded from 0x0 */
173 uint32_t initial_pc
; /* Loaded from 0x4 */
176 env
->daif
&= ~PSTATE_I
;
179 /* Address zero is covered by ROM which hasn't yet been
180 * copied into physical memory.
182 initial_msp
= ldl_p(rom
);
183 initial_pc
= ldl_p(rom
+ 4);
185 /* Address zero not covered by a ROM blob, or the ROM blob
186 * is in non-modifiable memory and this is a second reset after
187 * it got copied into memory. In the latter case, rom_ptr
188 * will return a NULL pointer and we should use ldl_phys instead.
190 initial_msp
= ldl_phys(s
->as
, 0);
191 initial_pc
= ldl_phys(s
->as
, 4);
194 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
195 env
->regs
[15] = initial_pc
& ~1;
196 env
->thumb
= initial_pc
& 1;
199 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
200 * executing as AArch32 then check if highvecs are enabled and
201 * adjust the PC accordingly.
203 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
204 env
->regs
[15] = 0xFFFF0000;
207 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
209 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
210 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
211 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
212 set_float_detect_tininess(float_tininess_before_rounding
,
213 &env
->vfp
.fp_status
);
214 set_float_detect_tininess(float_tininess_before_rounding
,
215 &env
->vfp
.standard_fp_status
);
218 #ifndef CONFIG_USER_ONLY
220 kvm_arm_reset_vcpu(cpu
);
224 hw_breakpoint_update_all(cpu
);
225 hw_watchpoint_update_all(cpu
);
228 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
230 CPUClass
*cc
= CPU_GET_CLASS(cs
);
231 CPUARMState
*env
= cs
->env_ptr
;
232 uint32_t cur_el
= arm_current_el(env
);
233 bool secure
= arm_is_secure(env
);
238 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
240 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
241 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
242 cs
->exception_index
= excp_idx
;
243 env
->exception
.target_el
= target_el
;
244 cc
->do_interrupt(cs
);
248 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
250 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
251 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
252 cs
->exception_index
= excp_idx
;
253 env
->exception
.target_el
= target_el
;
254 cc
->do_interrupt(cs
);
258 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
259 excp_idx
= EXCP_VIRQ
;
261 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
262 cs
->exception_index
= excp_idx
;
263 env
->exception
.target_el
= target_el
;
264 cc
->do_interrupt(cs
);
268 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
269 excp_idx
= EXCP_VFIQ
;
271 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
272 cs
->exception_index
= excp_idx
;
273 env
->exception
.target_el
= target_el
;
274 cc
->do_interrupt(cs
);
282 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
283 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
285 CPUClass
*cc
= CPU_GET_CLASS(cs
);
286 ARMCPU
*cpu
= ARM_CPU(cs
);
287 CPUARMState
*env
= &cpu
->env
;
291 if (interrupt_request
& CPU_INTERRUPT_FIQ
292 && !(env
->daif
& PSTATE_F
)) {
293 cs
->exception_index
= EXCP_FIQ
;
294 cc
->do_interrupt(cs
);
297 /* ARMv7-M interrupt return works by loading a magic value
298 * into the PC. On real hardware the load causes the
299 * return to occur. The qemu implementation performs the
300 * jump normally, then does the exception return when the
301 * CPU tries to execute code at the magic address.
302 * This will cause the magic PC value to be pushed to
303 * the stack if an interrupt occurred at the wrong time.
304 * We avoid this by disabling interrupts when
305 * pc contains a magic address.
307 if (interrupt_request
& CPU_INTERRUPT_HARD
308 && !(env
->daif
& PSTATE_I
)
309 && (env
->regs
[15] < 0xfffffff0)) {
310 cs
->exception_index
= EXCP_IRQ
;
311 cc
->do_interrupt(cs
);
318 #ifndef CONFIG_USER_ONLY
319 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
321 ARMCPU
*cpu
= opaque
;
322 CPUARMState
*env
= &cpu
->env
;
323 CPUState
*cs
= CPU(cpu
);
324 static const int mask
[] = {
325 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
326 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
327 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
328 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
334 assert(arm_feature(env
, ARM_FEATURE_EL2
));
339 cpu_interrupt(cs
, mask
[irq
]);
341 cpu_reset_interrupt(cs
, mask
[irq
]);
345 g_assert_not_reached();
349 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
352 ARMCPU
*cpu
= opaque
;
353 CPUState
*cs
= CPU(cpu
);
354 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
358 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
361 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
364 g_assert_not_reached();
366 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
367 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
371 static bool arm_cpu_is_big_endian(CPUState
*cs
)
373 ARMCPU
*cpu
= ARM_CPU(cs
);
374 CPUARMState
*env
= &cpu
->env
;
377 cpu_synchronize_state(cs
);
379 /* In 32bit guest endianness is determined by looking at CPSR's E bit */
381 return (env
->uncached_cpsr
& CPSR_E
) ? 1 : 0;
384 cur_el
= arm_current_el(env
);
387 return (env
->cp15
.sctlr_el
[1] & SCTLR_E0E
) != 0;
390 return (env
->cp15
.sctlr_el
[cur_el
] & SCTLR_EE
) != 0;
395 static inline void set_feature(CPUARMState
*env
, int feature
)
397 env
->features
|= 1ULL << feature
;
400 static inline void unset_feature(CPUARMState
*env
, int feature
)
402 env
->features
&= ~(1ULL << feature
);
406 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
408 return print_insn_arm(pc
| 1, info
);
411 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
413 ARMCPU
*ac
= ARM_CPU(cpu
);
414 CPUARMState
*env
= &ac
->env
;
417 /* We might not be compiled with the A64 disassembler
418 * because it needs a C++ compiler. Leave print_insn
419 * unset in this case to use the caller default behaviour.
421 #if defined(CONFIG_ARM_A64_DIS)
422 info
->print_insn
= print_insn_arm_a64
;
424 } else if (env
->thumb
) {
425 info
->print_insn
= print_insn_thumb1
;
427 info
->print_insn
= print_insn_arm
;
429 if (env
->bswap_code
) {
430 #ifdef TARGET_WORDS_BIGENDIAN
431 info
->endian
= BFD_ENDIAN_LITTLE
;
433 info
->endian
= BFD_ENDIAN_BIG
;
438 #define ARM_CPUS_PER_CLUSTER 8
440 static void arm_cpu_initfn(Object
*obj
)
442 CPUState
*cs
= CPU(obj
);
443 ARMCPU
*cpu
= ARM_CPU(obj
);
447 cs
->env_ptr
= &cpu
->env
;
448 cpu_exec_init(cs
, &error_abort
);
449 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
452 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
453 * We don't support setting cluster ID ([16..23]) (known as Aff2
454 * in later ARM ARM versions), or any of the higher affinity level fields,
455 * so these bits always RAZ.
457 Aff1
= cs
->cpu_index
/ ARM_CPUS_PER_CLUSTER
;
458 Aff0
= cs
->cpu_index
% ARM_CPUS_PER_CLUSTER
;
459 cpu
->mp_affinity
= (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
461 #ifndef CONFIG_USER_ONLY
462 /* Our inbound IRQ and FIQ lines */
464 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
465 * the same interface as non-KVM CPUs.
467 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
469 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
472 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
473 arm_gt_ptimer_cb
, cpu
);
474 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
475 arm_gt_vtimer_cb
, cpu
);
476 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
477 arm_gt_htimer_cb
, cpu
);
478 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
479 arm_gt_stimer_cb
, cpu
);
480 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
481 ARRAY_SIZE(cpu
->gt_timer_outputs
));
484 /* DTB consumers generally don't in fact care what the 'compatible'
485 * string is, so always provide some string and trust that a hypothetical
486 * picky DTB consumer will also provide a helpful error message.
488 cpu
->dtb_compatible
= "qemu,unknown";
489 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
490 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
493 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
496 arm_translate_init();
501 static Property arm_cpu_reset_cbar_property
=
502 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
504 static Property arm_cpu_reset_hivecs_property
=
505 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
507 static Property arm_cpu_rvbar_property
=
508 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
510 static Property arm_cpu_has_el3_property
=
511 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
513 static Property arm_cpu_has_mpu_property
=
514 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
516 static Property arm_cpu_pmsav7_dregion_property
=
517 DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU
, pmsav7_dregion
, 16);
519 static void arm_cpu_post_init(Object
*obj
)
521 ARMCPU
*cpu
= ARM_CPU(obj
);
523 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
524 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
525 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
529 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
530 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
534 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
535 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
539 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
540 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
541 * prevent "has_el3" from existing on CPUs which cannot support EL3.
543 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
547 if (arm_feature(&cpu
->env
, ARM_FEATURE_MPU
)) {
548 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
550 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
551 qdev_property_add_static(DEVICE(obj
),
552 &arm_cpu_pmsav7_dregion_property
,
559 static void arm_cpu_finalizefn(Object
*obj
)
561 ARMCPU
*cpu
= ARM_CPU(obj
);
562 g_hash_table_destroy(cpu
->cp_regs
);
565 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
567 CPUState
*cs
= CPU(dev
);
568 ARMCPU
*cpu
= ARM_CPU(dev
);
569 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
570 CPUARMState
*env
= &cpu
->env
;
572 /* Some features automatically imply others: */
573 if (arm_feature(env
, ARM_FEATURE_V8
)) {
574 set_feature(env
, ARM_FEATURE_V7
);
575 set_feature(env
, ARM_FEATURE_ARM_DIV
);
576 set_feature(env
, ARM_FEATURE_LPAE
);
578 if (arm_feature(env
, ARM_FEATURE_V7
)) {
579 set_feature(env
, ARM_FEATURE_VAPA
);
580 set_feature(env
, ARM_FEATURE_THUMB2
);
581 set_feature(env
, ARM_FEATURE_MPIDR
);
582 if (!arm_feature(env
, ARM_FEATURE_M
)) {
583 set_feature(env
, ARM_FEATURE_V6K
);
585 set_feature(env
, ARM_FEATURE_V6
);
588 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
589 set_feature(env
, ARM_FEATURE_V6
);
590 set_feature(env
, ARM_FEATURE_MVFR
);
592 if (arm_feature(env
, ARM_FEATURE_V6
)) {
593 set_feature(env
, ARM_FEATURE_V5
);
594 if (!arm_feature(env
, ARM_FEATURE_M
)) {
595 set_feature(env
, ARM_FEATURE_AUXCR
);
598 if (arm_feature(env
, ARM_FEATURE_V5
)) {
599 set_feature(env
, ARM_FEATURE_V4T
);
601 if (arm_feature(env
, ARM_FEATURE_M
)) {
602 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
604 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
605 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
607 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
608 set_feature(env
, ARM_FEATURE_VFP3
);
609 set_feature(env
, ARM_FEATURE_VFP_FP16
);
611 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
612 set_feature(env
, ARM_FEATURE_VFP
);
614 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
615 set_feature(env
, ARM_FEATURE_V7MP
);
616 set_feature(env
, ARM_FEATURE_PXN
);
618 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
619 set_feature(env
, ARM_FEATURE_CBAR
);
621 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
622 !arm_feature(env
, ARM_FEATURE_M
)) {
623 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
626 if (cpu
->reset_hivecs
) {
627 cpu
->reset_sctlr
|= (1 << 13);
631 /* If the has_el3 CPU property is disabled then we need to disable the
634 unset_feature(env
, ARM_FEATURE_EL3
);
636 /* Disable the security extension feature bits in the processor feature
637 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
639 cpu
->id_pfr1
&= ~0xf0;
640 cpu
->id_aa64pfr0
&= ~0xf000;
644 unset_feature(env
, ARM_FEATURE_MPU
);
647 if (arm_feature(env
, ARM_FEATURE_MPU
) &&
648 arm_feature(env
, ARM_FEATURE_V7
)) {
649 uint32_t nr
= cpu
->pmsav7_dregion
;
652 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
"\n", nr
);
657 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
658 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
659 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
663 register_cp_regs_for_features(cpu
);
664 arm_cpu_register_gdb_regs_for_features(cpu
);
666 init_cpreg_list(cpu
);
671 acc
->parent_realize(dev
, errp
);
674 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
684 cpuname
= g_strsplit(cpu_model
, ",", 1);
685 typename
= g_strdup_printf("%s-" TYPE_ARM_CPU
, cpuname
[0]);
686 oc
= object_class_by_name(typename
);
689 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
690 object_class_is_abstract(oc
)) {
696 /* CPU models. These are not needed for the AArch64 linux-user build. */
697 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
699 static void arm920t_initfn(Object
*obj
)
701 ARMCPU
*cpu
= ARM_CPU(obj
);
702 /* TODO: check features. */
703 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
704 cpu
->midr
= 0x41129200;
705 cpu
->ctr
= 0x0d172172;
706 cpu
->reset_sctlr
= 0x00000078;
709 static void arm926_initfn(Object
*obj
)
711 ARMCPU
*cpu
= ARM_CPU(obj
);
713 cpu
->dtb_compatible
= "arm,arm926";
714 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
715 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
716 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
717 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
718 cpu
->midr
= 0x41069265;
719 cpu
->reset_fpsid
= 0x41011090;
720 cpu
->ctr
= 0x1dd20d2;
721 cpu
->reset_sctlr
= 0x00090078;
724 static void arm946_initfn(Object
*obj
)
726 ARMCPU
*cpu
= ARM_CPU(obj
);
728 cpu
->dtb_compatible
= "arm,arm946";
729 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
730 set_feature(&cpu
->env
, ARM_FEATURE_MPU
);
731 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
732 cpu
->midr
= 0x41059461;
733 cpu
->ctr
= 0x0f004006;
734 cpu
->reset_sctlr
= 0x00000078;
737 static void arm1026_initfn(Object
*obj
)
739 ARMCPU
*cpu
= ARM_CPU(obj
);
741 cpu
->dtb_compatible
= "arm,arm1026";
742 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
743 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
744 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
745 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
746 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
747 cpu
->midr
= 0x4106a262;
748 cpu
->reset_fpsid
= 0x410110a0;
749 cpu
->ctr
= 0x1dd20d2;
750 cpu
->reset_sctlr
= 0x00090078;
751 cpu
->reset_auxcr
= 1;
753 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
754 ARMCPRegInfo ifar
= {
755 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
757 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
760 define_one_arm_cp_reg(cpu
, &ifar
);
764 static void arm1136_r2_initfn(Object
*obj
)
766 ARMCPU
*cpu
= ARM_CPU(obj
);
767 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
768 * older core than plain "arm1136". In particular this does not
769 * have the v6K features.
770 * These ID register values are correct for 1136 but may be wrong
771 * for 1136_r2 (in particular r0p2 does not actually implement most
772 * of the ID registers).
775 cpu
->dtb_compatible
= "arm,arm1136";
776 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
777 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
778 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
779 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
780 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
781 cpu
->midr
= 0x4107b362;
782 cpu
->reset_fpsid
= 0x410120b4;
783 cpu
->mvfr0
= 0x11111111;
784 cpu
->mvfr1
= 0x00000000;
785 cpu
->ctr
= 0x1dd20d2;
786 cpu
->reset_sctlr
= 0x00050078;
787 cpu
->id_pfr0
= 0x111;
791 cpu
->id_mmfr0
= 0x01130003;
792 cpu
->id_mmfr1
= 0x10030302;
793 cpu
->id_mmfr2
= 0x01222110;
794 cpu
->id_isar0
= 0x00140011;
795 cpu
->id_isar1
= 0x12002111;
796 cpu
->id_isar2
= 0x11231111;
797 cpu
->id_isar3
= 0x01102131;
798 cpu
->id_isar4
= 0x141;
799 cpu
->reset_auxcr
= 7;
802 static void arm1136_initfn(Object
*obj
)
804 ARMCPU
*cpu
= ARM_CPU(obj
);
806 cpu
->dtb_compatible
= "arm,arm1136";
807 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
808 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
809 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
810 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
811 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
812 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
813 cpu
->midr
= 0x4117b363;
814 cpu
->reset_fpsid
= 0x410120b4;
815 cpu
->mvfr0
= 0x11111111;
816 cpu
->mvfr1
= 0x00000000;
817 cpu
->ctr
= 0x1dd20d2;
818 cpu
->reset_sctlr
= 0x00050078;
819 cpu
->id_pfr0
= 0x111;
823 cpu
->id_mmfr0
= 0x01130003;
824 cpu
->id_mmfr1
= 0x10030302;
825 cpu
->id_mmfr2
= 0x01222110;
826 cpu
->id_isar0
= 0x00140011;
827 cpu
->id_isar1
= 0x12002111;
828 cpu
->id_isar2
= 0x11231111;
829 cpu
->id_isar3
= 0x01102131;
830 cpu
->id_isar4
= 0x141;
831 cpu
->reset_auxcr
= 7;
834 static void arm1176_initfn(Object
*obj
)
836 ARMCPU
*cpu
= ARM_CPU(obj
);
838 cpu
->dtb_compatible
= "arm,arm1176";
839 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
840 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
841 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
842 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
843 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
844 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
845 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
846 cpu
->midr
= 0x410fb767;
847 cpu
->reset_fpsid
= 0x410120b5;
848 cpu
->mvfr0
= 0x11111111;
849 cpu
->mvfr1
= 0x00000000;
850 cpu
->ctr
= 0x1dd20d2;
851 cpu
->reset_sctlr
= 0x00050078;
852 cpu
->id_pfr0
= 0x111;
856 cpu
->id_mmfr0
= 0x01130003;
857 cpu
->id_mmfr1
= 0x10030302;
858 cpu
->id_mmfr2
= 0x01222100;
859 cpu
->id_isar0
= 0x0140011;
860 cpu
->id_isar1
= 0x12002111;
861 cpu
->id_isar2
= 0x11231121;
862 cpu
->id_isar3
= 0x01102131;
863 cpu
->id_isar4
= 0x01141;
864 cpu
->reset_auxcr
= 7;
867 static void arm11mpcore_initfn(Object
*obj
)
869 ARMCPU
*cpu
= ARM_CPU(obj
);
871 cpu
->dtb_compatible
= "arm,arm11mpcore";
872 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
873 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
874 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
875 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
876 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
877 cpu
->midr
= 0x410fb022;
878 cpu
->reset_fpsid
= 0x410120b4;
879 cpu
->mvfr0
= 0x11111111;
880 cpu
->mvfr1
= 0x00000000;
881 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
882 cpu
->id_pfr0
= 0x111;
886 cpu
->id_mmfr0
= 0x01100103;
887 cpu
->id_mmfr1
= 0x10020302;
888 cpu
->id_mmfr2
= 0x01222000;
889 cpu
->id_isar0
= 0x00100011;
890 cpu
->id_isar1
= 0x12002111;
891 cpu
->id_isar2
= 0x11221011;
892 cpu
->id_isar3
= 0x01102131;
893 cpu
->id_isar4
= 0x141;
894 cpu
->reset_auxcr
= 1;
897 static void cortex_m3_initfn(Object
*obj
)
899 ARMCPU
*cpu
= ARM_CPU(obj
);
900 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
901 set_feature(&cpu
->env
, ARM_FEATURE_M
);
902 cpu
->midr
= 0x410fc231;
905 static void cortex_m4_initfn(Object
*obj
)
907 ARMCPU
*cpu
= ARM_CPU(obj
);
909 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
910 set_feature(&cpu
->env
, ARM_FEATURE_M
);
911 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
912 cpu
->midr
= 0x410fc240; /* r0p0 */
914 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
916 CPUClass
*cc
= CPU_CLASS(oc
);
918 #ifndef CONFIG_USER_ONLY
919 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
922 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
925 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
926 /* Dummy the TCM region regs for the moment */
927 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
928 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
929 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
930 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
934 static void cortex_r5_initfn(Object
*obj
)
936 ARMCPU
*cpu
= ARM_CPU(obj
);
938 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
939 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DIV
);
940 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
941 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
942 set_feature(&cpu
->env
, ARM_FEATURE_MPU
);
943 cpu
->midr
= 0x411fc153; /* r1p3 */
944 cpu
->id_pfr0
= 0x0131;
945 cpu
->id_pfr1
= 0x001;
946 cpu
->id_dfr0
= 0x010400;
948 cpu
->id_mmfr0
= 0x0210030;
949 cpu
->id_mmfr1
= 0x00000000;
950 cpu
->id_mmfr2
= 0x01200000;
951 cpu
->id_mmfr3
= 0x0211;
952 cpu
->id_isar0
= 0x2101111;
953 cpu
->id_isar1
= 0x13112111;
954 cpu
->id_isar2
= 0x21232141;
955 cpu
->id_isar3
= 0x01112131;
956 cpu
->id_isar4
= 0x0010142;
958 cpu
->mp_is_up
= true;
959 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
962 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
963 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
964 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
965 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
966 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
970 static void cortex_a8_initfn(Object
*obj
)
972 ARMCPU
*cpu
= ARM_CPU(obj
);
974 cpu
->dtb_compatible
= "arm,cortex-a8";
975 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
976 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
977 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
978 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
979 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
980 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
981 cpu
->midr
= 0x410fc080;
982 cpu
->reset_fpsid
= 0x410330c0;
983 cpu
->mvfr0
= 0x11110222;
984 cpu
->mvfr1
= 0x00011100;
985 cpu
->ctr
= 0x82048004;
986 cpu
->reset_sctlr
= 0x00c50078;
987 cpu
->id_pfr0
= 0x1031;
989 cpu
->id_dfr0
= 0x400;
991 cpu
->id_mmfr0
= 0x31100003;
992 cpu
->id_mmfr1
= 0x20000000;
993 cpu
->id_mmfr2
= 0x01202000;
994 cpu
->id_mmfr3
= 0x11;
995 cpu
->id_isar0
= 0x00101111;
996 cpu
->id_isar1
= 0x12112111;
997 cpu
->id_isar2
= 0x21232031;
998 cpu
->id_isar3
= 0x11112131;
999 cpu
->id_isar4
= 0x00111142;
1000 cpu
->dbgdidr
= 0x15141000;
1001 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1002 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1003 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1004 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1005 cpu
->reset_auxcr
= 2;
1006 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1009 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1010 /* power_control should be set to maximum latency. Again,
1011 * default to 0 and set by private hook
1013 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1014 .access
= PL1_RW
, .resetvalue
= 0,
1015 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1016 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1017 .access
= PL1_RW
, .resetvalue
= 0,
1018 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1019 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1020 .access
= PL1_RW
, .resetvalue
= 0,
1021 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1022 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1023 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1024 /* TLB lockdown control */
1025 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1026 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1027 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1028 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1029 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1030 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1031 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1032 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1033 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1034 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1038 static void cortex_a9_initfn(Object
*obj
)
1040 ARMCPU
*cpu
= ARM_CPU(obj
);
1042 cpu
->dtb_compatible
= "arm,cortex-a9";
1043 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1044 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1045 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
1046 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1047 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1048 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1049 /* Note that A9 supports the MP extensions even for
1050 * A9UP and single-core A9MP (which are both different
1051 * and valid configurations; we don't model A9UP).
1053 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1054 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1055 cpu
->midr
= 0x410fc090;
1056 cpu
->reset_fpsid
= 0x41033090;
1057 cpu
->mvfr0
= 0x11110222;
1058 cpu
->mvfr1
= 0x01111111;
1059 cpu
->ctr
= 0x80038003;
1060 cpu
->reset_sctlr
= 0x00c50078;
1061 cpu
->id_pfr0
= 0x1031;
1062 cpu
->id_pfr1
= 0x11;
1063 cpu
->id_dfr0
= 0x000;
1065 cpu
->id_mmfr0
= 0x00100103;
1066 cpu
->id_mmfr1
= 0x20000000;
1067 cpu
->id_mmfr2
= 0x01230000;
1068 cpu
->id_mmfr3
= 0x00002111;
1069 cpu
->id_isar0
= 0x00101111;
1070 cpu
->id_isar1
= 0x13112111;
1071 cpu
->id_isar2
= 0x21232041;
1072 cpu
->id_isar3
= 0x11112131;
1073 cpu
->id_isar4
= 0x00111142;
1074 cpu
->dbgdidr
= 0x35141000;
1075 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
1076 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
1077 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
1078 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
1081 #ifndef CONFIG_USER_ONLY
1082 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1084 /* Linux wants the number of processors from here.
1085 * Might as well set the interrupt-controller bit too.
1087 return ((smp_cpus
- 1) << 24) | (1 << 23);
1091 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
1092 #ifndef CONFIG_USER_ONLY
1093 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1094 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
1095 .writefn
= arm_cp_write_ignore
, },
1097 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
1098 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1102 static void cortex_a15_initfn(Object
*obj
)
1104 ARMCPU
*cpu
= ARM_CPU(obj
);
1106 cpu
->dtb_compatible
= "arm,cortex-a15";
1107 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1108 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1109 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1110 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1111 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1112 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1113 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1114 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1115 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1116 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1117 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
1118 cpu
->midr
= 0x412fc0f1;
1119 cpu
->reset_fpsid
= 0x410430f0;
1120 cpu
->mvfr0
= 0x10110222;
1121 cpu
->mvfr1
= 0x11111111;
1122 cpu
->ctr
= 0x8444c004;
1123 cpu
->reset_sctlr
= 0x00c50078;
1124 cpu
->id_pfr0
= 0x00001131;
1125 cpu
->id_pfr1
= 0x00011011;
1126 cpu
->id_dfr0
= 0x02010555;
1127 cpu
->id_afr0
= 0x00000000;
1128 cpu
->id_mmfr0
= 0x10201105;
1129 cpu
->id_mmfr1
= 0x20000000;
1130 cpu
->id_mmfr2
= 0x01240000;
1131 cpu
->id_mmfr3
= 0x02102211;
1132 cpu
->id_isar0
= 0x02101110;
1133 cpu
->id_isar1
= 0x13112111;
1134 cpu
->id_isar2
= 0x21232041;
1135 cpu
->id_isar3
= 0x11112131;
1136 cpu
->id_isar4
= 0x10011142;
1137 cpu
->dbgdidr
= 0x3515f021;
1138 cpu
->clidr
= 0x0a200023;
1139 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1140 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1141 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1142 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
1145 static void ti925t_initfn(Object
*obj
)
1147 ARMCPU
*cpu
= ARM_CPU(obj
);
1148 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
1149 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
1150 cpu
->midr
= ARM_CPUID_TI925T
;
1151 cpu
->ctr
= 0x5109149;
1152 cpu
->reset_sctlr
= 0x00000070;
1155 static void sa1100_initfn(Object
*obj
)
1157 ARMCPU
*cpu
= ARM_CPU(obj
);
1159 cpu
->dtb_compatible
= "intel,sa1100";
1160 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1161 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1162 cpu
->midr
= 0x4401A11B;
1163 cpu
->reset_sctlr
= 0x00000070;
1166 static void sa1110_initfn(Object
*obj
)
1168 ARMCPU
*cpu
= ARM_CPU(obj
);
1169 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1170 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1171 cpu
->midr
= 0x6901B119;
1172 cpu
->reset_sctlr
= 0x00000070;
1175 static void pxa250_initfn(Object
*obj
)
1177 ARMCPU
*cpu
= ARM_CPU(obj
);
1179 cpu
->dtb_compatible
= "marvell,xscale";
1180 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1181 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1182 cpu
->midr
= 0x69052100;
1183 cpu
->ctr
= 0xd172172;
1184 cpu
->reset_sctlr
= 0x00000078;
1187 static void pxa255_initfn(Object
*obj
)
1189 ARMCPU
*cpu
= ARM_CPU(obj
);
1191 cpu
->dtb_compatible
= "marvell,xscale";
1192 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1193 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1194 cpu
->midr
= 0x69052d00;
1195 cpu
->ctr
= 0xd172172;
1196 cpu
->reset_sctlr
= 0x00000078;
1199 static void pxa260_initfn(Object
*obj
)
1201 ARMCPU
*cpu
= ARM_CPU(obj
);
1203 cpu
->dtb_compatible
= "marvell,xscale";
1204 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1205 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1206 cpu
->midr
= 0x69052903;
1207 cpu
->ctr
= 0xd172172;
1208 cpu
->reset_sctlr
= 0x00000078;
1211 static void pxa261_initfn(Object
*obj
)
1213 ARMCPU
*cpu
= ARM_CPU(obj
);
1215 cpu
->dtb_compatible
= "marvell,xscale";
1216 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1217 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1218 cpu
->midr
= 0x69052d05;
1219 cpu
->ctr
= 0xd172172;
1220 cpu
->reset_sctlr
= 0x00000078;
1223 static void pxa262_initfn(Object
*obj
)
1225 ARMCPU
*cpu
= ARM_CPU(obj
);
1227 cpu
->dtb_compatible
= "marvell,xscale";
1228 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1229 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1230 cpu
->midr
= 0x69052d06;
1231 cpu
->ctr
= 0xd172172;
1232 cpu
->reset_sctlr
= 0x00000078;
1235 static void pxa270a0_initfn(Object
*obj
)
1237 ARMCPU
*cpu
= ARM_CPU(obj
);
1239 cpu
->dtb_compatible
= "marvell,xscale";
1240 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1241 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1242 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1243 cpu
->midr
= 0x69054110;
1244 cpu
->ctr
= 0xd172172;
1245 cpu
->reset_sctlr
= 0x00000078;
1248 static void pxa270a1_initfn(Object
*obj
)
1250 ARMCPU
*cpu
= ARM_CPU(obj
);
1252 cpu
->dtb_compatible
= "marvell,xscale";
1253 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1254 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1255 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1256 cpu
->midr
= 0x69054111;
1257 cpu
->ctr
= 0xd172172;
1258 cpu
->reset_sctlr
= 0x00000078;
1261 static void pxa270b0_initfn(Object
*obj
)
1263 ARMCPU
*cpu
= ARM_CPU(obj
);
1265 cpu
->dtb_compatible
= "marvell,xscale";
1266 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1267 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1268 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1269 cpu
->midr
= 0x69054112;
1270 cpu
->ctr
= 0xd172172;
1271 cpu
->reset_sctlr
= 0x00000078;
1274 static void pxa270b1_initfn(Object
*obj
)
1276 ARMCPU
*cpu
= ARM_CPU(obj
);
1278 cpu
->dtb_compatible
= "marvell,xscale";
1279 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1280 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1281 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1282 cpu
->midr
= 0x69054113;
1283 cpu
->ctr
= 0xd172172;
1284 cpu
->reset_sctlr
= 0x00000078;
1287 static void pxa270c0_initfn(Object
*obj
)
1289 ARMCPU
*cpu
= ARM_CPU(obj
);
1291 cpu
->dtb_compatible
= "marvell,xscale";
1292 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1293 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1294 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1295 cpu
->midr
= 0x69054114;
1296 cpu
->ctr
= 0xd172172;
1297 cpu
->reset_sctlr
= 0x00000078;
1300 static void pxa270c5_initfn(Object
*obj
)
1302 ARMCPU
*cpu
= ARM_CPU(obj
);
1304 cpu
->dtb_compatible
= "marvell,xscale";
1305 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1306 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1307 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1308 cpu
->midr
= 0x69054117;
1309 cpu
->ctr
= 0xd172172;
1310 cpu
->reset_sctlr
= 0x00000078;
1313 #ifdef CONFIG_USER_ONLY
1314 static void arm_any_initfn(Object
*obj
)
1316 ARMCPU
*cpu
= ARM_CPU(obj
);
1317 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1318 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1319 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1320 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1321 set_feature(&cpu
->env
, ARM_FEATURE_V8_AES
);
1322 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA1
);
1323 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA256
);
1324 set_feature(&cpu
->env
, ARM_FEATURE_V8_PMULL
);
1325 set_feature(&cpu
->env
, ARM_FEATURE_CRC
);
1326 cpu
->midr
= 0xffffffff;
1330 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1332 typedef struct ARMCPUInfo
{
1334 void (*initfn
)(Object
*obj
);
1335 void (*class_init
)(ObjectClass
*oc
, void *data
);
1338 static const ARMCPUInfo arm_cpus
[] = {
1339 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1340 { .name
= "arm920t", .initfn
= arm920t_initfn
},
1341 { .name
= "arm926", .initfn
= arm926_initfn
},
1342 { .name
= "arm946", .initfn
= arm946_initfn
},
1343 { .name
= "arm1026", .initfn
= arm1026_initfn
},
1344 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1345 * older core than plain "arm1136". In particular this does not
1346 * have the v6K features.
1348 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
1349 { .name
= "arm1136", .initfn
= arm1136_initfn
},
1350 { .name
= "arm1176", .initfn
= arm1176_initfn
},
1351 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
1352 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
1353 .class_init
= arm_v7m_class_init
},
1354 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
1355 .class_init
= arm_v7m_class_init
},
1356 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
1357 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
1358 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
1359 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
1360 { .name
= "ti925t", .initfn
= ti925t_initfn
},
1361 { .name
= "sa1100", .initfn
= sa1100_initfn
},
1362 { .name
= "sa1110", .initfn
= sa1110_initfn
},
1363 { .name
= "pxa250", .initfn
= pxa250_initfn
},
1364 { .name
= "pxa255", .initfn
= pxa255_initfn
},
1365 { .name
= "pxa260", .initfn
= pxa260_initfn
},
1366 { .name
= "pxa261", .initfn
= pxa261_initfn
},
1367 { .name
= "pxa262", .initfn
= pxa262_initfn
},
1368 /* "pxa270" is an alias for "pxa270-a0" */
1369 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
1370 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
1371 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
1372 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
1373 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
1374 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
1375 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
1376 #ifdef CONFIG_USER_ONLY
1377 { .name
= "any", .initfn
= arm_any_initfn
},
1383 static Property arm_cpu_properties
[] = {
1384 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
1385 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1386 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
1387 DEFINE_PROP_END_OF_LIST()
1390 #ifdef CONFIG_USER_ONLY
1391 static int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
1394 ARMCPU
*cpu
= ARM_CPU(cs
);
1395 CPUARMState
*env
= &cpu
->env
;
1397 env
->exception
.vaddress
= address
;
1399 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
1401 cs
->exception_index
= EXCP_DATA_ABORT
;
1407 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
1409 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1410 CPUClass
*cc
= CPU_CLASS(acc
);
1411 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1413 acc
->parent_realize
= dc
->realize
;
1414 dc
->realize
= arm_cpu_realizefn
;
1415 dc
->props
= arm_cpu_properties
;
1417 acc
->parent_reset
= cc
->reset
;
1418 cc
->reset
= arm_cpu_reset
;
1420 cc
->class_by_name
= arm_cpu_class_by_name
;
1421 cc
->has_work
= arm_cpu_has_work
;
1422 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
1423 cc
->dump_state
= arm_cpu_dump_state
;
1424 cc
->set_pc
= arm_cpu_set_pc
;
1425 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
1426 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
1427 #ifdef CONFIG_USER_ONLY
1428 cc
->handle_mmu_fault
= arm_cpu_handle_mmu_fault
;
1430 cc
->do_interrupt
= arm_cpu_do_interrupt
;
1431 cc
->get_phys_page_debug
= arm_cpu_get_phys_page_debug
;
1432 cc
->vmsd
= &vmstate_arm_cpu
;
1433 cc
->virtio_is_big_endian
= arm_cpu_is_big_endian
;
1435 cc
->gdb_num_core_regs
= 26;
1436 cc
->gdb_core_xml_file
= "arm-core.xml";
1437 cc
->gdb_stop_before_watchpoint
= true;
1438 cc
->debug_excp_handler
= arm_debug_excp_handler
;
1440 cc
->disas_set_info
= arm_disas_set_info
;
1443 static void cpu_register(const ARMCPUInfo
*info
)
1445 TypeInfo type_info
= {
1446 .parent
= TYPE_ARM_CPU
,
1447 .instance_size
= sizeof(ARMCPU
),
1448 .instance_init
= info
->initfn
,
1449 .class_size
= sizeof(ARMCPUClass
),
1450 .class_init
= info
->class_init
,
1453 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
1454 type_register(&type_info
);
1455 g_free((void *)type_info
.name
);
1458 static const TypeInfo arm_cpu_type_info
= {
1459 .name
= TYPE_ARM_CPU
,
1461 .instance_size
= sizeof(ARMCPU
),
1462 .instance_init
= arm_cpu_initfn
,
1463 .instance_post_init
= arm_cpu_post_init
,
1464 .instance_finalize
= arm_cpu_finalizefn
,
1466 .class_size
= sizeof(ARMCPUClass
),
1467 .class_init
= arm_cpu_class_init
,
1470 static void arm_cpu_register_types(void)
1472 const ARMCPUInfo
*info
= arm_cpus
;
1474 type_register_static(&arm_cpu_type_info
);
1476 while (info
->name
) {
1482 type_init(arm_cpu_register_types
)