3 * Samsung s3c24xx cpu state and functions.
5 * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders
7 * Copyright 2010, 2013 Stefan Weil
9 * This file is under the terms of the GNU General Public License Version 2.
15 #include "hw/block/flash.h"
17 typedef struct S3C24xxGpioState S3C24xxGpioState
;
19 /* This structure type encapsulates the state of a S3C24XX SoC. */
20 typedef struct S3CState_s
{
28 /* Memory controller state */
29 struct s3c24xx_memc_state_s
*memc
;
31 /* IRQ controller state */
32 struct s3c24xx_irq_state_s
*irq
;
34 /* Clock and power control */
35 struct s3c24xx_clkcon_state_s
*clkcon
;
37 /* timer controller */
38 struct s3c24xx_timers_state_s
*timers
;
41 struct s3c24xx_serial_dev_s
*uart
[3];
44 struct s3c24xx_rtc_state_s
*rtc
;
47 S3C24xxGpioState
*gpio
;
50 struct s3c24xx_i2c_state_s
*iic
;
53 struct s3c24xx_nand_state_s
*nand
;
57 /* initialise memory controller peripheral */
58 struct s3c24xx_memc_state_s
*s3c24xx_memc_init(hwaddr base_addr
);
60 /* initialise the IRQ controller */
61 struct s3c24xx_irq_state_s
*s3c24xx_irq_init(S3CState
*soc
, hwaddr base_addr
);
63 /* get the qemu interrupt from an irq number */
64 qemu_irq
s3c24xx_get_irq(struct s3c24xx_irq_state_s
*s
, unsigned inum
);
66 /* initialise clock controller */
67 struct s3c24xx_clkcon_state_s
*s3c24xx_clkcon_init(S3CState
*soc
, hwaddr base_addr
, uint32_t ref_freq
);
69 /* initialise timer controller */
70 struct s3c24xx_timers_state_s
*s3c24xx_timers_init(S3CState
*soc
, hwaddr base_addr
, uint32_t tclk0
, uint32_t tclk1
);
72 /* initialise a serial port controller */
73 struct s3c24xx_serial_dev_s
*s3c24xx_serial_init(S3CState
*soc
, CharDriverState
*chr
, hwaddr base_addr
, int irqn
);
75 /* Initialise real time clock */
76 struct s3c24xx_rtc_state_s
*s3c24xx_rtc_init(hwaddr base_addr
);
79 S3C24xxGpioState
*s3c24xx_gpio_init(S3CState
*soc
, hwaddr base_addr
, uint32_t cpu_id
);
81 /* get the qemu interrupt from an eirq number */
82 qemu_irq
s3c24xx_get_eirq(S3C24xxGpioState
*s
, unsigned einum
);
84 /* Initialise I2c controller */
85 struct s3c24xx_i2c_state_s
*s3c24xx_iic_init(qemu_irq irq
, hwaddr base_addr
);
87 /* acquire bus from controller state */
88 I2CBus
*s3c24xx_i2c_bus(struct s3c24xx_i2c_state_s
*s
);
90 /* Initialise nand controller */
91 struct s3c24xx_nand_state_s
*s3c24xx_nand_init(hwaddr base_addr
);
93 /* set nand controller context */
94 void s3c24xx_nand_attach(struct s3c24xx_nand_state_s
*s
, DeviceState
*nand
);
96 #endif /* S3C24XX_H */