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target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()
[qemu/ar7.git] / target / riscv / cpu.c
blob2acf77949f273f65d7a57593aff5f0e2244fa3c0
1 /*
2 * QEMU RISC-V CPU
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
23 #include "qemu/log.h"
24 #include "cpu.h"
25 #include "cpu_vendorid.h"
26 #include "pmu.h"
27 #include "internals.h"
28 #include "time_helper.h"
29 #include "exec/exec-all.h"
30 #include "qapi/error.h"
31 #include "qapi/visitor.h"
32 #include "qemu/error-report.h"
33 #include "hw/qdev-properties.h"
34 #include "migration/vmstate.h"
35 #include "fpu/softfloat-helpers.h"
36 #include "sysemu/kvm.h"
37 #include "sysemu/tcg.h"
38 #include "kvm_riscv.h"
39 #include "tcg/tcg.h"
40
41 /* RISC-V CPU definitions */
42 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
43
44 struct isa_ext_data {
45 const char *name;
46 int min_version;
47 int ext_enable_offset;
48 };
49
50 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
51 {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
52
53 /*
54 * From vector_helper.c
55 * Note that vector data is stored in host-endian 64-bit chunks,
56 * so addressing bytes needs a host-endian fixup.
57 */
58 #if HOST_BIG_ENDIAN
59 #define BYTE(x) ((x) ^ 7)
60 #else
61 #define BYTE(x) (x)
62 #endif
63
64 /*
65 * Here are the ordering rules of extension naming defined by RISC-V
66 * specification :
67 * 1. All extensions should be separated from other multi-letter extensions
68 * by an underscore.
69 * 2. The first letter following the 'Z' conventionally indicates the most
70 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
71 * If multiple 'Z' extensions are named, they should be ordered first
72 * by category, then alphabetically within a category.
73 * 3. Standard supervisor-level extensions (starts with 'S') should be
74 * listed after standard unprivileged extensions. If multiple
75 * supervisor-level extensions are listed, they should be ordered
76 * alphabetically.
77 * 4. Non-standard extensions (starts with 'X') must be listed after all
78 * standard extensions. They must be separated from other multi-letter
79 * extensions by an underscore.
80 *
81 * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
82 * instead.
83 */
84 static const struct isa_ext_data isa_edata_arr[] = {
85 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
86 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
87 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
88 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
89 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
90 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
91 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
92 ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
93 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh),
94 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin),
95 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx),
96 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx),
97 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca),
98 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb),
99 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf),
100 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd),
101 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce),
102 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp),
103 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt),
104 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba),
105 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb),
106 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc),
107 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb),
108 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc),
109 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx),
110 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs),
111 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk),
112 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn),
113 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd),
114 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne),
115 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh),
116 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr),
117 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks),
118 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
119 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
120 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
121 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
122 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
123 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
124 ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
125 ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
126 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
127 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
128 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
129 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
130 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
131 ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
132 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
133 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
134 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
135 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
136 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
137 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
138 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
139 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
140 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
141 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
142 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo),
143 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
144 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
145 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv),
146 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac),
147 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
148 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
149 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
150 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
151 };
152
153 static bool isa_ext_is_enabled(RISCVCPU *cpu,
154 const struct isa_ext_data *edata)
155 {
156 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
157
158 return *ext_enabled;
159 }
160
161 static void isa_ext_update_enabled(RISCVCPU *cpu,
162 const struct isa_ext_data *edata, bool en)
163 {
164 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
165
166 *ext_enabled = en;
167 }
168
169 const char * const riscv_int_regnames[] = {
170 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
171 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
172 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
173 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
174 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
175 };
176
177 const char * const riscv_int_regnamesh[] = {
178 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
179 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
180 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
181 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
182 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
183 "x30h/t5h", "x31h/t6h"
184 };
185
186 const char * const riscv_fpr_regnames[] = {
187 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
188 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
189 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
190 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
191 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
192 "f30/ft10", "f31/ft11"
193 };
194
195 const char * const riscv_rvv_regnames[] = {
196 "v0", "v1", "v2", "v3", "v4", "v5", "v6",
197 "v7", "v8", "v9", "v10", "v11", "v12", "v13",
198 "v14", "v15", "v16", "v17", "v18", "v19", "v20",
199 "v21", "v22", "v23", "v24", "v25", "v26", "v27",
200 "v28", "v29", "v30", "v31"
201 };
202
203 static const char * const riscv_excp_names[] = {
204 "misaligned_fetch",
205 "fault_fetch",
206 "illegal_instruction",
207 "breakpoint",
208 "misaligned_load",
209 "fault_load",
210 "misaligned_store",
211 "fault_store",
212 "user_ecall",
213 "supervisor_ecall",
214 "hypervisor_ecall",
215 "machine_ecall",
216 "exec_page_fault",
217 "load_page_fault",
218 "reserved",
219 "store_page_fault",
220 "reserved",
221 "reserved",
222 "reserved",
223 "reserved",
224 "guest_exec_page_fault",
225 "guest_load_page_fault",
226 "reserved",
227 "guest_store_page_fault",
228 };
229
230 static const char * const riscv_intr_names[] = {
231 "u_software",
232 "s_software",
233 "vs_software",
234 "m_software",
235 "u_timer",
236 "s_timer",
237 "vs_timer",
238 "m_timer",
239 "u_external",
240 "s_external",
241 "vs_external",
242 "m_external",
243 "reserved",
244 "reserved",
245 "reserved",
246 "reserved"
247 };
248
249 static void riscv_cpu_add_user_properties(Object *obj);
250
251 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
252 {
253 if (async) {
254 return (cause < ARRAY_SIZE(riscv_intr_names)) ?
255 riscv_intr_names[cause] : "(unknown)";
256 } else {
257 return (cause < ARRAY_SIZE(riscv_excp_names)) ?
258 riscv_excp_names[cause] : "(unknown)";
259 }
260 }
261
262 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
263 {
264 env->misa_mxl_max = env->misa_mxl = mxl;
265 env->misa_ext_mask = env->misa_ext = ext;
266 }
267
268 #ifndef CONFIG_USER_ONLY
269 static uint8_t satp_mode_from_str(const char *satp_mode_str)
270 {
271 if (!strncmp(satp_mode_str, "mbare", 5)) {
272 return VM_1_10_MBARE;
273 }
274
275 if (!strncmp(satp_mode_str, "sv32", 4)) {
276 return VM_1_10_SV32;
277 }
278
279 if (!strncmp(satp_mode_str, "sv39", 4)) {
280 return VM_1_10_SV39;
281 }
282
283 if (!strncmp(satp_mode_str, "sv48", 4)) {
284 return VM_1_10_SV48;
285 }
286
287 if (!strncmp(satp_mode_str, "sv57", 4)) {
288 return VM_1_10_SV57;
289 }
290
291 if (!strncmp(satp_mode_str, "sv64", 4)) {
292 return VM_1_10_SV64;
293 }
294
295 g_assert_not_reached();
296 }
297
298 uint8_t satp_mode_max_from_map(uint32_t map)
299 {
300 /* map here has at least one bit set, so no problem with clz */
301 return 31 - __builtin_clz(map);
302 }
303
304 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
305 {
306 if (is_32_bit) {
307 switch (satp_mode) {
308 case VM_1_10_SV32:
309 return "sv32";
310 case VM_1_10_MBARE:
311 return "none";
312 }
313 } else {
314 switch (satp_mode) {
315 case VM_1_10_SV64:
316 return "sv64";
317 case VM_1_10_SV57:
318 return "sv57";
319 case VM_1_10_SV48:
320 return "sv48";
321 case VM_1_10_SV39:
322 return "sv39";
323 case VM_1_10_MBARE:
324 return "none";
325 }
326 }
327
328 g_assert_not_reached();
329 }
330
331 static void set_satp_mode_max_supported(RISCVCPU *cpu,
332 uint8_t satp_mode)
333 {
334 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
335 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
336
337 for (int i = 0; i <= satp_mode; ++i) {
338 if (valid_vm[i]) {
339 cpu->cfg.satp_mode.supported |= (1 << i);
340 }
341 }
342 }
343
344 /* Set the satp mode to the max supported */
345 static void set_satp_mode_default_map(RISCVCPU *cpu)
346 {
347 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;
348 }
349 #endif
350
351 static void riscv_any_cpu_init(Object *obj)
352 {
353 RISCVCPU *cpu = RISCV_CPU(obj);
354 CPURISCVState *env = &cpu->env;
355 #if defined(TARGET_RISCV32)
356 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
357 #elif defined(TARGET_RISCV64)
358 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
359 #endif
360
361 #ifndef CONFIG_USER_ONLY
362 set_satp_mode_max_supported(RISCV_CPU(obj),
363 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
364 VM_1_10_SV32 : VM_1_10_SV57);
365 #endif
366
367 env->priv_ver = PRIV_VERSION_LATEST;
368
369 /* inherited from parent obj via riscv_cpu_init() */
370 cpu->cfg.ext_ifencei = true;
371 cpu->cfg.ext_icsr = true;
372 cpu->cfg.mmu = true;
373 cpu->cfg.pmp = true;
374 }
375
376 #if defined(TARGET_RISCV64)
377 static void rv64_base_cpu_init(Object *obj)
378 {
379 CPURISCVState *env = &RISCV_CPU(obj)->env;
380 /* We set this in the realise function */
381 set_misa(env, MXL_RV64, 0);
382 riscv_cpu_add_user_properties(obj);
383 /* Set latest version of privileged specification */
384 env->priv_ver = PRIV_VERSION_LATEST;
385 #ifndef CONFIG_USER_ONLY
386 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
387 #endif
388 }
389
390 static void rv64_sifive_u_cpu_init(Object *obj)
391 {
392 RISCVCPU *cpu = RISCV_CPU(obj);
393 CPURISCVState *env = &cpu->env;
394 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
395 env->priv_ver = PRIV_VERSION_1_10_0;
396 #ifndef CONFIG_USER_ONLY
397 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
398 #endif
399
400 /* inherited from parent obj via riscv_cpu_init() */
401 cpu->cfg.ext_ifencei = true;
402 cpu->cfg.ext_icsr = true;
403 cpu->cfg.mmu = true;
404 cpu->cfg.pmp = true;
405 }
406
407 static void rv64_sifive_e_cpu_init(Object *obj)
408 {
409 CPURISCVState *env = &RISCV_CPU(obj)->env;
410 RISCVCPU *cpu = RISCV_CPU(obj);
411
412 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
413 env->priv_ver = PRIV_VERSION_1_10_0;
414 #ifndef CONFIG_USER_ONLY
415 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
416 #endif
417
418 /* inherited from parent obj via riscv_cpu_init() */
419 cpu->cfg.ext_ifencei = true;
420 cpu->cfg.ext_icsr = true;
421 cpu->cfg.pmp = true;
422 }
423
424 static void rv64_thead_c906_cpu_init(Object *obj)
425 {
426 CPURISCVState *env = &RISCV_CPU(obj)->env;
427 RISCVCPU *cpu = RISCV_CPU(obj);
428
429 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
430 env->priv_ver = PRIV_VERSION_1_11_0;
431
432 cpu->cfg.ext_zfh = true;
433 cpu->cfg.mmu = true;
434 cpu->cfg.ext_xtheadba = true;
435 cpu->cfg.ext_xtheadbb = true;
436 cpu->cfg.ext_xtheadbs = true;
437 cpu->cfg.ext_xtheadcmo = true;
438 cpu->cfg.ext_xtheadcondmov = true;
439 cpu->cfg.ext_xtheadfmemidx = true;
440 cpu->cfg.ext_xtheadmac = true;
441 cpu->cfg.ext_xtheadmemidx = true;
442 cpu->cfg.ext_xtheadmempair = true;
443 cpu->cfg.ext_xtheadsync = true;
444
445 cpu->cfg.mvendorid = THEAD_VENDOR_ID;
446 #ifndef CONFIG_USER_ONLY
447 set_satp_mode_max_supported(cpu, VM_1_10_SV39);
448 #endif
449
450 /* inherited from parent obj via riscv_cpu_init() */
451 cpu->cfg.pmp = true;
452 }
453
454 static void rv64_veyron_v1_cpu_init(Object *obj)
455 {
456 CPURISCVState *env = &RISCV_CPU(obj)->env;
457 RISCVCPU *cpu = RISCV_CPU(obj);
458
459 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
460 env->priv_ver = PRIV_VERSION_1_12_0;
461
462 /* Enable ISA extensions */
463 cpu->cfg.mmu = true;
464 cpu->cfg.ext_ifencei = true;
465 cpu->cfg.ext_icsr = true;
466 cpu->cfg.pmp = true;
467 cpu->cfg.ext_icbom = true;
468 cpu->cfg.cbom_blocksize = 64;
469 cpu->cfg.cboz_blocksize = 64;
470 cpu->cfg.ext_icboz = true;
471 cpu->cfg.ext_smaia = true;
472 cpu->cfg.ext_ssaia = true;
473 cpu->cfg.ext_sscofpmf = true;
474 cpu->cfg.ext_sstc = true;
475 cpu->cfg.ext_svinval = true;
476 cpu->cfg.ext_svnapot = true;
477 cpu->cfg.ext_svpbmt = true;
478 cpu->cfg.ext_smstateen = true;
479 cpu->cfg.ext_zba = true;
480 cpu->cfg.ext_zbb = true;
481 cpu->cfg.ext_zbc = true;
482 cpu->cfg.ext_zbs = true;
483 cpu->cfg.ext_XVentanaCondOps = true;
484
485 cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
486 cpu->cfg.marchid = VEYRON_V1_MARCHID;
487 cpu->cfg.mimpid = VEYRON_V1_MIMPID;
488
489 #ifndef CONFIG_USER_ONLY
490 set_satp_mode_max_supported(cpu, VM_1_10_SV48);
491 #endif
492 }
493
494 static void rv128_base_cpu_init(Object *obj)
495 {
496 if (qemu_tcg_mttcg_enabled()) {
497 /* Missing 128-bit aligned atomics */
498 error_report("128-bit RISC-V currently does not work with Multi "
499 "Threaded TCG. Please use: -accel tcg,thread=single");
500 exit(EXIT_FAILURE);
501 }
502 CPURISCVState *env = &RISCV_CPU(obj)->env;
503 /* We set this in the realise function */
504 set_misa(env, MXL_RV128, 0);
505 riscv_cpu_add_user_properties(obj);
506 /* Set latest version of privileged specification */
507 env->priv_ver = PRIV_VERSION_LATEST;
508 #ifndef CONFIG_USER_ONLY
509 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
510 #endif
511 }
512 #else
513 static void rv32_base_cpu_init(Object *obj)
514 {
515 CPURISCVState *env = &RISCV_CPU(obj)->env;
516 /* We set this in the realise function */
517 set_misa(env, MXL_RV32, 0);
518 riscv_cpu_add_user_properties(obj);
519 /* Set latest version of privileged specification */
520 env->priv_ver = PRIV_VERSION_LATEST;
521 #ifndef CONFIG_USER_ONLY
522 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
523 #endif
524 }
525
526 static void rv32_sifive_u_cpu_init(Object *obj)
527 {
528 RISCVCPU *cpu = RISCV_CPU(obj);
529 CPURISCVState *env = &cpu->env;
530 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
531 env->priv_ver = PRIV_VERSION_1_10_0;
532 #ifndef CONFIG_USER_ONLY
533 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
534 #endif
535
536 /* inherited from parent obj via riscv_cpu_init() */
537 cpu->cfg.ext_ifencei = true;
538 cpu->cfg.ext_icsr = true;
539 cpu->cfg.mmu = true;
540 cpu->cfg.pmp = true;
541 }
542
543 static void rv32_sifive_e_cpu_init(Object *obj)
544 {
545 CPURISCVState *env = &RISCV_CPU(obj)->env;
546 RISCVCPU *cpu = RISCV_CPU(obj);
547
548 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
549 env->priv_ver = PRIV_VERSION_1_10_0;
550 #ifndef CONFIG_USER_ONLY
551 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
552 #endif
553
554 /* inherited from parent obj via riscv_cpu_init() */
555 cpu->cfg.ext_ifencei = true;
556 cpu->cfg.ext_icsr = true;
557 cpu->cfg.pmp = true;
558 }
559
560 static void rv32_ibex_cpu_init(Object *obj)
561 {
562 CPURISCVState *env = &RISCV_CPU(obj)->env;
563 RISCVCPU *cpu = RISCV_CPU(obj);
564
565 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
566 env->priv_ver = PRIV_VERSION_1_11_0;
567 #ifndef CONFIG_USER_ONLY
568 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
569 #endif
570 cpu->cfg.epmp = true;
571
572 /* inherited from parent obj via riscv_cpu_init() */
573 cpu->cfg.ext_ifencei = true;
574 cpu->cfg.ext_icsr = true;
575 cpu->cfg.pmp = true;
576 }
577
578 static void rv32_imafcu_nommu_cpu_init(Object *obj)
579 {
580 CPURISCVState *env = &RISCV_CPU(obj)->env;
581 RISCVCPU *cpu = RISCV_CPU(obj);
582
583 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
584 env->priv_ver = PRIV_VERSION_1_10_0;
585 #ifndef CONFIG_USER_ONLY
586 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
587 #endif
588
589 /* inherited from parent obj via riscv_cpu_init() */
590 cpu->cfg.ext_ifencei = true;
591 cpu->cfg.ext_icsr = true;
592 cpu->cfg.pmp = true;
593 }
594 #endif
595
596 #if defined(CONFIG_KVM)
597 static void riscv_host_cpu_init(Object *obj)
598 {
599 CPURISCVState *env = &RISCV_CPU(obj)->env;
600 #if defined(TARGET_RISCV32)
601 set_misa(env, MXL_RV32, 0);
602 #elif defined(TARGET_RISCV64)
603 set_misa(env, MXL_RV64, 0);
604 #endif
605 riscv_cpu_add_user_properties(obj);
606 }
607 #endif /* CONFIG_KVM */
608
609 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
610 {
611 ObjectClass *oc;
612 char *typename;
613 char **cpuname;
614
615 cpuname = g_strsplit(cpu_model, ",", 1);
616 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
617 oc = object_class_by_name(typename);
618 g_strfreev(cpuname);
619 g_free(typename);
620 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
621 object_class_is_abstract(oc)) {
622 return NULL;
623 }
624 return oc;
625 }
626
627 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
628 {
629 RISCVCPU *cpu = RISCV_CPU(cs);
630 CPURISCVState *env = &cpu->env;
631 int i, j;
632 uint8_t *p;
633
634 #if !defined(CONFIG_USER_ONLY)
635 if (riscv_has_ext(env, RVH)) {
636 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled);
637 }
638 #endif
639 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
640 #ifndef CONFIG_USER_ONLY
641 {
642 static const int dump_csrs[] = {
643 CSR_MHARTID,
644 CSR_MSTATUS,
645 CSR_MSTATUSH,
646 /*
647 * CSR_SSTATUS is intentionally omitted here as its value
648 * can be figured out by looking at CSR_MSTATUS
649 */
650 CSR_HSTATUS,
651 CSR_VSSTATUS,
652 CSR_MIP,
653 CSR_MIE,
654 CSR_MIDELEG,
655 CSR_HIDELEG,
656 CSR_MEDELEG,
657 CSR_HEDELEG,
658 CSR_MTVEC,
659 CSR_STVEC,
660 CSR_VSTVEC,
661 CSR_MEPC,
662 CSR_SEPC,
663 CSR_VSEPC,
664 CSR_MCAUSE,
665 CSR_SCAUSE,
666 CSR_VSCAUSE,
667 CSR_MTVAL,
668 CSR_STVAL,
669 CSR_HTVAL,
670 CSR_MTVAL2,
671 CSR_MSCRATCH,
672 CSR_SSCRATCH,
673 CSR_SATP,
674 CSR_MMTE,
675 CSR_UPMBASE,
676 CSR_UPMMASK,
677 CSR_SPMBASE,
678 CSR_SPMMASK,
679 CSR_MPMBASE,
680 CSR_MPMMASK,
681 };
682
683 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
684 int csrno = dump_csrs[i];
685 target_ulong val = 0;
686 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
687
688 /*
689 * Rely on the smode, hmode, etc, predicates within csr.c
690 * to do the filtering of the registers that are present.
691 */
692 if (res == RISCV_EXCP_NONE) {
693 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
694 csr_ops[csrno].name, val);
695 }
696 }
697 }
698 #endif
699
700 for (i = 0; i < 32; i++) {
701 qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
702 riscv_int_regnames[i], env->gpr[i]);
703 if ((i & 3) == 3) {
704 qemu_fprintf(f, "\n");
705 }
706 }
707 if (flags & CPU_DUMP_FPU) {
708 for (i = 0; i < 32; i++) {
709 qemu_fprintf(f, " %-8s %016" PRIx64,
710 riscv_fpr_regnames[i], env->fpr[i]);
711 if ((i & 3) == 3) {
712 qemu_fprintf(f, "\n");
713 }
714 }
715 }
716 if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
717 static const int dump_rvv_csrs[] = {
718 CSR_VSTART,
719 CSR_VXSAT,
720 CSR_VXRM,
721 CSR_VCSR,
722 CSR_VL,
723 CSR_VTYPE,
724 CSR_VLENB,
725 };
726 for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
727 int csrno = dump_rvv_csrs[i];
728 target_ulong val = 0;
729 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
730
731 /*
732 * Rely on the smode, hmode, etc, predicates within csr.c
733 * to do the filtering of the registers that are present.
734 */
735 if (res == RISCV_EXCP_NONE) {
736 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
737 csr_ops[csrno].name, val);
738 }
739 }
740 uint16_t vlenb = cpu->cfg.vlen >> 3;
741
742 for (i = 0; i < 32; i++) {
743 qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
744 p = (uint8_t *)env->vreg;
745 for (j = vlenb - 1 ; j >= 0; j--) {
746 qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
747 }
748 qemu_fprintf(f, "\n");
749 }
750 }
751 }
752
753 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
754 {
755 RISCVCPU *cpu = RISCV_CPU(cs);
756 CPURISCVState *env = &cpu->env;
757
758 if (env->xl == MXL_RV32) {
759 env->pc = (int32_t)value;
760 } else {
761 env->pc = value;
762 }
763 }
764
765 static vaddr riscv_cpu_get_pc(CPUState *cs)
766 {
767 RISCVCPU *cpu = RISCV_CPU(cs);
768 CPURISCVState *env = &cpu->env;
769
770 /* Match cpu_get_tb_cpu_state. */
771 if (env->xl == MXL_RV32) {
772 return env->pc & UINT32_MAX;
773 }
774 return env->pc;
775 }
776
777 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
778 const TranslationBlock *tb)
779 {
780 if (!(tb_cflags(tb) & CF_PCREL)) {
781 RISCVCPU *cpu = RISCV_CPU(cs);
782 CPURISCVState *env = &cpu->env;
783 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
784
785 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
786
787 if (xl == MXL_RV32) {
788 env->pc = (int32_t) tb->pc;
789 } else {
790 env->pc = tb->pc;
791 }
792 }
793 }
794
795 static bool riscv_cpu_has_work(CPUState *cs)
796 {
797 #ifndef CONFIG_USER_ONLY
798 RISCVCPU *cpu = RISCV_CPU(cs);
799 CPURISCVState *env = &cpu->env;
800 /*
801 * Definition of the WFI instruction requires it to ignore the privilege
802 * mode and delegation registers, but respect individual enables
803 */
804 return riscv_cpu_all_pending(env) != 0;
805 #else
806 return true;
807 #endif
808 }
809
810 static void riscv_restore_state_to_opc(CPUState *cs,
811 const TranslationBlock *tb,
812 const uint64_t *data)
813 {
814 RISCVCPU *cpu = RISCV_CPU(cs);
815 CPURISCVState *env = &cpu->env;
816 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
817 target_ulong pc;
818
819 if (tb_cflags(tb) & CF_PCREL) {
820 pc = (env->pc & TARGET_PAGE_MASK) | data[0];
821 } else {
822 pc = data[0];
823 }
824
825 if (xl == MXL_RV32) {
826 env->pc = (int32_t)pc;
827 } else {
828 env->pc = pc;
829 }
830 env->bins = data[1];
831 }
832
833 static void riscv_cpu_reset_hold(Object *obj)
834 {
835 #ifndef CONFIG_USER_ONLY
836 uint8_t iprio;
837 int i, irq, rdzero;
838 #endif
839 CPUState *cs = CPU(obj);
840 RISCVCPU *cpu = RISCV_CPU(cs);
841 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
842 CPURISCVState *env = &cpu->env;
843
844 if (mcc->parent_phases.hold) {
845 mcc->parent_phases.hold(obj);
846 }
847 #ifndef CONFIG_USER_ONLY
848 env->misa_mxl = env->misa_mxl_max;
849 env->priv = PRV_M;
850 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
851 if (env->misa_mxl > MXL_RV32) {
852 /*
853 * The reset status of SXL/UXL is undefined, but mstatus is WARL
854 * and we must ensure that the value after init is valid for read.
855 */
856 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
857 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
858 if (riscv_has_ext(env, RVH)) {
859 env->vsstatus = set_field(env->vsstatus,
860 MSTATUS64_SXL, env->misa_mxl);
861 env->vsstatus = set_field(env->vsstatus,
862 MSTATUS64_UXL, env->misa_mxl);
863 env->mstatus_hs = set_field(env->mstatus_hs,
864 MSTATUS64_SXL, env->misa_mxl);
865 env->mstatus_hs = set_field(env->mstatus_hs,
866 MSTATUS64_UXL, env->misa_mxl);
867 }
868 }
869 env->mcause = 0;
870 env->miclaim = MIP_SGEIP;
871 env->pc = env->resetvec;
872 env->bins = 0;
873 env->two_stage_lookup = false;
874
875 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
876 (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0);
877 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
878 (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0);
879
880 /* Initialized default priorities of local interrupts. */
881 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
882 iprio = riscv_cpu_default_priority(i);
883 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
884 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
885 env->hviprio[i] = 0;
886 }
887 i = 0;
888 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) {
889 if (!rdzero) {
890 env->hviprio[irq] = env->miprio[irq];
891 }
892 i++;
893 }
894 /* mmte is supposed to have pm.current hardwired to 1 */
895 env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
896 #endif
897 env->xl = riscv_cpu_mxl(env);
898 riscv_cpu_update_mask(env);
899 cs->exception_index = RISCV_EXCP_NONE;
900 env->load_res = -1;
901 set_default_nan_mode(1, &env->fp_status);
902
903 #ifndef CONFIG_USER_ONLY
904 if (cpu->cfg.debug) {
905 riscv_trigger_init(env);
906 }
907
908 if (kvm_enabled()) {
909 kvm_riscv_reset_vcpu(cpu);
910 }
911 #endif
912 }
913
914 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
915 {
916 RISCVCPU *cpu = RISCV_CPU(s);
917 CPURISCVState *env = &cpu->env;
918 info->target_info = &cpu->cfg;
919
920 switch (env->xl) {
921 case MXL_RV32:
922 info->print_insn = print_insn_riscv32;
923 break;
924 case MXL_RV64:
925 info->print_insn = print_insn_riscv64;
926 break;
927 case MXL_RV128:
928 info->print_insn = print_insn_riscv128;
929 break;
930 default:
931 g_assert_not_reached();
932 }
933 }
934
935 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
936 Error **errp)
937 {
938 int vext_version = VEXT_VERSION_1_00_0;
939
940 if (!is_power_of_2(cfg->vlen)) {
941 error_setg(errp, "Vector extension VLEN must be power of 2");
942 return;
943 }
944 if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
945 error_setg(errp,
946 "Vector extension implementation only supports VLEN "
947 "in the range [128, %d]", RV_VLEN_MAX);
948 return;
949 }
950 if (!is_power_of_2(cfg->elen)) {
951 error_setg(errp, "Vector extension ELEN must be power of 2");
952 return;
953 }
954 if (cfg->elen > 64 || cfg->elen < 8) {
955 error_setg(errp,
956 "Vector extension implementation only supports ELEN "
957 "in the range [8, 64]");
958 return;
959 }
960 if (cfg->vext_spec) {
961 if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
962 vext_version = VEXT_VERSION_1_00_0;
963 } else {
964 error_setg(errp, "Unsupported vector spec version '%s'",
965 cfg->vext_spec);
966 return;
967 }
968 } else {
969 qemu_log("vector version is not specified, "
970 "use the default value v1.0\n");
971 }
972 env->vext_ver = vext_version;
973 }
974
975 static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
976 {
977 CPURISCVState *env = &cpu->env;
978 int priv_version = -1;
979
980 if (cpu->cfg.priv_spec) {
981 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
982 priv_version = PRIV_VERSION_1_12_0;
983 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
984 priv_version = PRIV_VERSION_1_11_0;
985 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
986 priv_version = PRIV_VERSION_1_10_0;
987 } else {
988 error_setg(errp,
989 "Unsupported privilege spec version '%s'",
990 cpu->cfg.priv_spec);
991 return;
992 }
993
994 env->priv_ver = priv_version;
995 }
996 }
997
998 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
999 {
1000 CPURISCVState *env = &cpu->env;
1001 int i;
1002
1003 /* Force disable extensions if priv spec version does not match */
1004 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
1005 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
1006 (env->priv_ver < isa_edata_arr[i].min_version)) {
1007 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
1008 #ifndef CONFIG_USER_ONLY
1009 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
1010 " because privilege spec version does not match",
1011 isa_edata_arr[i].name, env->mhartid);
1012 #else
1013 warn_report("disabling %s extension because "
1014 "privilege spec version does not match",
1015 isa_edata_arr[i].name);
1016 #endif
1017 }
1018 }
1019 }
1020
1021 static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
1022 {
1023 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
1024 CPUClass *cc = CPU_CLASS(mcc);
1025 CPURISCVState *env = &cpu->env;
1026
1027 /* Validate that MISA_MXL is set properly. */
1028 switch (env->misa_mxl_max) {
1029 #ifdef TARGET_RISCV64
1030 case MXL_RV64:
1031 case MXL_RV128:
1032 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
1033 break;
1034 #endif
1035 case MXL_RV32:
1036 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
1037 break;
1038 default:
1039 g_assert_not_reached();
1040 }
1041
1042 if (env->misa_mxl_max != env->misa_mxl) {
1043 error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
1044 return;
1045 }
1046 }
1047
1048 /*
1049 * Check consistency between chosen extensions while setting
1050 * cpu->cfg accordingly.
1051 */
1052 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
1053 {
1054 CPURISCVState *env = &cpu->env;
1055 Error *local_err = NULL;
1056
1057 /* Do some ISA extension error checking */
1058 if (riscv_has_ext(env, RVG) &&
1059 !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
1060 riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
1061 riscv_has_ext(env, RVD) &&
1062 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
1063 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
1064 cpu->cfg.ext_icsr = true;
1065 cpu->cfg.ext_ifencei = true;
1066
1067 env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
1068 env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
1069 }
1070
1071 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
1072 error_setg(errp,
1073 "I and E extensions are incompatible");
1074 return;
1075 }
1076
1077 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
1078 error_setg(errp,
1079 "Either I or E extension must be set");
1080 return;
1081 }
1082
1083 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
1084 error_setg(errp,
1085 "Setting S extension without U extension is illegal");
1086 return;
1087 }
1088
1089 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
1090 error_setg(errp,
1091 "H depends on an I base integer ISA with 32 x registers");
1092 return;
1093 }
1094
1095 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
1096 error_setg(errp, "H extension implicitly requires S-mode");
1097 return;
1098 }
1099
1100 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
1101 error_setg(errp, "F extension requires Zicsr");
1102 return;
1103 }
1104
1105 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
1106 error_setg(errp, "Zawrs extension requires A extension");
1107 return;
1108 }
1109
1110 if (cpu->cfg.ext_zfh) {
1111 cpu->cfg.ext_zfhmin = true;
1112 }
1113
1114 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
1115 error_setg(errp, "Zfh/Zfhmin extensions require F extension");
1116 return;
1117 }
1118
1119 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
1120 error_setg(errp, "Zfbfmin extension depends on F extension");
1121 return;
1122 }
1123
1124 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
1125 error_setg(errp, "D extension requires F extension");
1126 return;
1127 }
1128
1129 if (riscv_has_ext(env, RVV)) {
1130 riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
1131 if (local_err != NULL) {
1132 error_propagate(errp, local_err);
1133 return;
1134 }
1135
1136 /* The V vector extension depends on the Zve64d extension */
1137 cpu->cfg.ext_zve64d = true;
1138 }
1139
1140 /* The Zve64d extension depends on the Zve64f extension */
1141 if (cpu->cfg.ext_zve64d) {
1142 cpu->cfg.ext_zve64f = true;
1143 }
1144
1145 /* The Zve64f extension depends on the Zve32f extension */
1146 if (cpu->cfg.ext_zve64f) {
1147 cpu->cfg.ext_zve32f = true;
1148 }
1149
1150 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
1151 error_setg(errp, "Zve64d/V extensions require D extension");
1152 return;
1153 }
1154
1155 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
1156 error_setg(errp, "Zve32f/Zve64f extensions require F extension");
1157 return;
1158 }
1159
1160 if (cpu->cfg.ext_zvfh) {
1161 cpu->cfg.ext_zvfhmin = true;
1162 }
1163
1164 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
1165 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
1166 return;
1167 }
1168
1169 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
1170 error_setg(errp, "Zvfh extensions requires Zfhmin extension");
1171 return;
1172 }
1173
1174 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
1175 error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
1176 return;
1177 }
1178
1179 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
1180 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
1181 return;
1182 }
1183
1184 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
1185 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
1186 return;
1187 }
1188
1189 /* Set the ISA extensions, checks should have happened above */
1190 if (cpu->cfg.ext_zhinx) {
1191 cpu->cfg.ext_zhinxmin = true;
1192 }
1193
1194 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
1195 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
1196 return;
1197 }
1198
1199 if (cpu->cfg.ext_zfinx) {
1200 if (!cpu->cfg.ext_icsr) {
1201 error_setg(errp, "Zfinx extension requires Zicsr");
1202 return;
1203 }
1204 if (riscv_has_ext(env, RVF)) {
1205 error_setg(errp,
1206 "Zfinx cannot be supported together with F extension");
1207 return;
1208 }
1209 }
1210
1211 if (cpu->cfg.ext_zce) {
1212 cpu->cfg.ext_zca = true;
1213 cpu->cfg.ext_zcb = true;
1214 cpu->cfg.ext_zcmp = true;
1215 cpu->cfg.ext_zcmt = true;
1216 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
1217 cpu->cfg.ext_zcf = true;
1218 }
1219 }
1220
1221 if (riscv_has_ext(env, RVC)) {
1222 cpu->cfg.ext_zca = true;
1223 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
1224 cpu->cfg.ext_zcf = true;
1225 }
1226 if (riscv_has_ext(env, RVD)) {
1227 cpu->cfg.ext_zcd = true;
1228 }
1229 }
1230
1231 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
1232 error_setg(errp, "Zcf extension is only relevant to RV32");
1233 return;
1234 }
1235
1236 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
1237 error_setg(errp, "Zcf extension requires F extension");
1238 return;
1239 }
1240
1241 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
1242 error_setg(errp, "Zcd extension requires D extension");
1243 return;
1244 }
1245
1246 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
1247 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
1248 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
1249 "extension");
1250 return;
1251 }
1252
1253 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
1254 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
1255 "Zcd extension");
1256 return;
1257 }
1258
1259 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
1260 error_setg(errp, "Zcmt extension requires Zicsr extension");
1261 return;
1262 }
1263
1264 if (cpu->cfg.ext_zk) {
1265 cpu->cfg.ext_zkn = true;
1266 cpu->cfg.ext_zkr = true;
1267 cpu->cfg.ext_zkt = true;
1268 }
1269
1270 if (cpu->cfg.ext_zkn) {
1271 cpu->cfg.ext_zbkb = true;
1272 cpu->cfg.ext_zbkc = true;
1273 cpu->cfg.ext_zbkx = true;
1274 cpu->cfg.ext_zkne = true;
1275 cpu->cfg.ext_zknd = true;
1276 cpu->cfg.ext_zknh = true;
1277 }
1278
1279 if (cpu->cfg.ext_zks) {
1280 cpu->cfg.ext_zbkb = true;
1281 cpu->cfg.ext_zbkc = true;
1282 cpu->cfg.ext_zbkx = true;
1283 cpu->cfg.ext_zksed = true;
1284 cpu->cfg.ext_zksh = true;
1285 }
1286
1287 /*
1288 * Disable isa extensions based on priv spec after we
1289 * validated and set everything we need.
1290 */
1291 riscv_cpu_disable_priv_spec_isa_exts(cpu);
1292 }
1293
1294 #ifndef CONFIG_USER_ONLY
1295 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
1296 {
1297 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
1298 uint8_t satp_mode_map_max;
1299 uint8_t satp_mode_supported_max =
1300 satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
1301
1302 if (cpu->cfg.satp_mode.map == 0) {
1303 if (cpu->cfg.satp_mode.init == 0) {
1304 /* If unset by the user, we fallback to the default satp mode. */
1305 set_satp_mode_default_map(cpu);
1306 } else {
1307 /*
1308 * Find the lowest level that was disabled and then enable the
1309 * first valid level below which can be found in
1310 * valid_vm_1_10_32/64.
1311 */
1312 for (int i = 1; i < 16; ++i) {
1313 if ((cpu->cfg.satp_mode.init & (1 << i)) &&
1314 (cpu->cfg.satp_mode.supported & (1 << i))) {
1315 for (int j = i - 1; j >= 0; --j) {
1316 if (cpu->cfg.satp_mode.supported & (1 << j)) {
1317 cpu->cfg.satp_mode.map |= (1 << j);
1318 break;
1319 }
1320 }
1321 break;
1322 }
1323 }
1324 }
1325 }
1326
1327 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
1328
1329 /* Make sure the user asked for a supported configuration (HW and qemu) */
1330 if (satp_mode_map_max > satp_mode_supported_max) {
1331 error_setg(errp, "satp_mode %s is higher than hw max capability %s",
1332 satp_mode_str(satp_mode_map_max, rv32),
1333 satp_mode_str(satp_mode_supported_max, rv32));
1334 return;
1335 }
1336
1337 /*
1338 * Make sure the user did not ask for an invalid configuration as per
1339 * the specification.
1340 */
1341 if (!rv32) {
1342 for (int i = satp_mode_map_max - 1; i >= 0; --i) {
1343 if (!(cpu->cfg.satp_mode.map & (1 << i)) &&
1344 (cpu->cfg.satp_mode.init & (1 << i)) &&
1345 (cpu->cfg.satp_mode.supported & (1 << i))) {
1346 error_setg(errp, "cannot disable %s satp mode if %s "
1347 "is enabled", satp_mode_str(i, false),
1348 satp_mode_str(satp_mode_map_max, false));
1349 return;
1350 }
1351 }
1352 }
1353
1354 /* Finally expand the map so that all valid modes are set */
1355 for (int i = satp_mode_map_max - 1; i >= 0; --i) {
1356 if (cpu->cfg.satp_mode.supported & (1 << i)) {
1357 cpu->cfg.satp_mode.map |= (1 << i);
1358 }
1359 }
1360 }
1361 #endif
1362
1363 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
1364 {
1365 #ifndef CONFIG_USER_ONLY
1366 Error *local_err = NULL;
1367
1368 riscv_cpu_satp_mode_finalize(cpu, &local_err);
1369 if (local_err != NULL) {
1370 error_propagate(errp, local_err);
1371 return;
1372 }
1373 #endif
1374 }
1375
1376 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
1377 {
1378 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
1379 error_setg(errp, "H extension requires priv spec 1.12.0");
1380 return;
1381 }
1382 }
1383
1384 static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp)
1385 {
1386 RISCVCPU *cpu = RISCV_CPU(dev);
1387 CPURISCVState *env = &cpu->env;
1388 Error *local_err = NULL;
1389
1390 riscv_cpu_validate_misa_mxl(cpu, &local_err);
1391 if (local_err != NULL) {
1392 error_propagate(errp, local_err);
1393 return;
1394 }
1395
1396 riscv_cpu_validate_priv_spec(cpu, &local_err);
1397 if (local_err != NULL) {
1398 error_propagate(errp, local_err);
1399 return;
1400 }
1401
1402 riscv_cpu_validate_misa_priv(env, &local_err);
1403 if (local_err != NULL) {
1404 error_propagate(errp, local_err);
1405 return;
1406 }
1407
1408 if (cpu->cfg.epmp && !cpu->cfg.pmp) {
1409 /*
1410 * Enhanced PMP should only be available
1411 * on harts with PMP support
1412 */
1413 error_setg(errp, "Invalid configuration: EPMP requires PMP support");
1414 return;
1415 }
1416
1417 riscv_cpu_validate_set_extensions(cpu, &local_err);
1418 if (local_err != NULL) {
1419 error_propagate(errp, local_err);
1420 return;
1421 }
1422
1423 #ifndef CONFIG_USER_ONLY
1424 CPU(dev)->tcg_cflags |= CF_PCREL;
1425
1426 if (cpu->cfg.ext_sstc) {
1427 riscv_timer_init(cpu);
1428 }
1429
1430 if (cpu->cfg.pmu_num) {
1431 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
1432 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1433 riscv_pmu_timer_cb, cpu);
1434 }
1435 }
1436 #endif
1437 }
1438
1439 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
1440 {
1441 CPUState *cs = CPU(dev);
1442 RISCVCPU *cpu = RISCV_CPU(dev);
1443 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
1444 Error *local_err = NULL;
1445
1446 cpu_exec_realizefn(cs, &local_err);
1447 if (local_err != NULL) {
1448 error_propagate(errp, local_err);
1449 return;
1450 }
1451
1452 if (tcg_enabled()) {
1453 riscv_cpu_realize_tcg(dev, &local_err);
1454 if (local_err != NULL) {
1455 error_propagate(errp, local_err);
1456 return;
1457 }
1458 }
1459
1460 riscv_cpu_finalize_features(cpu, &local_err);
1461 if (local_err != NULL) {
1462 error_propagate(errp, local_err);
1463 return;
1464 }
1465
1466 riscv_cpu_register_gdb_regs_for_features(cs);
1467
1468 qemu_init_vcpu(cs);
1469 cpu_reset(cs);
1470
1471 mcc->parent_realize(dev, errp);
1472 }
1473
1474 #ifndef CONFIG_USER_ONLY
1475 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name,
1476 void *opaque, Error **errp)
1477 {
1478 RISCVSATPMap *satp_map = opaque;
1479 uint8_t satp = satp_mode_from_str(name);
1480 bool value;
1481
1482 value = satp_map->map & (1 << satp);
1483
1484 visit_type_bool(v, name, &value, errp);
1485 }
1486
1487 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
1488 void *opaque, Error **errp)
1489 {
1490 RISCVSATPMap *satp_map = opaque;
1491 uint8_t satp = satp_mode_from_str(name);
1492 bool value;
1493
1494 if (!visit_type_bool(v, name, &value, errp)) {
1495 return;
1496 }
1497
1498 satp_map->map = deposit32(satp_map->map, satp, 1, value);
1499 satp_map->init |= 1 << satp;
1500 }
1501
1502 static void riscv_add_satp_mode_properties(Object *obj)
1503 {
1504 RISCVCPU *cpu = RISCV_CPU(obj);
1505
1506 if (cpu->env.misa_mxl == MXL_RV32) {
1507 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp,
1508 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1509 } else {
1510 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp,
1511 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1512 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp,
1513 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1514 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp,
1515 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1516 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp,
1517 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1518 }
1519 }
1520
1521 static void riscv_cpu_set_irq(void *opaque, int irq, int level)
1522 {
1523 RISCVCPU *cpu = RISCV_CPU(opaque);
1524 CPURISCVState *env = &cpu->env;
1525
1526 if (irq < IRQ_LOCAL_MAX) {
1527 switch (irq) {
1528 case IRQ_U_SOFT:
1529 case IRQ_S_SOFT:
1530 case IRQ_VS_SOFT:
1531 case IRQ_M_SOFT:
1532 case IRQ_U_TIMER:
1533 case IRQ_S_TIMER:
1534 case IRQ_VS_TIMER:
1535 case IRQ_M_TIMER:
1536 case IRQ_U_EXT:
1537 case IRQ_VS_EXT:
1538 case IRQ_M_EXT:
1539 if (kvm_enabled()) {
1540 kvm_riscv_set_irq(cpu, irq, level);
1541 } else {
1542 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
1543 }
1544 break;
1545 case IRQ_S_EXT:
1546 if (kvm_enabled()) {
1547 kvm_riscv_set_irq(cpu, irq, level);
1548 } else {
1549 env->external_seip = level;
1550 riscv_cpu_update_mip(env, 1 << irq,
1551 BOOL_TO_MASK(level | env->software_seip));
1552 }
1553 break;
1554 default:
1555 g_assert_not_reached();
1556 }
1557 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
1558 /* Require H-extension for handling guest local interrupts */
1559 if (!riscv_has_ext(env, RVH)) {
1560 g_assert_not_reached();
1561 }
1562
1563 /* Compute bit position in HGEIP CSR */
1564 irq = irq - IRQ_LOCAL_MAX + 1;
1565 if (env->geilen < irq) {
1566 g_assert_not_reached();
1567 }
1568
1569 /* Update HGEIP CSR */
1570 env->hgeip &= ~((target_ulong)1 << irq);
1571 if (level) {
1572 env->hgeip |= (target_ulong)1 << irq;
1573 }
1574
1575 /* Update mip.SGEIP bit */
1576 riscv_cpu_update_mip(env, MIP_SGEIP,
1577 BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
1578 } else {
1579 g_assert_not_reached();
1580 }
1581 }
1582 #endif /* CONFIG_USER_ONLY */
1583
1584 static void riscv_cpu_init(Object *obj)
1585 {
1586 RISCVCPU *cpu = RISCV_CPU(obj);
1587
1588 cpu_set_cpustate_pointers(cpu);
1589
1590 #ifndef CONFIG_USER_ONLY
1591 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
1592 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
1593 #endif /* CONFIG_USER_ONLY */
1594 }
1595
1596 typedef struct RISCVCPUMisaExtConfig {
1597 const char *name;
1598 const char *description;
1599 target_ulong misa_bit;
1600 bool enabled;
1601 } RISCVCPUMisaExtConfig;
1602
1603 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
1604 void *opaque, Error **errp)
1605 {
1606 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
1607 target_ulong misa_bit = misa_ext_cfg->misa_bit;
1608 RISCVCPU *cpu = RISCV_CPU(obj);
1609 CPURISCVState *env = &cpu->env;
1610 bool value;
1611
1612 if (!visit_type_bool(v, name, &value, errp)) {
1613 return;
1614 }
1615
1616 if (value) {
1617 env->misa_ext |= misa_bit;
1618 env->misa_ext_mask |= misa_bit;
1619 } else {
1620 env->misa_ext &= ~misa_bit;
1621 env->misa_ext_mask &= ~misa_bit;
1622 }
1623 }
1624
1625 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
1626 void *opaque, Error **errp)
1627 {
1628 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
1629 target_ulong misa_bit = misa_ext_cfg->misa_bit;
1630 RISCVCPU *cpu = RISCV_CPU(obj);
1631 CPURISCVState *env = &cpu->env;
1632 bool value;
1633
1634 value = env->misa_ext & misa_bit;
1635
1636 visit_type_bool(v, name, &value, errp);
1637 }
1638
1639 typedef struct misa_ext_info {
1640 const char *name;
1641 const char *description;
1642 } MISAExtInfo;
1643
1644 #define MISA_INFO_IDX(_bit) \
1645 __builtin_ctz(_bit)
1646
1647 #define MISA_EXT_INFO(_bit, _propname, _descr) \
1648 [MISA_INFO_IDX(_bit)] = {.name = _propname, .description = _descr}
1649
1650 static const MISAExtInfo misa_ext_info_arr[] = {
1651 MISA_EXT_INFO(RVA, "a", "Atomic instructions"),
1652 MISA_EXT_INFO(RVC, "c", "Compressed instructions"),
1653 MISA_EXT_INFO(RVD, "d", "Double-precision float point"),
1654 MISA_EXT_INFO(RVF, "f", "Single-precision float point"),
1655 MISA_EXT_INFO(RVI, "i", "Base integer instruction set"),
1656 MISA_EXT_INFO(RVE, "e", "Base integer instruction set (embedded)"),
1657 MISA_EXT_INFO(RVM, "m", "Integer multiplication and division"),
1658 MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"),
1659 MISA_EXT_INFO(RVU, "u", "User-level instructions"),
1660 MISA_EXT_INFO(RVH, "h", "Hypervisor"),
1661 MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
1662 MISA_EXT_INFO(RVV, "v", "Vector operations"),
1663 MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
1664 };
1665
1666 static int riscv_validate_misa_info_idx(uint32_t bit)
1667 {
1668 int idx;
1669
1670 /*
1671 * Our lowest valid input (RVA) is 1 and
1672 * __builtin_ctz() is UB with zero.
1673 */
1674 g_assert(bit != 0);
1675 idx = MISA_INFO_IDX(bit);
1676
1677 g_assert(idx < ARRAY_SIZE(misa_ext_info_arr));
1678 return idx;
1679 }
1680
1681 const char *riscv_get_misa_ext_name(uint32_t bit)
1682 {
1683 int idx = riscv_validate_misa_info_idx(bit);
1684 const char *val = misa_ext_info_arr[idx].name;
1685
1686 g_assert(val != NULL);
1687 return val;
1688 }
1689
1690 const char *riscv_get_misa_ext_description(uint32_t bit)
1691 {
1692 int idx = riscv_validate_misa_info_idx(bit);
1693 const char *val = misa_ext_info_arr[idx].description;
1694
1695 g_assert(val != NULL);
1696 return val;
1697 }
1698
1699 #define MISA_CFG(_bit, _enabled) \
1700 {.misa_bit = _bit, .enabled = _enabled}
1701
1702 static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
1703 MISA_CFG(RVA, true),
1704 MISA_CFG(RVC, true),
1705 MISA_CFG(RVD, true),
1706 MISA_CFG(RVF, true),
1707 MISA_CFG(RVI, true),
1708 MISA_CFG(RVE, false),
1709 MISA_CFG(RVM, true),
1710 MISA_CFG(RVS, true),
1711 MISA_CFG(RVU, true),
1712 MISA_CFG(RVH, true),
1713 MISA_CFG(RVJ, false),
1714 MISA_CFG(RVV, false),
1715 MISA_CFG(RVG, false),
1716 };
1717
1718 static void riscv_cpu_add_misa_properties(Object *cpu_obj)
1719 {
1720 int i;
1721
1722 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
1723 RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
1724 int bit = misa_cfg->misa_bit;
1725
1726 misa_cfg->name = riscv_get_misa_ext_name(bit);
1727 misa_cfg->description = riscv_get_misa_ext_description(bit);
1728
1729 /* Check if KVM already created the property */
1730 if (object_property_find(cpu_obj, misa_cfg->name)) {
1731 continue;
1732 }
1733
1734 object_property_add(cpu_obj, misa_cfg->name, "bool",
1735 cpu_get_misa_ext_cfg,
1736 cpu_set_misa_ext_cfg,
1737 NULL, (void *)misa_cfg);
1738 object_property_set_description(cpu_obj, misa_cfg->name,
1739 misa_cfg->description);
1740 object_property_set_bool(cpu_obj, misa_cfg->name,
1741 misa_cfg->enabled, NULL);
1742 }
1743 }
1744
1745 static Property riscv_cpu_extensions[] = {
1746 /* Defaults for standard extensions */
1747 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
1748 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
1749 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
1750 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
1751 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
1752 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
1753 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
1754 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
1755 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
1756 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
1757 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
1758 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
1759 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
1760 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
1761
1762 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
1763 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
1764 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
1765 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
1766
1767 DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
1768 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
1769 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
1770 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
1771 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
1772
1773 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
1774 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
1775 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
1776 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
1777 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
1778 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
1779 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
1780 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
1781 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
1782 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
1783 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
1784 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
1785 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
1786 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
1787 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
1788 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
1789 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
1790
1791 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
1792 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
1793 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
1794 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
1795
1796 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
1797 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
1798 DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
1799 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
1800
1801 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
1802
1803 DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false),
1804 DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false),
1805 DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false),
1806 DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false),
1807 DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
1808 DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
1809 DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
1810
1811 /* Vendor-specific custom extensions */
1812 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
1813 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
1814 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
1815 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
1816 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
1817 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
1818 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false),
1819 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
1820 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
1821 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
1822 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
1823 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
1824
1825 /* These are experimental so mark with 'x-' */
1826 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
1827
1828 /* ePMP 0.9.3 */
1829 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
1830 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
1831 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
1832
1833 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
1834 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
1835
1836 DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false),
1837 DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false),
1838 DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
1839
1840 DEFINE_PROP_END_OF_LIST(),
1841 };
1842
1843 /*
1844 * Add CPU properties with user-facing flags.
1845 *
1846 * This will overwrite existing env->misa_ext values with the
1847 * defaults set via riscv_cpu_add_misa_properties().
1848 */
1849 static void riscv_cpu_add_user_properties(Object *obj)
1850 {
1851 Property *prop;
1852 DeviceState *dev = DEVICE(obj);
1853
1854 #ifndef CONFIG_USER_ONLY
1855 riscv_add_satp_mode_properties(obj);
1856
1857 if (kvm_enabled()) {
1858 kvm_riscv_init_user_properties(obj);
1859 }
1860 #endif
1861
1862 riscv_cpu_add_misa_properties(obj);
1863
1864 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
1865 #ifndef CONFIG_USER_ONLY
1866 if (kvm_enabled()) {
1867 /* Check if KVM created the property already */
1868 if (object_property_find(obj, prop->name)) {
1869 continue;
1870 }
1871 }
1872 #endif
1873 qdev_property_add_static(dev, prop);
1874 }
1875 }
1876
1877 static Property riscv_cpu_properties[] = {
1878 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
1879
1880 #ifndef CONFIG_USER_ONLY
1881 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
1882 #endif
1883
1884 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
1885
1886 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
1887 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
1888
1889 /*
1890 * write_misa() is marked as experimental for now so mark
1891 * it with -x and default to 'false'.
1892 */
1893 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
1894 DEFINE_PROP_END_OF_LIST(),
1895 };
1896
1897 static gchar *riscv_gdb_arch_name(CPUState *cs)
1898 {
1899 RISCVCPU *cpu = RISCV_CPU(cs);
1900 CPURISCVState *env = &cpu->env;
1901
1902 switch (riscv_cpu_mxl(env)) {
1903 case MXL_RV32:
1904 return g_strdup("riscv:rv32");
1905 case MXL_RV64:
1906 case MXL_RV128:
1907 return g_strdup("riscv:rv64");
1908 default:
1909 g_assert_not_reached();
1910 }
1911 }
1912
1913 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
1914 {
1915 RISCVCPU *cpu = RISCV_CPU(cs);
1916
1917 if (strcmp(xmlname, "riscv-csr.xml") == 0) {
1918 return cpu->dyn_csr_xml;
1919 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) {
1920 return cpu->dyn_vreg_xml;
1921 }
1922
1923 return NULL;
1924 }
1925
1926 #ifndef CONFIG_USER_ONLY
1927 static int64_t riscv_get_arch_id(CPUState *cs)
1928 {
1929 RISCVCPU *cpu = RISCV_CPU(cs);
1930
1931 return cpu->env.mhartid;
1932 }
1933
1934 #include "hw/core/sysemu-cpu-ops.h"
1935
1936 static const struct SysemuCPUOps riscv_sysemu_ops = {
1937 .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
1938 .write_elf64_note = riscv_cpu_write_elf64_note,
1939 .write_elf32_note = riscv_cpu_write_elf32_note,
1940 .legacy_vmsd = &vmstate_riscv_cpu,
1941 };
1942 #endif
1943
1944 #include "hw/core/tcg-cpu-ops.h"
1945
1946 static const struct TCGCPUOps riscv_tcg_ops = {
1947 .initialize = riscv_translate_init,
1948 .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
1949 .restore_state_to_opc = riscv_restore_state_to_opc,
1950
1951 #ifndef CONFIG_USER_ONLY
1952 .tlb_fill = riscv_cpu_tlb_fill,
1953 .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
1954 .do_interrupt = riscv_cpu_do_interrupt,
1955 .do_transaction_failed = riscv_cpu_do_transaction_failed,
1956 .do_unaligned_access = riscv_cpu_do_unaligned_access,
1957 .debug_excp_handler = riscv_cpu_debug_excp_handler,
1958 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
1959 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
1960 #endif /* !CONFIG_USER_ONLY */
1961 };
1962
1963 static bool riscv_cpu_is_dynamic(Object *cpu_obj)
1964 {
1965 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
1966 }
1967
1968 static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
1969 void *opaque, Error **errp)
1970 {
1971 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
1972 RISCVCPU *cpu = RISCV_CPU(obj);
1973 uint32_t prev_val = cpu->cfg.mvendorid;
1974 uint32_t value;
1975
1976 if (!visit_type_uint32(v, name, &value, errp)) {
1977 return;
1978 }
1979
1980 if (!dynamic_cpu && prev_val != value) {
1981 error_setg(errp, "Unable to change %s mvendorid (0x%x)",
1982 object_get_typename(obj), prev_val);
1983 return;
1984 }
1985
1986 cpu->cfg.mvendorid = value;
1987 }
1988
1989 static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name,
1990 void *opaque, Error **errp)
1991 {
1992 bool value = RISCV_CPU(obj)->cfg.mvendorid;
1993
1994 visit_type_bool(v, name, &value, errp);
1995 }
1996
1997 static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name,
1998 void *opaque, Error **errp)
1999 {
2000 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
2001 RISCVCPU *cpu = RISCV_CPU(obj);
2002 uint64_t prev_val = cpu->cfg.mimpid;
2003 uint64_t value;
2004
2005 if (!visit_type_uint64(v, name, &value, errp)) {
2006 return;
2007 }
2008
2009 if (!dynamic_cpu && prev_val != value) {
2010 error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")",
2011 object_get_typename(obj), prev_val);
2012 return;
2013 }
2014
2015 cpu->cfg.mimpid = value;
2016 }
2017
2018 static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name,
2019 void *opaque, Error **errp)
2020 {
2021 bool value = RISCV_CPU(obj)->cfg.mimpid;
2022
2023 visit_type_bool(v, name, &value, errp);
2024 }
2025
2026 static void cpu_set_marchid(Object *obj, Visitor *v, const char *name,
2027 void *opaque, Error **errp)
2028 {
2029 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
2030 RISCVCPU *cpu = RISCV_CPU(obj);
2031 uint64_t prev_val = cpu->cfg.marchid;
2032 uint64_t value, invalid_val;
2033 uint32_t mxlen = 0;
2034
2035 if (!visit_type_uint64(v, name, &value, errp)) {
2036 return;
2037 }
2038
2039 if (!dynamic_cpu && prev_val != value) {
2040 error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")",
2041 object_get_typename(obj), prev_val);
2042 return;
2043 }
2044
2045 switch (riscv_cpu_mxl(&cpu->env)) {
2046 case MXL_RV32:
2047 mxlen = 32;
2048 break;
2049 case MXL_RV64:
2050 case MXL_RV128:
2051 mxlen = 64;
2052 break;
2053 default:
2054 g_assert_not_reached();
2055 }
2056
2057 invalid_val = 1LL << (mxlen - 1);
2058
2059 if (value == invalid_val) {
2060 error_setg(errp, "Unable to set marchid with MSB (%u) bit set "
2061 "and the remaining bits zero", mxlen);
2062 return;
2063 }
2064
2065 cpu->cfg.marchid = value;
2066 }
2067
2068 static void cpu_get_marchid(Object *obj, Visitor *v, const char *name,
2069 void *opaque, Error **errp)
2070 {
2071 bool value = RISCV_CPU(obj)->cfg.marchid;
2072
2073 visit_type_bool(v, name, &value, errp);
2074 }
2075
2076 static void riscv_cpu_class_init(ObjectClass *c, void *data)
2077 {
2078 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
2079 CPUClass *cc = CPU_CLASS(c);
2080 DeviceClass *dc = DEVICE_CLASS(c);
2081 ResettableClass *rc = RESETTABLE_CLASS(c);
2082
2083 device_class_set_parent_realize(dc, riscv_cpu_realize,
2084 &mcc->parent_realize);
2085
2086 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,
2087 &mcc->parent_phases);
2088
2089 cc->class_by_name = riscv_cpu_class_by_name;
2090 cc->has_work = riscv_cpu_has_work;
2091 cc->dump_state = riscv_cpu_dump_state;
2092 cc->set_pc = riscv_cpu_set_pc;
2093 cc->get_pc = riscv_cpu_get_pc;
2094 cc->gdb_read_register = riscv_cpu_gdb_read_register;
2095 cc->gdb_write_register = riscv_cpu_gdb_write_register;
2096 cc->gdb_num_core_regs = 33;
2097 cc->gdb_stop_before_watchpoint = true;
2098 cc->disas_set_info = riscv_cpu_disas_set_info;
2099 #ifndef CONFIG_USER_ONLY
2100 cc->sysemu_ops = &riscv_sysemu_ops;
2101 cc->get_arch_id = riscv_get_arch_id;
2102 #endif
2103 cc->gdb_arch_name = riscv_gdb_arch_name;
2104 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
2105 cc->tcg_ops = &riscv_tcg_ops;
2106
2107 object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
2108 cpu_set_mvendorid, NULL, NULL);
2109
2110 object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid,
2111 cpu_set_mimpid, NULL, NULL);
2112
2113 object_class_property_add(c, "marchid", "uint64", cpu_get_marchid,
2114 cpu_set_marchid, NULL, NULL);
2115
2116 device_class_set_props(dc, riscv_cpu_properties);
2117 }
2118
2119 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
2120 int max_str_len)
2121 {
2122 char *old = *isa_str;
2123 char *new = *isa_str;
2124 int i;
2125
2126 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
2127 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
2128 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
2129 g_free(old);
2130 old = new;
2131 }
2132 }
2133
2134 *isa_str = new;
2135 }
2136
2137 char *riscv_isa_string(RISCVCPU *cpu)
2138 {
2139 int i;
2140 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts);
2141 char *isa_str = g_new(char, maxlen);
2142 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
2143 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
2144 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
2145 *p++ = qemu_tolower(riscv_single_letter_exts[i]);
2146 }
2147 }
2148 *p = '\0';
2149 if (!cpu->cfg.short_isa_string) {
2150 riscv_isa_string_ext(cpu, &isa_str, maxlen);
2151 }
2152 return isa_str;
2153 }
2154
2155 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
2156 {
2157 ObjectClass *class_a = (ObjectClass *)a;
2158 ObjectClass *class_b = (ObjectClass *)b;
2159 const char *name_a, *name_b;
2160
2161 name_a = object_class_get_name(class_a);
2162 name_b = object_class_get_name(class_b);
2163 return strcmp(name_a, name_b);
2164 }
2165
2166 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
2167 {
2168 const char *typename = object_class_get_name(OBJECT_CLASS(data));
2169 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
2170
2171 qemu_printf("%.*s\n", len, typename);
2172 }
2173
2174 void riscv_cpu_list(void)
2175 {
2176 GSList *list;
2177
2178 list = object_class_get_list(TYPE_RISCV_CPU, false);
2179 list = g_slist_sort(list, riscv_cpu_list_compare);
2180 g_slist_foreach(list, riscv_cpu_list_entry, NULL);
2181 g_slist_free(list);
2182 }
2183
2184 #define DEFINE_CPU(type_name, initfn) \
2185 { \
2186 .name = type_name, \
2187 .parent = TYPE_RISCV_CPU, \
2188 .instance_init = initfn \
2189 }
2190
2191 #define DEFINE_DYNAMIC_CPU(type_name, initfn) \
2192 { \
2193 .name = type_name, \
2194 .parent = TYPE_RISCV_DYNAMIC_CPU, \
2195 .instance_init = initfn \
2196 }
2197
2198 static const TypeInfo riscv_cpu_type_infos[] = {
2199 {
2200 .name = TYPE_RISCV_CPU,
2201 .parent = TYPE_CPU,
2202 .instance_size = sizeof(RISCVCPU),
2203 .instance_align = __alignof__(RISCVCPU),
2204 .instance_init = riscv_cpu_init,
2205 .abstract = true,
2206 .class_size = sizeof(RISCVCPUClass),
2207 .class_init = riscv_cpu_class_init,
2208 },
2209 {
2210 .name = TYPE_RISCV_DYNAMIC_CPU,
2211 .parent = TYPE_RISCV_CPU,
2212 .abstract = true,
2213 },
2214 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
2215 #if defined(CONFIG_KVM)
2216 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
2217 #endif
2218 #if defined(TARGET_RISCV32)
2219 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
2220 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
2221 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
2222 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
2223 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
2224 #elif defined(TARGET_RISCV64)
2225 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
2226 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
2227 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
2228 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
2229 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
2230 DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
2231 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
2232 #endif
2233 };
2234
2235 DEFINE_TYPES(riscv_cpu_type_infos)
AR7 emulation for QEMU