2 * QEMU model of the Milkymist UART block.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 * Specification available at:
21 * http://milkymist.walle.cc/socdoc/uart.pdf
24 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
28 #include "chardev/char-fe.h"
29 #include "qemu/error-report.h"
30 #include "qemu/module.h"
48 CTRL_RX_IRQ_EN
= (1<<0),
49 CTRL_TX_IRQ_EN
= (1<<1),
50 CTRL_THRU_EN
= (1<<2),
54 DBG_BREAK_EN
= (1<<0),
57 #define TYPE_MILKYMIST_UART "milkymist-uart"
58 #define MILKYMIST_UART(obj) \
59 OBJECT_CHECK(MilkymistUartState, (obj), TYPE_MILKYMIST_UART)
61 struct MilkymistUartState
{
62 SysBusDevice parent_obj
;
64 MemoryRegion regs_region
;
70 typedef struct MilkymistUartState MilkymistUartState
;
72 static void uart_update_irq(MilkymistUartState
*s
)
74 int rx_event
= s
->regs
[R_STAT
] & STAT_RX_EVT
;
75 int tx_event
= s
->regs
[R_STAT
] & STAT_TX_EVT
;
76 int rx_irq_en
= s
->regs
[R_CTRL
] & CTRL_RX_IRQ_EN
;
77 int tx_irq_en
= s
->regs
[R_CTRL
] & CTRL_TX_IRQ_EN
;
79 if ((rx_irq_en
&& rx_event
) || (tx_irq_en
&& tx_event
)) {
80 trace_milkymist_uart_raise_irq();
81 qemu_irq_raise(s
->irq
);
83 trace_milkymist_uart_lower_irq();
84 qemu_irq_lower(s
->irq
);
88 static uint64_t uart_read(void *opaque
, hwaddr addr
,
91 MilkymistUartState
*s
= opaque
;
107 error_report("milkymist_uart: read access to unknown register 0x"
108 TARGET_FMT_plx
, addr
<< 2);
112 trace_milkymist_uart_memory_read(addr
<< 2, r
);
117 static void uart_write(void *opaque
, hwaddr addr
, uint64_t value
,
120 MilkymistUartState
*s
= opaque
;
121 unsigned char ch
= value
;
123 trace_milkymist_uart_memory_write(addr
, value
);
128 qemu_chr_fe_write_all(&s
->chr
, &ch
, 1);
129 s
->regs
[R_STAT
] |= STAT_TX_EVT
;
134 s
->regs
[addr
] = value
;
138 /* write one to clear bits */
139 s
->regs
[addr
] &= ~(value
& (STAT_RX_EVT
| STAT_TX_EVT
));
140 qemu_chr_fe_accept_input(&s
->chr
);
144 error_report("milkymist_uart: write access to unknown register 0x"
145 TARGET_FMT_plx
, addr
<< 2);
152 static const MemoryRegionOps uart_mmio_ops
= {
156 .min_access_size
= 4,
157 .max_access_size
= 4,
159 .endianness
= DEVICE_NATIVE_ENDIAN
,
162 static void uart_rx(void *opaque
, const uint8_t *buf
, int size
)
164 MilkymistUartState
*s
= opaque
;
166 assert(!(s
->regs
[R_STAT
] & STAT_RX_EVT
));
168 s
->regs
[R_STAT
] |= STAT_RX_EVT
;
169 s
->regs
[R_RXTX
] = *buf
;
174 static int uart_can_rx(void *opaque
)
176 MilkymistUartState
*s
= opaque
;
178 return !(s
->regs
[R_STAT
] & STAT_RX_EVT
);
181 static void uart_event(void *opaque
, int event
)
185 static void milkymist_uart_reset(DeviceState
*d
)
187 MilkymistUartState
*s
= MILKYMIST_UART(d
);
190 for (i
= 0; i
< R_MAX
; i
++) {
194 /* THRE is always set */
195 s
->regs
[R_STAT
] = STAT_THRE
;
198 static void milkymist_uart_realize(DeviceState
*dev
, Error
**errp
)
200 MilkymistUartState
*s
= MILKYMIST_UART(dev
);
202 qemu_chr_fe_set_handlers(&s
->chr
, uart_can_rx
, uart_rx
,
203 uart_event
, NULL
, s
, NULL
, true);
206 static void milkymist_uart_init(Object
*obj
)
208 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
209 MilkymistUartState
*s
= MILKYMIST_UART(obj
);
211 sysbus_init_irq(sbd
, &s
->irq
);
213 memory_region_init_io(&s
->regs_region
, OBJECT(s
), &uart_mmio_ops
, s
,
214 "milkymist-uart", R_MAX
* 4);
215 sysbus_init_mmio(sbd
, &s
->regs_region
);
218 static const VMStateDescription vmstate_milkymist_uart
= {
219 .name
= "milkymist-uart",
221 .minimum_version_id
= 1,
222 .fields
= (VMStateField
[]) {
223 VMSTATE_UINT32_ARRAY(regs
, MilkymistUartState
, R_MAX
),
224 VMSTATE_END_OF_LIST()
228 static Property milkymist_uart_properties
[] = {
229 DEFINE_PROP_CHR("chardev", MilkymistUartState
, chr
),
230 DEFINE_PROP_END_OF_LIST(),
233 static void milkymist_uart_class_init(ObjectClass
*klass
, void *data
)
235 DeviceClass
*dc
= DEVICE_CLASS(klass
);
237 dc
->realize
= milkymist_uart_realize
;
238 dc
->reset
= milkymist_uart_reset
;
239 dc
->vmsd
= &vmstate_milkymist_uart
;
240 dc
->props
= milkymist_uart_properties
;
243 static const TypeInfo milkymist_uart_info
= {
244 .name
= TYPE_MILKYMIST_UART
,
245 .parent
= TYPE_SYS_BUS_DEVICE
,
246 .instance_size
= sizeof(MilkymistUartState
),
247 .instance_init
= milkymist_uart_init
,
248 .class_init
= milkymist_uart_class_init
,
251 static void milkymist_uart_register_types(void)
253 type_register_static(&milkymist_uart_info
);
256 type_init(milkymist_uart_register_types
)