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pc: acpi-build: reserve PCIHP MMIO resources
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob4d5d7e3d18d03c10d1612359022cce64b23dbeb4
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "acpi-build.h"
24 #include <stddef.h>
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/range.h"
30 #include "qemu/error-report.h"
31 #include "hw/pci/pci.h"
32 #include "qom/cpu.h"
33 #include "hw/i386/pc.h"
34 #include "target-i386/cpu.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/i386/acpi-defs.h"
37 #include "hw/acpi/acpi.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/loader.h"
41 #include "hw/isa/isa.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45
46 /* Supported chipsets: */
47 #include "hw/acpi/piix4.h"
48 #include "hw/acpi/pcihp.h"
49 #include "hw/i386/ich9.h"
50 #include "hw/pci/pci_bus.h"
51 #include "hw/pci-host/q35.h"
52 #include "hw/i386/intel_iommu.h"
53
54 #include "hw/i386/q35-acpi-dsdt.hex"
55 #include "hw/i386/acpi-dsdt.hex"
56
57 #include "hw/acpi/aml-build.h"
58
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61 #include "exec/ram_addr.h"
62
63 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
64 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
65 * a little bit, there should be plenty of free space since the DSDT
66 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
67 */
68 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
69 #define ACPI_BUILD_ALIGN_SIZE 0x1000
70
71 #define ACPI_BUILD_TABLE_SIZE 0x20000
72
73 /* Reserve RAM space for tables: add another order of magnitude. */
74 #define ACPI_BUILD_TABLE_MAX_SIZE 0x200000
75
76 /* #define DEBUG_ACPI_BUILD */
77 #ifdef DEBUG_ACPI_BUILD
78 #define ACPI_BUILD_DPRINTF(fmt, ...) \
79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
80 #else
81 #define ACPI_BUILD_DPRINTF(fmt, ...)
82 #endif
83
84 typedef struct AcpiCpuInfo {
85 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
86 } AcpiCpuInfo;
87
88 typedef struct AcpiMcfgInfo {
89 uint64_t mcfg_base;
90 uint32_t mcfg_size;
91 } AcpiMcfgInfo;
92
93 typedef struct AcpiPmInfo {
94 bool s3_disabled;
95 bool s4_disabled;
96 bool pcihp_bridge_en;
97 uint8_t s4_val;
98 uint16_t sci_int;
99 uint8_t acpi_enable_cmd;
100 uint8_t acpi_disable_cmd;
101 uint32_t gpe0_blk;
102 uint32_t gpe0_blk_len;
103 uint32_t io_base;
104 uint16_t cpu_hp_io_base;
105 uint16_t cpu_hp_io_len;
106 uint16_t mem_hp_io_base;
107 uint16_t mem_hp_io_len;
108 uint16_t pcihp_io_base;
109 uint16_t pcihp_io_len;
110 } AcpiPmInfo;
111
112 typedef struct AcpiMiscInfo {
113 bool has_hpet;
114 bool has_tpm;
115 DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
116 const unsigned char *dsdt_code;
117 unsigned dsdt_size;
118 uint16_t pvpanic_port;
119 } AcpiMiscInfo;
120
121 typedef struct AcpiBuildPciBusHotplugState {
122 GArray *device_table;
123 GArray *notify_table;
124 struct AcpiBuildPciBusHotplugState *parent;
125 bool pcihp_bridge_en;
126 } AcpiBuildPciBusHotplugState;
127
128 static void acpi_get_dsdt(AcpiMiscInfo *info)
129 {
130 uint16_t *applesmc_sta;
131 Object *piix = piix4_pm_find();
132 Object *lpc = ich9_lpc_find();
133 assert(!!piix != !!lpc);
134
135 if (piix) {
136 info->dsdt_code = AcpiDsdtAmlCode;
137 info->dsdt_size = sizeof AcpiDsdtAmlCode;
138 applesmc_sta = piix_dsdt_applesmc_sta;
139 }
140 if (lpc) {
141 info->dsdt_code = Q35AcpiDsdtAmlCode;
142 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
143 applesmc_sta = q35_dsdt_applesmc_sta;
144 }
145
146 /* Patch in appropriate value for AppleSMC _STA */
147 *(uint8_t *)(info->dsdt_code + *applesmc_sta) =
148 applesmc_find() ? 0x0b : 0x00;
149 }
150
151 static
152 int acpi_add_cpu_info(Object *o, void *opaque)
153 {
154 AcpiCpuInfo *cpu = opaque;
155 uint64_t apic_id;
156
157 if (object_dynamic_cast(o, TYPE_CPU)) {
158 apic_id = object_property_get_int(o, "apic-id", NULL);
159 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
160
161 set_bit(apic_id, cpu->found_cpus);
162 }
163
164 object_child_foreach(o, acpi_add_cpu_info, opaque);
165 return 0;
166 }
167
168 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
169 {
170 Object *root = object_get_root();
171
172 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
173 object_child_foreach(root, acpi_add_cpu_info, cpu);
174 }
175
176 static void acpi_get_pm_info(AcpiPmInfo *pm)
177 {
178 Object *piix = piix4_pm_find();
179 Object *lpc = ich9_lpc_find();
180 Object *obj = NULL;
181 QObject *o;
182
183 pm->pcihp_io_base = 0;
184 pm->pcihp_io_len = 0;
185 if (piix) {
186 obj = piix;
187 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
188 pm->pcihp_io_base =
189 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
190 pm->pcihp_io_len =
191 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
192 }
193 if (lpc) {
194 obj = lpc;
195 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
196 }
197 assert(obj);
198
199 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
200 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
201 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
202
203 /* Fill in optional s3/s4 related properties */
204 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
205 if (o) {
206 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
207 } else {
208 pm->s3_disabled = false;
209 }
210 qobject_decref(o);
211 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
212 if (o) {
213 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
214 } else {
215 pm->s4_disabled = false;
216 }
217 qobject_decref(o);
218 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
219 if (o) {
220 pm->s4_val = qint_get_int(qobject_to_qint(o));
221 } else {
222 pm->s4_val = false;
223 }
224 qobject_decref(o);
225
226 /* Fill in mandatory properties */
227 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
228
229 pm->acpi_enable_cmd = object_property_get_int(obj,
230 ACPI_PM_PROP_ACPI_ENABLE_CMD,
231 NULL);
232 pm->acpi_disable_cmd = object_property_get_int(obj,
233 ACPI_PM_PROP_ACPI_DISABLE_CMD,
234 NULL);
235 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
236 NULL);
237 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
238 NULL);
239 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
240 NULL);
241 pm->pcihp_bridge_en =
242 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
243 NULL);
244 }
245
246 static void acpi_get_misc_info(AcpiMiscInfo *info)
247 {
248 info->has_hpet = hpet_find();
249 info->has_tpm = tpm_find();
250 info->pvpanic_port = pvpanic_port();
251 }
252
253 static void acpi_get_pci_info(PcPciInfo *info)
254 {
255 Object *pci_host;
256 bool ambiguous;
257
258 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
259 g_assert(!ambiguous);
260 g_assert(pci_host);
261
262 info->w32.begin = object_property_get_int(pci_host,
263 PCI_HOST_PROP_PCI_HOLE_START,
264 NULL);
265 info->w32.end = object_property_get_int(pci_host,
266 PCI_HOST_PROP_PCI_HOLE_END,
267 NULL);
268 info->w64.begin = object_property_get_int(pci_host,
269 PCI_HOST_PROP_PCI_HOLE64_START,
270 NULL);
271 info->w64.end = object_property_get_int(pci_host,
272 PCI_HOST_PROP_PCI_HOLE64_END,
273 NULL);
274 }
275
276 #define ACPI_BUILD_APPNAME "Bochs"
277 #define ACPI_BUILD_APPNAME6 "BOCHS "
278 #define ACPI_BUILD_APPNAME4 "BXPC"
279
280 #define ACPI_BUILD_TABLE_FILE "etc/acpi/tables"
281 #define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp"
282 #define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log"
283
284 static void
285 build_header(GArray *linker, GArray *table_data,
286 AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
287 {
288 memcpy(&h->signature, sig, 4);
289 h->length = cpu_to_le32(len);
290 h->revision = rev;
291 memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6);
292 memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4);
293 memcpy(h->oem_table_id + 4, sig, 4);
294 h->oem_revision = cpu_to_le32(1);
295 memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4);
296 h->asl_compiler_revision = cpu_to_le32(1);
297 h->checksum = 0;
298 /* Checksum to be filled in by Guest linker */
299 bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE,
300 table_data->data, h, len, &h->checksum);
301 }
302
303 static GArray *build_alloc_method(const char *name, uint8_t arg_count)
304 {
305 GArray *method = build_alloc_array();
306
307 build_append_namestring(method, "%s", name);
308 build_append_byte(method, arg_count); /* MethodFlags: ArgCount */
309
310 return method;
311 }
312
313 static void build_append_and_cleanup_method(GArray *device, GArray *method)
314 {
315 uint8_t op = 0x14; /* MethodOp */
316
317 build_package(method, op);
318
319 build_append_array(device, method);
320 build_free_array(method);
321 }
322
323 /* End here */
324 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
325
326 static inline void *acpi_data_push(GArray *table_data, unsigned size)
327 {
328 unsigned off = table_data->len;
329 g_array_set_size(table_data, off + size);
330 return table_data->data + off;
331 }
332
333 static unsigned acpi_data_len(GArray *table)
334 {
335 #if GLIB_CHECK_VERSION(2, 22, 0)
336 assert(g_array_get_element_size(table) == 1);
337 #endif
338 return table->len;
339 }
340
341 static void acpi_align_size(GArray *blob, unsigned align)
342 {
343 /* Align size to multiple of given size. This reduces the chance
344 * we need to change size in the future (breaking cross version migration).
345 */
346 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
347 }
348
349 /* Set a value within table in a safe manner */
350 #define ACPI_BUILD_SET_LE(table, size, off, bits, val) \
351 do { \
352 uint64_t ACPI_BUILD_SET_LE_val = cpu_to_le64(val); \
353 memcpy(acpi_data_get_ptr(table, size, off, \
354 (bits) / BITS_PER_BYTE), \
355 &ACPI_BUILD_SET_LE_val, \
356 (bits) / BITS_PER_BYTE); \
357 } while (0)
358
359 static inline void *acpi_data_get_ptr(uint8_t *table_data, unsigned table_size,
360 unsigned off, unsigned size)
361 {
362 assert(off + size > off);
363 assert(off + size <= table_size);
364 return table_data + off;
365 }
366
367 static inline void acpi_add_table(GArray *table_offsets, GArray *table_data)
368 {
369 uint32_t offset = cpu_to_le32(table_data->len);
370 g_array_append_val(table_offsets, offset);
371 }
372
373 /* FACS */
374 static void
375 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
376 {
377 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
378 memcpy(&facs->signature, "FACS", 4);
379 facs->length = cpu_to_le32(sizeof(*facs));
380 }
381
382 /* Load chipset information in FADT */
383 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
384 {
385 fadt->model = 1;
386 fadt->reserved1 = 0;
387 fadt->sci_int = cpu_to_le16(pm->sci_int);
388 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
389 fadt->acpi_enable = pm->acpi_enable_cmd;
390 fadt->acpi_disable = pm->acpi_disable_cmd;
391 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
392 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
393 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
394 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
395 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
396 /* EVT, CNT, TMR length matches hw/acpi/core.c */
397 fadt->pm1_evt_len = 4;
398 fadt->pm1_cnt_len = 2;
399 fadt->pm_tmr_len = 4;
400 fadt->gpe0_blk_len = pm->gpe0_blk_len;
401 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
402 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
403 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
404 (1 << ACPI_FADT_F_PROC_C1) |
405 (1 << ACPI_FADT_F_SLP_BUTTON) |
406 (1 << ACPI_FADT_F_RTC_S4));
407 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
408 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
409 * For more than 8 CPUs, "Clustered Logical" mode has to be used
410 */
411 if (max_cpus > 8) {
412 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
413 }
414 }
415
416
417 /* FADT */
418 static void
419 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
420 unsigned facs, unsigned dsdt)
421 {
422 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
423
424 fadt->firmware_ctrl = cpu_to_le32(facs);
425 /* FACS address to be filled by Guest linker */
426 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
427 ACPI_BUILD_TABLE_FILE,
428 table_data, &fadt->firmware_ctrl,
429 sizeof fadt->firmware_ctrl);
430
431 fadt->dsdt = cpu_to_le32(dsdt);
432 /* DSDT address to be filled by Guest linker */
433 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
434 ACPI_BUILD_TABLE_FILE,
435 table_data, &fadt->dsdt,
436 sizeof fadt->dsdt);
437
438 fadt_setup(fadt, pm);
439
440 build_header(linker, table_data,
441 (void *)fadt, "FACP", sizeof(*fadt), 1);
442 }
443
444 static void
445 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu,
446 PcGuestInfo *guest_info)
447 {
448 int madt_start = table_data->len;
449
450 AcpiMultipleApicTable *madt;
451 AcpiMadtIoApic *io_apic;
452 AcpiMadtIntsrcovr *intsrcovr;
453 AcpiMadtLocalNmi *local_nmi;
454 int i;
455
456 madt = acpi_data_push(table_data, sizeof *madt);
457 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
458 madt->flags = cpu_to_le32(1);
459
460 for (i = 0; i < guest_info->apic_id_limit; i++) {
461 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
462 apic->type = ACPI_APIC_PROCESSOR;
463 apic->length = sizeof(*apic);
464 apic->processor_id = i;
465 apic->local_apic_id = i;
466 if (test_bit(i, cpu->found_cpus)) {
467 apic->flags = cpu_to_le32(1);
468 } else {
469 apic->flags = cpu_to_le32(0);
470 }
471 }
472 io_apic = acpi_data_push(table_data, sizeof *io_apic);
473 io_apic->type = ACPI_APIC_IO;
474 io_apic->length = sizeof(*io_apic);
475 #define ACPI_BUILD_IOAPIC_ID 0x0
476 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
477 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
478 io_apic->interrupt = cpu_to_le32(0);
479
480 if (guest_info->apic_xrupt_override) {
481 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
482 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
483 intsrcovr->length = sizeof(*intsrcovr);
484 intsrcovr->source = 0;
485 intsrcovr->gsi = cpu_to_le32(2);
486 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
487 }
488 for (i = 1; i < 16; i++) {
489 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
490 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
491 /* No need for a INT source override structure. */
492 continue;
493 }
494 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
495 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
496 intsrcovr->length = sizeof(*intsrcovr);
497 intsrcovr->source = i;
498 intsrcovr->gsi = cpu_to_le32(i);
499 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
500 }
501
502 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
503 local_nmi->type = ACPI_APIC_LOCAL_NMI;
504 local_nmi->length = sizeof(*local_nmi);
505 local_nmi->processor_id = 0xff; /* all processors */
506 local_nmi->flags = cpu_to_le16(0);
507 local_nmi->lint = 1; /* ACPI_LINT1 */
508
509 build_header(linker, table_data,
510 (void *)(table_data->data + madt_start), "APIC",
511 table_data->len - madt_start, 1);
512 }
513
514 /* Encode a hex value */
515 static inline char acpi_get_hex(uint32_t val)
516 {
517 val &= 0x0f;
518 return (val <= 9) ? ('0' + val) : ('A' + val - 10);
519 }
520
521 /* 0x5B 0x82 DeviceOp PkgLength NameString */
522 #define ACPI_PCIHP_OFFSET_HEX (*ssdt_pcihp_name - *ssdt_pcihp_start + 1)
523 #define ACPI_PCIHP_OFFSET_ID (*ssdt_pcihp_id - *ssdt_pcihp_start)
524 #define ACPI_PCIHP_OFFSET_ADR (*ssdt_pcihp_adr - *ssdt_pcihp_start)
525 #define ACPI_PCIHP_OFFSET_EJ0 (*ssdt_pcihp_ej0 - *ssdt_pcihp_start)
526 #define ACPI_PCIHP_SIZEOF (*ssdt_pcihp_end - *ssdt_pcihp_start)
527 #define ACPI_PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start)
528
529 #define ACPI_PCINOHP_OFFSET_HEX (*ssdt_pcinohp_name - *ssdt_pcinohp_start + 1)
530 #define ACPI_PCINOHP_OFFSET_ADR (*ssdt_pcinohp_adr - *ssdt_pcinohp_start)
531 #define ACPI_PCINOHP_SIZEOF (*ssdt_pcinohp_end - *ssdt_pcinohp_start)
532 #define ACPI_PCINOHP_AML (ssdp_pcihp_aml + *ssdt_pcinohp_start)
533
534 #define ACPI_PCIVGA_OFFSET_HEX (*ssdt_pcivga_name - *ssdt_pcivga_start + 1)
535 #define ACPI_PCIVGA_OFFSET_ADR (*ssdt_pcivga_adr - *ssdt_pcivga_start)
536 #define ACPI_PCIVGA_SIZEOF (*ssdt_pcivga_end - *ssdt_pcivga_start)
537 #define ACPI_PCIVGA_AML (ssdp_pcihp_aml + *ssdt_pcivga_start)
538
539 #define ACPI_PCIQXL_OFFSET_HEX (*ssdt_pciqxl_name - *ssdt_pciqxl_start + 1)
540 #define ACPI_PCIQXL_OFFSET_ADR (*ssdt_pciqxl_adr - *ssdt_pciqxl_start)
541 #define ACPI_PCIQXL_SIZEOF (*ssdt_pciqxl_end - *ssdt_pciqxl_start)
542 #define ACPI_PCIQXL_AML (ssdp_pcihp_aml + *ssdt_pciqxl_start)
543
544 #define ACPI_SSDT_SIGNATURE 0x54445353 /* SSDT */
545 #define ACPI_SSDT_HEADER_LENGTH 36
546
547 #include "hw/i386/ssdt-misc.hex"
548 #include "hw/i386/ssdt-pcihp.hex"
549 #include "hw/i386/ssdt-tpm.hex"
550
551 static void patch_pcihp(int slot, uint8_t *ssdt_ptr)
552 {
553 unsigned devfn = PCI_DEVFN(slot, 0);
554
555 ssdt_ptr[ACPI_PCIHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
556 ssdt_ptr[ACPI_PCIHP_OFFSET_HEX + 1] = acpi_get_hex(devfn);
557 ssdt_ptr[ACPI_PCIHP_OFFSET_ID] = slot;
558 ssdt_ptr[ACPI_PCIHP_OFFSET_ADR + 2] = slot;
559 }
560
561 static void patch_pcinohp(int slot, uint8_t *ssdt_ptr)
562 {
563 unsigned devfn = PCI_DEVFN(slot, 0);
564
565 ssdt_ptr[ACPI_PCINOHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
566 ssdt_ptr[ACPI_PCINOHP_OFFSET_HEX + 1] = acpi_get_hex(devfn);
567 ssdt_ptr[ACPI_PCINOHP_OFFSET_ADR + 2] = slot;
568 }
569
570 static void patch_pcivga(int slot, uint8_t *ssdt_ptr)
571 {
572 unsigned devfn = PCI_DEVFN(slot, 0);
573
574 ssdt_ptr[ACPI_PCIVGA_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
575 ssdt_ptr[ACPI_PCIVGA_OFFSET_HEX + 1] = acpi_get_hex(devfn);
576 ssdt_ptr[ACPI_PCIVGA_OFFSET_ADR + 2] = slot;
577 }
578
579 static void patch_pciqxl(int slot, uint8_t *ssdt_ptr)
580 {
581 unsigned devfn = PCI_DEVFN(slot, 0);
582
583 ssdt_ptr[ACPI_PCIQXL_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
584 ssdt_ptr[ACPI_PCIQXL_OFFSET_HEX + 1] = acpi_get_hex(devfn);
585 ssdt_ptr[ACPI_PCIQXL_OFFSET_ADR + 2] = slot;
586 }
587
588 /* Assign BSEL property to all buses. In the future, this can be changed
589 * to only assign to buses that support hotplug.
590 */
591 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
592 {
593 unsigned *bsel_alloc = opaque;
594 unsigned *bus_bsel;
595
596 if (qbus_is_hotpluggable(BUS(bus))) {
597 bus_bsel = g_malloc(sizeof *bus_bsel);
598
599 *bus_bsel = (*bsel_alloc)++;
600 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
601 bus_bsel, NULL);
602 }
603
604 return bsel_alloc;
605 }
606
607 static void acpi_set_pci_info(void)
608 {
609 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
610 unsigned bsel_alloc = 0;
611
612 if (bus) {
613 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
614 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
615 }
616 }
617
618 static void build_pci_bus_state_init(AcpiBuildPciBusHotplugState *state,
619 AcpiBuildPciBusHotplugState *parent,
620 bool pcihp_bridge_en)
621 {
622 state->parent = parent;
623 state->device_table = build_alloc_array();
624 state->notify_table = build_alloc_array();
625 state->pcihp_bridge_en = pcihp_bridge_en;
626 }
627
628 static void build_pci_bus_state_cleanup(AcpiBuildPciBusHotplugState *state)
629 {
630 build_free_array(state->device_table);
631 build_free_array(state->notify_table);
632 }
633
634 static void *build_pci_bus_begin(PCIBus *bus, void *parent_state)
635 {
636 AcpiBuildPciBusHotplugState *parent = parent_state;
637 AcpiBuildPciBusHotplugState *child = g_malloc(sizeof *child);
638
639 build_pci_bus_state_init(child, parent, parent->pcihp_bridge_en);
640
641 return child;
642 }
643
644 static void build_pci_bus_end(PCIBus *bus, void *bus_state)
645 {
646 AcpiBuildPciBusHotplugState *child = bus_state;
647 AcpiBuildPciBusHotplugState *parent = child->parent;
648 GArray *bus_table = build_alloc_array();
649 DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
650 DECLARE_BITMAP(slot_device_present, PCI_SLOT_MAX);
651 DECLARE_BITMAP(slot_device_system, PCI_SLOT_MAX);
652 DECLARE_BITMAP(slot_device_vga, PCI_SLOT_MAX);
653 DECLARE_BITMAP(slot_device_qxl, PCI_SLOT_MAX);
654 uint8_t op;
655 int i;
656 QObject *bsel;
657 GArray *method;
658 bool bus_hotplug_support = false;
659
660 /*
661 * Skip bridge subtree creation if bridge hotplug is disabled
662 * to make acpi tables compatible with legacy machine types.
663 * Skip creation for hotplugged bridges as well.
664 */
665 if (bus->parent_dev && (!child->pcihp_bridge_en ||
666 DEVICE(bus->parent_dev)->hotplugged)) {
667 build_free_array(bus_table);
668 build_pci_bus_state_cleanup(child);
669 g_free(child);
670 return;
671 }
672
673 if (bus->parent_dev) {
674 op = 0x82; /* DeviceOp */
675 build_append_namestring(bus_table, "S%.02X",
676 bus->parent_dev->devfn);
677 build_append_byte(bus_table, 0x08); /* NameOp */
678 build_append_namestring(bus_table, "_SUN");
679 build_append_int(bus_table, PCI_SLOT(bus->parent_dev->devfn));
680 build_append_byte(bus_table, 0x08); /* NameOp */
681 build_append_namestring(bus_table, "_ADR");
682 build_append_int(bus_table, (PCI_SLOT(bus->parent_dev->devfn) << 16) |
683 PCI_FUNC(bus->parent_dev->devfn));
684 } else {
685 op = 0x10; /* ScopeOp */;
686 build_append_namestring(bus_table, "PCI0");
687 }
688
689 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
690 if (bsel) {
691 build_append_byte(bus_table, 0x08); /* NameOp */
692 build_append_namestring(bus_table, "BSEL");
693 build_append_int(bus_table, qint_get_int(qobject_to_qint(bsel)));
694 memset(slot_hotplug_enable, 0xff, sizeof slot_hotplug_enable);
695 } else {
696 /* No bsel - no slots are hot-pluggable */
697 memset(slot_hotplug_enable, 0x00, sizeof slot_hotplug_enable);
698 }
699
700 memset(slot_device_present, 0x00, sizeof slot_device_present);
701 memset(slot_device_system, 0x00, sizeof slot_device_present);
702 memset(slot_device_vga, 0x00, sizeof slot_device_vga);
703 memset(slot_device_qxl, 0x00, sizeof slot_device_qxl);
704
705 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
706 DeviceClass *dc;
707 PCIDeviceClass *pc;
708 PCIDevice *pdev = bus->devices[i];
709 int slot = PCI_SLOT(i);
710 bool bridge_in_acpi;
711
712 if (!pdev) {
713 continue;
714 }
715
716 set_bit(slot, slot_device_present);
717 pc = PCI_DEVICE_GET_CLASS(pdev);
718 dc = DEVICE_GET_CLASS(pdev);
719
720 /* When hotplug for bridges is enabled, bridges are
721 * described in ACPI separately (see build_pci_bus_end).
722 * In this case they aren't themselves hot-pluggable.
723 * Hotplugged bridges *are* hot-pluggable.
724 */
725 bridge_in_acpi = pc->is_bridge && child->pcihp_bridge_en &&
726 !DEVICE(pdev)->hotplugged;
727
728 if (pc->class_id == PCI_CLASS_BRIDGE_ISA || bridge_in_acpi) {
729 set_bit(slot, slot_device_system);
730 }
731
732 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
733 set_bit(slot, slot_device_vga);
734
735 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
736 set_bit(slot, slot_device_qxl);
737 }
738 }
739
740 if (!dc->hotpluggable || bridge_in_acpi) {
741 clear_bit(slot, slot_hotplug_enable);
742 }
743 }
744
745 /* Append Device object for each slot */
746 for (i = 0; i < PCI_SLOT_MAX; i++) {
747 bool can_eject = test_bit(i, slot_hotplug_enable);
748 bool present = test_bit(i, slot_device_present);
749 bool vga = test_bit(i, slot_device_vga);
750 bool qxl = test_bit(i, slot_device_qxl);
751 bool system = test_bit(i, slot_device_system);
752 if (can_eject) {
753 void *pcihp = acpi_data_push(bus_table,
754 ACPI_PCIHP_SIZEOF);
755 memcpy(pcihp, ACPI_PCIHP_AML, ACPI_PCIHP_SIZEOF);
756 patch_pcihp(i, pcihp);
757 bus_hotplug_support = true;
758 } else if (qxl) {
759 void *pcihp = acpi_data_push(bus_table,
760 ACPI_PCIQXL_SIZEOF);
761 memcpy(pcihp, ACPI_PCIQXL_AML, ACPI_PCIQXL_SIZEOF);
762 patch_pciqxl(i, pcihp);
763 } else if (vga) {
764 void *pcihp = acpi_data_push(bus_table,
765 ACPI_PCIVGA_SIZEOF);
766 memcpy(pcihp, ACPI_PCIVGA_AML, ACPI_PCIVGA_SIZEOF);
767 patch_pcivga(i, pcihp);
768 } else if (system) {
769 /* Nothing to do: system devices are in DSDT or in SSDT above. */
770 } else if (present) {
771 void *pcihp = acpi_data_push(bus_table,
772 ACPI_PCINOHP_SIZEOF);
773 memcpy(pcihp, ACPI_PCINOHP_AML, ACPI_PCINOHP_SIZEOF);
774 patch_pcinohp(i, pcihp);
775 }
776 }
777
778 if (bsel) {
779 method = build_alloc_method("DVNT", 2);
780
781 for (i = 0; i < PCI_SLOT_MAX; i++) {
782 GArray *notify;
783 uint8_t op;
784
785 if (!test_bit(i, slot_hotplug_enable)) {
786 continue;
787 }
788
789 notify = build_alloc_array();
790 op = 0xA0; /* IfOp */
791
792 build_append_byte(notify, 0x7B); /* AndOp */
793 build_append_byte(notify, 0x68); /* Arg0Op */
794 build_append_int(notify, 0x1U << i);
795 build_append_byte(notify, 0x00); /* NullName */
796 build_append_byte(notify, 0x86); /* NotifyOp */
797 build_append_namestring(notify, "S%.02X", PCI_DEVFN(i, 0));
798 build_append_byte(notify, 0x69); /* Arg1Op */
799
800 /* Pack it up */
801 build_package(notify, op);
802
803 build_append_array(method, notify);
804
805 build_free_array(notify);
806 }
807
808 build_append_and_cleanup_method(bus_table, method);
809 }
810
811 /* Append PCNT method to notify about events on local and child buses.
812 * Add unconditionally for root since DSDT expects it.
813 */
814 if (bus_hotplug_support || child->notify_table->len || !bus->parent_dev) {
815 method = build_alloc_method("PCNT", 0);
816
817 /* If bus supports hotplug select it and notify about local events */
818 if (bsel) {
819 build_append_byte(method, 0x70); /* StoreOp */
820 build_append_int(method, qint_get_int(qobject_to_qint(bsel)));
821 build_append_namestring(method, "BNUM");
822 build_append_namestring(method, "DVNT");
823 build_append_namestring(method, "PCIU");
824 build_append_int(method, 1); /* Device Check */
825 build_append_namestring(method, "DVNT");
826 build_append_namestring(method, "PCID");
827 build_append_int(method, 3); /* Eject Request */
828 }
829
830 /* Notify about child bus events in any case */
831 build_append_array(method, child->notify_table);
832
833 build_append_and_cleanup_method(bus_table, method);
834
835 /* Append description of child buses */
836 build_append_array(bus_table, child->device_table);
837
838 /* Pack it up */
839 if (bus->parent_dev) {
840 build_extop_package(bus_table, op);
841 } else {
842 build_package(bus_table, op);
843 }
844
845 /* Append our bus description to parent table */
846 build_append_array(parent->device_table, bus_table);
847
848 /* Also tell parent how to notify us, invoking PCNT method.
849 * At the moment this is not needed for root as we have a single root.
850 */
851 if (bus->parent_dev) {
852 build_append_namestring(parent->notify_table, "^PCNT.S%.02X",
853 bus->parent_dev->devfn);
854 }
855 }
856
857 qobject_decref(bsel);
858 build_free_array(bus_table);
859 build_pci_bus_state_cleanup(child);
860 g_free(child);
861 }
862
863 static void patch_pci_windows(PcPciInfo *pci, uint8_t *start, unsigned size)
864 {
865 ACPI_BUILD_SET_LE(start, size, acpi_pci32_start[0], 32, pci->w32.begin);
866
867 ACPI_BUILD_SET_LE(start, size, acpi_pci32_end[0], 32, pci->w32.end - 1);
868
869 if (pci->w64.end || pci->w64.begin) {
870 ACPI_BUILD_SET_LE(start, size, acpi_pci64_valid[0], 8, 1);
871 ACPI_BUILD_SET_LE(start, size, acpi_pci64_start[0], 64, pci->w64.begin);
872 ACPI_BUILD_SET_LE(start, size, acpi_pci64_end[0], 64, pci->w64.end - 1);
873 ACPI_BUILD_SET_LE(start, size, acpi_pci64_length[0], 64, pci->w64.end - pci->w64.begin);
874 } else {
875 ACPI_BUILD_SET_LE(start, size, acpi_pci64_valid[0], 8, 0);
876 }
877 }
878
879 static void
880 build_ssdt(GArray *table_data, GArray *linker,
881 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
882 PcPciInfo *pci, PcGuestInfo *guest_info)
883 {
884 MachineState *machine = MACHINE(qdev_get_machine());
885 uint32_t nr_mem = machine->ram_slots;
886 unsigned acpi_cpus = guest_info->apic_id_limit;
887 uint8_t *ssdt_ptr;
888 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx;
889 int i;
890
891 ssdt = init_aml_allocator();
892 /* The current AML generator can cover the APIC ID range [0..255],
893 * inclusive, for VCPU hotplug. */
894 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
895 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
896
897 /* Copy header and patch values in the S3_ / S4_ / S5_ packages */
898 ssdt_ptr = acpi_data_push(ssdt->buf, sizeof(ssdp_misc_aml));
899 memcpy(ssdt_ptr, ssdp_misc_aml, sizeof(ssdp_misc_aml));
900
901 patch_pci_windows(pci, ssdt_ptr, sizeof(ssdp_misc_aml));
902
903 scope = aml_scope("\\_SB.PCI0");
904 /* reserve PCIHP resources */
905 if (pm->pcihp_io_len) {
906 dev = aml_device("PHPR");
907 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
908 aml_append(dev,
909 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
910 /* device present, functioning, decoding, not shown in UI */
911 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
912 crs = aml_resource_template();
913 aml_append(crs,
914 aml_io(aml_decode16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
915 pm->pcihp_io_len)
916 );
917 aml_append(dev, aml_name_decl("_CRS", crs));
918 aml_append(scope, dev);
919 }
920 aml_append(ssdt, scope);
921
922 /* create S3_ / S4_ / S5_ packages if necessary */
923 scope = aml_scope("\\");
924 if (!pm->s3_disabled) {
925 pkg = aml_package(4);
926 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
927 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
928 aml_append(pkg, aml_int(0)); /* reserved */
929 aml_append(pkg, aml_int(0)); /* reserved */
930 aml_append(scope, aml_name_decl("_S3", pkg));
931 }
932
933 if (!pm->s4_disabled) {
934 pkg = aml_package(4);
935 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
936 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
937 aml_append(pkg, aml_int(pm->s4_val));
938 aml_append(pkg, aml_int(0)); /* reserved */
939 aml_append(pkg, aml_int(0)); /* reserved */
940 aml_append(scope, aml_name_decl("_S4", pkg));
941 }
942
943 pkg = aml_package(4);
944 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
945 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
946 aml_append(pkg, aml_int(0)); /* reserved */
947 aml_append(pkg, aml_int(0)); /* reserved */
948 aml_append(scope, aml_name_decl("_S5", pkg));
949 aml_append(ssdt, scope);
950
951 if (misc->pvpanic_port) {
952 scope = aml_scope("\\_SB.PCI0.ISA");
953
954 dev = aml_device("PEVR");
955 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
956
957 crs = aml_resource_template();
958 aml_append(crs,
959 aml_io(aml_decode16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
960 );
961 aml_append(dev, aml_name_decl("_CRS", crs));
962
963 aml_append(dev, aml_operation_region("PEOR", aml_system_io,
964 misc->pvpanic_port, 1));
965 field = aml_field("PEOR", aml_byte_acc);
966 aml_append(field, aml_named_field("PEPT", 8));
967 aml_append(dev, field);
968
969 method = aml_method("RDPT", 0);
970 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
971 aml_append(method, aml_return(aml_local(0)));
972 aml_append(dev, method);
973
974 method = aml_method("WRPT", 1);
975 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
976 aml_append(dev, method);
977
978 aml_append(scope, dev);
979 aml_append(ssdt, scope);
980 }
981
982 sb_scope = aml_scope("_SB");
983 {
984 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
985 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
986 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
987 aml_append(dev,
988 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
989 );
990 /* device present, functioning, decoding, not shown in UI */
991 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
992 crs = aml_resource_template();
993 aml_append(crs,
994 aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
995 pm->cpu_hp_io_len)
996 );
997 aml_append(dev, aml_name_decl("_CRS", crs));
998 aml_append(sb_scope, dev);
999 /* declare CPU hotplug MMIO region and PRS field to access it */
1000 aml_append(sb_scope, aml_operation_region(
1001 "PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
1002 field = aml_field("PRST", aml_byte_acc);
1003 aml_append(field, aml_named_field("PRS", 256));
1004 aml_append(sb_scope, field);
1005
1006 /* build Processor object for each processor */
1007 for (i = 0; i < acpi_cpus; i++) {
1008 dev = aml_processor(i, 0, 0, "CP%.02X", i);
1009
1010 method = aml_method("_MAT", 0);
1011 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i))));
1012 aml_append(dev, method);
1013
1014 method = aml_method("_STA", 0);
1015 aml_append(method, aml_return(aml_call1("CPST", aml_int(i))));
1016 aml_append(dev, method);
1017
1018 method = aml_method("_EJ0", 1);
1019 aml_append(method,
1020 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0)))
1021 );
1022 aml_append(dev, method);
1023
1024 aml_append(sb_scope, dev);
1025 }
1026
1027 /* build this code:
1028 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1029 */
1030 /* Arg0 = Processor ID = APIC ID */
1031 method = aml_method("NTFY", 2);
1032 for (i = 0; i < acpi_cpus; i++) {
1033 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1034 aml_append(ifctx,
1035 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1036 );
1037 aml_append(method, ifctx);
1038 }
1039 aml_append(sb_scope, method);
1040
1041 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1042 *
1043 * Note: The ability to create variable-sized packages was first
1044 * ntroduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1045 * ith up to 255 elements. Windows guests up to win2k8 fail when
1046 * VarPackageOp is used.
1047 */
1048 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1049 aml_varpackage(acpi_cpus);
1050
1051 for (i = 0; i < acpi_cpus; i++) {
1052 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1053 aml_append(pkg, aml_int(b));
1054 }
1055 aml_append(sb_scope, aml_name_decl("CPON", pkg));
1056
1057 /* build memory devices */
1058 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1059 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE));
1060 aml_append(scope,
1061 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem))
1062 );
1063
1064 crs = aml_resource_template();
1065 aml_append(crs,
1066 aml_io(aml_decode16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0,
1067 pm->mem_hp_io_len)
1068 );
1069 aml_append(scope, aml_name_decl("_CRS", crs));
1070
1071 aml_append(scope, aml_operation_region(
1072 stringify(MEMORY_HOTPLUG_IO_REGION), aml_system_io,
1073 pm->mem_hp_io_base, pm->mem_hp_io_len)
1074 );
1075
1076 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc);
1077 aml_append(field, /* read only */
1078 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32));
1079 aml_append(field, /* read only */
1080 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32));
1081 aml_append(field, /* read only */
1082 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32));
1083 aml_append(field, /* read only */
1084 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32));
1085 aml_append(field, /* read only */
1086 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32));
1087 aml_append(scope, field);
1088
1089 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_byte_acc);
1090 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1091 aml_append(field, /* 1 if enabled, read only */
1092 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1));
1093 aml_append(field,
1094 /*(read) 1 if has a insert event. (write) 1 to clear event */
1095 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1));
1096 aml_append(scope, field);
1097
1098 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc);
1099 aml_append(field, /* DIMM selector, write only */
1100 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32));
1101 aml_append(field, /* _OST event code, write only */
1102 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32));
1103 aml_append(field, /* _OST status code, write only */
1104 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32));
1105 aml_append(scope, field);
1106
1107 aml_append(sb_scope, scope);
1108
1109 for (i = 0; i < nr_mem; i++) {
1110 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "."
1111 const char *s;
1112
1113 dev = aml_device("MP%02X", i);
1114 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1115 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1116
1117 method = aml_method("_CRS", 0);
1118 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD);
1119 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1120 aml_append(dev, method);
1121
1122 method = aml_method("_STA", 0);
1123 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD);
1124 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1125 aml_append(dev, method);
1126
1127 method = aml_method("_PXM", 0);
1128 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD);
1129 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1130 aml_append(dev, method);
1131
1132 method = aml_method("_OST", 3);
1133 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD);
1134 aml_append(method, aml_return(aml_call4(
1135 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1136 )));
1137 aml_append(dev, method);
1138
1139 aml_append(sb_scope, dev);
1140 }
1141
1142 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1143 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ...
1144 */
1145 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2);
1146 for (i = 0; i < nr_mem; i++) {
1147 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1148 aml_append(ifctx,
1149 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1150 );
1151 aml_append(method, ifctx);
1152 }
1153 aml_append(sb_scope, method);
1154
1155 {
1156 AcpiBuildPciBusHotplugState hotplug_state;
1157 Object *pci_host;
1158 PCIBus *bus = NULL;
1159 bool ambiguous;
1160
1161 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1162 if (!ambiguous && pci_host) {
1163 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1164 }
1165
1166 build_pci_bus_state_init(&hotplug_state, NULL, pm->pcihp_bridge_en);
1167
1168 if (bus) {
1169 /* Scan all PCI buses. Generate tables to support hotplug. */
1170 pci_for_each_bus_depth_first(bus, build_pci_bus_begin,
1171 build_pci_bus_end, &hotplug_state);
1172 }
1173
1174 build_append_array(sb_scope->buf, hotplug_state.device_table);
1175 build_pci_bus_state_cleanup(&hotplug_state);
1176 }
1177 aml_append(ssdt, sb_scope);
1178 }
1179
1180 /* copy AML table into ACPI tables blob and patch header there */
1181 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
1182 build_header(linker, table_data,
1183 (void *)(table_data->data + table_data->len - ssdt->buf->len),
1184 "SSDT", ssdt->buf->len, 1);
1185 free_aml_allocator();
1186 }
1187
1188 static void
1189 build_hpet(GArray *table_data, GArray *linker)
1190 {
1191 Acpi20Hpet *hpet;
1192
1193 hpet = acpi_data_push(table_data, sizeof(*hpet));
1194 /* Note timer_block_id value must be kept in sync with value advertised by
1195 * emulated hpet
1196 */
1197 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1198 hpet->addr.address = cpu_to_le64(HPET_BASE);
1199 build_header(linker, table_data,
1200 (void *)hpet, "HPET", sizeof(*hpet), 1);
1201 }
1202
1203 static void
1204 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
1205 {
1206 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1207 uint64_t log_area_start_address = acpi_data_len(tcpalog);
1208
1209 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1210 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1211 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
1212
1213 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
1214 false /* high memory */);
1215
1216 /* log area start address to be filled by Guest linker */
1217 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1218 ACPI_BUILD_TPMLOG_FILE,
1219 table_data, &tcpa->log_area_start_address,
1220 sizeof(tcpa->log_area_start_address));
1221
1222 build_header(linker, table_data,
1223 (void *)tcpa, "TCPA", sizeof(*tcpa), 2);
1224
1225 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1226 }
1227
1228 static void
1229 build_tpm_ssdt(GArray *table_data, GArray *linker)
1230 {
1231 void *tpm_ptr;
1232
1233 tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml));
1234 memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml));
1235 }
1236
1237 typedef enum {
1238 MEM_AFFINITY_NOFLAGS = 0,
1239 MEM_AFFINITY_ENABLED = (1 << 0),
1240 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
1241 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
1242 } MemoryAffinityFlags;
1243
1244 static void
1245 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
1246 uint64_t len, int node, MemoryAffinityFlags flags)
1247 {
1248 numamem->type = ACPI_SRAT_MEMORY;
1249 numamem->length = sizeof(*numamem);
1250 memset(numamem->proximity, 0, 4);
1251 numamem->proximity[0] = node;
1252 numamem->flags = cpu_to_le32(flags);
1253 numamem->base_addr = cpu_to_le64(base);
1254 numamem->range_length = cpu_to_le64(len);
1255 }
1256
1257 static void
1258 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
1259 {
1260 AcpiSystemResourceAffinityTable *srat;
1261 AcpiSratProcessorAffinity *core;
1262 AcpiSratMemoryAffinity *numamem;
1263
1264 int i;
1265 uint64_t curnode;
1266 int srat_start, numa_start, slots;
1267 uint64_t mem_len, mem_base, next_base;
1268 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1269 ram_addr_t hotplugabble_address_space_size =
1270 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
1271 NULL);
1272
1273 srat_start = table_data->len;
1274
1275 srat = acpi_data_push(table_data, sizeof *srat);
1276 srat->reserved1 = cpu_to_le32(1);
1277 core = (void *)(srat + 1);
1278
1279 for (i = 0; i < guest_info->apic_id_limit; ++i) {
1280 core = acpi_data_push(table_data, sizeof *core);
1281 core->type = ACPI_SRAT_PROCESSOR;
1282 core->length = sizeof(*core);
1283 core->local_apic_id = i;
1284 curnode = guest_info->node_cpu[i];
1285 core->proximity_lo = curnode;
1286 memset(core->proximity_hi, 0, 3);
1287 core->local_sapic_eid = 0;
1288 core->flags = cpu_to_le32(1);
1289 }
1290
1291
1292 /* the memory map is a bit tricky, it contains at least one hole
1293 * from 640k-1M and possibly another one from 3.5G-4G.
1294 */
1295 next_base = 0;
1296 numa_start = table_data->len;
1297
1298 numamem = acpi_data_push(table_data, sizeof *numamem);
1299 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
1300 next_base = 1024 * 1024;
1301 for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
1302 mem_base = next_base;
1303 mem_len = guest_info->node_mem[i - 1];
1304 if (i == 1) {
1305 mem_len -= 1024 * 1024;
1306 }
1307 next_base = mem_base + mem_len;
1308
1309 /* Cut out the ACPI_PCI hole */
1310 if (mem_base <= guest_info->ram_size_below_4g &&
1311 next_base > guest_info->ram_size_below_4g) {
1312 mem_len -= next_base - guest_info->ram_size_below_4g;
1313 if (mem_len > 0) {
1314 numamem = acpi_data_push(table_data, sizeof *numamem);
1315 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1316 MEM_AFFINITY_ENABLED);
1317 }
1318 mem_base = 1ULL << 32;
1319 mem_len = next_base - guest_info->ram_size_below_4g;
1320 next_base += (1ULL << 32) - guest_info->ram_size_below_4g;
1321 }
1322 numamem = acpi_data_push(table_data, sizeof *numamem);
1323 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1324 MEM_AFFINITY_ENABLED);
1325 }
1326 slots = (table_data->len - numa_start) / sizeof *numamem;
1327 for (; slots < guest_info->numa_nodes + 2; slots++) {
1328 numamem = acpi_data_push(table_data, sizeof *numamem);
1329 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1330 }
1331
1332 /*
1333 * Entry is required for Windows to enable memory hotplug in OS.
1334 * Memory devices may override proximity set by this entry,
1335 * providing _PXM method if necessary.
1336 */
1337 if (hotplugabble_address_space_size) {
1338 numamem = acpi_data_push(table_data, sizeof *numamem);
1339 acpi_build_srat_memory(numamem, pcms->hotplug_memory_base,
1340 hotplugabble_address_space_size, 0,
1341 MEM_AFFINITY_HOTPLUGGABLE |
1342 MEM_AFFINITY_ENABLED);
1343 }
1344
1345 build_header(linker, table_data,
1346 (void *)(table_data->data + srat_start),
1347 "SRAT",
1348 table_data->len - srat_start, 1);
1349 }
1350
1351 static void
1352 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
1353 {
1354 AcpiTableMcfg *mcfg;
1355 const char *sig;
1356 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
1357
1358 mcfg = acpi_data_push(table_data, len);
1359 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
1360 /* Only a single allocation so no need to play with segments */
1361 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
1362 mcfg->allocation[0].start_bus_number = 0;
1363 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
1364
1365 /* MCFG is used for ECAM which can be enabled or disabled by guest.
1366 * To avoid table size changes (which create migration issues),
1367 * always create the table even if there are no allocations,
1368 * but set the signature to a reserved value in this case.
1369 * ACPI spec requires OSPMs to ignore such tables.
1370 */
1371 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
1372 /* Reserved signature: ignored by OSPM */
1373 sig = "QEMU";
1374 } else {
1375 sig = "MCFG";
1376 }
1377 build_header(linker, table_data, (void *)mcfg, sig, len, 1);
1378 }
1379
1380 static void
1381 build_dmar_q35(GArray *table_data, GArray *linker)
1382 {
1383 int dmar_start = table_data->len;
1384
1385 AcpiTableDmar *dmar;
1386 AcpiDmarHardwareUnit *drhd;
1387
1388 dmar = acpi_data_push(table_data, sizeof(*dmar));
1389 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
1390 dmar->flags = 0; /* No intr_remap for now */
1391
1392 /* DMAR Remapping Hardware Unit Definition structure */
1393 drhd = acpi_data_push(table_data, sizeof(*drhd));
1394 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
1395 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
1396 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
1397 drhd->pci_segment = cpu_to_le16(0);
1398 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
1399
1400 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
1401 "DMAR", table_data->len - dmar_start, 1);
1402 }
1403
1404 static void
1405 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
1406 {
1407 AcpiTableHeader *dsdt;
1408
1409 assert(misc->dsdt_code && misc->dsdt_size);
1410
1411 dsdt = acpi_data_push(table_data, misc->dsdt_size);
1412 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size);
1413
1414 memset(dsdt, 0, sizeof *dsdt);
1415 build_header(linker, table_data, dsdt, "DSDT",
1416 misc->dsdt_size, 1);
1417 }
1418
1419 /* Build final rsdt table */
1420 static void
1421 build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
1422 {
1423 AcpiRsdtDescriptorRev1 *rsdt;
1424 size_t rsdt_len;
1425 int i;
1426
1427 rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len;
1428 rsdt = acpi_data_push(table_data, rsdt_len);
1429 memcpy(rsdt->table_offset_entry, table_offsets->data,
1430 sizeof(uint32_t) * table_offsets->len);
1431 for (i = 0; i < table_offsets->len; ++i) {
1432 /* rsdt->table_offset_entry to be filled by Guest linker */
1433 bios_linker_loader_add_pointer(linker,
1434 ACPI_BUILD_TABLE_FILE,
1435 ACPI_BUILD_TABLE_FILE,
1436 table_data, &rsdt->table_offset_entry[i],
1437 sizeof(uint32_t));
1438 }
1439 build_header(linker, table_data,
1440 (void *)rsdt, "RSDT", rsdt_len, 1);
1441 }
1442
1443 static GArray *
1444 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
1445 {
1446 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
1447
1448 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
1449 true /* fseg memory */);
1450
1451 memcpy(&rsdp->signature, "RSD PTR ", 8);
1452 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
1453 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
1454 /* Address to be filled by Guest linker */
1455 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
1456 ACPI_BUILD_TABLE_FILE,
1457 rsdp_table, &rsdp->rsdt_physical_address,
1458 sizeof rsdp->rsdt_physical_address);
1459 rsdp->checksum = 0;
1460 /* Checksum to be filled by Guest linker */
1461 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
1462 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
1463
1464 return rsdp_table;
1465 }
1466
1467 typedef
1468 struct AcpiBuildTables {
1469 GArray *table_data;
1470 GArray *rsdp;
1471 GArray *tcpalog;
1472 GArray *linker;
1473 } AcpiBuildTables;
1474
1475 static inline void acpi_build_tables_init(AcpiBuildTables *tables)
1476 {
1477 tables->rsdp = g_array_new(false, true /* clear */, 1);
1478 tables->table_data = g_array_new(false, true /* clear */, 1);
1479 tables->tcpalog = g_array_new(false, true /* clear */, 1);
1480 tables->linker = bios_linker_loader_init();
1481 }
1482
1483 static inline void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
1484 {
1485 void *linker_data = bios_linker_loader_cleanup(tables->linker);
1486 g_free(linker_data);
1487 g_array_free(tables->rsdp, true);
1488 g_array_free(tables->table_data, true);
1489 g_array_free(tables->tcpalog, mfre);
1490 }
1491
1492 typedef
1493 struct AcpiBuildState {
1494 /* Copy of table in RAM (for patching). */
1495 ram_addr_t table_ram;
1496 /* Is table patched? */
1497 uint8_t patched;
1498 PcGuestInfo *guest_info;
1499 void *rsdp;
1500 ram_addr_t rsdp_ram;
1501 ram_addr_t linker_ram;
1502 } AcpiBuildState;
1503
1504 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
1505 {
1506 Object *pci_host;
1507 QObject *o;
1508 bool ambiguous;
1509
1510 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1511 g_assert(!ambiguous);
1512 g_assert(pci_host);
1513
1514 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
1515 if (!o) {
1516 return false;
1517 }
1518 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
1519 qobject_decref(o);
1520
1521 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
1522 assert(o);
1523 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
1524 qobject_decref(o);
1525 return true;
1526 }
1527
1528 static bool acpi_has_iommu(void)
1529 {
1530 bool ambiguous;
1531 Object *intel_iommu;
1532
1533 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
1534 &ambiguous);
1535 return intel_iommu && !ambiguous;
1536 }
1537
1538 static
1539 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
1540 {
1541 GArray *table_offsets;
1542 unsigned facs, ssdt, dsdt, rsdt;
1543 AcpiCpuInfo cpu;
1544 AcpiPmInfo pm;
1545 AcpiMiscInfo misc;
1546 AcpiMcfgInfo mcfg;
1547 PcPciInfo pci;
1548 uint8_t *u;
1549 size_t aml_len = 0;
1550 GArray *tables_blob = tables->table_data;
1551
1552 acpi_get_cpu_info(&cpu);
1553 acpi_get_pm_info(&pm);
1554 acpi_get_dsdt(&misc);
1555 acpi_get_misc_info(&misc);
1556 acpi_get_pci_info(&pci);
1557
1558 table_offsets = g_array_new(false, true /* clear */,
1559 sizeof(uint32_t));
1560 ACPI_BUILD_DPRINTF("init ACPI tables\n");
1561
1562 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
1563 64 /* Ensure FACS is aligned */,
1564 false /* high memory */);
1565
1566 /*
1567 * FACS is pointed to by FADT.
1568 * We place it first since it's the only table that has alignment
1569 * requirements.
1570 */
1571 facs = tables_blob->len;
1572 build_facs(tables_blob, tables->linker, guest_info);
1573
1574 /* DSDT is pointed to by FADT */
1575 dsdt = tables_blob->len;
1576 build_dsdt(tables_blob, tables->linker, &misc);
1577
1578 /* Count the size of the DSDT and SSDT, we will need it for legacy
1579 * sizing of ACPI tables.
1580 */
1581 aml_len += tables_blob->len - dsdt;
1582
1583 /* ACPI tables pointed to by RSDT */
1584 acpi_add_table(table_offsets, tables_blob);
1585 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt);
1586
1587 ssdt = tables_blob->len;
1588 acpi_add_table(table_offsets, tables_blob);
1589 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci,
1590 guest_info);
1591 aml_len += tables_blob->len - ssdt;
1592
1593 acpi_add_table(table_offsets, tables_blob);
1594 build_madt(tables_blob, tables->linker, &cpu, guest_info);
1595
1596 if (misc.has_hpet) {
1597 acpi_add_table(table_offsets, tables_blob);
1598 build_hpet(tables_blob, tables->linker);
1599 }
1600 if (misc.has_tpm) {
1601 acpi_add_table(table_offsets, tables_blob);
1602 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
1603
1604 acpi_add_table(table_offsets, tables_blob);
1605 build_tpm_ssdt(tables_blob, tables->linker);
1606 }
1607 if (guest_info->numa_nodes) {
1608 acpi_add_table(table_offsets, tables_blob);
1609 build_srat(tables_blob, tables->linker, guest_info);
1610 }
1611 if (acpi_get_mcfg(&mcfg)) {
1612 acpi_add_table(table_offsets, tables_blob);
1613 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
1614 }
1615 if (acpi_has_iommu()) {
1616 acpi_add_table(table_offsets, tables_blob);
1617 build_dmar_q35(tables_blob, tables->linker);
1618 }
1619
1620 /* Add tables supplied by user (if any) */
1621 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
1622 unsigned len = acpi_table_len(u);
1623
1624 acpi_add_table(table_offsets, tables_blob);
1625 g_array_append_vals(tables_blob, u, len);
1626 }
1627
1628 /* RSDT is pointed to by RSDP */
1629 rsdt = tables_blob->len;
1630 build_rsdt(tables_blob, tables->linker, table_offsets);
1631
1632 /* RSDP is in FSEG memory, so allocate it separately */
1633 build_rsdp(tables->rsdp, tables->linker, rsdt);
1634
1635 /* We'll expose it all to Guest so we want to reduce
1636 * chance of size changes.
1637 *
1638 * We used to align the tables to 4k, but of course this would
1639 * too simple to be enough. 4k turned out to be too small an
1640 * alignment very soon, and in fact it is almost impossible to
1641 * keep the table size stable for all (max_cpus, max_memory_slots)
1642 * combinations. So the table size is always 64k for pc-i440fx-2.1
1643 * and we give an error if the table grows beyond that limit.
1644 *
1645 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
1646 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
1647 * than 2.0 and we can always pad the smaller tables with zeros. We can
1648 * then use the exact size of the 2.0 tables.
1649 *
1650 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
1651 */
1652 if (guest_info->legacy_acpi_table_size) {
1653 /* Subtracting aml_len gives the size of fixed tables. Then add the
1654 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
1655 */
1656 int legacy_aml_len =
1657 guest_info->legacy_acpi_table_size +
1658 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
1659 int legacy_table_size =
1660 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
1661 ACPI_BUILD_ALIGN_SIZE);
1662 if (tables_blob->len > legacy_table_size) {
1663 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
1664 error_report("Warning: migration may not work.");
1665 }
1666 g_array_set_size(tables_blob, legacy_table_size);
1667 } else {
1668 /* Make sure we have a buffer in case we need to resize the tables. */
1669 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1670 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
1671 error_report("Warning: ACPI tables are larger than 64k.");
1672 error_report("Warning: migration may not work.");
1673 error_report("Warning: please remove CPUs, NUMA nodes, "
1674 "memory slots or PCI bridges.");
1675 }
1676 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1677 }
1678
1679 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
1680
1681 /* Cleanup memory that's no longer used. */
1682 g_array_free(table_offsets, true);
1683 }
1684
1685 static void acpi_ram_update(ram_addr_t ram, GArray *data)
1686 {
1687 uint32_t size = acpi_data_len(data);
1688
1689 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
1690 qemu_ram_resize(ram, size, &error_abort);
1691
1692 memcpy(qemu_get_ram_ptr(ram), data->data, size);
1693 cpu_physical_memory_set_dirty_range_nocode(ram, size);
1694 }
1695
1696 static void acpi_build_update(void *build_opaque, uint32_t offset)
1697 {
1698 AcpiBuildState *build_state = build_opaque;
1699 AcpiBuildTables tables;
1700
1701 /* No state to update or already patched? Nothing to do. */
1702 if (!build_state || build_state->patched) {
1703 return;
1704 }
1705 build_state->patched = 1;
1706
1707 acpi_build_tables_init(&tables);
1708
1709 acpi_build(build_state->guest_info, &tables);
1710
1711 acpi_ram_update(build_state->table_ram, tables.table_data);
1712
1713 if (build_state->rsdp) {
1714 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
1715 } else {
1716 acpi_ram_update(build_state->rsdp_ram, tables.rsdp);
1717 }
1718
1719 acpi_ram_update(build_state->linker_ram, tables.linker);
1720 acpi_build_tables_cleanup(&tables, true);
1721 }
1722
1723 static void acpi_build_reset(void *build_opaque)
1724 {
1725 AcpiBuildState *build_state = build_opaque;
1726 build_state->patched = 0;
1727 }
1728
1729 static ram_addr_t acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob,
1730 const char *name, uint64_t max_size)
1731 {
1732 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
1733 name, acpi_build_update, build_state);
1734 }
1735
1736 static const VMStateDescription vmstate_acpi_build = {
1737 .name = "acpi_build",
1738 .version_id = 1,
1739 .minimum_version_id = 1,
1740 .fields = (VMStateField[]) {
1741 VMSTATE_UINT8(patched, AcpiBuildState),
1742 VMSTATE_END_OF_LIST()
1743 },
1744 };
1745
1746 void acpi_setup(PcGuestInfo *guest_info)
1747 {
1748 AcpiBuildTables tables;
1749 AcpiBuildState *build_state;
1750
1751 if (!guest_info->fw_cfg) {
1752 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
1753 return;
1754 }
1755
1756 if (!guest_info->has_acpi_build) {
1757 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
1758 return;
1759 }
1760
1761 if (!acpi_enabled) {
1762 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
1763 return;
1764 }
1765
1766 build_state = g_malloc0(sizeof *build_state);
1767
1768 build_state->guest_info = guest_info;
1769
1770 acpi_set_pci_info();
1771
1772 acpi_build_tables_init(&tables);
1773 acpi_build(build_state->guest_info, &tables);
1774
1775 /* Now expose it all to Guest */
1776 build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data,
1777 ACPI_BUILD_TABLE_FILE,
1778 ACPI_BUILD_TABLE_MAX_SIZE);
1779 assert(build_state->table_ram != RAM_ADDR_MAX);
1780
1781 build_state->linker_ram =
1782 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
1783
1784 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
1785 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
1786
1787 if (!guest_info->rsdp_in_ram) {
1788 /*
1789 * Keep for compatibility with old machine types.
1790 * Though RSDP is small, its contents isn't immutable, so
1791 * we'll update it along with the rest of tables on guest access.
1792 */
1793 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
1794
1795 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
1796 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
1797 acpi_build_update, build_state,
1798 build_state->rsdp, rsdp_size);
1799 build_state->rsdp_ram = (ram_addr_t)-1;
1800 } else {
1801 build_state->rsdp = NULL;
1802 build_state->rsdp_ram = acpi_add_rom_blob(build_state, tables.rsdp,
1803 ACPI_BUILD_RSDP_FILE, 0);
1804 }
1805
1806 qemu_register_reset(acpi_build_reset, build_state);
1807 acpi_build_reset(build_state);
1808 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
1809
1810 /* Cleanup tables but don't free the memory: we track it
1811 * in build_state.
1812 */
1813 acpi_build_tables_cleanup(&tables, false);
1814 }
AR7 emulation for QEMU