1 /* Copyright 2008 IBM Corporation
3 * Copyright 2011 Intel Corporation
4 * Copyright 2016 Veertu, Inc.
5 * Copyright 2017 The Android Open Source Project
7 * QEMU Hypervisor.framework support
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of version 2 of the GNU General Public
11 * License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 * This file contain code under public domain from the hvdos project:
22 * https://github.com/mist64/hvdos
24 * Parts Copyright (c) 2011 NetApp, Inc.
25 * All rights reserved.
27 * Redistribution and use in source and binary forms, with or without
28 * modification, are permitted provided that the following conditions
30 * 1. Redistributions of source code must retain the above copyright
31 * notice, this list of conditions and the following disclaimer.
32 * 2. Redistributions in binary form must reproduce the above copyright
33 * notice, this list of conditions and the following disclaimer in the
34 * documentation and/or other materials provided with the distribution.
36 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
37 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
39 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
42 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
43 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
44 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
45 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
49 #include "qemu/osdep.h"
50 #include "qemu-common.h"
51 #include "qemu/error-report.h"
53 #include "sysemu/hvf.h"
54 #include "sysemu/runstate.h"
59 #include "x86_descr.h"
61 #include "x86_decode.h"
66 #include <Hypervisor/hv.h>
67 #include <Hypervisor/hv_vmx.h>
69 #include "exec/address-spaces.h"
70 #include "hw/i386/apic_internal.h"
71 #include "qemu/main-loop.h"
72 #include "sysemu/accel.h"
73 #include "target/i386/cpu.h"
77 static void assert_hvf_ok(hv_return_t ret
)
79 if (ret
== HV_SUCCESS
) {
85 error_report("Error: HV_ERROR");
88 error_report("Error: HV_BUSY");
91 error_report("Error: HV_BAD_ARGUMENT");
94 error_report("Error: HV_NO_RESOURCES");
97 error_report("Error: HV_NO_DEVICE");
100 error_report("Error: HV_UNSUPPORTED");
103 error_report("Unknown Error");
110 hvf_slot
*hvf_find_overlap_slot(uint64_t start
, uint64_t size
)
114 for (x
= 0; x
< hvf_state
->num_slots
; ++x
) {
115 slot
= &hvf_state
->slots
[x
];
116 if (slot
->size
&& start
< (slot
->start
+ slot
->size
) &&
117 (start
+ size
) > slot
->start
) {
131 struct mac_slot mac_slots
[32];
133 static int do_hvf_set_memory(hvf_slot
*slot
, hv_memory_flags_t flags
)
135 struct mac_slot
*macslot
;
138 macslot
= &mac_slots
[slot
->slot_id
];
140 if (macslot
->present
) {
141 if (macslot
->size
!= slot
->size
) {
142 macslot
->present
= 0;
143 ret
= hv_vm_unmap(macslot
->gpa_start
, macslot
->size
);
152 macslot
->present
= 1;
153 macslot
->gpa_start
= slot
->start
;
154 macslot
->size
= slot
->size
;
155 ret
= hv_vm_map((hv_uvaddr_t
)slot
->mem
, slot
->start
, slot
->size
, flags
);
160 void hvf_set_phys_mem(MemoryRegionSection
*section
, bool add
)
163 MemoryRegion
*area
= section
->mr
;
164 bool writeable
= !area
->readonly
&& !area
->rom_device
;
165 hv_memory_flags_t flags
;
167 if (!memory_region_is_ram(area
)) {
170 } else if (!memory_region_is_romd(area
)) {
172 * If the memory device is not in romd_mode, then we actually want
173 * to remove the hvf memory slot so all accesses will trap.
179 mem
= hvf_find_overlap_slot(
180 section
->offset_within_address_space
,
181 int128_get64(section
->size
));
184 if (mem
->size
== int128_get64(section
->size
) &&
185 mem
->start
== section
->offset_within_address_space
&&
186 mem
->mem
== (memory_region_get_ram_ptr(area
) +
187 section
->offset_within_region
)) {
188 return; /* Same region was attempted to register, go away. */
192 /* Region needs to be reset. set the size to 0 and remap it. */
195 if (do_hvf_set_memory(mem
, 0)) {
196 error_report("Failed to reset overlapping slot");
205 if (area
->readonly
||
206 (!memory_region_is_ram(area
) && memory_region_is_romd(area
))) {
207 flags
= HV_MEMORY_READ
| HV_MEMORY_EXEC
;
209 flags
= HV_MEMORY_READ
| HV_MEMORY_WRITE
| HV_MEMORY_EXEC
;
212 /* Now make a new slot. */
215 for (x
= 0; x
< hvf_state
->num_slots
; ++x
) {
216 mem
= &hvf_state
->slots
[x
];
222 if (x
== hvf_state
->num_slots
) {
223 error_report("No free slots");
227 mem
->size
= int128_get64(section
->size
);
228 mem
->mem
= memory_region_get_ram_ptr(area
) + section
->offset_within_region
;
229 mem
->start
= section
->offset_within_address_space
;
232 if (do_hvf_set_memory(mem
, flags
)) {
233 error_report("Error registering new memory slot");
238 void vmx_update_tpr(CPUState
*cpu
)
240 /* TODO: need integrate APIC handling */
241 X86CPU
*x86_cpu
= X86_CPU(cpu
);
242 int tpr
= cpu_get_apic_tpr(x86_cpu
->apic_state
) << 4;
243 int irr
= apic_get_highest_priority_irr(x86_cpu
->apic_state
);
245 wreg(cpu
->hvf_fd
, HV_X86_TPR
, tpr
);
247 wvmcs(cpu
->hvf_fd
, VMCS_TPR_THRESHOLD
, 0);
249 wvmcs(cpu
->hvf_fd
, VMCS_TPR_THRESHOLD
, (irr
> tpr
) ? tpr
>> 4 :
254 static void update_apic_tpr(CPUState
*cpu
)
256 X86CPU
*x86_cpu
= X86_CPU(cpu
);
257 int tpr
= rreg(cpu
->hvf_fd
, HV_X86_TPR
) >> 4;
258 cpu_set_apic_tpr(x86_cpu
->apic_state
, tpr
);
261 #define VECTORING_INFO_VECTOR_MASK 0xff
263 static void hvf_handle_interrupt(CPUState
* cpu
, int mask
)
265 cpu
->interrupt_request
|= mask
;
266 if (!qemu_cpu_is_self(cpu
)) {
271 void hvf_handle_io(CPUArchState
*env
, uint16_t port
, void *buffer
,
272 int direction
, int size
, int count
)
275 uint8_t *ptr
= buffer
;
277 for (i
= 0; i
< count
; i
++) {
278 address_space_rw(&address_space_io
, port
, MEMTXATTRS_UNSPECIFIED
,
285 /* TODO: synchronize vcpu state */
286 static void do_hvf_cpu_synchronize_state(CPUState
*cpu
, run_on_cpu_data arg
)
288 CPUState
*cpu_state
= cpu
;
289 if (cpu_state
->vcpu_dirty
== 0) {
290 hvf_get_registers(cpu_state
);
293 cpu_state
->vcpu_dirty
= 1;
296 void hvf_cpu_synchronize_state(CPUState
*cpu_state
)
298 if (cpu_state
->vcpu_dirty
== 0) {
299 run_on_cpu(cpu_state
, do_hvf_cpu_synchronize_state
, RUN_ON_CPU_NULL
);
303 static void do_hvf_cpu_synchronize_post_reset(CPUState
*cpu
, run_on_cpu_data arg
)
305 CPUState
*cpu_state
= cpu
;
306 hvf_put_registers(cpu_state
);
307 cpu_state
->vcpu_dirty
= false;
310 void hvf_cpu_synchronize_post_reset(CPUState
*cpu_state
)
312 run_on_cpu(cpu_state
, do_hvf_cpu_synchronize_post_reset
, RUN_ON_CPU_NULL
);
315 static void do_hvf_cpu_synchronize_post_init(CPUState
*cpu
,
318 CPUState
*cpu_state
= cpu
;
319 hvf_put_registers(cpu_state
);
320 cpu_state
->vcpu_dirty
= false;
323 void hvf_cpu_synchronize_post_init(CPUState
*cpu_state
)
325 run_on_cpu(cpu_state
, do_hvf_cpu_synchronize_post_init
, RUN_ON_CPU_NULL
);
328 static void do_hvf_cpu_synchronize_pre_loadvm(CPUState
*cpu
,
331 cpu
->vcpu_dirty
= true;
334 void hvf_cpu_synchronize_pre_loadvm(CPUState
*cpu
)
336 run_on_cpu(cpu
, do_hvf_cpu_synchronize_pre_loadvm
, RUN_ON_CPU_NULL
);
339 static bool ept_emulation_fault(hvf_slot
*slot
, uint64_t gpa
, uint64_t ept_qual
)
343 /* EPT fault on an instruction fetch doesn't make sense here */
344 if (ept_qual
& EPT_VIOLATION_INST_FETCH
) {
348 /* EPT fault must be a read fault or a write fault */
349 read
= ept_qual
& EPT_VIOLATION_DATA_READ
? 1 : 0;
350 write
= ept_qual
& EPT_VIOLATION_DATA_WRITE
? 1 : 0;
351 if ((read
| write
) == 0) {
356 if (slot
->flags
& HVF_SLOT_LOG
) {
357 memory_region_set_dirty(slot
->region
, gpa
- slot
->start
, 1);
358 hv_vm_protect((hv_gpaddr_t
)slot
->start
, (size_t)slot
->size
,
359 HV_MEMORY_READ
| HV_MEMORY_WRITE
);
364 * The EPT violation must have been caused by accessing a
365 * guest-physical address that is a translation of a guest-linear
368 if ((ept_qual
& EPT_VIOLATION_GLA_VALID
) == 0 ||
369 (ept_qual
& EPT_VIOLATION_XLAT_VALID
) == 0) {
376 if (!memory_region_is_ram(slot
->region
) &&
377 !(read
&& memory_region_is_romd(slot
->region
))) {
383 static void hvf_set_dirty_tracking(MemoryRegionSection
*section
, bool on
)
387 slot
= hvf_find_overlap_slot(
388 section
->offset_within_address_space
,
389 int128_get64(section
->size
));
391 /* protect region against writes; begin tracking it */
393 slot
->flags
|= HVF_SLOT_LOG
;
394 hv_vm_protect((hv_gpaddr_t
)slot
->start
, (size_t)slot
->size
,
396 /* stop tracking region*/
398 slot
->flags
&= ~HVF_SLOT_LOG
;
399 hv_vm_protect((hv_gpaddr_t
)slot
->start
, (size_t)slot
->size
,
400 HV_MEMORY_READ
| HV_MEMORY_WRITE
);
404 static void hvf_log_start(MemoryListener
*listener
,
405 MemoryRegionSection
*section
, int old
, int new)
411 hvf_set_dirty_tracking(section
, 1);
414 static void hvf_log_stop(MemoryListener
*listener
,
415 MemoryRegionSection
*section
, int old
, int new)
421 hvf_set_dirty_tracking(section
, 0);
424 static void hvf_log_sync(MemoryListener
*listener
,
425 MemoryRegionSection
*section
)
428 * sync of dirty pages is handled elsewhere; just make sure we keep
429 * tracking the region.
431 hvf_set_dirty_tracking(section
, 1);
434 static void hvf_region_add(MemoryListener
*listener
,
435 MemoryRegionSection
*section
)
437 hvf_set_phys_mem(section
, true);
440 static void hvf_region_del(MemoryListener
*listener
,
441 MemoryRegionSection
*section
)
443 hvf_set_phys_mem(section
, false);
446 static MemoryListener hvf_memory_listener
= {
448 .region_add
= hvf_region_add
,
449 .region_del
= hvf_region_del
,
450 .log_start
= hvf_log_start
,
451 .log_stop
= hvf_log_stop
,
452 .log_sync
= hvf_log_sync
,
455 void hvf_vcpu_destroy(CPUState
*cpu
)
457 X86CPU
*x86_cpu
= X86_CPU(cpu
);
458 CPUX86State
*env
= &x86_cpu
->env
;
460 hv_return_t ret
= hv_vcpu_destroy((hv_vcpuid_t
)cpu
->hvf_fd
);
461 g_free(env
->hvf_mmio_buf
);
465 static void dummy_signal(int sig
)
469 int hvf_init_vcpu(CPUState
*cpu
)
472 X86CPU
*x86cpu
= X86_CPU(cpu
);
473 CPUX86State
*env
= &x86cpu
->env
;
476 /* init cpu signals */
478 struct sigaction sigact
;
480 memset(&sigact
, 0, sizeof(sigact
));
481 sigact
.sa_handler
= dummy_signal
;
482 sigaction(SIG_IPI
, &sigact
, NULL
);
484 pthread_sigmask(SIG_BLOCK
, NULL
, &set
);
485 sigdelset(&set
, SIG_IPI
);
490 hvf_state
->hvf_caps
= g_new0(struct hvf_vcpu_caps
, 1);
491 env
->hvf_mmio_buf
= g_new(char, 4096);
493 r
= hv_vcpu_create((hv_vcpuid_t
*)&cpu
->hvf_fd
, HV_VCPU_DEFAULT
);
497 if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED
,
498 &hvf_state
->hvf_caps
->vmx_cap_pinbased
)) {
501 if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED
,
502 &hvf_state
->hvf_caps
->vmx_cap_procbased
)) {
505 if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2
,
506 &hvf_state
->hvf_caps
->vmx_cap_procbased2
)) {
509 if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY
,
510 &hvf_state
->hvf_caps
->vmx_cap_entry
)) {
514 /* set VMCS control fields */
515 wvmcs(cpu
->hvf_fd
, VMCS_PIN_BASED_CTLS
,
516 cap2ctrl(hvf_state
->hvf_caps
->vmx_cap_pinbased
,
517 VMCS_PIN_BASED_CTLS_EXTINT
|
518 VMCS_PIN_BASED_CTLS_NMI
|
519 VMCS_PIN_BASED_CTLS_VNMI
));
520 wvmcs(cpu
->hvf_fd
, VMCS_PRI_PROC_BASED_CTLS
,
521 cap2ctrl(hvf_state
->hvf_caps
->vmx_cap_procbased
,
522 VMCS_PRI_PROC_BASED_CTLS_HLT
|
523 VMCS_PRI_PROC_BASED_CTLS_MWAIT
|
524 VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET
|
525 VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW
) |
526 VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL
);
527 wvmcs(cpu
->hvf_fd
, VMCS_SEC_PROC_BASED_CTLS
,
528 cap2ctrl(hvf_state
->hvf_caps
->vmx_cap_procbased2
,
529 VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES
));
531 wvmcs(cpu
->hvf_fd
, VMCS_ENTRY_CTLS
, cap2ctrl(hvf_state
->hvf_caps
->vmx_cap_entry
,
533 wvmcs(cpu
->hvf_fd
, VMCS_EXCEPTION_BITMAP
, 0); /* Double fault */
535 wvmcs(cpu
->hvf_fd
, VMCS_TPR_THRESHOLD
, 0);
537 x86cpu
= X86_CPU(cpu
);
538 x86cpu
->env
.xsave_buf
= qemu_memalign(4096, 4096);
540 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_STAR
, 1);
541 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_LSTAR
, 1);
542 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_CSTAR
, 1);
543 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_FMASK
, 1);
544 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_FSBASE
, 1);
545 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_GSBASE
, 1);
546 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_KERNELGSBASE
, 1);
547 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_TSC_AUX
, 1);
548 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_IA32_TSC
, 1);
549 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_IA32_SYSENTER_CS
, 1);
550 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_IA32_SYSENTER_EIP
, 1);
551 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_IA32_SYSENTER_ESP
, 1);
556 static void hvf_store_events(CPUState
*cpu
, uint32_t ins_len
, uint64_t idtvec_info
)
558 X86CPU
*x86_cpu
= X86_CPU(cpu
);
559 CPUX86State
*env
= &x86_cpu
->env
;
561 env
->exception_nr
= -1;
562 env
->exception_pending
= 0;
563 env
->exception_injected
= 0;
564 env
->interrupt_injected
= -1;
565 env
->nmi_injected
= false;
567 env
->has_error_code
= false;
568 if (idtvec_info
& VMCS_IDT_VEC_VALID
) {
569 switch (idtvec_info
& VMCS_IDT_VEC_TYPE
) {
570 case VMCS_IDT_VEC_HWINTR
:
571 case VMCS_IDT_VEC_SWINTR
:
572 env
->interrupt_injected
= idtvec_info
& VMCS_IDT_VEC_VECNUM
;
574 case VMCS_IDT_VEC_NMI
:
575 env
->nmi_injected
= true;
577 case VMCS_IDT_VEC_HWEXCEPTION
:
578 case VMCS_IDT_VEC_SWEXCEPTION
:
579 env
->exception_nr
= idtvec_info
& VMCS_IDT_VEC_VECNUM
;
580 env
->exception_injected
= 1;
582 case VMCS_IDT_VEC_PRIV_SWEXCEPTION
:
586 if ((idtvec_info
& VMCS_IDT_VEC_TYPE
) == VMCS_IDT_VEC_SWEXCEPTION
||
587 (idtvec_info
& VMCS_IDT_VEC_TYPE
) == VMCS_IDT_VEC_SWINTR
) {
588 env
->ins_len
= ins_len
;
590 if (idtvec_info
& VMCS_IDT_VEC_ERRCODE_VALID
) {
591 env
->has_error_code
= true;
592 env
->error_code
= rvmcs(cpu
->hvf_fd
, VMCS_IDT_VECTORING_ERROR
);
595 if ((rvmcs(cpu
->hvf_fd
, VMCS_GUEST_INTERRUPTIBILITY
) &
596 VMCS_INTERRUPTIBILITY_NMI_BLOCKING
)) {
597 env
->hflags2
|= HF2_NMI_MASK
;
599 env
->hflags2
&= ~HF2_NMI_MASK
;
601 if (rvmcs(cpu
->hvf_fd
, VMCS_GUEST_INTERRUPTIBILITY
) &
602 (VMCS_INTERRUPTIBILITY_STI_BLOCKING
|
603 VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING
)) {
604 env
->hflags
|= HF_INHIBIT_IRQ_MASK
;
606 env
->hflags
&= ~HF_INHIBIT_IRQ_MASK
;
610 int hvf_vcpu_exec(CPUState
*cpu
)
612 X86CPU
*x86_cpu
= X86_CPU(cpu
);
613 CPUX86State
*env
= &x86_cpu
->env
;
617 if (hvf_process_events(cpu
)) {
622 if (cpu
->vcpu_dirty
) {
623 hvf_put_registers(cpu
);
624 cpu
->vcpu_dirty
= false;
627 if (hvf_inject_interrupts(cpu
)) {
628 return EXCP_INTERRUPT
;
632 qemu_mutex_unlock_iothread();
633 if (!cpu_is_bsp(X86_CPU(cpu
)) && cpu
->halted
) {
634 qemu_mutex_lock_iothread();
638 hv_return_t r
= hv_vcpu_run(cpu
->hvf_fd
);
642 uint64_t exit_reason
= rvmcs(cpu
->hvf_fd
, VMCS_EXIT_REASON
);
643 uint64_t exit_qual
= rvmcs(cpu
->hvf_fd
, VMCS_EXIT_QUALIFICATION
);
644 uint32_t ins_len
= (uint32_t)rvmcs(cpu
->hvf_fd
,
645 VMCS_EXIT_INSTRUCTION_LENGTH
);
647 uint64_t idtvec_info
= rvmcs(cpu
->hvf_fd
, VMCS_IDT_VECTORING_INFO
);
649 hvf_store_events(cpu
, ins_len
, idtvec_info
);
650 rip
= rreg(cpu
->hvf_fd
, HV_X86_RIP
);
651 env
->eflags
= rreg(cpu
->hvf_fd
, HV_X86_RFLAGS
);
653 qemu_mutex_lock_iothread();
655 update_apic_tpr(cpu
);
659 switch (exit_reason
) {
660 case EXIT_REASON_HLT
: {
661 macvm_set_rip(cpu
, rip
+ ins_len
);
662 if (!((cpu
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
663 (env
->eflags
& IF_MASK
))
664 && !(cpu
->interrupt_request
& CPU_INTERRUPT_NMI
) &&
665 !(idtvec_info
& VMCS_IDT_VEC_VALID
)) {
670 ret
= EXCP_INTERRUPT
;
673 case EXIT_REASON_MWAIT
: {
674 ret
= EXCP_INTERRUPT
;
677 /* Need to check if MMIO or unmapped fault */
678 case EXIT_REASON_EPT_FAULT
:
681 uint64_t gpa
= rvmcs(cpu
->hvf_fd
, VMCS_GUEST_PHYSICAL_ADDRESS
);
683 if (((idtvec_info
& VMCS_IDT_VEC_VALID
) == 0) &&
684 ((exit_qual
& EXIT_QUAL_NMIUDTI
) != 0)) {
685 vmx_set_nmi_blocking(cpu
);
688 slot
= hvf_find_overlap_slot(gpa
, 1);
690 if (ept_emulation_fault(slot
, gpa
, exit_qual
)) {
691 struct x86_decode decode
;
694 decode_instruction(env
, &decode
);
695 exec_instruction(env
, &decode
);
701 case EXIT_REASON_INOUT
:
703 uint32_t in
= (exit_qual
& 8) != 0;
704 uint32_t size
= (exit_qual
& 7) + 1;
705 uint32_t string
= (exit_qual
& 16) != 0;
706 uint32_t port
= exit_qual
>> 16;
707 /*uint32_t rep = (exit_qual & 0x20) != 0;*/
712 hvf_handle_io(env
, port
, &val
, 0, size
, 1);
715 } else if (size
== 2) {
717 } else if (size
== 4) {
718 RAX(env
) = (uint32_t)val
;
720 RAX(env
) = (uint64_t)val
;
725 } else if (!string
&& !in
) {
726 RAX(env
) = rreg(cpu
->hvf_fd
, HV_X86_RAX
);
727 hvf_handle_io(env
, port
, &RAX(env
), 1, size
, 1);
728 macvm_set_rip(cpu
, rip
+ ins_len
);
731 struct x86_decode decode
;
734 decode_instruction(env
, &decode
);
735 assert(ins_len
== decode
.len
);
736 exec_instruction(env
, &decode
);
741 case EXIT_REASON_CPUID
: {
742 uint32_t rax
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RAX
);
743 uint32_t rbx
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RBX
);
744 uint32_t rcx
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RCX
);
745 uint32_t rdx
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RDX
);
747 cpu_x86_cpuid(env
, rax
, rcx
, &rax
, &rbx
, &rcx
, &rdx
);
749 wreg(cpu
->hvf_fd
, HV_X86_RAX
, rax
);
750 wreg(cpu
->hvf_fd
, HV_X86_RBX
, rbx
);
751 wreg(cpu
->hvf_fd
, HV_X86_RCX
, rcx
);
752 wreg(cpu
->hvf_fd
, HV_X86_RDX
, rdx
);
754 macvm_set_rip(cpu
, rip
+ ins_len
);
757 case EXIT_REASON_XSETBV
: {
758 X86CPU
*x86_cpu
= X86_CPU(cpu
);
759 CPUX86State
*env
= &x86_cpu
->env
;
760 uint32_t eax
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RAX
);
761 uint32_t ecx
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RCX
);
762 uint32_t edx
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RDX
);
765 macvm_set_rip(cpu
, rip
+ ins_len
);
768 env
->xcr0
= ((uint64_t)edx
<< 32) | eax
;
769 wreg(cpu
->hvf_fd
, HV_X86_XCR0
, env
->xcr0
| 1);
770 macvm_set_rip(cpu
, rip
+ ins_len
);
773 case EXIT_REASON_INTR_WINDOW
:
774 vmx_clear_int_window_exiting(cpu
);
775 ret
= EXCP_INTERRUPT
;
777 case EXIT_REASON_NMI_WINDOW
:
778 vmx_clear_nmi_window_exiting(cpu
);
779 ret
= EXCP_INTERRUPT
;
781 case EXIT_REASON_EXT_INTR
:
782 /* force exit and allow io handling */
783 ret
= EXCP_INTERRUPT
;
785 case EXIT_REASON_RDMSR
:
786 case EXIT_REASON_WRMSR
:
789 if (exit_reason
== EXIT_REASON_RDMSR
) {
798 case EXIT_REASON_CR_ACCESS
: {
804 reg
= (exit_qual
>> 8) & 15;
808 macvm_set_cr0(cpu
->hvf_fd
, RRX(env
, reg
));
812 macvm_set_cr4(cpu
->hvf_fd
, RRX(env
, reg
));
816 X86CPU
*x86_cpu
= X86_CPU(cpu
);
817 if (exit_qual
& 0x10) {
818 RRX(env
, reg
) = cpu_get_apic_tpr(x86_cpu
->apic_state
);
820 int tpr
= RRX(env
, reg
);
821 cpu_set_apic_tpr(x86_cpu
->apic_state
, tpr
);
822 ret
= EXCP_INTERRUPT
;
827 error_report("Unrecognized CR %d", cr
);
834 case EXIT_REASON_APIC_ACCESS
: { /* TODO */
835 struct x86_decode decode
;
838 decode_instruction(env
, &decode
);
839 exec_instruction(env
, &decode
);
843 case EXIT_REASON_TPR
: {
847 case EXIT_REASON_TASK_SWITCH
: {
848 uint64_t vinfo
= rvmcs(cpu
->hvf_fd
, VMCS_IDT_VECTORING_INFO
);
849 x68_segment_selector sel
= {.sel
= exit_qual
& 0xffff};
850 vmx_handle_task_switch(cpu
, sel
, (exit_qual
>> 30) & 0x3,
851 vinfo
& VMCS_INTR_VALID
, vinfo
& VECTORING_INFO_VECTOR_MASK
, vinfo
855 case EXIT_REASON_TRIPLE_FAULT
: {
856 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
857 ret
= EXCP_INTERRUPT
;
860 case EXIT_REASON_RDPMC
:
861 wreg(cpu
->hvf_fd
, HV_X86_RAX
, 0);
862 wreg(cpu
->hvf_fd
, HV_X86_RDX
, 0);
863 macvm_set_rip(cpu
, rip
+ ins_len
);
865 case VMX_REASON_VMCALL
:
866 env
->exception_nr
= EXCP0D_GPF
;
867 env
->exception_injected
= 1;
868 env
->has_error_code
= true;
872 error_report("%llx: unhandled exit %llx", rip
, exit_reason
);
881 static int hvf_accel_init(MachineState
*ms
)
887 ret
= hv_vm_create(HV_VM_DEFAULT
);
890 s
= g_new0(HVFState
, 1);
893 for (x
= 0; x
< s
->num_slots
; ++x
) {
894 s
->slots
[x
].size
= 0;
895 s
->slots
[x
].slot_id
= x
;
899 cpu_interrupt_handler
= hvf_handle_interrupt
;
900 memory_listener_register(&hvf_memory_listener
, &address_space_memory
);
904 static void hvf_accel_class_init(ObjectClass
*oc
, void *data
)
906 AccelClass
*ac
= ACCEL_CLASS(oc
);
908 ac
->init_machine
= hvf_accel_init
;
909 ac
->allowed
= &hvf_allowed
;
912 static const TypeInfo hvf_accel_type
= {
913 .name
= TYPE_HVF_ACCEL
,
914 .parent
= TYPE_ACCEL
,
915 .class_init
= hvf_accel_class_init
,
918 static void hvf_type_init(void)
920 type_register_static(&hvf_accel_type
);
923 type_init(hvf_type_init
);