4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
27 #include "qemu/qemu-print.h"
28 #include "exec/cpu_ldst.h"
29 #include "exec/translator.h"
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
34 #include "trace-tcg.h"
36 #include "fpu/softfloat.h"
39 //#define DEBUG_DISPATCH 1
41 #define DEFO32(name, offset) static TCGv QREG_##name;
42 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
47 static TCGv_i32 cpu_halted
;
48 static TCGv_i32 cpu_exception_index
;
50 static char cpu_reg_names
[2 * 8 * 3 + 5 * 4];
51 static TCGv cpu_dregs
[8];
52 static TCGv cpu_aregs
[8];
53 static TCGv_i64 cpu_macc
[4];
55 #define REG(insn, pos) (((insn) >> (pos)) & 7)
56 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
57 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
58 #define MACREG(acc) cpu_macc[acc]
59 #define QREG_SP get_areg(s, 7)
61 static TCGv NULL_QREG
;
62 #define IS_NULL_QREG(t) (t == NULL_QREG)
63 /* Used to distinguish stores from bad addressing modes. */
64 static TCGv store_dummy
;
66 #include "exec/gen-icount.h"
68 void m68k_tcg_init(void)
73 #define DEFO32(name, offset) \
74 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
75 offsetof(CPUM68KState, offset), #name);
76 #define DEFO64(name, offset) \
77 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
78 offsetof(CPUM68KState, offset), #name);
83 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
84 -offsetof(M68kCPU
, env
) +
85 offsetof(CPUState
, halted
), "HALTED");
86 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
87 -offsetof(M68kCPU
, env
) +
88 offsetof(CPUState
, exception_index
),
92 for (i
= 0; i
< 8; i
++) {
94 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
95 offsetof(CPUM68KState
, dregs
[i
]), p
);
98 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
99 offsetof(CPUM68KState
, aregs
[i
]), p
);
102 for (i
= 0; i
< 4; i
++) {
103 sprintf(p
, "ACC%d", i
);
104 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUM68KState
, macc
[i
]), p
);
109 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
110 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
113 /* internal defines */
114 typedef struct DisasContext
{
115 DisasContextBase base
;
118 CCOp cc_op
; /* Current CC operation */
124 #define MAX_TO_RELEASE 8
126 TCGv release
[MAX_TO_RELEASE
];
129 static void init_release_array(DisasContext
*s
)
131 #ifdef CONFIG_DEBUG_TCG
132 memset(s
->release
, 0, sizeof(s
->release
));
134 s
->release_count
= 0;
137 static void do_release(DisasContext
*s
)
140 for (i
= 0; i
< s
->release_count
; i
++) {
141 tcg_temp_free(s
->release
[i
]);
143 init_release_array(s
);
146 static TCGv
mark_to_release(DisasContext
*s
, TCGv tmp
)
148 g_assert(s
->release_count
< MAX_TO_RELEASE
);
149 return s
->release
[s
->release_count
++] = tmp
;
152 static TCGv
get_areg(DisasContext
*s
, unsigned regno
)
154 if (s
->writeback_mask
& (1 << regno
)) {
155 return s
->writeback
[regno
];
157 return cpu_aregs
[regno
];
161 static void delay_set_areg(DisasContext
*s
, unsigned regno
,
162 TCGv val
, bool give_temp
)
164 if (s
->writeback_mask
& (1 << regno
)) {
166 tcg_temp_free(s
->writeback
[regno
]);
167 s
->writeback
[regno
] = val
;
169 tcg_gen_mov_i32(s
->writeback
[regno
], val
);
172 s
->writeback_mask
|= 1 << regno
;
174 s
->writeback
[regno
] = val
;
176 TCGv tmp
= tcg_temp_new();
177 s
->writeback
[regno
] = tmp
;
178 tcg_gen_mov_i32(tmp
, val
);
183 static void do_writebacks(DisasContext
*s
)
185 unsigned mask
= s
->writeback_mask
;
187 s
->writeback_mask
= 0;
189 unsigned regno
= ctz32(mask
);
190 tcg_gen_mov_i32(cpu_aregs
[regno
], s
->writeback
[regno
]);
191 tcg_temp_free(s
->writeback
[regno
]);
197 static bool is_singlestepping(DisasContext
*s
)
200 * Return true if we are singlestepping either because of QEMU gdbstub
201 * singlestep. This does not include the command line '-singlestep' mode
202 * which is rather misnamed as it only means "one instruction per TB" and
203 * doesn't affect the code we generate.
205 return s
->base
.singlestep_enabled
;
208 /* is_jmp field values */
209 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
210 #define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
212 #if defined(CONFIG_USER_ONLY)
215 #define IS_USER(s) (!(s->base.tb->flags & TB_FLAGS_MSR_S))
216 #define SFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_SFC_S) ? \
217 MMU_KERNEL_IDX : MMU_USER_IDX)
218 #define DFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_DFC_S) ? \
219 MMU_KERNEL_IDX : MMU_USER_IDX)
222 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
224 #ifdef DEBUG_DISPATCH
225 #define DISAS_INSN(name) \
226 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
228 static void disas_##name(CPUM68KState *env, DisasContext *s, \
231 qemu_log("Dispatch " #name "\n"); \
232 real_disas_##name(env, s, insn); \
234 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
237 #define DISAS_INSN(name) \
238 static void disas_##name(CPUM68KState *env, DisasContext *s, \
242 static const uint8_t cc_op_live
[CC_OP_NB
] = {
243 [CC_OP_DYNAMIC
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
244 [CC_OP_FLAGS
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
245 [CC_OP_ADDB
... CC_OP_ADDL
] = CCF_X
| CCF_N
| CCF_V
,
246 [CC_OP_SUBB
... CC_OP_SUBL
] = CCF_X
| CCF_N
| CCF_V
,
247 [CC_OP_CMPB
... CC_OP_CMPL
] = CCF_X
| CCF_N
| CCF_V
,
248 [CC_OP_LOGIC
] = CCF_X
| CCF_N
251 static void set_cc_op(DisasContext
*s
, CCOp op
)
253 CCOp old_op
= s
->cc_op
;
263 * Discard CC computation that will no longer be used.
264 * Note that X and N are never dead.
266 dead
= cc_op_live
[old_op
] & ~cc_op_live
[op
];
268 tcg_gen_discard_i32(QREG_CC_C
);
271 tcg_gen_discard_i32(QREG_CC_Z
);
274 tcg_gen_discard_i32(QREG_CC_V
);
278 /* Update the CPU env CC_OP state. */
279 static void update_cc_op(DisasContext
*s
)
281 if (!s
->cc_op_synced
) {
283 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
287 /* Generate a jump to an immediate address. */
288 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
291 tcg_gen_movi_i32(QREG_PC
, dest
);
292 s
->base
.is_jmp
= DISAS_JUMP
;
295 /* Generate a jump to the address in qreg DEST. */
296 static void gen_jmp(DisasContext
*s
, TCGv dest
)
299 tcg_gen_mov_i32(QREG_PC
, dest
);
300 s
->base
.is_jmp
= DISAS_JUMP
;
303 static void gen_raise_exception(int nr
)
307 tmp
= tcg_const_i32(nr
);
308 gen_helper_raise_exception(cpu_env
, tmp
);
309 tcg_temp_free_i32(tmp
);
312 static void gen_exception(DisasContext
*s
, uint32_t dest
, int nr
)
315 tcg_gen_movi_i32(QREG_PC
, dest
);
317 gen_raise_exception(nr
);
319 s
->base
.is_jmp
= DISAS_NORETURN
;
322 static inline void gen_addr_fault(DisasContext
*s
)
324 gen_exception(s
, s
->base
.pc_next
, EXCP_ADDRESS
);
328 * Generate a load from the specified address. Narrow values are
329 * sign extended to full register width.
331 static inline TCGv
gen_load(DisasContext
*s
, int opsize
, TCGv addr
,
335 tmp
= tcg_temp_new_i32();
339 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
341 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
345 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
347 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
350 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
353 g_assert_not_reached();
358 /* Generate a store. */
359 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
364 tcg_gen_qemu_st8(val
, addr
, index
);
367 tcg_gen_qemu_st16(val
, addr
, index
);
370 tcg_gen_qemu_st32(val
, addr
, index
);
373 g_assert_not_reached();
384 * Generate an unsigned load if VAL is 0 a signed load if val is -1,
385 * otherwise generate a store.
387 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
388 ea_what what
, int index
)
390 if (what
== EA_STORE
) {
391 gen_store(s
, opsize
, addr
, val
, index
);
394 return mark_to_release(s
, gen_load(s
, opsize
, addr
,
395 what
== EA_LOADS
, index
));
399 /* Read a 16-bit immediate constant */
400 static inline uint16_t read_im16(CPUM68KState
*env
, DisasContext
*s
)
403 im
= translator_lduw(env
, s
->pc
);
408 /* Read an 8-bit immediate constant */
409 static inline uint8_t read_im8(CPUM68KState
*env
, DisasContext
*s
)
411 return read_im16(env
, s
);
414 /* Read a 32-bit immediate constant. */
415 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
418 im
= read_im16(env
, s
) << 16;
419 im
|= 0xffff & read_im16(env
, s
);
423 /* Read a 64-bit immediate constant. */
424 static inline uint64_t read_im64(CPUM68KState
*env
, DisasContext
*s
)
427 im
= (uint64_t)read_im32(env
, s
) << 32;
428 im
|= (uint64_t)read_im32(env
, s
);
432 /* Calculate and address index. */
433 static TCGv
gen_addr_index(DisasContext
*s
, uint16_t ext
, TCGv tmp
)
438 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
439 if ((ext
& 0x800) == 0) {
440 tcg_gen_ext16s_i32(tmp
, add
);
443 scale
= (ext
>> 9) & 3;
445 tcg_gen_shli_i32(tmp
, add
, scale
);
452 * Handle a base + index + displacement effective address.
453 * A NULL_QREG base means pc-relative.
455 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
464 ext
= read_im16(env
, s
);
466 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
469 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
) &&
470 !m68k_feature(s
->env
, M68K_FEATURE_SCALED_INDEX
)) {
475 /* full extension word format */
476 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
479 if ((ext
& 0x30) > 0x10) {
480 /* base displacement */
481 if ((ext
& 0x30) == 0x20) {
482 bd
= (int16_t)read_im16(env
, s
);
484 bd
= read_im32(env
, s
);
489 tmp
= mark_to_release(s
, tcg_temp_new());
490 if ((ext
& 0x44) == 0) {
492 add
= gen_addr_index(s
, ext
, tmp
);
496 if ((ext
& 0x80) == 0) {
497 /* base not suppressed */
498 if (IS_NULL_QREG(base
)) {
499 base
= mark_to_release(s
, tcg_const_i32(offset
+ bd
));
502 if (!IS_NULL_QREG(add
)) {
503 tcg_gen_add_i32(tmp
, add
, base
);
509 if (!IS_NULL_QREG(add
)) {
511 tcg_gen_addi_i32(tmp
, add
, bd
);
515 add
= mark_to_release(s
, tcg_const_i32(bd
));
517 if ((ext
& 3) != 0) {
518 /* memory indirect */
519 base
= mark_to_release(s
, gen_load(s
, OS_LONG
, add
, 0, IS_USER(s
)));
520 if ((ext
& 0x44) == 4) {
521 add
= gen_addr_index(s
, ext
, tmp
);
522 tcg_gen_add_i32(tmp
, add
, base
);
528 /* outer displacement */
529 if ((ext
& 3) == 2) {
530 od
= (int16_t)read_im16(env
, s
);
532 od
= read_im32(env
, s
);
538 tcg_gen_addi_i32(tmp
, add
, od
);
543 /* brief extension word format */
544 tmp
= mark_to_release(s
, tcg_temp_new());
545 add
= gen_addr_index(s
, ext
, tmp
);
546 if (!IS_NULL_QREG(base
)) {
547 tcg_gen_add_i32(tmp
, add
, base
);
549 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
551 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
558 /* Sign or zero extend a value. */
560 static inline void gen_ext(TCGv res
, TCGv val
, int opsize
, int sign
)
565 tcg_gen_ext8s_i32(res
, val
);
567 tcg_gen_ext8u_i32(res
, val
);
572 tcg_gen_ext16s_i32(res
, val
);
574 tcg_gen_ext16u_i32(res
, val
);
578 tcg_gen_mov_i32(res
, val
);
581 g_assert_not_reached();
585 /* Evaluate all the CC flags. */
587 static void gen_flush_flags(DisasContext
*s
)
598 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
599 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
600 /* Compute signed overflow for addition. */
603 tcg_gen_sub_i32(t0
, QREG_CC_N
, QREG_CC_V
);
604 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_ADDB
, 1);
605 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
606 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
608 tcg_gen_andc_i32(QREG_CC_V
, t1
, QREG_CC_V
);
615 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
616 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
617 /* Compute signed overflow for subtraction. */
620 tcg_gen_add_i32(t0
, QREG_CC_N
, QREG_CC_V
);
621 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_SUBB
, 1);
622 tcg_gen_xor_i32(t1
, QREG_CC_N
, t0
);
623 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
625 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t1
);
632 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_C
, QREG_CC_N
, QREG_CC_V
);
633 tcg_gen_sub_i32(QREG_CC_Z
, QREG_CC_N
, QREG_CC_V
);
634 gen_ext(QREG_CC_Z
, QREG_CC_Z
, s
->cc_op
- CC_OP_CMPB
, 1);
635 /* Compute signed overflow for subtraction. */
637 tcg_gen_xor_i32(t0
, QREG_CC_Z
, QREG_CC_N
);
638 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, QREG_CC_N
);
639 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t0
);
641 tcg_gen_mov_i32(QREG_CC_N
, QREG_CC_Z
);
645 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
646 tcg_gen_movi_i32(QREG_CC_C
, 0);
647 tcg_gen_movi_i32(QREG_CC_V
, 0);
651 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
656 t0
= tcg_const_i32(s
->cc_op
);
657 gen_helper_flush_flags(cpu_env
, t0
);
663 /* Note that flush_flags also assigned to env->cc_op. */
664 s
->cc_op
= CC_OP_FLAGS
;
667 static inline TCGv
gen_extend(DisasContext
*s
, TCGv val
, int opsize
, int sign
)
671 if (opsize
== OS_LONG
) {
674 tmp
= mark_to_release(s
, tcg_temp_new());
675 gen_ext(tmp
, val
, opsize
, sign
);
681 static void gen_logic_cc(DisasContext
*s
, TCGv val
, int opsize
)
683 gen_ext(QREG_CC_N
, val
, opsize
, 1);
684 set_cc_op(s
, CC_OP_LOGIC
);
687 static void gen_update_cc_cmp(DisasContext
*s
, TCGv dest
, TCGv src
, int opsize
)
689 tcg_gen_mov_i32(QREG_CC_N
, dest
);
690 tcg_gen_mov_i32(QREG_CC_V
, src
);
691 set_cc_op(s
, CC_OP_CMPB
+ opsize
);
694 static void gen_update_cc_add(TCGv dest
, TCGv src
, int opsize
)
696 gen_ext(QREG_CC_N
, dest
, opsize
, 1);
697 tcg_gen_mov_i32(QREG_CC_V
, src
);
700 static inline int opsize_bytes(int opsize
)
703 case OS_BYTE
: return 1;
704 case OS_WORD
: return 2;
705 case OS_LONG
: return 4;
706 case OS_SINGLE
: return 4;
707 case OS_DOUBLE
: return 8;
708 case OS_EXTENDED
: return 12;
709 case OS_PACKED
: return 12;
711 g_assert_not_reached();
715 static inline int insn_opsize(int insn
)
717 switch ((insn
>> 6) & 3) {
718 case 0: return OS_BYTE
;
719 case 1: return OS_WORD
;
720 case 2: return OS_LONG
;
722 g_assert_not_reached();
726 static inline int ext_opsize(int ext
, int pos
)
728 switch ((ext
>> pos
) & 7) {
729 case 0: return OS_LONG
;
730 case 1: return OS_SINGLE
;
731 case 2: return OS_EXTENDED
;
732 case 3: return OS_PACKED
;
733 case 4: return OS_WORD
;
734 case 5: return OS_DOUBLE
;
735 case 6: return OS_BYTE
;
737 g_assert_not_reached();
742 * Assign value to a register. If the width is less than the register width
743 * only the low part of the register is set.
745 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
750 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
751 tmp
= tcg_temp_new();
752 tcg_gen_ext8u_i32(tmp
, val
);
753 tcg_gen_or_i32(reg
, reg
, tmp
);
757 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
758 tmp
= tcg_temp_new();
759 tcg_gen_ext16u_i32(tmp
, val
);
760 tcg_gen_or_i32(reg
, reg
, tmp
);
765 tcg_gen_mov_i32(reg
, val
);
768 g_assert_not_reached();
773 * Generate code for an "effective address". Does not adjust the base
774 * register for autoincrement addressing modes.
776 static TCGv
gen_lea_mode(CPUM68KState
*env
, DisasContext
*s
,
777 int mode
, int reg0
, int opsize
)
785 case 0: /* Data register direct. */
786 case 1: /* Address register direct. */
788 case 3: /* Indirect postincrement. */
789 if (opsize
== OS_UNSIZED
) {
793 case 2: /* Indirect register */
794 return get_areg(s
, reg0
);
795 case 4: /* Indirect predecrememnt. */
796 if (opsize
== OS_UNSIZED
) {
799 reg
= get_areg(s
, reg0
);
800 tmp
= mark_to_release(s
, tcg_temp_new());
801 if (reg0
== 7 && opsize
== OS_BYTE
&&
802 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
803 tcg_gen_subi_i32(tmp
, reg
, 2);
805 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
808 case 5: /* Indirect displacement. */
809 reg
= get_areg(s
, reg0
);
810 tmp
= mark_to_release(s
, tcg_temp_new());
811 ext
= read_im16(env
, s
);
812 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
814 case 6: /* Indirect index + displacement. */
815 reg
= get_areg(s
, reg0
);
816 return gen_lea_indexed(env
, s
, reg
);
819 case 0: /* Absolute short. */
820 offset
= (int16_t)read_im16(env
, s
);
821 return mark_to_release(s
, tcg_const_i32(offset
));
822 case 1: /* Absolute long. */
823 offset
= read_im32(env
, s
);
824 return mark_to_release(s
, tcg_const_i32(offset
));
825 case 2: /* pc displacement */
827 offset
+= (int16_t)read_im16(env
, s
);
828 return mark_to_release(s
, tcg_const_i32(offset
));
829 case 3: /* pc index+displacement. */
830 return gen_lea_indexed(env
, s
, NULL_QREG
);
831 case 4: /* Immediate. */
836 /* Should never happen. */
840 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
843 int mode
= extract32(insn
, 3, 3);
844 int reg0
= REG(insn
, 0);
845 return gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
849 * Generate code to load/store a value from/into an EA. If WHAT > 0 this is
850 * a write otherwise it is a read (0 == sign extend, -1 == zero extend).
851 * ADDRP is non-null for readwrite operands.
853 static TCGv
gen_ea_mode(CPUM68KState
*env
, DisasContext
*s
, int mode
, int reg0
,
854 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
,
857 TCGv reg
, tmp
, result
;
861 case 0: /* Data register direct. */
862 reg
= cpu_dregs
[reg0
];
863 if (what
== EA_STORE
) {
864 gen_partset_reg(opsize
, reg
, val
);
867 return gen_extend(s
, reg
, opsize
, what
== EA_LOADS
);
869 case 1: /* Address register direct. */
870 reg
= get_areg(s
, reg0
);
871 if (what
== EA_STORE
) {
872 tcg_gen_mov_i32(reg
, val
);
875 return gen_extend(s
, reg
, opsize
, what
== EA_LOADS
);
877 case 2: /* Indirect register */
878 reg
= get_areg(s
, reg0
);
879 return gen_ldst(s
, opsize
, reg
, val
, what
, index
);
880 case 3: /* Indirect postincrement. */
881 reg
= get_areg(s
, reg0
);
882 result
= gen_ldst(s
, opsize
, reg
, val
, what
, index
);
883 if (what
== EA_STORE
|| !addrp
) {
884 TCGv tmp
= tcg_temp_new();
885 if (reg0
== 7 && opsize
== OS_BYTE
&&
886 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
887 tcg_gen_addi_i32(tmp
, reg
, 2);
889 tcg_gen_addi_i32(tmp
, reg
, opsize_bytes(opsize
));
891 delay_set_areg(s
, reg0
, tmp
, true);
894 case 4: /* Indirect predecrememnt. */
895 if (addrp
&& what
== EA_STORE
) {
898 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
899 if (IS_NULL_QREG(tmp
)) {
906 result
= gen_ldst(s
, opsize
, tmp
, val
, what
, index
);
907 if (what
== EA_STORE
|| !addrp
) {
908 delay_set_areg(s
, reg0
, tmp
, false);
911 case 5: /* Indirect displacement. */
912 case 6: /* Indirect index + displacement. */
914 if (addrp
&& what
== EA_STORE
) {
917 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
918 if (IS_NULL_QREG(tmp
)) {
925 return gen_ldst(s
, opsize
, tmp
, val
, what
, index
);
928 case 0: /* Absolute short. */
929 case 1: /* Absolute long. */
930 case 2: /* pc displacement */
931 case 3: /* pc index+displacement. */
933 case 4: /* Immediate. */
934 /* Sign extend values for consistency. */
937 if (what
== EA_LOADS
) {
938 offset
= (int8_t)read_im8(env
, s
);
940 offset
= read_im8(env
, s
);
944 if (what
== EA_LOADS
) {
945 offset
= (int16_t)read_im16(env
, s
);
947 offset
= read_im16(env
, s
);
951 offset
= read_im32(env
, s
);
954 g_assert_not_reached();
956 return mark_to_release(s
, tcg_const_i32(offset
));
961 /* Should never happen. */
965 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
966 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
, int index
)
968 int mode
= extract32(insn
, 3, 3);
969 int reg0
= REG(insn
, 0);
970 return gen_ea_mode(env
, s
, mode
, reg0
, opsize
, val
, addrp
, what
, index
);
973 static TCGv_ptr
gen_fp_ptr(int freg
)
975 TCGv_ptr fp
= tcg_temp_new_ptr();
976 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fregs
[freg
]));
980 static TCGv_ptr
gen_fp_result_ptr(void)
982 TCGv_ptr fp
= tcg_temp_new_ptr();
983 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fp_result
));
987 static void gen_fp_move(TCGv_ptr dest
, TCGv_ptr src
)
992 t32
= tcg_temp_new();
993 tcg_gen_ld16u_i32(t32
, src
, offsetof(FPReg
, l
.upper
));
994 tcg_gen_st16_i32(t32
, dest
, offsetof(FPReg
, l
.upper
));
997 t64
= tcg_temp_new_i64();
998 tcg_gen_ld_i64(t64
, src
, offsetof(FPReg
, l
.lower
));
999 tcg_gen_st_i64(t64
, dest
, offsetof(FPReg
, l
.lower
));
1000 tcg_temp_free_i64(t64
);
1003 static void gen_load_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
,
1009 t64
= tcg_temp_new_i64();
1010 tmp
= tcg_temp_new();
1013 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
1014 gen_helper_exts32(cpu_env
, fp
, tmp
);
1017 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
1018 gen_helper_exts32(cpu_env
, fp
, tmp
);
1021 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1022 gen_helper_exts32(cpu_env
, fp
, tmp
);
1025 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1026 gen_helper_extf32(cpu_env
, fp
, tmp
);
1029 tcg_gen_qemu_ld64(t64
, addr
, index
);
1030 gen_helper_extf64(cpu_env
, fp
, t64
);
1033 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1034 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1037 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1038 tcg_gen_shri_i32(tmp
, tmp
, 16);
1039 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1040 tcg_gen_addi_i32(tmp
, addr
, 4);
1041 tcg_gen_qemu_ld64(t64
, tmp
, index
);
1042 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1046 * unimplemented data type on 68040/ColdFire
1047 * FIXME if needed for another FPU
1049 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1052 g_assert_not_reached();
1055 tcg_temp_free_i64(t64
);
1058 static void gen_store_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
,
1064 t64
= tcg_temp_new_i64();
1065 tmp
= tcg_temp_new();
1068 gen_helper_reds32(tmp
, cpu_env
, fp
);
1069 tcg_gen_qemu_st8(tmp
, addr
, index
);
1072 gen_helper_reds32(tmp
, cpu_env
, fp
);
1073 tcg_gen_qemu_st16(tmp
, addr
, index
);
1076 gen_helper_reds32(tmp
, cpu_env
, fp
);
1077 tcg_gen_qemu_st32(tmp
, addr
, index
);
1080 gen_helper_redf32(tmp
, cpu_env
, fp
);
1081 tcg_gen_qemu_st32(tmp
, addr
, index
);
1084 gen_helper_redf64(t64
, cpu_env
, fp
);
1085 tcg_gen_qemu_st64(t64
, addr
, index
);
1088 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1089 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1092 tcg_gen_ld16u_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1093 tcg_gen_shli_i32(tmp
, tmp
, 16);
1094 tcg_gen_qemu_st32(tmp
, addr
, index
);
1095 tcg_gen_addi_i32(tmp
, addr
, 4);
1096 tcg_gen_ld_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1097 tcg_gen_qemu_st64(t64
, tmp
, index
);
1101 * unimplemented data type on 68040/ColdFire
1102 * FIXME if needed for another FPU
1104 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1107 g_assert_not_reached();
1110 tcg_temp_free_i64(t64
);
1113 static void gen_ldst_fp(DisasContext
*s
, int opsize
, TCGv addr
,
1114 TCGv_ptr fp
, ea_what what
, int index
)
1116 if (what
== EA_STORE
) {
1117 gen_store_fp(s
, opsize
, addr
, fp
, index
);
1119 gen_load_fp(s
, opsize
, addr
, fp
, index
);
1123 static int gen_ea_mode_fp(CPUM68KState
*env
, DisasContext
*s
, int mode
,
1124 int reg0
, int opsize
, TCGv_ptr fp
, ea_what what
,
1127 TCGv reg
, addr
, tmp
;
1131 case 0: /* Data register direct. */
1132 reg
= cpu_dregs
[reg0
];
1133 if (what
== EA_STORE
) {
1138 gen_helper_reds32(reg
, cpu_env
, fp
);
1141 gen_helper_redf32(reg
, cpu_env
, fp
);
1144 g_assert_not_reached();
1147 tmp
= tcg_temp_new();
1150 tcg_gen_ext8s_i32(tmp
, reg
);
1151 gen_helper_exts32(cpu_env
, fp
, tmp
);
1154 tcg_gen_ext16s_i32(tmp
, reg
);
1155 gen_helper_exts32(cpu_env
, fp
, tmp
);
1158 gen_helper_exts32(cpu_env
, fp
, reg
);
1161 gen_helper_extf32(cpu_env
, fp
, reg
);
1164 g_assert_not_reached();
1169 case 1: /* Address register direct. */
1171 case 2: /* Indirect register */
1172 addr
= get_areg(s
, reg0
);
1173 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1175 case 3: /* Indirect postincrement. */
1176 addr
= cpu_aregs
[reg0
];
1177 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1178 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(opsize
));
1180 case 4: /* Indirect predecrememnt. */
1181 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1182 if (IS_NULL_QREG(addr
)) {
1185 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1186 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
1188 case 5: /* Indirect displacement. */
1189 case 6: /* Indirect index + displacement. */
1191 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1192 if (IS_NULL_QREG(addr
)) {
1195 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1199 case 0: /* Absolute short. */
1200 case 1: /* Absolute long. */
1201 case 2: /* pc displacement */
1202 case 3: /* pc index+displacement. */
1204 case 4: /* Immediate. */
1205 if (what
== EA_STORE
) {
1210 tmp
= tcg_const_i32((int8_t)read_im8(env
, s
));
1211 gen_helper_exts32(cpu_env
, fp
, tmp
);
1215 tmp
= tcg_const_i32((int16_t)read_im16(env
, s
));
1216 gen_helper_exts32(cpu_env
, fp
, tmp
);
1220 tmp
= tcg_const_i32(read_im32(env
, s
));
1221 gen_helper_exts32(cpu_env
, fp
, tmp
);
1225 tmp
= tcg_const_i32(read_im32(env
, s
));
1226 gen_helper_extf32(cpu_env
, fp
, tmp
);
1230 t64
= tcg_const_i64(read_im64(env
, s
));
1231 gen_helper_extf64(cpu_env
, fp
, t64
);
1232 tcg_temp_free_i64(t64
);
1235 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1236 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1239 tmp
= tcg_const_i32(read_im32(env
, s
) >> 16);
1240 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1242 t64
= tcg_const_i64(read_im64(env
, s
));
1243 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1244 tcg_temp_free_i64(t64
);
1248 * unimplemented data type on 68040/ColdFire
1249 * FIXME if needed for another FPU
1251 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1254 g_assert_not_reached();
1264 static int gen_ea_fp(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1265 int opsize
, TCGv_ptr fp
, ea_what what
, int index
)
1267 int mode
= extract32(insn
, 3, 3);
1268 int reg0
= REG(insn
, 0);
1269 return gen_ea_mode_fp(env
, s
, mode
, reg0
, opsize
, fp
, what
, index
);
1280 static void gen_cc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
1286 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1287 if (op
== CC_OP_CMPB
|| op
== CC_OP_CMPW
|| op
== CC_OP_CMPL
) {
1294 tcond
= TCG_COND_LEU
;
1298 tcond
= TCG_COND_LTU
;
1302 tcond
= TCG_COND_EQ
;
1307 c
->v2
= tcg_const_i32(0);
1308 c
->v1
= tmp
= tcg_temp_new();
1309 tcg_gen_sub_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1310 gen_ext(tmp
, tmp
, op
- CC_OP_CMPB
, 1);
1314 tcond
= TCG_COND_LT
;
1318 tcond
= TCG_COND_LE
;
1325 c
->v2
= tcg_const_i32(0);
1331 tcond
= TCG_COND_NEVER
;
1333 case 14: /* GT (!(Z || (N ^ V))) */
1334 case 15: /* LE (Z || (N ^ V)) */
1336 * Logic operations clear V, which simplifies LE to (Z || N),
1337 * and since Z and N are co-located, this becomes a normal
1340 if (op
== CC_OP_LOGIC
) {
1342 tcond
= TCG_COND_LE
;
1346 case 12: /* GE (!(N ^ V)) */
1347 case 13: /* LT (N ^ V) */
1348 /* Logic operations clear V, which simplifies this to N. */
1349 if (op
!= CC_OP_LOGIC
) {
1353 case 10: /* PL (!N) */
1354 case 11: /* MI (N) */
1355 /* Several cases represent N normally. */
1356 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1357 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1358 op
== CC_OP_LOGIC
) {
1360 tcond
= TCG_COND_LT
;
1364 case 6: /* NE (!Z) */
1365 case 7: /* EQ (Z) */
1366 /* Some cases fold Z into N. */
1367 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1368 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1369 op
== CC_OP_LOGIC
) {
1370 tcond
= TCG_COND_EQ
;
1375 case 4: /* CC (!C) */
1376 case 5: /* CS (C) */
1377 /* Some cases fold C into X. */
1378 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1379 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
) {
1380 tcond
= TCG_COND_NE
;
1385 case 8: /* VC (!V) */
1386 case 9: /* VS (V) */
1387 /* Logic operations clear V and C. */
1388 if (op
== CC_OP_LOGIC
) {
1389 tcond
= TCG_COND_NEVER
;
1396 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1403 /* Invalid, or handled above. */
1405 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1406 case 3: /* LS (C || Z) */
1407 c
->v1
= tmp
= tcg_temp_new();
1409 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1410 tcg_gen_or_i32(tmp
, tmp
, QREG_CC_C
);
1411 tcond
= TCG_COND_NE
;
1413 case 4: /* CC (!C) */
1414 case 5: /* CS (C) */
1416 tcond
= TCG_COND_NE
;
1418 case 6: /* NE (!Z) */
1419 case 7: /* EQ (Z) */
1421 tcond
= TCG_COND_EQ
;
1423 case 8: /* VC (!V) */
1424 case 9: /* VS (V) */
1426 tcond
= TCG_COND_LT
;
1428 case 10: /* PL (!N) */
1429 case 11: /* MI (N) */
1431 tcond
= TCG_COND_LT
;
1433 case 12: /* GE (!(N ^ V)) */
1434 case 13: /* LT (N ^ V) */
1435 c
->v1
= tmp
= tcg_temp_new();
1437 tcg_gen_xor_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1438 tcond
= TCG_COND_LT
;
1440 case 14: /* GT (!(Z || (N ^ V))) */
1441 case 15: /* LE (Z || (N ^ V)) */
1442 c
->v1
= tmp
= tcg_temp_new();
1444 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1445 tcg_gen_neg_i32(tmp
, tmp
);
1446 tmp2
= tcg_temp_new();
1447 tcg_gen_xor_i32(tmp2
, QREG_CC_N
, QREG_CC_V
);
1448 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1449 tcg_temp_free(tmp2
);
1450 tcond
= TCG_COND_LT
;
1455 if ((cond
& 1) == 0) {
1456 tcond
= tcg_invert_cond(tcond
);
1461 static void free_cond(DisasCompare
*c
)
1464 tcg_temp_free(c
->v1
);
1467 tcg_temp_free(c
->v2
);
1471 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
1475 gen_cc_cond(&c
, s
, cond
);
1477 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
1481 /* Force a TB lookup after an instruction that changes the CPU state. */
1482 static void gen_exit_tb(DisasContext
*s
)
1485 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
1486 s
->base
.is_jmp
= DISAS_EXIT
;
1489 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1490 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1491 op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \
1492 if (IS_NULL_QREG(result)) { \
1493 gen_addr_fault(s); \
1498 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1499 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, \
1500 EA_STORE, IS_USER(s)); \
1501 if (IS_NULL_QREG(ea_result)) { \
1502 gen_addr_fault(s); \
1507 static inline bool use_goto_tb(DisasContext
*s
, uint32_t dest
)
1509 #ifndef CONFIG_USER_ONLY
1510 return (s
->base
.pc_first
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)
1511 || (s
->base
.pc_next
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
1517 /* Generate a jump to an immediate address. */
1518 static void gen_jmp_tb(DisasContext
*s
, int n
, uint32_t dest
)
1520 if (unlikely(is_singlestepping(s
))) {
1522 tcg_gen_movi_i32(QREG_PC
, dest
);
1523 gen_raise_exception(EXCP_DEBUG
);
1524 } else if (use_goto_tb(s
, dest
)) {
1526 tcg_gen_movi_i32(QREG_PC
, dest
);
1527 tcg_gen_exit_tb(s
->base
.tb
, n
);
1529 gen_jmp_im(s
, dest
);
1530 tcg_gen_exit_tb(NULL
, 0);
1532 s
->base
.is_jmp
= DISAS_NORETURN
;
1541 cond
= (insn
>> 8) & 0xf;
1542 gen_cc_cond(&c
, s
, cond
);
1544 tmp
= tcg_temp_new();
1545 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
1548 tcg_gen_neg_i32(tmp
, tmp
);
1549 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
1561 reg
= DREG(insn
, 0);
1563 offset
= (int16_t)read_im16(env
, s
);
1564 l1
= gen_new_label();
1565 gen_jmpcc(s
, (insn
>> 8) & 0xf, l1
);
1567 tmp
= tcg_temp_new();
1568 tcg_gen_ext16s_i32(tmp
, reg
);
1569 tcg_gen_addi_i32(tmp
, tmp
, -1);
1570 gen_partset_reg(OS_WORD
, reg
, tmp
);
1571 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, -1, l1
);
1572 gen_jmp_tb(s
, 1, base
+ offset
);
1574 gen_jmp_tb(s
, 0, s
->pc
);
1577 DISAS_INSN(undef_mac
)
1579 gen_exception(s
, s
->base
.pc_next
, EXCP_LINEA
);
1582 DISAS_INSN(undef_fpu
)
1584 gen_exception(s
, s
->base
.pc_next
, EXCP_LINEF
);
1590 * ??? This is both instructions that are as yet unimplemented
1591 * for the 680x0 series, as well as those that are implemented
1592 * but actually illegal for CPU32 or pre-68020.
1594 qemu_log_mask(LOG_UNIMP
, "Illegal instruction: %04x @ %08x\n",
1595 insn
, s
->base
.pc_next
);
1596 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
1606 sign
= (insn
& 0x100) != 0;
1607 reg
= DREG(insn
, 9);
1608 tmp
= tcg_temp_new();
1610 tcg_gen_ext16s_i32(tmp
, reg
);
1612 tcg_gen_ext16u_i32(tmp
, reg
);
1613 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1614 tcg_gen_mul_i32(tmp
, tmp
, src
);
1615 tcg_gen_mov_i32(reg
, tmp
);
1616 gen_logic_cc(s
, tmp
, OS_LONG
);
1626 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1628 sign
= (insn
& 0x100) != 0;
1630 /* dest.l / src.w */
1632 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1633 destr
= tcg_const_i32(REG(insn
, 9));
1635 gen_helper_divsw(cpu_env
, destr
, src
);
1637 gen_helper_divuw(cpu_env
, destr
, src
);
1639 tcg_temp_free(destr
);
1641 set_cc_op(s
, CC_OP_FLAGS
);
1650 ext
= read_im16(env
, s
);
1652 sign
= (ext
& 0x0800) != 0;
1655 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
1656 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
1660 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1662 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1663 num
= tcg_const_i32(REG(ext
, 12));
1664 reg
= tcg_const_i32(REG(ext
, 0));
1666 gen_helper_divsll(cpu_env
, num
, reg
, den
);
1668 gen_helper_divull(cpu_env
, num
, reg
, den
);
1672 set_cc_op(s
, CC_OP_FLAGS
);
1676 /* divX.l <EA>, Dq 32/32 -> 32q */
1677 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1679 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1680 num
= tcg_const_i32(REG(ext
, 12));
1681 reg
= tcg_const_i32(REG(ext
, 0));
1683 gen_helper_divsl(cpu_env
, num
, reg
, den
);
1685 gen_helper_divul(cpu_env
, num
, reg
, den
);
1690 set_cc_op(s
, CC_OP_FLAGS
);
1693 static void bcd_add(TCGv dest
, TCGv src
)
1698 * dest10 = dest10 + src10 + X
1702 * t3 = t2 + dest + X
1706 * t7 = (t6 >> 2) | (t6 >> 3)
1711 * t1 = (src + 0x066) + dest + X
1712 * = result with some possible exceeding 0x6
1715 t0
= tcg_const_i32(0x066);
1716 tcg_gen_add_i32(t0
, t0
, src
);
1718 t1
= tcg_temp_new();
1719 tcg_gen_add_i32(t1
, t0
, dest
);
1720 tcg_gen_add_i32(t1
, t1
, QREG_CC_X
);
1722 /* we will remove exceeding 0x6 where there is no carry */
1725 * t0 = (src + 0x0066) ^ dest
1726 * = t1 without carries
1729 tcg_gen_xor_i32(t0
, t0
, dest
);
1732 * extract the carries
1734 * = only the carries
1737 tcg_gen_xor_i32(t0
, t0
, t1
);
1740 * generate 0x1 where there is no carry
1741 * and for each 0x10, generate a 0x6
1744 tcg_gen_shri_i32(t0
, t0
, 3);
1745 tcg_gen_not_i32(t0
, t0
);
1746 tcg_gen_andi_i32(t0
, t0
, 0x22);
1747 tcg_gen_add_i32(dest
, t0
, t0
);
1748 tcg_gen_add_i32(dest
, dest
, t0
);
1752 * remove the exceeding 0x6
1753 * for digits that have not generated a carry
1756 tcg_gen_sub_i32(dest
, t1
, dest
);
1760 static void bcd_sub(TCGv dest
, TCGv src
)
1765 * dest10 = dest10 - src10 - X
1766 * = bcd_add(dest + 1 - X, 0x199 - src)
1769 /* t0 = 0x066 + (0x199 - src) */
1771 t0
= tcg_temp_new();
1772 tcg_gen_subfi_i32(t0
, 0x1ff, src
);
1774 /* t1 = t0 + dest + 1 - X*/
1776 t1
= tcg_temp_new();
1777 tcg_gen_add_i32(t1
, t0
, dest
);
1778 tcg_gen_addi_i32(t1
, t1
, 1);
1779 tcg_gen_sub_i32(t1
, t1
, QREG_CC_X
);
1781 /* t2 = t0 ^ dest */
1783 t2
= tcg_temp_new();
1784 tcg_gen_xor_i32(t2
, t0
, dest
);
1788 tcg_gen_xor_i32(t0
, t1
, t2
);
1792 * t0 = (t2 >> 2) | (t2 >> 3)
1794 * to fit on 8bit operands, changed in:
1796 * t2 = ~(t0 >> 3) & 0x22
1801 tcg_gen_shri_i32(t2
, t0
, 3);
1802 tcg_gen_not_i32(t2
, t2
);
1803 tcg_gen_andi_i32(t2
, t2
, 0x22);
1804 tcg_gen_add_i32(t0
, t2
, t2
);
1805 tcg_gen_add_i32(t0
, t0
, t2
);
1808 /* return t1 - t0 */
1810 tcg_gen_sub_i32(dest
, t1
, t0
);
1815 static void bcd_flags(TCGv val
)
1817 tcg_gen_andi_i32(QREG_CC_C
, val
, 0x0ff);
1818 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_C
);
1820 tcg_gen_extract_i32(QREG_CC_C
, val
, 8, 1);
1822 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
1825 DISAS_INSN(abcd_reg
)
1830 gen_flush_flags(s
); /* !Z is sticky */
1832 src
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
1833 dest
= gen_extend(s
, DREG(insn
, 9), OS_BYTE
, 0);
1835 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1840 DISAS_INSN(abcd_mem
)
1842 TCGv src
, dest
, addr
;
1844 gen_flush_flags(s
); /* !Z is sticky */
1846 /* Indirect pre-decrement load (mode 4) */
1848 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1849 NULL_QREG
, NULL
, EA_LOADU
, IS_USER(s
));
1850 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1851 NULL_QREG
, &addr
, EA_LOADU
, IS_USER(s
));
1855 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
,
1856 EA_STORE
, IS_USER(s
));
1861 DISAS_INSN(sbcd_reg
)
1865 gen_flush_flags(s
); /* !Z is sticky */
1867 src
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
1868 dest
= gen_extend(s
, DREG(insn
, 9), OS_BYTE
, 0);
1872 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1877 DISAS_INSN(sbcd_mem
)
1879 TCGv src
, dest
, addr
;
1881 gen_flush_flags(s
); /* !Z is sticky */
1883 /* Indirect pre-decrement load (mode 4) */
1885 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1886 NULL_QREG
, NULL
, EA_LOADU
, IS_USER(s
));
1887 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1888 NULL_QREG
, &addr
, EA_LOADU
, IS_USER(s
));
1892 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
,
1893 EA_STORE
, IS_USER(s
));
1903 gen_flush_flags(s
); /* !Z is sticky */
1905 SRC_EA(env
, src
, OS_BYTE
, 0, &addr
);
1907 dest
= tcg_const_i32(0);
1910 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1914 tcg_temp_free(dest
);
1927 add
= (insn
& 0x4000) != 0;
1928 opsize
= insn_opsize(insn
);
1929 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
1930 dest
= tcg_temp_new();
1932 SRC_EA(env
, tmp
, opsize
, 1, &addr
);
1936 SRC_EA(env
, src
, opsize
, 1, NULL
);
1939 tcg_gen_add_i32(dest
, tmp
, src
);
1940 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src
);
1941 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
1943 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, tmp
, src
);
1944 tcg_gen_sub_i32(dest
, tmp
, src
);
1945 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
1947 gen_update_cc_add(dest
, src
, opsize
);
1949 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1951 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
1953 tcg_temp_free(dest
);
1956 /* Reverse the order of the bits in REG. */
1960 reg
= DREG(insn
, 0);
1961 gen_helper_bitrev(reg
, reg
);
1964 DISAS_INSN(bitop_reg
)
1974 if ((insn
& 0x38) != 0)
1978 op
= (insn
>> 6) & 3;
1979 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1982 src2
= tcg_temp_new();
1983 if (opsize
== OS_BYTE
)
1984 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 7);
1986 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 31);
1988 tmp
= tcg_const_i32(1);
1989 tcg_gen_shl_i32(tmp
, tmp
, src2
);
1990 tcg_temp_free(src2
);
1992 tcg_gen_and_i32(QREG_CC_Z
, src1
, tmp
);
1994 dest
= tcg_temp_new();
1997 tcg_gen_xor_i32(dest
, src1
, tmp
);
2000 tcg_gen_andc_i32(dest
, src1
, tmp
);
2003 tcg_gen_or_i32(dest
, src1
, tmp
);
2010 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2012 tcg_temp_free(dest
);
2018 reg
= DREG(insn
, 0);
2020 gen_helper_sats(reg
, reg
, QREG_CC_V
);
2021 gen_logic_cc(s
, reg
, OS_LONG
);
2024 static void gen_push(DisasContext
*s
, TCGv val
)
2028 tmp
= tcg_temp_new();
2029 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
2030 gen_store(s
, OS_LONG
, tmp
, val
, IS_USER(s
));
2031 tcg_gen_mov_i32(QREG_SP
, tmp
);
2035 static TCGv
mreg(int reg
)
2039 return cpu_dregs
[reg
];
2042 return cpu_aregs
[reg
& 7];
2047 TCGv addr
, incr
, tmp
, r
[16];
2048 int is_load
= (insn
& 0x0400) != 0;
2049 int opsize
= (insn
& 0x40) != 0 ? OS_LONG
: OS_WORD
;
2050 uint16_t mask
= read_im16(env
, s
);
2051 int mode
= extract32(insn
, 3, 3);
2052 int reg0
= REG(insn
, 0);
2055 tmp
= cpu_aregs
[reg0
];
2058 case 0: /* data register direct */
2059 case 1: /* addr register direct */
2064 case 2: /* indirect */
2067 case 3: /* indirect post-increment */
2069 /* post-increment is not allowed */
2074 case 4: /* indirect pre-decrement */
2076 /* pre-decrement is not allowed */
2080 * We want a bare copy of the address reg, without any pre-decrement
2081 * adjustment, as gen_lea would provide.
2086 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
2087 if (IS_NULL_QREG(tmp
)) {
2093 addr
= tcg_temp_new();
2094 tcg_gen_mov_i32(addr
, tmp
);
2095 incr
= tcg_const_i32(opsize_bytes(opsize
));
2098 /* memory to register */
2099 for (i
= 0; i
< 16; i
++) {
2100 if (mask
& (1 << i
)) {
2101 r
[i
] = gen_load(s
, opsize
, addr
, 1, IS_USER(s
));
2102 tcg_gen_add_i32(addr
, addr
, incr
);
2105 for (i
= 0; i
< 16; i
++) {
2106 if (mask
& (1 << i
)) {
2107 tcg_gen_mov_i32(mreg(i
), r
[i
]);
2108 tcg_temp_free(r
[i
]);
2112 /* post-increment: movem (An)+,X */
2113 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2116 /* register to memory */
2118 /* pre-decrement: movem X,-(An) */
2119 for (i
= 15; i
>= 0; i
--) {
2120 if ((mask
<< i
) & 0x8000) {
2121 tcg_gen_sub_i32(addr
, addr
, incr
);
2122 if (reg0
+ 8 == i
&&
2123 m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
)) {
2125 * M68020+: if the addressing register is the
2126 * register moved to memory, the value written
2127 * is the initial value decremented by the size of
2128 * the operation, regardless of how many actual
2129 * stores have been performed until this point.
2130 * M68000/M68010: the value is the initial value.
2132 tmp
= tcg_temp_new();
2133 tcg_gen_sub_i32(tmp
, cpu_aregs
[reg0
], incr
);
2134 gen_store(s
, opsize
, addr
, tmp
, IS_USER(s
));
2137 gen_store(s
, opsize
, addr
, mreg(i
), IS_USER(s
));
2141 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2143 for (i
= 0; i
< 16; i
++) {
2144 if (mask
& (1 << i
)) {
2145 gen_store(s
, opsize
, addr
, mreg(i
), IS_USER(s
));
2146 tcg_gen_add_i32(addr
, addr
, incr
);
2152 tcg_temp_free(incr
);
2153 tcg_temp_free(addr
);
2165 displ
= read_im16(env
, s
);
2167 addr
= AREG(insn
, 0);
2168 reg
= DREG(insn
, 9);
2170 abuf
= tcg_temp_new();
2171 tcg_gen_addi_i32(abuf
, addr
, displ
);
2172 dbuf
= tcg_temp_new();
2181 for ( ; i
> 0 ; i
--) {
2182 tcg_gen_shri_i32(dbuf
, reg
, (i
- 1) * 8);
2183 tcg_gen_qemu_st8(dbuf
, abuf
, IS_USER(s
));
2185 tcg_gen_addi_i32(abuf
, abuf
, 2);
2189 for ( ; i
> 0 ; i
--) {
2190 tcg_gen_qemu_ld8u(dbuf
, abuf
, IS_USER(s
));
2191 tcg_gen_deposit_i32(reg
, reg
, dbuf
, (i
- 1) * 8, 8);
2193 tcg_gen_addi_i32(abuf
, abuf
, 2);
2197 tcg_temp_free(abuf
);
2198 tcg_temp_free(dbuf
);
2201 DISAS_INSN(bitop_im
)
2211 if ((insn
& 0x38) != 0)
2215 op
= (insn
>> 6) & 3;
2217 bitnum
= read_im16(env
, s
);
2218 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2219 if (bitnum
& 0xfe00) {
2220 disas_undef(env
, s
, insn
);
2224 if (bitnum
& 0xff00) {
2225 disas_undef(env
, s
, insn
);
2230 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
2233 if (opsize
== OS_BYTE
)
2239 tcg_gen_andi_i32(QREG_CC_Z
, src1
, mask
);
2242 tmp
= tcg_temp_new();
2245 tcg_gen_xori_i32(tmp
, src1
, mask
);
2248 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
2251 tcg_gen_ori_i32(tmp
, src1
, mask
);
2256 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
2261 static TCGv
gen_get_ccr(DisasContext
*s
)
2266 dest
= tcg_temp_new();
2267 gen_helper_get_ccr(dest
, cpu_env
);
2271 static TCGv
gen_get_sr(DisasContext
*s
)
2276 ccr
= gen_get_ccr(s
);
2277 sr
= tcg_temp_new();
2278 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
2279 tcg_gen_or_i32(sr
, sr
, ccr
);
2284 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
2287 tcg_gen_movi_i32(QREG_CC_C
, val
& CCF_C
? 1 : 0);
2288 tcg_gen_movi_i32(QREG_CC_V
, val
& CCF_V
? -1 : 0);
2289 tcg_gen_movi_i32(QREG_CC_Z
, val
& CCF_Z
? 0 : 1);
2290 tcg_gen_movi_i32(QREG_CC_N
, val
& CCF_N
? -1 : 0);
2291 tcg_gen_movi_i32(QREG_CC_X
, val
& CCF_X
? 1 : 0);
2293 TCGv sr
= tcg_const_i32(val
);
2294 gen_helper_set_sr(cpu_env
, sr
);
2297 set_cc_op(s
, CC_OP_FLAGS
);
2300 static void gen_set_sr(DisasContext
*s
, TCGv val
, int ccr_only
)
2303 gen_helper_set_ccr(cpu_env
, val
);
2305 gen_helper_set_sr(cpu_env
, val
);
2307 set_cc_op(s
, CC_OP_FLAGS
);
2310 static void gen_move_to_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
2313 if ((insn
& 0x3f) == 0x3c) {
2315 val
= read_im16(env
, s
);
2316 gen_set_sr_im(s
, val
, ccr_only
);
2319 SRC_EA(env
, src
, OS_WORD
, 0, NULL
);
2320 gen_set_sr(s
, src
, ccr_only
);
2324 DISAS_INSN(arith_im
)
2332 bool with_SR
= ((insn
& 0x3f) == 0x3c);
2334 op
= (insn
>> 9) & 7;
2335 opsize
= insn_opsize(insn
);
2338 im
= tcg_const_i32((int8_t)read_im8(env
, s
));
2341 im
= tcg_const_i32((int16_t)read_im16(env
, s
));
2344 im
= tcg_const_i32(read_im32(env
, s
));
2347 g_assert_not_reached();
2351 /* SR/CCR can only be used with andi/eori/ori */
2352 if (op
== 2 || op
== 3 || op
== 6) {
2353 disas_undef(env
, s
, insn
);
2358 src1
= gen_get_ccr(s
);
2362 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
2365 src1
= gen_get_sr(s
);
2368 /* OS_LONG; others already g_assert_not_reached. */
2369 disas_undef(env
, s
, insn
);
2373 SRC_EA(env
, src1
, opsize
, 1, (op
== 6) ? NULL
: &addr
);
2375 dest
= tcg_temp_new();
2378 tcg_gen_or_i32(dest
, src1
, im
);
2380 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2382 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2383 gen_logic_cc(s
, dest
, opsize
);
2387 tcg_gen_and_i32(dest
, src1
, im
);
2389 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2391 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2392 gen_logic_cc(s
, dest
, opsize
);
2396 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, src1
, im
);
2397 tcg_gen_sub_i32(dest
, src1
, im
);
2398 gen_update_cc_add(dest
, im
, opsize
);
2399 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2400 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2403 tcg_gen_add_i32(dest
, src1
, im
);
2404 gen_update_cc_add(dest
, im
, opsize
);
2405 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
2406 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
2407 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2410 tcg_gen_xor_i32(dest
, src1
, im
);
2412 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2414 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2415 gen_logic_cc(s
, dest
, opsize
);
2419 gen_update_cc_cmp(s
, src1
, im
, opsize
);
2425 tcg_temp_free(dest
);
2437 switch ((insn
>> 9) & 3) {
2451 g_assert_not_reached();
2454 ext
= read_im16(env
, s
);
2456 /* cas Dc,Du,<EA> */
2458 addr
= gen_lea(env
, s
, insn
, opsize
);
2459 if (IS_NULL_QREG(addr
)) {
2464 cmp
= gen_extend(s
, DREG(ext
, 0), opsize
, 1);
2467 * if <EA> == Dc then
2469 * Dc = <EA> (because <EA> == Dc)
2474 load
= tcg_temp_new();
2475 tcg_gen_atomic_cmpxchg_i32(load
, addr
, cmp
, DREG(ext
, 6),
2477 /* update flags before setting cmp to load */
2478 gen_update_cc_cmp(s
, load
, cmp
, opsize
);
2479 gen_partset_reg(opsize
, DREG(ext
, 0), load
);
2481 tcg_temp_free(load
);
2483 switch (extract32(insn
, 3, 3)) {
2484 case 3: /* Indirect postincrement. */
2485 tcg_gen_addi_i32(AREG(insn
, 0), addr
, opsize_bytes(opsize
));
2487 case 4: /* Indirect predecrememnt. */
2488 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2495 uint16_t ext1
, ext2
;
2499 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2501 ext1
= read_im16(env
, s
);
2503 if (ext1
& 0x8000) {
2504 /* Address Register */
2505 addr1
= AREG(ext1
, 12);
2508 addr1
= DREG(ext1
, 12);
2511 ext2
= read_im16(env
, s
);
2512 if (ext2
& 0x8000) {
2513 /* Address Register */
2514 addr2
= AREG(ext2
, 12);
2517 addr2
= DREG(ext2
, 12);
2521 * if (R1) == Dc1 && (R2) == Dc2 then
2529 regs
= tcg_const_i32(REG(ext2
, 6) |
2530 (REG(ext1
, 6) << 3) |
2531 (REG(ext2
, 0) << 6) |
2532 (REG(ext1
, 0) << 9));
2533 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2534 gen_helper_exit_atomic(cpu_env
);
2536 gen_helper_cas2w(cpu_env
, regs
, addr1
, addr2
);
2538 tcg_temp_free(regs
);
2540 /* Note that cas2w also assigned to env->cc_op. */
2541 s
->cc_op
= CC_OP_CMPW
;
2542 s
->cc_op_synced
= 1;
2547 uint16_t ext1
, ext2
;
2548 TCGv addr1
, addr2
, regs
;
2550 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2552 ext1
= read_im16(env
, s
);
2554 if (ext1
& 0x8000) {
2555 /* Address Register */
2556 addr1
= AREG(ext1
, 12);
2559 addr1
= DREG(ext1
, 12);
2562 ext2
= read_im16(env
, s
);
2563 if (ext2
& 0x8000) {
2564 /* Address Register */
2565 addr2
= AREG(ext2
, 12);
2568 addr2
= DREG(ext2
, 12);
2572 * if (R1) == Dc1 && (R2) == Dc2 then
2580 regs
= tcg_const_i32(REG(ext2
, 6) |
2581 (REG(ext1
, 6) << 3) |
2582 (REG(ext2
, 0) << 6) |
2583 (REG(ext1
, 0) << 9));
2584 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2585 gen_helper_cas2l_parallel(cpu_env
, regs
, addr1
, addr2
);
2587 gen_helper_cas2l(cpu_env
, regs
, addr1
, addr2
);
2589 tcg_temp_free(regs
);
2591 /* Note that cas2l also assigned to env->cc_op. */
2592 s
->cc_op
= CC_OP_CMPL
;
2593 s
->cc_op_synced
= 1;
2600 reg
= DREG(insn
, 0);
2601 tcg_gen_bswap32_i32(reg
, reg
);
2611 switch (insn
>> 12) {
2612 case 1: /* move.b */
2615 case 2: /* move.l */
2618 case 3: /* move.w */
2624 SRC_EA(env
, src
, opsize
, 1, NULL
);
2625 op
= (insn
>> 6) & 7;
2628 /* The value will already have been sign extended. */
2629 dest
= AREG(insn
, 9);
2630 tcg_gen_mov_i32(dest
, src
);
2634 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
2635 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
2636 /* This will be correct because loads sign extend. */
2637 gen_logic_cc(s
, src
, opsize
);
2648 opsize
= insn_opsize(insn
);
2649 SRC_EA(env
, src
, opsize
, 1, &addr
);
2651 gen_flush_flags(s
); /* compute old Z */
2654 * Perform subtract with borrow.
2655 * (X, N) = -(src + X);
2658 z
= tcg_const_i32(0);
2659 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, z
, QREG_CC_X
, z
);
2660 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, z
, z
, QREG_CC_N
, QREG_CC_X
);
2662 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2664 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
2667 * Compute signed-overflow for negation. The normal formula for
2668 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2669 * this simplifies to res & src.
2672 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_N
, src
);
2674 /* Copy the rest of the results into place. */
2675 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2676 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2678 set_cc_op(s
, CC_OP_FLAGS
);
2680 /* result is in QREG_CC_N */
2682 DEST_EA(env
, insn
, opsize
, QREG_CC_N
, &addr
);
2690 reg
= AREG(insn
, 9);
2691 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2692 if (IS_NULL_QREG(tmp
)) {
2696 tcg_gen_mov_i32(reg
, tmp
);
2704 zero
= tcg_const_i32(0);
2706 opsize
= insn_opsize(insn
);
2707 DEST_EA(env
, insn
, opsize
, zero
, NULL
);
2708 gen_logic_cc(s
, zero
, opsize
);
2709 tcg_temp_free(zero
);
2712 DISAS_INSN(move_from_ccr
)
2716 ccr
= gen_get_ccr(s
);
2717 DEST_EA(env
, insn
, OS_WORD
, ccr
, NULL
);
2727 opsize
= insn_opsize(insn
);
2728 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2729 dest
= tcg_temp_new();
2730 tcg_gen_neg_i32(dest
, src1
);
2731 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2732 gen_update_cc_add(dest
, src1
, opsize
);
2733 tcg_gen_setcondi_i32(TCG_COND_NE
, QREG_CC_X
, dest
, 0);
2734 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2735 tcg_temp_free(dest
);
2738 DISAS_INSN(move_to_ccr
)
2740 gen_move_to_sr(env
, s
, insn
, true);
2750 opsize
= insn_opsize(insn
);
2751 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2752 dest
= tcg_temp_new();
2753 tcg_gen_not_i32(dest
, src1
);
2754 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2755 gen_logic_cc(s
, dest
, opsize
);
2764 src1
= tcg_temp_new();
2765 src2
= tcg_temp_new();
2766 reg
= DREG(insn
, 0);
2767 tcg_gen_shli_i32(src1
, reg
, 16);
2768 tcg_gen_shri_i32(src2
, reg
, 16);
2769 tcg_gen_or_i32(reg
, src1
, src2
);
2770 tcg_temp_free(src2
);
2771 tcg_temp_free(src1
);
2772 gen_logic_cc(s
, reg
, OS_LONG
);
2777 gen_exception(s
, s
->base
.pc_next
, EXCP_DEBUG
);
2784 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2785 if (IS_NULL_QREG(tmp
)) {
2798 reg
= DREG(insn
, 0);
2799 op
= (insn
>> 6) & 7;
2800 tmp
= tcg_temp_new();
2802 tcg_gen_ext16s_i32(tmp
, reg
);
2804 tcg_gen_ext8s_i32(tmp
, reg
);
2806 gen_partset_reg(OS_WORD
, reg
, tmp
);
2808 tcg_gen_mov_i32(reg
, tmp
);
2809 gen_logic_cc(s
, tmp
, OS_LONG
);
2818 opsize
= insn_opsize(insn
);
2819 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
2820 gen_logic_cc(s
, tmp
, opsize
);
2825 /* Implemented as a NOP. */
2830 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
2833 /* ??? This should be atomic. */
2840 dest
= tcg_temp_new();
2841 SRC_EA(env
, src1
, OS_BYTE
, 1, &addr
);
2842 gen_logic_cc(s
, src1
, OS_BYTE
);
2843 tcg_gen_ori_i32(dest
, src1
, 0x80);
2844 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
2845 tcg_temp_free(dest
);
2854 ext
= read_im16(env
, s
);
2859 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
2860 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
2864 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2867 tcg_gen_muls2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2869 tcg_gen_mulu2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2871 /* if Dl == Dh, 68040 returns low word */
2872 tcg_gen_mov_i32(DREG(ext
, 0), QREG_CC_N
);
2873 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_Z
);
2874 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
);
2876 tcg_gen_movi_i32(QREG_CC_V
, 0);
2877 tcg_gen_movi_i32(QREG_CC_C
, 0);
2879 set_cc_op(s
, CC_OP_FLAGS
);
2882 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2883 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2884 tcg_gen_movi_i32(QREG_CC_C
, 0);
2886 tcg_gen_muls2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2887 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2888 tcg_gen_sari_i32(QREG_CC_Z
, QREG_CC_N
, 31);
2889 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_Z
);
2891 tcg_gen_mulu2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2892 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2893 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_C
);
2895 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
2896 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_N
);
2898 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
2900 set_cc_op(s
, CC_OP_FLAGS
);
2903 * The upper 32 bits of the product are discarded, so
2904 * muls.l and mulu.l are functionally equivalent.
2906 tcg_gen_mul_i32(DREG(ext
, 12), src1
, DREG(ext
, 12));
2907 gen_logic_cc(s
, DREG(ext
, 12), OS_LONG
);
2911 static void gen_link(DisasContext
*s
, uint16_t insn
, int32_t offset
)
2916 reg
= AREG(insn
, 0);
2917 tmp
= tcg_temp_new();
2918 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
2919 gen_store(s
, OS_LONG
, tmp
, reg
, IS_USER(s
));
2920 if ((insn
& 7) != 7) {
2921 tcg_gen_mov_i32(reg
, tmp
);
2923 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
2931 offset
= read_im16(env
, s
);
2932 gen_link(s
, insn
, offset
);
2939 offset
= read_im32(env
, s
);
2940 gen_link(s
, insn
, offset
);
2949 src
= tcg_temp_new();
2950 reg
= AREG(insn
, 0);
2951 tcg_gen_mov_i32(src
, reg
);
2952 tmp
= gen_load(s
, OS_LONG
, src
, 0, IS_USER(s
));
2953 tcg_gen_mov_i32(reg
, tmp
);
2954 tcg_gen_addi_i32(QREG_SP
, src
, 4);
2959 #if defined(CONFIG_SOFTMMU)
2963 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
2967 gen_helper_reset(cpu_env
);
2978 int16_t offset
= read_im16(env
, s
);
2980 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0, IS_USER(s
));
2981 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, offset
+ 4);
2991 sp
= tcg_temp_new();
2992 ccr
= gen_load(s
, OS_WORD
, QREG_SP
, 0, IS_USER(s
));
2993 tcg_gen_addi_i32(sp
, QREG_SP
, 2);
2994 tmp
= gen_load(s
, OS_LONG
, sp
, 0, IS_USER(s
));
2995 tcg_gen_addi_i32(QREG_SP
, sp
, 4);
2998 gen_set_sr(s
, ccr
, true);
3008 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0, IS_USER(s
));
3009 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
3018 * Load the target address first to ensure correct exception
3021 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
3022 if (IS_NULL_QREG(tmp
)) {
3026 if ((insn
& 0x40) == 0) {
3028 gen_push(s
, tcg_const_i32(s
->pc
));
3042 if ((insn
& 070) == 010) {
3043 /* Operation on address register is always long. */
3046 opsize
= insn_opsize(insn
);
3048 SRC_EA(env
, src
, opsize
, 1, &addr
);
3049 imm
= (insn
>> 9) & 7;
3053 val
= tcg_const_i32(imm
);
3054 dest
= tcg_temp_new();
3055 tcg_gen_mov_i32(dest
, src
);
3056 if ((insn
& 0x38) == 0x08) {
3058 * Don't update condition codes if the destination is an
3061 if (insn
& 0x0100) {
3062 tcg_gen_sub_i32(dest
, dest
, val
);
3064 tcg_gen_add_i32(dest
, dest
, val
);
3067 if (insn
& 0x0100) {
3068 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
3069 tcg_gen_sub_i32(dest
, dest
, val
);
3070 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
3072 tcg_gen_add_i32(dest
, dest
, val
);
3073 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
3074 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
3076 gen_update_cc_add(dest
, val
, opsize
);
3079 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3080 tcg_temp_free(dest
);
3086 case 2: /* One extension word. */
3089 case 3: /* Two extension words. */
3092 case 4: /* No extension words. */
3095 disas_undef(env
, s
, insn
);
3106 op
= (insn
>> 8) & 0xf;
3107 offset
= (int8_t)insn
;
3109 offset
= (int16_t)read_im16(env
, s
);
3110 } else if (offset
== -1) {
3111 offset
= read_im32(env
, s
);
3115 gen_push(s
, tcg_const_i32(s
->pc
));
3119 TCGLabel
*l1
= gen_new_label();
3120 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
3121 gen_jmp_tb(s
, 1, base
+ offset
);
3123 gen_jmp_tb(s
, 0, s
->pc
);
3125 /* Unconditional branch. */
3127 gen_jmp_tb(s
, 0, base
+ offset
);
3133 tcg_gen_movi_i32(DREG(insn
, 9), (int8_t)insn
);
3134 gen_logic_cc(s
, DREG(insn
, 9), OS_LONG
);
3147 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
3148 reg
= DREG(insn
, 9);
3149 tcg_gen_mov_i32(reg
, src
);
3150 gen_logic_cc(s
, src
, opsize
);
3161 opsize
= insn_opsize(insn
);
3162 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 0);
3163 dest
= tcg_temp_new();
3165 SRC_EA(env
, src
, opsize
, 0, &addr
);
3166 tcg_gen_or_i32(dest
, src
, reg
);
3167 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3169 SRC_EA(env
, src
, opsize
, 0, NULL
);
3170 tcg_gen_or_i32(dest
, src
, reg
);
3171 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
3173 gen_logic_cc(s
, dest
, opsize
);
3174 tcg_temp_free(dest
);
3182 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3183 reg
= AREG(insn
, 9);
3184 tcg_gen_sub_i32(reg
, reg
, src
);
3187 static inline void gen_subx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3191 gen_flush_flags(s
); /* compute old Z */
3194 * Perform subtract with borrow.
3195 * (X, N) = dest - (src + X);
3198 tmp
= tcg_const_i32(0);
3199 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, tmp
, QREG_CC_X
, tmp
);
3200 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, dest
, tmp
, QREG_CC_N
, QREG_CC_X
);
3201 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3202 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
3204 /* Compute signed-overflow for subtract. */
3206 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, dest
);
3207 tcg_gen_xor_i32(tmp
, dest
, src
);
3208 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3211 /* Copy the rest of the results into place. */
3212 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3213 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3215 set_cc_op(s
, CC_OP_FLAGS
);
3217 /* result is in QREG_CC_N */
3220 DISAS_INSN(subx_reg
)
3226 opsize
= insn_opsize(insn
);
3228 src
= gen_extend(s
, DREG(insn
, 0), opsize
, 1);
3229 dest
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3231 gen_subx(s
, src
, dest
, opsize
);
3233 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3236 DISAS_INSN(subx_mem
)
3244 opsize
= insn_opsize(insn
);
3246 addr_src
= AREG(insn
, 0);
3247 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3248 src
= gen_load(s
, opsize
, addr_src
, 1, IS_USER(s
));
3250 addr_dest
= AREG(insn
, 9);
3251 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3252 dest
= gen_load(s
, opsize
, addr_dest
, 1, IS_USER(s
));
3254 gen_subx(s
, src
, dest
, opsize
);
3256 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
, IS_USER(s
));
3258 tcg_temp_free(dest
);
3267 val
= (insn
>> 9) & 7;
3270 src
= tcg_const_i32(val
);
3271 gen_logic_cc(s
, src
, OS_LONG
);
3272 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
3282 opsize
= insn_opsize(insn
);
3283 SRC_EA(env
, src
, opsize
, 1, NULL
);
3284 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3285 gen_update_cc_cmp(s
, reg
, src
, opsize
);
3299 SRC_EA(env
, src
, opsize
, 1, NULL
);
3300 reg
= AREG(insn
, 9);
3301 gen_update_cc_cmp(s
, reg
, src
, OS_LONG
);
3306 int opsize
= insn_opsize(insn
);
3309 /* Post-increment load (mode 3) from Ay. */
3310 src
= gen_ea_mode(env
, s
, 3, REG(insn
, 0), opsize
,
3311 NULL_QREG
, NULL
, EA_LOADS
, IS_USER(s
));
3312 /* Post-increment load (mode 3) from Ax. */
3313 dst
= gen_ea_mode(env
, s
, 3, REG(insn
, 9), opsize
,
3314 NULL_QREG
, NULL
, EA_LOADS
, IS_USER(s
));
3316 gen_update_cc_cmp(s
, dst
, src
, opsize
);
3326 opsize
= insn_opsize(insn
);
3328 SRC_EA(env
, src
, opsize
, 0, &addr
);
3329 dest
= tcg_temp_new();
3330 tcg_gen_xor_i32(dest
, src
, DREG(insn
, 9));
3331 gen_logic_cc(s
, dest
, opsize
);
3332 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3333 tcg_temp_free(dest
);
3336 static void do_exg(TCGv reg1
, TCGv reg2
)
3338 TCGv temp
= tcg_temp_new();
3339 tcg_gen_mov_i32(temp
, reg1
);
3340 tcg_gen_mov_i32(reg1
, reg2
);
3341 tcg_gen_mov_i32(reg2
, temp
);
3342 tcg_temp_free(temp
);
3347 /* exchange Dx and Dy */
3348 do_exg(DREG(insn
, 9), DREG(insn
, 0));
3353 /* exchange Ax and Ay */
3354 do_exg(AREG(insn
, 9), AREG(insn
, 0));
3359 /* exchange Dx and Ay */
3360 do_exg(DREG(insn
, 9), AREG(insn
, 0));
3371 dest
= tcg_temp_new();
3373 opsize
= insn_opsize(insn
);
3374 reg
= DREG(insn
, 9);
3376 SRC_EA(env
, src
, opsize
, 0, &addr
);
3377 tcg_gen_and_i32(dest
, src
, reg
);
3378 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3380 SRC_EA(env
, src
, opsize
, 0, NULL
);
3381 tcg_gen_and_i32(dest
, src
, reg
);
3382 gen_partset_reg(opsize
, reg
, dest
);
3384 gen_logic_cc(s
, dest
, opsize
);
3385 tcg_temp_free(dest
);
3393 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3394 reg
= AREG(insn
, 9);
3395 tcg_gen_add_i32(reg
, reg
, src
);
3398 static inline void gen_addx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3402 gen_flush_flags(s
); /* compute old Z */
3405 * Perform addition with carry.
3406 * (X, N) = src + dest + X;
3409 tmp
= tcg_const_i32(0);
3410 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_X
, tmp
, dest
, tmp
);
3411 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_N
, QREG_CC_X
, src
, tmp
);
3412 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3414 /* Compute signed-overflow for addition. */
3416 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3417 tcg_gen_xor_i32(tmp
, dest
, src
);
3418 tcg_gen_andc_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3421 /* Copy the rest of the results into place. */
3422 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3423 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3425 set_cc_op(s
, CC_OP_FLAGS
);
3427 /* result is in QREG_CC_N */
3430 DISAS_INSN(addx_reg
)
3436 opsize
= insn_opsize(insn
);
3438 dest
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3439 src
= gen_extend(s
, DREG(insn
, 0), opsize
, 1);
3441 gen_addx(s
, src
, dest
, opsize
);
3443 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3446 DISAS_INSN(addx_mem
)
3454 opsize
= insn_opsize(insn
);
3456 addr_src
= AREG(insn
, 0);
3457 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3458 src
= gen_load(s
, opsize
, addr_src
, 1, IS_USER(s
));
3460 addr_dest
= AREG(insn
, 9);
3461 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3462 dest
= gen_load(s
, opsize
, addr_dest
, 1, IS_USER(s
));
3464 gen_addx(s
, src
, dest
, opsize
);
3466 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
, IS_USER(s
));
3468 tcg_temp_free(dest
);
3472 static inline void shift_im(DisasContext
*s
, uint16_t insn
, int opsize
)
3474 int count
= (insn
>> 9) & 7;
3475 int logical
= insn
& 8;
3476 int left
= insn
& 0x100;
3477 int bits
= opsize_bytes(opsize
) * 8;
3478 TCGv reg
= gen_extend(s
, DREG(insn
, 0), opsize
, !logical
);
3484 tcg_gen_movi_i32(QREG_CC_V
, 0);
3486 tcg_gen_shri_i32(QREG_CC_C
, reg
, bits
- count
);
3487 tcg_gen_shli_i32(QREG_CC_N
, reg
, count
);
3490 * Note that ColdFire always clears V (done above),
3491 * while M68000 sets if the most significant bit is changed at
3492 * any time during the shift operation.
3494 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3495 /* if shift count >= bits, V is (reg != 0) */
3496 if (count
>= bits
) {
3497 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, reg
, QREG_CC_V
);
3499 TCGv t0
= tcg_temp_new();
3500 tcg_gen_sari_i32(QREG_CC_V
, reg
, bits
- 1);
3501 tcg_gen_sari_i32(t0
, reg
, bits
- count
- 1);
3502 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, t0
);
3505 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3508 tcg_gen_shri_i32(QREG_CC_C
, reg
, count
- 1);
3510 tcg_gen_shri_i32(QREG_CC_N
, reg
, count
);
3512 tcg_gen_sari_i32(QREG_CC_N
, reg
, count
);
3516 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3517 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3518 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3519 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3521 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3522 set_cc_op(s
, CC_OP_FLAGS
);
3525 static inline void shift_reg(DisasContext
*s
, uint16_t insn
, int opsize
)
3527 int logical
= insn
& 8;
3528 int left
= insn
& 0x100;
3529 int bits
= opsize_bytes(opsize
) * 8;
3530 TCGv reg
= gen_extend(s
, DREG(insn
, 0), opsize
, !logical
);
3534 t64
= tcg_temp_new_i64();
3535 s64
= tcg_temp_new_i64();
3536 s32
= tcg_temp_new();
3539 * Note that m68k truncates the shift count modulo 64, not 32.
3540 * In addition, a 64-bit shift makes it easy to find "the last
3541 * bit shifted out", for the carry flag.
3543 tcg_gen_andi_i32(s32
, DREG(insn
, 9), 63);
3544 tcg_gen_extu_i32_i64(s64
, s32
);
3545 tcg_gen_extu_i32_i64(t64
, reg
);
3547 /* Optimistically set V=0. Also used as a zero source below. */
3548 tcg_gen_movi_i32(QREG_CC_V
, 0);
3550 tcg_gen_shl_i64(t64
, t64
, s64
);
3552 if (opsize
== OS_LONG
) {
3553 tcg_gen_extr_i64_i32(QREG_CC_N
, QREG_CC_C
, t64
);
3554 /* Note that C=0 if shift count is 0, and we get that for free. */
3556 TCGv zero
= tcg_const_i32(0);
3557 tcg_gen_extrl_i64_i32(QREG_CC_N
, t64
);
3558 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_N
, bits
);
3559 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3560 s32
, zero
, zero
, QREG_CC_C
);
3561 tcg_temp_free(zero
);
3563 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3565 /* X = C, but only if the shift count was non-zero. */
3566 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3567 QREG_CC_C
, QREG_CC_X
);
3570 * M68000 sets V if the most significant bit is changed at
3571 * any time during the shift operation. Do this via creating
3572 * an extension of the sign bit, comparing, and discarding
3573 * the bits below the sign bit. I.e.
3574 * int64_t s = (intN_t)reg;
3575 * int64_t t = (int64_t)(intN_t)reg << count;
3576 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3578 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3579 TCGv_i64 tt
= tcg_const_i64(32);
3580 /* if shift is greater than 32, use 32 */
3581 tcg_gen_movcond_i64(TCG_COND_GT
, s64
, s64
, tt
, tt
, s64
);
3582 tcg_temp_free_i64(tt
);
3583 /* Sign extend the input to 64 bits; re-do the shift. */
3584 tcg_gen_ext_i32_i64(t64
, reg
);
3585 tcg_gen_shl_i64(s64
, t64
, s64
);
3586 /* Clear all bits that are unchanged. */
3587 tcg_gen_xor_i64(t64
, t64
, s64
);
3588 /* Ignore the bits below the sign bit. */
3589 tcg_gen_andi_i64(t64
, t64
, -1ULL << (bits
- 1));
3590 /* If any bits remain set, we have overflow. */
3591 tcg_gen_setcondi_i64(TCG_COND_NE
, t64
, t64
, 0);
3592 tcg_gen_extrl_i64_i32(QREG_CC_V
, t64
);
3593 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3596 tcg_gen_shli_i64(t64
, t64
, 32);
3598 tcg_gen_shr_i64(t64
, t64
, s64
);
3600 tcg_gen_sar_i64(t64
, t64
, s64
);
3602 tcg_gen_extr_i64_i32(QREG_CC_C
, QREG_CC_N
, t64
);
3604 /* Note that C=0 if shift count is 0, and we get that for free. */
3605 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_C
, 31);
3607 /* X = C, but only if the shift count was non-zero. */
3608 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3609 QREG_CC_C
, QREG_CC_X
);
3611 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3612 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3615 tcg_temp_free_i64(s64
);
3616 tcg_temp_free_i64(t64
);
3618 /* Write back the result. */
3619 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3620 set_cc_op(s
, CC_OP_FLAGS
);
3623 DISAS_INSN(shift8_im
)
3625 shift_im(s
, insn
, OS_BYTE
);
3628 DISAS_INSN(shift16_im
)
3630 shift_im(s
, insn
, OS_WORD
);
3633 DISAS_INSN(shift_im
)
3635 shift_im(s
, insn
, OS_LONG
);
3638 DISAS_INSN(shift8_reg
)
3640 shift_reg(s
, insn
, OS_BYTE
);
3643 DISAS_INSN(shift16_reg
)
3645 shift_reg(s
, insn
, OS_WORD
);
3648 DISAS_INSN(shift_reg
)
3650 shift_reg(s
, insn
, OS_LONG
);
3653 DISAS_INSN(shift_mem
)
3655 int logical
= insn
& 8;
3656 int left
= insn
& 0x100;
3660 SRC_EA(env
, src
, OS_WORD
, !logical
, &addr
);
3661 tcg_gen_movi_i32(QREG_CC_V
, 0);
3663 tcg_gen_shri_i32(QREG_CC_C
, src
, 15);
3664 tcg_gen_shli_i32(QREG_CC_N
, src
, 1);
3667 * Note that ColdFire always clears V,
3668 * while M68000 sets if the most significant bit is changed at
3669 * any time during the shift operation
3671 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3672 src
= gen_extend(s
, src
, OS_WORD
, 1);
3673 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3676 tcg_gen_mov_i32(QREG_CC_C
, src
);
3678 tcg_gen_shri_i32(QREG_CC_N
, src
, 1);
3680 tcg_gen_sari_i32(QREG_CC_N
, src
, 1);
3684 gen_ext(QREG_CC_N
, QREG_CC_N
, OS_WORD
, 1);
3685 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3686 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3687 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3689 DEST_EA(env
, insn
, OS_WORD
, QREG_CC_N
, &addr
);
3690 set_cc_op(s
, CC_OP_FLAGS
);
3693 static void rotate(TCGv reg
, TCGv shift
, int left
, int size
)
3697 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3698 tcg_gen_ext8u_i32(reg
, reg
);
3699 tcg_gen_muli_i32(reg
, reg
, 0x01010101);
3702 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3703 tcg_gen_deposit_i32(reg
, reg
, reg
, 16, 16);
3708 tcg_gen_rotl_i32(reg
, reg
, shift
);
3710 tcg_gen_rotr_i32(reg
, reg
, shift
);
3718 tcg_gen_ext8s_i32(reg
, reg
);
3721 tcg_gen_ext16s_i32(reg
, reg
);
3727 /* QREG_CC_X is not affected */
3729 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3730 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3733 tcg_gen_andi_i32(QREG_CC_C
, reg
, 1);
3735 tcg_gen_shri_i32(QREG_CC_C
, reg
, 31);
3738 tcg_gen_movi_i32(QREG_CC_V
, 0); /* always cleared */
3741 static void rotate_x_flags(TCGv reg
, TCGv X
, int size
)
3745 tcg_gen_ext8s_i32(reg
, reg
);
3748 tcg_gen_ext16s_i32(reg
, reg
);
3753 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3754 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3755 tcg_gen_mov_i32(QREG_CC_X
, X
);
3756 tcg_gen_mov_i32(QREG_CC_C
, X
);
3757 tcg_gen_movi_i32(QREG_CC_V
, 0);
3760 /* Result of rotate_x() is valid if 0 <= shift <= size */
3761 static TCGv
rotate_x(TCGv reg
, TCGv shift
, int left
, int size
)
3763 TCGv X
, shl
, shr
, shx
, sz
, zero
;
3765 sz
= tcg_const_i32(size
);
3767 shr
= tcg_temp_new();
3768 shl
= tcg_temp_new();
3769 shx
= tcg_temp_new();
3771 tcg_gen_mov_i32(shl
, shift
); /* shl = shift */
3772 tcg_gen_movi_i32(shr
, size
+ 1);
3773 tcg_gen_sub_i32(shr
, shr
, shift
); /* shr = size + 1 - shift */
3774 tcg_gen_subi_i32(shx
, shift
, 1); /* shx = shift - 1 */
3775 /* shx = shx < 0 ? size : shx; */
3776 zero
= tcg_const_i32(0);
3777 tcg_gen_movcond_i32(TCG_COND_LT
, shx
, shx
, zero
, sz
, shx
);
3778 tcg_temp_free(zero
);
3780 tcg_gen_mov_i32(shr
, shift
); /* shr = shift */
3781 tcg_gen_movi_i32(shl
, size
+ 1);
3782 tcg_gen_sub_i32(shl
, shl
, shift
); /* shl = size + 1 - shift */
3783 tcg_gen_sub_i32(shx
, sz
, shift
); /* shx = size - shift */
3785 tcg_temp_free_i32(sz
);
3787 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3789 tcg_gen_shl_i32(shl
, reg
, shl
);
3790 tcg_gen_shr_i32(shr
, reg
, shr
);
3791 tcg_gen_or_i32(reg
, shl
, shr
);
3794 tcg_gen_shl_i32(shx
, QREG_CC_X
, shx
);
3795 tcg_gen_or_i32(reg
, reg
, shx
);
3798 /* X = (reg >> size) & 1 */
3801 tcg_gen_extract_i32(X
, reg
, size
, 1);
3806 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3807 static TCGv
rotate32_x(TCGv reg
, TCGv shift
, int left
)
3809 TCGv_i64 t0
, shift64
;
3810 TCGv X
, lo
, hi
, zero
;
3812 shift64
= tcg_temp_new_i64();
3813 tcg_gen_extu_i32_i64(shift64
, shift
);
3815 t0
= tcg_temp_new_i64();
3818 lo
= tcg_temp_new();
3819 hi
= tcg_temp_new();
3822 /* create [reg:X:..] */
3824 tcg_gen_shli_i32(lo
, QREG_CC_X
, 31);
3825 tcg_gen_concat_i32_i64(t0
, lo
, reg
);
3829 tcg_gen_rotl_i64(t0
, t0
, shift64
);
3830 tcg_temp_free_i64(shift64
);
3832 /* result is [reg:..:reg:X] */
3834 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3835 tcg_gen_andi_i32(X
, lo
, 1);
3837 tcg_gen_shri_i32(lo
, lo
, 1);
3839 /* create [..:X:reg] */
3841 tcg_gen_concat_i32_i64(t0
, reg
, QREG_CC_X
);
3843 tcg_gen_rotr_i64(t0
, t0
, shift64
);
3844 tcg_temp_free_i64(shift64
);
3846 /* result is value: [X:reg:..:reg] */
3848 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3852 tcg_gen_shri_i32(X
, hi
, 31);
3854 /* extract result */
3856 tcg_gen_shli_i32(hi
, hi
, 1);
3858 tcg_temp_free_i64(t0
);
3859 tcg_gen_or_i32(lo
, lo
, hi
);
3862 /* if shift == 0, register and X are not affected */
3864 zero
= tcg_const_i32(0);
3865 tcg_gen_movcond_i32(TCG_COND_EQ
, X
, shift
, zero
, QREG_CC_X
, X
);
3866 tcg_gen_movcond_i32(TCG_COND_EQ
, reg
, shift
, zero
, reg
, lo
);
3867 tcg_temp_free(zero
);
3873 DISAS_INSN(rotate_im
)
3877 int left
= (insn
& 0x100);
3879 tmp
= (insn
>> 9) & 7;
3884 shift
= tcg_const_i32(tmp
);
3886 rotate(DREG(insn
, 0), shift
, left
, 32);
3888 TCGv X
= rotate32_x(DREG(insn
, 0), shift
, left
);
3889 rotate_x_flags(DREG(insn
, 0), X
, 32);
3892 tcg_temp_free(shift
);
3894 set_cc_op(s
, CC_OP_FLAGS
);
3897 DISAS_INSN(rotate8_im
)
3899 int left
= (insn
& 0x100);
3904 reg
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
3906 tmp
= (insn
>> 9) & 7;
3911 shift
= tcg_const_i32(tmp
);
3913 rotate(reg
, shift
, left
, 8);
3915 TCGv X
= rotate_x(reg
, shift
, left
, 8);
3916 rotate_x_flags(reg
, X
, 8);
3919 tcg_temp_free(shift
);
3920 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3921 set_cc_op(s
, CC_OP_FLAGS
);
3924 DISAS_INSN(rotate16_im
)
3926 int left
= (insn
& 0x100);
3931 reg
= gen_extend(s
, DREG(insn
, 0), OS_WORD
, 0);
3932 tmp
= (insn
>> 9) & 7;
3937 shift
= tcg_const_i32(tmp
);
3939 rotate(reg
, shift
, left
, 16);
3941 TCGv X
= rotate_x(reg
, shift
, left
, 16);
3942 rotate_x_flags(reg
, X
, 16);
3945 tcg_temp_free(shift
);
3946 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
3947 set_cc_op(s
, CC_OP_FLAGS
);
3950 DISAS_INSN(rotate_reg
)
3955 int left
= (insn
& 0x100);
3957 reg
= DREG(insn
, 0);
3958 src
= DREG(insn
, 9);
3959 /* shift in [0..63] */
3960 t0
= tcg_temp_new();
3961 tcg_gen_andi_i32(t0
, src
, 63);
3962 t1
= tcg_temp_new_i32();
3964 tcg_gen_andi_i32(t1
, src
, 31);
3965 rotate(reg
, t1
, left
, 32);
3966 /* if shift == 0, clear C */
3967 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3968 t0
, QREG_CC_V
/* 0 */,
3969 QREG_CC_V
/* 0 */, QREG_CC_C
);
3973 tcg_gen_movi_i32(t1
, 33);
3974 tcg_gen_remu_i32(t1
, t0
, t1
);
3975 X
= rotate32_x(DREG(insn
, 0), t1
, left
);
3976 rotate_x_flags(DREG(insn
, 0), X
, 32);
3981 set_cc_op(s
, CC_OP_FLAGS
);
3984 DISAS_INSN(rotate8_reg
)
3989 int left
= (insn
& 0x100);
3991 reg
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
3992 src
= DREG(insn
, 9);
3993 /* shift in [0..63] */
3994 t0
= tcg_temp_new_i32();
3995 tcg_gen_andi_i32(t0
, src
, 63);
3996 t1
= tcg_temp_new_i32();
3998 tcg_gen_andi_i32(t1
, src
, 7);
3999 rotate(reg
, t1
, left
, 8);
4000 /* if shift == 0, clear C */
4001 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
4002 t0
, QREG_CC_V
/* 0 */,
4003 QREG_CC_V
/* 0 */, QREG_CC_C
);
4007 tcg_gen_movi_i32(t1
, 9);
4008 tcg_gen_remu_i32(t1
, t0
, t1
);
4009 X
= rotate_x(reg
, t1
, left
, 8);
4010 rotate_x_flags(reg
, X
, 8);
4015 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
4016 set_cc_op(s
, CC_OP_FLAGS
);
4019 DISAS_INSN(rotate16_reg
)
4024 int left
= (insn
& 0x100);
4026 reg
= gen_extend(s
, DREG(insn
, 0), OS_WORD
, 0);
4027 src
= DREG(insn
, 9);
4028 /* shift in [0..63] */
4029 t0
= tcg_temp_new_i32();
4030 tcg_gen_andi_i32(t0
, src
, 63);
4031 t1
= tcg_temp_new_i32();
4033 tcg_gen_andi_i32(t1
, src
, 15);
4034 rotate(reg
, t1
, left
, 16);
4035 /* if shift == 0, clear C */
4036 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
4037 t0
, QREG_CC_V
/* 0 */,
4038 QREG_CC_V
/* 0 */, QREG_CC_C
);
4042 tcg_gen_movi_i32(t1
, 17);
4043 tcg_gen_remu_i32(t1
, t0
, t1
);
4044 X
= rotate_x(reg
, t1
, left
, 16);
4045 rotate_x_flags(reg
, X
, 16);
4050 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
4051 set_cc_op(s
, CC_OP_FLAGS
);
4054 DISAS_INSN(rotate_mem
)
4059 int left
= (insn
& 0x100);
4061 SRC_EA(env
, src
, OS_WORD
, 0, &addr
);
4063 shift
= tcg_const_i32(1);
4064 if (insn
& 0x0200) {
4065 rotate(src
, shift
, left
, 16);
4067 TCGv X
= rotate_x(src
, shift
, left
, 16);
4068 rotate_x_flags(src
, X
, 16);
4071 tcg_temp_free(shift
);
4072 DEST_EA(env
, insn
, OS_WORD
, src
, &addr
);
4073 set_cc_op(s
, CC_OP_FLAGS
);
4076 DISAS_INSN(bfext_reg
)
4078 int ext
= read_im16(env
, s
);
4079 int is_sign
= insn
& 0x200;
4080 TCGv src
= DREG(insn
, 0);
4081 TCGv dst
= DREG(ext
, 12);
4082 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4083 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4084 int pos
= 32 - ofs
- len
; /* little bit-endian */
4085 TCGv tmp
= tcg_temp_new();
4089 * In general, we're going to rotate the field so that it's at the
4090 * top of the word and then right-shift by the complement of the
4091 * width to extend the field.
4094 /* Variable width. */
4096 /* Variable offset. */
4097 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4098 tcg_gen_rotl_i32(tmp
, src
, tmp
);
4100 tcg_gen_rotli_i32(tmp
, src
, ofs
);
4103 shift
= tcg_temp_new();
4104 tcg_gen_neg_i32(shift
, DREG(ext
, 0));
4105 tcg_gen_andi_i32(shift
, shift
, 31);
4106 tcg_gen_sar_i32(QREG_CC_N
, tmp
, shift
);
4108 tcg_gen_mov_i32(dst
, QREG_CC_N
);
4110 tcg_gen_shr_i32(dst
, tmp
, shift
);
4112 tcg_temp_free(shift
);
4114 /* Immediate width. */
4116 /* Variable offset */
4117 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4118 tcg_gen_rotl_i32(tmp
, src
, tmp
);
4123 * Immediate offset. If the field doesn't wrap around the
4124 * end of the word, rely on (s)extract completely.
4127 tcg_gen_rotli_i32(tmp
, src
, ofs
);
4133 tcg_gen_sextract_i32(QREG_CC_N
, src
, pos
, len
);
4135 tcg_gen_mov_i32(dst
, QREG_CC_N
);
4137 tcg_gen_extract_i32(dst
, src
, pos
, len
);
4142 set_cc_op(s
, CC_OP_LOGIC
);
4145 DISAS_INSN(bfext_mem
)
4147 int ext
= read_im16(env
, s
);
4148 int is_sign
= insn
& 0x200;
4149 TCGv dest
= DREG(ext
, 12);
4150 TCGv addr
, len
, ofs
;
4152 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4153 if (IS_NULL_QREG(addr
)) {
4161 len
= tcg_const_i32(extract32(ext
, 0, 5));
4166 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4170 gen_helper_bfexts_mem(dest
, cpu_env
, addr
, ofs
, len
);
4171 tcg_gen_mov_i32(QREG_CC_N
, dest
);
4173 TCGv_i64 tmp
= tcg_temp_new_i64();
4174 gen_helper_bfextu_mem(tmp
, cpu_env
, addr
, ofs
, len
);
4175 tcg_gen_extr_i64_i32(dest
, QREG_CC_N
, tmp
);
4176 tcg_temp_free_i64(tmp
);
4178 set_cc_op(s
, CC_OP_LOGIC
);
4180 if (!(ext
& 0x20)) {
4183 if (!(ext
& 0x800)) {
4188 DISAS_INSN(bfop_reg
)
4190 int ext
= read_im16(env
, s
);
4191 TCGv src
= DREG(insn
, 0);
4192 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4193 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4194 TCGv mask
, tofs
, tlen
;
4198 if ((insn
& 0x0f00) == 0x0d00) { /* bfffo */
4199 tofs
= tcg_temp_new();
4200 tlen
= tcg_temp_new();
4203 if ((ext
& 0x820) == 0) {
4204 /* Immediate width and offset. */
4205 uint32_t maski
= 0x7fffffffu
>> (len
- 1);
4206 if (ofs
+ len
<= 32) {
4207 tcg_gen_shli_i32(QREG_CC_N
, src
, ofs
);
4209 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4211 tcg_gen_andi_i32(QREG_CC_N
, QREG_CC_N
, ~maski
);
4212 mask
= tcg_const_i32(ror32(maski
, ofs
));
4214 tcg_gen_movi_i32(tofs
, ofs
);
4215 tcg_gen_movi_i32(tlen
, len
);
4218 TCGv tmp
= tcg_temp_new();
4220 /* Variable width */
4221 tcg_gen_subi_i32(tmp
, DREG(ext
, 0), 1);
4222 tcg_gen_andi_i32(tmp
, tmp
, 31);
4223 mask
= tcg_const_i32(0x7fffffffu
);
4224 tcg_gen_shr_i32(mask
, mask
, tmp
);
4226 tcg_gen_addi_i32(tlen
, tmp
, 1);
4229 /* Immediate width */
4230 mask
= tcg_const_i32(0x7fffffffu
>> (len
- 1));
4232 tcg_gen_movi_i32(tlen
, len
);
4236 /* Variable offset */
4237 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4238 tcg_gen_rotl_i32(QREG_CC_N
, src
, tmp
);
4239 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4240 tcg_gen_rotr_i32(mask
, mask
, tmp
);
4242 tcg_gen_mov_i32(tofs
, tmp
);
4245 /* Immediate offset (and variable width) */
4246 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4247 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4248 tcg_gen_rotri_i32(mask
, mask
, ofs
);
4250 tcg_gen_movi_i32(tofs
, ofs
);
4255 set_cc_op(s
, CC_OP_LOGIC
);
4257 switch (insn
& 0x0f00) {
4258 case 0x0a00: /* bfchg */
4259 tcg_gen_eqv_i32(src
, src
, mask
);
4261 case 0x0c00: /* bfclr */
4262 tcg_gen_and_i32(src
, src
, mask
);
4264 case 0x0d00: /* bfffo */
4265 gen_helper_bfffo_reg(DREG(ext
, 12), QREG_CC_N
, tofs
, tlen
);
4266 tcg_temp_free(tlen
);
4267 tcg_temp_free(tofs
);
4269 case 0x0e00: /* bfset */
4270 tcg_gen_orc_i32(src
, src
, mask
);
4272 case 0x0800: /* bftst */
4273 /* flags already set; no other work to do. */
4276 g_assert_not_reached();
4278 tcg_temp_free(mask
);
4281 DISAS_INSN(bfop_mem
)
4283 int ext
= read_im16(env
, s
);
4284 TCGv addr
, len
, ofs
;
4287 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4288 if (IS_NULL_QREG(addr
)) {
4296 len
= tcg_const_i32(extract32(ext
, 0, 5));
4301 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4304 switch (insn
& 0x0f00) {
4305 case 0x0a00: /* bfchg */
4306 gen_helper_bfchg_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4308 case 0x0c00: /* bfclr */
4309 gen_helper_bfclr_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4311 case 0x0d00: /* bfffo */
4312 t64
= tcg_temp_new_i64();
4313 gen_helper_bfffo_mem(t64
, cpu_env
, addr
, ofs
, len
);
4314 tcg_gen_extr_i64_i32(DREG(ext
, 12), QREG_CC_N
, t64
);
4315 tcg_temp_free_i64(t64
);
4317 case 0x0e00: /* bfset */
4318 gen_helper_bfset_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4320 case 0x0800: /* bftst */
4321 gen_helper_bfexts_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4324 g_assert_not_reached();
4326 set_cc_op(s
, CC_OP_LOGIC
);
4328 if (!(ext
& 0x20)) {
4331 if (!(ext
& 0x800)) {
4336 DISAS_INSN(bfins_reg
)
4338 int ext
= read_im16(env
, s
);
4339 TCGv dst
= DREG(insn
, 0);
4340 TCGv src
= DREG(ext
, 12);
4341 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4342 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4343 int pos
= 32 - ofs
- len
; /* little bit-endian */
4346 tmp
= tcg_temp_new();
4349 /* Variable width */
4350 tcg_gen_neg_i32(tmp
, DREG(ext
, 0));
4351 tcg_gen_andi_i32(tmp
, tmp
, 31);
4352 tcg_gen_shl_i32(QREG_CC_N
, src
, tmp
);
4354 /* Immediate width */
4355 tcg_gen_shli_i32(QREG_CC_N
, src
, 32 - len
);
4357 set_cc_op(s
, CC_OP_LOGIC
);
4359 /* Immediate width and offset */
4360 if ((ext
& 0x820) == 0) {
4361 /* Check for suitability for deposit. */
4363 tcg_gen_deposit_i32(dst
, dst
, src
, pos
, len
);
4365 uint32_t maski
= -2U << (len
- 1);
4366 uint32_t roti
= (ofs
+ len
) & 31;
4367 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4368 tcg_gen_rotri_i32(tmp
, tmp
, roti
);
4369 tcg_gen_andi_i32(dst
, dst
, ror32(maski
, roti
));
4370 tcg_gen_or_i32(dst
, dst
, tmp
);
4373 TCGv mask
= tcg_temp_new();
4374 TCGv rot
= tcg_temp_new();
4377 /* Variable width */
4378 tcg_gen_subi_i32(rot
, DREG(ext
, 0), 1);
4379 tcg_gen_andi_i32(rot
, rot
, 31);
4380 tcg_gen_movi_i32(mask
, -2);
4381 tcg_gen_shl_i32(mask
, mask
, rot
);
4382 tcg_gen_mov_i32(rot
, DREG(ext
, 0));
4383 tcg_gen_andc_i32(tmp
, src
, mask
);
4385 /* Immediate width (variable offset) */
4386 uint32_t maski
= -2U << (len
- 1);
4387 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4388 tcg_gen_movi_i32(mask
, maski
);
4389 tcg_gen_movi_i32(rot
, len
& 31);
4392 /* Variable offset */
4393 tcg_gen_add_i32(rot
, rot
, DREG(ext
, 6));
4395 /* Immediate offset (variable width) */
4396 tcg_gen_addi_i32(rot
, rot
, ofs
);
4398 tcg_gen_andi_i32(rot
, rot
, 31);
4399 tcg_gen_rotr_i32(mask
, mask
, rot
);
4400 tcg_gen_rotr_i32(tmp
, tmp
, rot
);
4401 tcg_gen_and_i32(dst
, dst
, mask
);
4402 tcg_gen_or_i32(dst
, dst
, tmp
);
4405 tcg_temp_free(mask
);
4410 DISAS_INSN(bfins_mem
)
4412 int ext
= read_im16(env
, s
);
4413 TCGv src
= DREG(ext
, 12);
4414 TCGv addr
, len
, ofs
;
4416 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4417 if (IS_NULL_QREG(addr
)) {
4425 len
= tcg_const_i32(extract32(ext
, 0, 5));
4430 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4433 gen_helper_bfins_mem(QREG_CC_N
, cpu_env
, addr
, src
, ofs
, len
);
4434 set_cc_op(s
, CC_OP_LOGIC
);
4436 if (!(ext
& 0x20)) {
4439 if (!(ext
& 0x800)) {
4447 reg
= DREG(insn
, 0);
4448 gen_logic_cc(s
, reg
, OS_LONG
);
4449 gen_helper_ff1(reg
, reg
);
4457 switch ((insn
>> 7) & 3) {
4462 if (m68k_feature(env
, M68K_FEATURE_CHK2
)) {
4468 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4471 SRC_EA(env
, src
, opsize
, 1, NULL
);
4472 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
4475 gen_helper_chk(cpu_env
, reg
, src
);
4481 TCGv addr1
, addr2
, bound1
, bound2
, reg
;
4484 switch ((insn
>> 9) & 3) {
4495 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4499 ext
= read_im16(env
, s
);
4500 if ((ext
& 0x0800) == 0) {
4501 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4505 addr1
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4506 addr2
= tcg_temp_new();
4507 tcg_gen_addi_i32(addr2
, addr1
, opsize_bytes(opsize
));
4509 bound1
= gen_load(s
, opsize
, addr1
, 1, IS_USER(s
));
4510 tcg_temp_free(addr1
);
4511 bound2
= gen_load(s
, opsize
, addr2
, 1, IS_USER(s
));
4512 tcg_temp_free(addr2
);
4514 reg
= tcg_temp_new();
4516 tcg_gen_mov_i32(reg
, AREG(ext
, 12));
4518 gen_ext(reg
, DREG(ext
, 12), opsize
, 1);
4522 gen_helper_chk2(cpu_env
, reg
, bound1
, bound2
);
4524 tcg_temp_free(bound1
);
4525 tcg_temp_free(bound2
);
4528 static void m68k_copy_line(TCGv dst
, TCGv src
, int index
)
4533 addr
= tcg_temp_new();
4535 t0
= tcg_temp_new_i64();
4536 t1
= tcg_temp_new_i64();
4538 tcg_gen_andi_i32(addr
, src
, ~15);
4539 tcg_gen_qemu_ld64(t0
, addr
, index
);
4540 tcg_gen_addi_i32(addr
, addr
, 8);
4541 tcg_gen_qemu_ld64(t1
, addr
, index
);
4543 tcg_gen_andi_i32(addr
, dst
, ~15);
4544 tcg_gen_qemu_st64(t0
, addr
, index
);
4545 tcg_gen_addi_i32(addr
, addr
, 8);
4546 tcg_gen_qemu_st64(t1
, addr
, index
);
4548 tcg_temp_free_i64(t0
);
4549 tcg_temp_free_i64(t1
);
4550 tcg_temp_free(addr
);
4553 DISAS_INSN(move16_reg
)
4555 int index
= IS_USER(s
);
4559 ext
= read_im16(env
, s
);
4560 if ((ext
& (1 << 15)) == 0) {
4561 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4564 m68k_copy_line(AREG(ext
, 12), AREG(insn
, 0), index
);
4566 /* Ax can be Ay, so save Ay before incrementing Ax */
4567 tmp
= tcg_temp_new();
4568 tcg_gen_mov_i32(tmp
, AREG(ext
, 12));
4569 tcg_gen_addi_i32(AREG(insn
, 0), AREG(insn
, 0), 16);
4570 tcg_gen_addi_i32(AREG(ext
, 12), tmp
, 16);
4574 DISAS_INSN(move16_mem
)
4576 int index
= IS_USER(s
);
4579 reg
= AREG(insn
, 0);
4580 addr
= tcg_const_i32(read_im32(env
, s
));
4582 if ((insn
>> 3) & 1) {
4583 /* MOVE16 (xxx).L, (Ay) */
4584 m68k_copy_line(reg
, addr
, index
);
4586 /* MOVE16 (Ay), (xxx).L */
4587 m68k_copy_line(addr
, reg
, index
);
4590 tcg_temp_free(addr
);
4592 if (((insn
>> 3) & 2) == 0) {
4594 tcg_gen_addi_i32(reg
, reg
, 16);
4604 ext
= read_im16(env
, s
);
4605 if (ext
!= 0x46FC) {
4606 gen_exception(s
, addr
, EXCP_ILLEGAL
);
4609 ext
= read_im16(env
, s
);
4610 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
4611 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
4614 gen_push(s
, gen_get_sr(s
));
4615 gen_set_sr_im(s
, ext
, 0);
4618 DISAS_INSN(move_from_sr
)
4622 if (IS_USER(s
) && !m68k_feature(env
, M68K_FEATURE_M68000
)) {
4623 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4627 DEST_EA(env
, insn
, OS_WORD
, sr
, NULL
);
4630 #if defined(CONFIG_SOFTMMU)
4640 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4644 ext
= read_im16(env
, s
);
4646 opsize
= insn_opsize(insn
);
4649 /* address register */
4650 reg
= AREG(ext
, 12);
4654 reg
= DREG(ext
, 12);
4658 addr
= gen_lea(env
, s
, insn
, opsize
);
4659 if (IS_NULL_QREG(addr
)) {
4665 /* from reg to ea */
4666 gen_store(s
, opsize
, addr
, reg
, DFC_INDEX(s
));
4668 /* from ea to reg */
4669 TCGv tmp
= gen_load(s
, opsize
, addr
, 0, SFC_INDEX(s
));
4671 gen_ext(reg
, tmp
, opsize
, 1);
4673 gen_partset_reg(opsize
, reg
, tmp
);
4677 switch (extract32(insn
, 3, 3)) {
4678 case 3: /* Indirect postincrement. */
4679 tcg_gen_addi_i32(AREG(insn
, 0), addr
,
4680 REG(insn
, 0) == 7 && opsize
== OS_BYTE
4682 : opsize_bytes(opsize
));
4684 case 4: /* Indirect predecrememnt. */
4685 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4690 DISAS_INSN(move_to_sr
)
4693 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4696 gen_move_to_sr(env
, s
, insn
, false);
4700 DISAS_INSN(move_from_usp
)
4703 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4706 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
4707 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4710 DISAS_INSN(move_to_usp
)
4713 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4716 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
4717 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4723 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4727 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
4735 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4739 ext
= read_im16(env
, s
);
4741 gen_set_sr_im(s
, ext
, 0);
4742 tcg_gen_movi_i32(cpu_halted
, 1);
4743 gen_exception(s
, s
->pc
, EXCP_HLT
);
4749 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4752 gen_exception(s
, s
->base
.pc_next
, EXCP_RTE
);
4755 DISAS_INSN(cf_movec
)
4761 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4765 ext
= read_im16(env
, s
);
4768 reg
= AREG(ext
, 12);
4770 reg
= DREG(ext
, 12);
4772 gen_helper_cf_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4776 DISAS_INSN(m68k_movec
)
4782 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4786 ext
= read_im16(env
, s
);
4789 reg
= AREG(ext
, 12);
4791 reg
= DREG(ext
, 12);
4794 gen_helper_m68k_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4796 gen_helper_m68k_movec_from(reg
, cpu_env
, tcg_const_i32(ext
& 0xfff));
4804 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4807 /* ICache fetch. Implement as no-op. */
4813 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4816 /* Cache push/invalidate. Implement as no-op. */
4822 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4825 /* Cache push/invalidate. Implement as no-op. */
4831 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4834 /* Invalidate cache line. Implement as no-op. */
4837 #if defined(CONFIG_SOFTMMU)
4843 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4847 opmode
= tcg_const_i32((insn
>> 3) & 3);
4848 gen_helper_pflush(cpu_env
, AREG(insn
, 0), opmode
);
4849 tcg_temp_free(opmode
);
4857 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4860 is_read
= tcg_const_i32((insn
>> 5) & 1);
4861 gen_helper_ptest(cpu_env
, AREG(insn
, 0), is_read
);
4862 tcg_temp_free(is_read
);
4868 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4874 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4877 /* TODO: Implement wdebug. */
4878 cpu_abort(env_cpu(env
), "WDEBUG not implemented");
4884 gen_exception(s
, s
->base
.pc_next
, EXCP_TRAP0
+ (insn
& 0xf));
4887 static void gen_load_fcr(DisasContext
*s
, TCGv res
, int reg
)
4891 tcg_gen_movi_i32(res
, 0);
4894 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4897 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpcr
));
4902 static void gen_store_fcr(DisasContext
*s
, TCGv val
, int reg
)
4908 tcg_gen_st_i32(val
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4911 gen_helper_set_fpcr(cpu_env
, val
);
4916 static void gen_qemu_store_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4918 int index
= IS_USER(s
);
4921 tmp
= tcg_temp_new();
4922 gen_load_fcr(s
, tmp
, reg
);
4923 tcg_gen_qemu_st32(tmp
, addr
, index
);
4927 static void gen_qemu_load_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4929 int index
= IS_USER(s
);
4932 tmp
= tcg_temp_new();
4933 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
4934 gen_store_fcr(s
, tmp
, reg
);
4939 static void gen_op_fmove_fcr(CPUM68KState
*env
, DisasContext
*s
,
4940 uint32_t insn
, uint32_t ext
)
4942 int mask
= (ext
>> 10) & 7;
4943 int is_write
= (ext
>> 13) & 1;
4944 int mode
= extract32(insn
, 3, 3);
4950 if (mask
!= M68K_FPIAR
&& mask
!= M68K_FPSR
&& mask
!= M68K_FPCR
) {
4951 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4955 gen_load_fcr(s
, DREG(insn
, 0), mask
);
4957 gen_store_fcr(s
, DREG(insn
, 0), mask
);
4960 case 1: /* An, only with FPIAR */
4961 if (mask
!= M68K_FPIAR
) {
4962 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4966 gen_load_fcr(s
, AREG(insn
, 0), mask
);
4968 gen_store_fcr(s
, AREG(insn
, 0), mask
);
4971 case 7: /* Immediate */
4972 if (REG(insn
, 0) == 4) {
4974 (mask
!= M68K_FPIAR
&& mask
!= M68K_FPSR
&&
4975 mask
!= M68K_FPCR
)) {
4976 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4979 tmp
= tcg_const_i32(read_im32(env
, s
));
4980 gen_store_fcr(s
, tmp
, mask
);
4989 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
4990 if (IS_NULL_QREG(tmp
)) {
4995 addr
= tcg_temp_new();
4996 tcg_gen_mov_i32(addr
, tmp
);
5001 * 0b100 Floating-Point Control Register
5002 * 0b010 Floating-Point Status Register
5003 * 0b001 Floating-Point Instruction Address Register
5007 if (is_write
&& mode
== 4) {
5008 for (i
= 2; i
>= 0; i
--, mask
>>= 1) {
5010 gen_qemu_store_fcr(s
, addr
, 1 << i
);
5012 tcg_gen_subi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
5016 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5018 for (i
= 0; i
< 3; i
++, mask
>>= 1) {
5021 gen_qemu_store_fcr(s
, addr
, 1 << i
);
5023 gen_qemu_load_fcr(s
, addr
, 1 << i
);
5025 if (mask
!= 1 || mode
== 3) {
5026 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
5031 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5034 tcg_temp_free_i32(addr
);
5037 static void gen_op_fmovem(CPUM68KState
*env
, DisasContext
*s
,
5038 uint32_t insn
, uint32_t ext
)
5042 int mode
= (ext
>> 11) & 0x3;
5043 int is_load
= ((ext
& 0x2000) == 0);
5045 if (m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
5046 opsize
= OS_EXTENDED
;
5048 opsize
= OS_DOUBLE
; /* FIXME */
5051 addr
= gen_lea(env
, s
, insn
, opsize
);
5052 if (IS_NULL_QREG(addr
)) {
5057 tmp
= tcg_temp_new();
5059 /* Dynamic register list */
5060 tcg_gen_ext8u_i32(tmp
, DREG(ext
, 4));
5062 /* Static register list */
5063 tcg_gen_movi_i32(tmp
, ext
& 0xff);
5066 if (!is_load
&& (mode
& 2) == 0) {
5068 * predecrement addressing mode
5069 * only available to store register to memory
5071 if (opsize
== OS_EXTENDED
) {
5072 gen_helper_fmovemx_st_predec(tmp
, cpu_env
, addr
, tmp
);
5074 gen_helper_fmovemd_st_predec(tmp
, cpu_env
, addr
, tmp
);
5077 /* postincrement addressing mode */
5078 if (opsize
== OS_EXTENDED
) {
5080 gen_helper_fmovemx_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
5082 gen_helper_fmovemx_st_postinc(tmp
, cpu_env
, addr
, tmp
);
5086 gen_helper_fmovemd_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
5088 gen_helper_fmovemd_st_postinc(tmp
, cpu_env
, addr
, tmp
);
5092 if ((insn
& 070) == 030 || (insn
& 070) == 040) {
5093 tcg_gen_mov_i32(AREG(insn
, 0), tmp
);
5099 * ??? FP exceptions are not implemented. Most exceptions are deferred until
5100 * immediately before the next FP instruction is executed.
5107 TCGv_ptr cpu_src
, cpu_dest
;
5109 ext
= read_im16(env
, s
);
5110 opmode
= ext
& 0x7f;
5111 switch ((ext
>> 13) & 7) {
5117 if (insn
== 0xf200 && (ext
& 0xfc00) == 0x5c00) {
5119 TCGv rom_offset
= tcg_const_i32(opmode
);
5120 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
5121 gen_helper_fconst(cpu_env
, cpu_dest
, rom_offset
);
5122 tcg_temp_free_ptr(cpu_dest
);
5123 tcg_temp_free(rom_offset
);
5127 case 3: /* fmove out */
5128 cpu_src
= gen_fp_ptr(REG(ext
, 7));
5129 opsize
= ext_opsize(ext
, 10);
5130 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
,
5131 EA_STORE
, IS_USER(s
)) == -1) {
5134 gen_helper_ftst(cpu_env
, cpu_src
);
5135 tcg_temp_free_ptr(cpu_src
);
5137 case 4: /* fmove to control register. */
5138 case 5: /* fmove from control register. */
5139 gen_op_fmove_fcr(env
, s
, insn
, ext
);
5141 case 6: /* fmovem */
5143 if ((ext
& 0x1000) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
5146 gen_op_fmovem(env
, s
, insn
, ext
);
5149 if (ext
& (1 << 14)) {
5150 /* Source effective address. */
5151 opsize
= ext_opsize(ext
, 10);
5152 cpu_src
= gen_fp_result_ptr();
5153 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
,
5154 EA_LOADS
, IS_USER(s
)) == -1) {
5159 /* Source register. */
5160 opsize
= OS_EXTENDED
;
5161 cpu_src
= gen_fp_ptr(REG(ext
, 10));
5163 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
5166 gen_fp_move(cpu_dest
, cpu_src
);
5168 case 0x40: /* fsmove */
5169 gen_helper_fsround(cpu_env
, cpu_dest
, cpu_src
);
5171 case 0x44: /* fdmove */
5172 gen_helper_fdround(cpu_env
, cpu_dest
, cpu_src
);
5175 gen_helper_firound(cpu_env
, cpu_dest
, cpu_src
);
5178 gen_helper_fsinh(cpu_env
, cpu_dest
, cpu_src
);
5180 case 3: /* fintrz */
5181 gen_helper_fitrunc(cpu_env
, cpu_dest
, cpu_src
);
5184 gen_helper_fsqrt(cpu_env
, cpu_dest
, cpu_src
);
5186 case 0x41: /* fssqrt */
5187 gen_helper_fssqrt(cpu_env
, cpu_dest
, cpu_src
);
5189 case 0x45: /* fdsqrt */
5190 gen_helper_fdsqrt(cpu_env
, cpu_dest
, cpu_src
);
5192 case 0x06: /* flognp1 */
5193 gen_helper_flognp1(cpu_env
, cpu_dest
, cpu_src
);
5195 case 0x08: /* fetoxm1 */
5196 gen_helper_fetoxm1(cpu_env
, cpu_dest
, cpu_src
);
5198 case 0x09: /* ftanh */
5199 gen_helper_ftanh(cpu_env
, cpu_dest
, cpu_src
);
5201 case 0x0a: /* fatan */
5202 gen_helper_fatan(cpu_env
, cpu_dest
, cpu_src
);
5204 case 0x0c: /* fasin */
5205 gen_helper_fasin(cpu_env
, cpu_dest
, cpu_src
);
5207 case 0x0d: /* fatanh */
5208 gen_helper_fatanh(cpu_env
, cpu_dest
, cpu_src
);
5210 case 0x0e: /* fsin */
5211 gen_helper_fsin(cpu_env
, cpu_dest
, cpu_src
);
5213 case 0x0f: /* ftan */
5214 gen_helper_ftan(cpu_env
, cpu_dest
, cpu_src
);
5216 case 0x10: /* fetox */
5217 gen_helper_fetox(cpu_env
, cpu_dest
, cpu_src
);
5219 case 0x11: /* ftwotox */
5220 gen_helper_ftwotox(cpu_env
, cpu_dest
, cpu_src
);
5222 case 0x12: /* ftentox */
5223 gen_helper_ftentox(cpu_env
, cpu_dest
, cpu_src
);
5225 case 0x14: /* flogn */
5226 gen_helper_flogn(cpu_env
, cpu_dest
, cpu_src
);
5228 case 0x15: /* flog10 */
5229 gen_helper_flog10(cpu_env
, cpu_dest
, cpu_src
);
5231 case 0x16: /* flog2 */
5232 gen_helper_flog2(cpu_env
, cpu_dest
, cpu_src
);
5234 case 0x18: /* fabs */
5235 gen_helper_fabs(cpu_env
, cpu_dest
, cpu_src
);
5237 case 0x58: /* fsabs */
5238 gen_helper_fsabs(cpu_env
, cpu_dest
, cpu_src
);
5240 case 0x5c: /* fdabs */
5241 gen_helper_fdabs(cpu_env
, cpu_dest
, cpu_src
);
5243 case 0x19: /* fcosh */
5244 gen_helper_fcosh(cpu_env
, cpu_dest
, cpu_src
);
5246 case 0x1a: /* fneg */
5247 gen_helper_fneg(cpu_env
, cpu_dest
, cpu_src
);
5249 case 0x5a: /* fsneg */
5250 gen_helper_fsneg(cpu_env
, cpu_dest
, cpu_src
);
5252 case 0x5e: /* fdneg */
5253 gen_helper_fdneg(cpu_env
, cpu_dest
, cpu_src
);
5255 case 0x1c: /* facos */
5256 gen_helper_facos(cpu_env
, cpu_dest
, cpu_src
);
5258 case 0x1d: /* fcos */
5259 gen_helper_fcos(cpu_env
, cpu_dest
, cpu_src
);
5261 case 0x1e: /* fgetexp */
5262 gen_helper_fgetexp(cpu_env
, cpu_dest
, cpu_src
);
5264 case 0x1f: /* fgetman */
5265 gen_helper_fgetman(cpu_env
, cpu_dest
, cpu_src
);
5267 case 0x20: /* fdiv */
5268 gen_helper_fdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5270 case 0x60: /* fsdiv */
5271 gen_helper_fsdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5273 case 0x64: /* fddiv */
5274 gen_helper_fddiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5276 case 0x21: /* fmod */
5277 gen_helper_fmod(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5279 case 0x22: /* fadd */
5280 gen_helper_fadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5282 case 0x62: /* fsadd */
5283 gen_helper_fsadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5285 case 0x66: /* fdadd */
5286 gen_helper_fdadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5288 case 0x23: /* fmul */
5289 gen_helper_fmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5291 case 0x63: /* fsmul */
5292 gen_helper_fsmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5294 case 0x67: /* fdmul */
5295 gen_helper_fdmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5297 case 0x24: /* fsgldiv */
5298 gen_helper_fsgldiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5300 case 0x25: /* frem */
5301 gen_helper_frem(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5303 case 0x26: /* fscale */
5304 gen_helper_fscale(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5306 case 0x27: /* fsglmul */
5307 gen_helper_fsglmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5309 case 0x28: /* fsub */
5310 gen_helper_fsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5312 case 0x68: /* fssub */
5313 gen_helper_fssub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5315 case 0x6c: /* fdsub */
5316 gen_helper_fdsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5318 case 0x30: case 0x31: case 0x32:
5319 case 0x33: case 0x34: case 0x35:
5320 case 0x36: case 0x37: {
5321 TCGv_ptr cpu_dest2
= gen_fp_ptr(REG(ext
, 0));
5322 gen_helper_fsincos(cpu_env
, cpu_dest
, cpu_dest2
, cpu_src
);
5323 tcg_temp_free_ptr(cpu_dest2
);
5326 case 0x38: /* fcmp */
5327 gen_helper_fcmp(cpu_env
, cpu_src
, cpu_dest
);
5329 case 0x3a: /* ftst */
5330 gen_helper_ftst(cpu_env
, cpu_src
);
5335 tcg_temp_free_ptr(cpu_src
);
5336 gen_helper_ftst(cpu_env
, cpu_dest
);
5337 tcg_temp_free_ptr(cpu_dest
);
5340 /* FIXME: Is this right for offset addressing modes? */
5342 disas_undef_fpu(env
, s
, insn
);
5345 static void gen_fcc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
5350 c
->v2
= tcg_const_i32(0);
5352 /* TODO: Raise BSUN exception. */
5353 fpsr
= tcg_temp_new();
5354 gen_load_fcr(s
, fpsr
, M68K_FPSR
);
5357 case 16: /* Signaling False */
5359 c
->tcond
= TCG_COND_NEVER
;
5361 case 1: /* EQual Z */
5362 case 17: /* Signaling EQual Z */
5363 c
->v1
= tcg_temp_new();
5365 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5366 c
->tcond
= TCG_COND_NE
;
5368 case 2: /* Ordered Greater Than !(A || Z || N) */
5369 case 18: /* Greater Than !(A || Z || N) */
5370 c
->v1
= tcg_temp_new();
5372 tcg_gen_andi_i32(c
->v1
, fpsr
,
5373 FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5374 c
->tcond
= TCG_COND_EQ
;
5376 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
5377 case 19: /* Greater than or Equal Z || !(A || N) */
5378 c
->v1
= tcg_temp_new();
5380 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5381 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5382 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_Z
| FPSR_CC_N
);
5383 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5384 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5385 c
->tcond
= TCG_COND_NE
;
5387 case 4: /* Ordered Less Than !(!N || A || Z); */
5388 case 20: /* Less Than !(!N || A || Z); */
5389 c
->v1
= tcg_temp_new();
5391 tcg_gen_xori_i32(c
->v1
, fpsr
, FPSR_CC_N
);
5392 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_N
| FPSR_CC_A
| FPSR_CC_Z
);
5393 c
->tcond
= TCG_COND_EQ
;
5395 case 5: /* Ordered Less than or Equal Z || (N && !A) */
5396 case 21: /* Less than or Equal Z || (N && !A) */
5397 c
->v1
= tcg_temp_new();
5399 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5400 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5401 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5402 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_Z
| FPSR_CC_N
);
5403 c
->tcond
= TCG_COND_NE
;
5405 case 6: /* Ordered Greater or Less than !(A || Z) */
5406 case 22: /* Greater or Less than !(A || Z) */
5407 c
->v1
= tcg_temp_new();
5409 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5410 c
->tcond
= TCG_COND_EQ
;
5412 case 7: /* Ordered !A */
5413 case 23: /* Greater, Less or Equal !A */
5414 c
->v1
= tcg_temp_new();
5416 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5417 c
->tcond
= TCG_COND_EQ
;
5419 case 8: /* Unordered A */
5420 case 24: /* Not Greater, Less or Equal A */
5421 c
->v1
= tcg_temp_new();
5423 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5424 c
->tcond
= TCG_COND_NE
;
5426 case 9: /* Unordered or Equal A || Z */
5427 case 25: /* Not Greater or Less then A || Z */
5428 c
->v1
= tcg_temp_new();
5430 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5431 c
->tcond
= TCG_COND_NE
;
5433 case 10: /* Unordered or Greater Than A || !(N || Z)) */
5434 case 26: /* Not Less or Equal A || !(N || Z)) */
5435 c
->v1
= tcg_temp_new();
5437 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5438 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5439 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_A
| FPSR_CC_N
);
5440 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5441 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5442 c
->tcond
= TCG_COND_NE
;
5444 case 11: /* Unordered or Greater or Equal A || Z || !N */
5445 case 27: /* Not Less Than A || Z || !N */
5446 c
->v1
= tcg_temp_new();
5448 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5449 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5450 c
->tcond
= TCG_COND_NE
;
5452 case 12: /* Unordered or Less Than A || (N && !Z) */
5453 case 28: /* Not Greater than or Equal A || (N && !Z) */
5454 c
->v1
= tcg_temp_new();
5456 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5457 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5458 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5459 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_A
| FPSR_CC_N
);
5460 c
->tcond
= TCG_COND_NE
;
5462 case 13: /* Unordered or Less or Equal A || Z || N */
5463 case 29: /* Not Greater Than A || Z || N */
5464 c
->v1
= tcg_temp_new();
5466 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5467 c
->tcond
= TCG_COND_NE
;
5469 case 14: /* Not Equal !Z */
5470 case 30: /* Signaling Not Equal !Z */
5471 c
->v1
= tcg_temp_new();
5473 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5474 c
->tcond
= TCG_COND_EQ
;
5477 case 31: /* Signaling True */
5479 c
->tcond
= TCG_COND_ALWAYS
;
5482 tcg_temp_free(fpsr
);
5485 static void gen_fjmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
5489 gen_fcc_cond(&c
, s
, cond
);
5491 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
5502 offset
= (int16_t)read_im16(env
, s
);
5503 if (insn
& (1 << 6)) {
5504 offset
= (offset
<< 16) | read_im16(env
, s
);
5507 l1
= gen_new_label();
5509 gen_fjmpcc(s
, insn
& 0x3f, l1
);
5510 gen_jmp_tb(s
, 0, s
->pc
);
5512 gen_jmp_tb(s
, 1, base
+ offset
);
5522 ext
= read_im16(env
, s
);
5524 gen_fcc_cond(&c
, s
, cond
);
5526 tmp
= tcg_temp_new();
5527 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
5530 tcg_gen_neg_i32(tmp
, tmp
);
5531 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
5535 #if defined(CONFIG_SOFTMMU)
5536 DISAS_INSN(frestore
)
5541 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
5544 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5545 SRC_EA(env
, addr
, OS_LONG
, 0, NULL
);
5546 /* FIXME: check the state frame */
5548 disas_undef(env
, s
, insn
);
5555 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
5559 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5560 /* always write IDLE */
5561 TCGv idle
= tcg_const_i32(0x41000000);
5562 DEST_EA(env
, insn
, OS_LONG
, idle
, NULL
);
5563 tcg_temp_free(idle
);
5565 disas_undef(env
, s
, insn
);
5570 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
5572 TCGv tmp
= tcg_temp_new();
5573 if (s
->env
->macsr
& MACSR_FI
) {
5575 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
5577 tcg_gen_shli_i32(tmp
, val
, 16);
5578 } else if (s
->env
->macsr
& MACSR_SU
) {
5580 tcg_gen_sari_i32(tmp
, val
, 16);
5582 tcg_gen_ext16s_i32(tmp
, val
);
5585 tcg_gen_shri_i32(tmp
, val
, 16);
5587 tcg_gen_ext16u_i32(tmp
, val
);
5592 static void gen_mac_clear_flags(void)
5594 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
5595 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
5611 s
->mactmp
= tcg_temp_new_i64();
5615 ext
= read_im16(env
, s
);
5617 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
5618 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
5619 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
5620 disas_undef(env
, s
, insn
);
5624 /* MAC with load. */
5625 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
5626 addr
= tcg_temp_new();
5627 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
5629 * Load the value now to ensure correct exception behavior.
5630 * Perform writeback after reading the MAC inputs.
5632 loadval
= gen_load(s
, OS_LONG
, addr
, 0, IS_USER(s
));
5635 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
5636 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
5638 loadval
= addr
= NULL_QREG
;
5639 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5640 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5643 gen_mac_clear_flags();
5646 /* Disabled because conditional branches clobber temporary vars. */
5647 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
5648 /* Skip the multiply if we know we will ignore it. */
5649 l1
= gen_new_label();
5650 tmp
= tcg_temp_new();
5651 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
5652 gen_op_jmp_nz32(tmp
, l1
);
5656 if ((ext
& 0x0800) == 0) {
5658 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
5659 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
5661 if (s
->env
->macsr
& MACSR_FI
) {
5662 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
5664 if (s
->env
->macsr
& MACSR_SU
)
5665 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
5667 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
5668 switch ((ext
>> 9) & 3) {
5670 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
5673 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
5679 /* Save the overflow flag from the multiply. */
5680 saved_flags
= tcg_temp_new();
5681 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
5683 saved_flags
= NULL_QREG
;
5687 /* Disabled because conditional branches clobber temporary vars. */
5688 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
5689 /* Skip the accumulate if the value is already saturated. */
5690 l1
= gen_new_label();
5691 tmp
= tcg_temp_new();
5692 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5693 gen_op_jmp_nz32(tmp
, l1
);
5698 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5700 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5702 if (s
->env
->macsr
& MACSR_FI
)
5703 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5704 else if (s
->env
->macsr
& MACSR_SU
)
5705 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5707 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5710 /* Disabled because conditional branches clobber temporary vars. */
5716 /* Dual accumulate variant. */
5717 acc
= (ext
>> 2) & 3;
5718 /* Restore the overflow flag from the multiplier. */
5719 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
5721 /* Disabled because conditional branches clobber temporary vars. */
5722 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
5723 /* Skip the accumulate if the value is already saturated. */
5724 l1
= gen_new_label();
5725 tmp
= tcg_temp_new();
5726 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5727 gen_op_jmp_nz32(tmp
, l1
);
5731 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5733 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5734 if (s
->env
->macsr
& MACSR_FI
)
5735 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5736 else if (s
->env
->macsr
& MACSR_SU
)
5737 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5739 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5741 /* Disabled because conditional branches clobber temporary vars. */
5746 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
5750 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5751 tcg_gen_mov_i32(rw
, loadval
);
5753 * FIXME: Should address writeback happen with the masked or
5756 switch ((insn
>> 3) & 7) {
5757 case 3: /* Post-increment. */
5758 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
5760 case 4: /* Pre-decrement. */
5761 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5763 tcg_temp_free(loadval
);
5767 DISAS_INSN(from_mac
)
5773 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5774 accnum
= (insn
>> 9) & 3;
5775 acc
= MACREG(accnum
);
5776 if (s
->env
->macsr
& MACSR_FI
) {
5777 gen_helper_get_macf(rx
, cpu_env
, acc
);
5778 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
5779 tcg_gen_extrl_i64_i32(rx
, acc
);
5780 } else if (s
->env
->macsr
& MACSR_SU
) {
5781 gen_helper_get_macs(rx
, acc
);
5783 gen_helper_get_macu(rx
, acc
);
5786 tcg_gen_movi_i64(acc
, 0);
5787 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5791 DISAS_INSN(move_mac
)
5793 /* FIXME: This can be done without a helper. */
5797 dest
= tcg_const_i32((insn
>> 9) & 3);
5798 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
5799 gen_mac_clear_flags();
5800 gen_helper_mac_set_flags(cpu_env
, dest
);
5803 DISAS_INSN(from_macsr
)
5807 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5808 tcg_gen_mov_i32(reg
, QREG_MACSR
);
5811 DISAS_INSN(from_mask
)
5814 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5815 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
5818 DISAS_INSN(from_mext
)
5822 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5823 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5824 if (s
->env
->macsr
& MACSR_FI
)
5825 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
5827 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
5830 DISAS_INSN(macsr_to_ccr
)
5832 TCGv tmp
= tcg_temp_new();
5833 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 0xf);
5834 gen_helper_set_sr(cpu_env
, tmp
);
5836 set_cc_op(s
, CC_OP_FLAGS
);
5844 accnum
= (insn
>> 9) & 3;
5845 acc
= MACREG(accnum
);
5846 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5847 if (s
->env
->macsr
& MACSR_FI
) {
5848 tcg_gen_ext_i32_i64(acc
, val
);
5849 tcg_gen_shli_i64(acc
, acc
, 8);
5850 } else if (s
->env
->macsr
& MACSR_SU
) {
5851 tcg_gen_ext_i32_i64(acc
, val
);
5853 tcg_gen_extu_i32_i64(acc
, val
);
5855 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5856 gen_mac_clear_flags();
5857 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
5860 DISAS_INSN(to_macsr
)
5863 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5864 gen_helper_set_macsr(cpu_env
, val
);
5871 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5872 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
5879 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5880 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5881 if (s
->env
->macsr
& MACSR_FI
)
5882 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
5883 else if (s
->env
->macsr
& MACSR_SU
)
5884 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
5886 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
5889 static disas_proc opcode_table
[65536];
5892 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
5898 /* Sanity check. All set bits must be included in the mask. */
5899 if (opcode
& ~mask
) {
5901 "qemu internal error: bogus opcode definition %04x/%04x\n",
5906 * This could probably be cleverer. For now just optimize the case where
5907 * the top bits are known.
5909 /* Find the first zero bit in the mask. */
5911 while ((i
& mask
) != 0)
5913 /* Iterate over all combinations of this and lower bits. */
5918 from
= opcode
& ~(i
- 1);
5920 for (i
= from
; i
< to
; i
++) {
5921 if ((i
& mask
) == opcode
)
5922 opcode_table
[i
] = proc
;
5927 * Register m68k opcode handlers. Order is important.
5928 * Later insn override earlier ones.
5930 void register_m68k_insns (CPUM68KState
*env
)
5933 * Build the opcode table only once to avoid
5934 * multithreading issues.
5936 if (opcode_table
[0] != NULL
) {
5941 * use BASE() for instruction available
5942 * for CF_ISA_A and M68000.
5944 #define BASE(name, opcode, mask) \
5945 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5946 #define INSN(name, opcode, mask, feature) do { \
5947 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5948 BASE(name, opcode, mask); \
5950 BASE(undef
, 0000, 0000);
5951 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
5952 INSN(arith_im
, 0000, ff00
, M68000
);
5953 INSN(chk2
, 00c0
, f9c0
, CHK2
);
5954 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
5955 BASE(bitop_reg
, 0100, f1c0
);
5956 BASE(bitop_reg
, 0140, f1c0
);
5957 BASE(bitop_reg
, 0180, f1c0
);
5958 BASE(bitop_reg
, 01c0
, f1c0
);
5959 INSN(movep
, 0108, f138
, MOVEP
);
5960 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
5961 INSN(arith_im
, 0200, ff00
, M68000
);
5962 INSN(undef
, 02c0
, ffc0
, M68000
);
5963 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
5964 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
5965 INSN(arith_im
, 0400, ff00
, M68000
);
5966 INSN(undef
, 04c0
, ffc0
, M68000
);
5967 INSN(arith_im
, 0600, ff00
, M68000
);
5968 INSN(undef
, 06c0
, ffc0
, M68000
);
5969 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
5970 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
5971 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
5972 INSN(arith_im
, 0c00
, ff00
, M68000
);
5973 BASE(bitop_im
, 0800, ffc0
);
5974 BASE(bitop_im
, 0840, ffc0
);
5975 BASE(bitop_im
, 0880, ffc0
);
5976 BASE(bitop_im
, 08c0
, ffc0
);
5977 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
5978 INSN(arith_im
, 0a00
, ff00
, M68000
);
5979 #if defined(CONFIG_SOFTMMU)
5980 INSN(moves
, 0e00
, ff00
, M68000
);
5982 INSN(cas
, 0ac0
, ffc0
, CAS
);
5983 INSN(cas
, 0cc0
, ffc0
, CAS
);
5984 INSN(cas
, 0ec0
, ffc0
, CAS
);
5985 INSN(cas2w
, 0cfc
, ffff
, CAS
);
5986 INSN(cas2l
, 0efc
, ffff
, CAS
);
5987 BASE(move
, 1000, f000
);
5988 BASE(move
, 2000, f000
);
5989 BASE(move
, 3000, f000
);
5990 INSN(chk
, 4000, f040
, M68000
);
5991 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
5992 INSN(negx
, 4080, fff8
, CF_ISA_A
);
5993 INSN(negx
, 4000, ff00
, M68000
);
5994 INSN(undef
, 40c0
, ffc0
, M68000
);
5995 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
5996 INSN(move_from_sr
, 40c0
, ffc0
, M68000
);
5997 BASE(lea
, 41c0
, f1c0
);
5998 BASE(clr
, 4200, ff00
);
5999 BASE(undef
, 42c0
, ffc0
);
6000 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
6001 INSN(move_from_ccr
, 42c0
, ffc0
, M68000
);
6002 INSN(neg
, 4480, fff8
, CF_ISA_A
);
6003 INSN(neg
, 4400, ff00
, M68000
);
6004 INSN(undef
, 44c0
, ffc0
, M68000
);
6005 BASE(move_to_ccr
, 44c0
, ffc0
);
6006 INSN(not, 4680, fff8
, CF_ISA_A
);
6007 INSN(not, 4600, ff00
, M68000
);
6008 #if defined(CONFIG_SOFTMMU)
6009 BASE(move_to_sr
, 46c0
, ffc0
);
6011 INSN(nbcd
, 4800, ffc0
, M68000
);
6012 INSN(linkl
, 4808, fff8
, M68000
);
6013 BASE(pea
, 4840, ffc0
);
6014 BASE(swap
, 4840, fff8
);
6015 INSN(bkpt
, 4848, fff8
, BKPT
);
6016 INSN(movem
, 48d0
, fbf8
, CF_ISA_A
);
6017 INSN(movem
, 48e8
, fbf8
, CF_ISA_A
);
6018 INSN(movem
, 4880, fb80
, M68000
);
6019 BASE(ext
, 4880, fff8
);
6020 BASE(ext
, 48c0
, fff8
);
6021 BASE(ext
, 49c0
, fff8
);
6022 BASE(tst
, 4a00
, ff00
);
6023 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
6024 INSN(tas
, 4ac0
, ffc0
, M68000
);
6025 #if defined(CONFIG_SOFTMMU)
6026 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
6028 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
6029 BASE(illegal
, 4afc
, ffff
);
6030 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
6031 INSN(mull
, 4c00
, ffc0
, LONG_MULDIV
);
6032 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
6033 INSN(divl
, 4c40
, ffc0
, LONG_MULDIV
);
6034 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
6035 BASE(trap
, 4e40
, fff0
);
6036 BASE(link
, 4e50
, fff8
);
6037 BASE(unlk
, 4e58
, fff8
);
6038 #if defined(CONFIG_SOFTMMU)
6039 INSN(move_to_usp
, 4e60
, fff8
, USP
);
6040 INSN(move_from_usp
, 4e68
, fff8
, USP
);
6041 INSN(reset
, 4e70
, ffff
, M68000
);
6042 BASE(stop
, 4e72
, ffff
);
6043 BASE(rte
, 4e73
, ffff
);
6044 INSN(cf_movec
, 4e7b
, ffff
, CF_ISA_A
);
6045 INSN(m68k_movec
, 4e7a
, fffe
, MOVEC
);
6047 BASE(nop
, 4e71
, ffff
);
6048 INSN(rtd
, 4e74
, ffff
, RTD
);
6049 BASE(rts
, 4e75
, ffff
);
6050 INSN(rtr
, 4e77
, ffff
, M68000
);
6051 BASE(jump
, 4e80
, ffc0
);
6052 BASE(jump
, 4ec0
, ffc0
);
6053 INSN(addsubq
, 5000, f080
, M68000
);
6054 BASE(addsubq
, 5080, f0c0
);
6055 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
); /* Scc.B Dx */
6056 INSN(scc
, 50c0
, f0c0
, M68000
); /* Scc.B <EA> */
6057 INSN(dbcc
, 50c8
, f0f8
, M68000
);
6058 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
6060 /* Branch instructions. */
6061 BASE(branch
, 6000, f000
);
6062 /* Disable long branch instructions, then add back the ones we want. */
6063 BASE(undef
, 60ff
, f0ff
); /* All long branches. */
6064 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
6065 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
6066 INSN(branch
, 60ff
, ffff
, BRAL
);
6067 INSN(branch
, 60ff
, f0ff
, BCCL
);
6069 BASE(moveq
, 7000, f100
);
6070 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
6071 BASE(or, 8000, f000
);
6072 BASE(divw
, 80c0
, f0c0
);
6073 INSN(sbcd_reg
, 8100, f1f8
, M68000
);
6074 INSN(sbcd_mem
, 8108, f1f8
, M68000
);
6075 BASE(addsub
, 9000, f000
);
6076 INSN(undef
, 90c0
, f0c0
, CF_ISA_A
);
6077 INSN(subx_reg
, 9180, f1f8
, CF_ISA_A
);
6078 INSN(subx_reg
, 9100, f138
, M68000
);
6079 INSN(subx_mem
, 9108, f138
, M68000
);
6080 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
6081 INSN(suba
, 90c0
, f0c0
, M68000
);
6083 BASE(undef_mac
, a000
, f000
);
6084 INSN(mac
, a000
, f100
, CF_EMAC
);
6085 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
6086 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
6087 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
6088 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
6089 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
6090 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
6091 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
6092 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
6093 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
6094 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
6096 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
6097 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
6098 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
6099 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
6100 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
6101 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
6102 INSN(cmp
, b000
, f100
, M68000
);
6103 INSN(eor
, b100
, f100
, M68000
);
6104 INSN(cmpm
, b108
, f138
, M68000
);
6105 INSN(cmpa
, b0c0
, f0c0
, M68000
);
6106 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
6107 BASE(and, c000
, f000
);
6108 INSN(exg_dd
, c140
, f1f8
, M68000
);
6109 INSN(exg_aa
, c148
, f1f8
, M68000
);
6110 INSN(exg_da
, c188
, f1f8
, M68000
);
6111 BASE(mulw
, c0c0
, f0c0
);
6112 INSN(abcd_reg
, c100
, f1f8
, M68000
);
6113 INSN(abcd_mem
, c108
, f1f8
, M68000
);
6114 BASE(addsub
, d000
, f000
);
6115 INSN(undef
, d0c0
, f0c0
, CF_ISA_A
);
6116 INSN(addx_reg
, d180
, f1f8
, CF_ISA_A
);
6117 INSN(addx_reg
, d100
, f138
, M68000
);
6118 INSN(addx_mem
, d108
, f138
, M68000
);
6119 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
6120 INSN(adda
, d0c0
, f0c0
, M68000
);
6121 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
6122 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
6123 INSN(shift8_im
, e000
, f0f0
, M68000
);
6124 INSN(shift16_im
, e040
, f0f0
, M68000
);
6125 INSN(shift_im
, e080
, f0f0
, M68000
);
6126 INSN(shift8_reg
, e020
, f0f0
, M68000
);
6127 INSN(shift16_reg
, e060
, f0f0
, M68000
);
6128 INSN(shift_reg
, e0a0
, f0f0
, M68000
);
6129 INSN(shift_mem
, e0c0
, fcc0
, M68000
);
6130 INSN(rotate_im
, e090
, f0f0
, M68000
);
6131 INSN(rotate8_im
, e010
, f0f0
, M68000
);
6132 INSN(rotate16_im
, e050
, f0f0
, M68000
);
6133 INSN(rotate_reg
, e0b0
, f0f0
, M68000
);
6134 INSN(rotate8_reg
, e030
, f0f0
, M68000
);
6135 INSN(rotate16_reg
, e070
, f0f0
, M68000
);
6136 INSN(rotate_mem
, e4c0
, fcc0
, M68000
);
6137 INSN(bfext_mem
, e9c0
, fdc0
, BITFIELD
); /* bfextu & bfexts */
6138 INSN(bfext_reg
, e9c0
, fdf8
, BITFIELD
);
6139 INSN(bfins_mem
, efc0
, ffc0
, BITFIELD
);
6140 INSN(bfins_reg
, efc0
, fff8
, BITFIELD
);
6141 INSN(bfop_mem
, eac0
, ffc0
, BITFIELD
); /* bfchg */
6142 INSN(bfop_reg
, eac0
, fff8
, BITFIELD
); /* bfchg */
6143 INSN(bfop_mem
, ecc0
, ffc0
, BITFIELD
); /* bfclr */
6144 INSN(bfop_reg
, ecc0
, fff8
, BITFIELD
); /* bfclr */
6145 INSN(bfop_mem
, edc0
, ffc0
, BITFIELD
); /* bfffo */
6146 INSN(bfop_reg
, edc0
, fff8
, BITFIELD
); /* bfffo */
6147 INSN(bfop_mem
, eec0
, ffc0
, BITFIELD
); /* bfset */
6148 INSN(bfop_reg
, eec0
, fff8
, BITFIELD
); /* bfset */
6149 INSN(bfop_mem
, e8c0
, ffc0
, BITFIELD
); /* bftst */
6150 INSN(bfop_reg
, e8c0
, fff8
, BITFIELD
); /* bftst */
6151 BASE(undef_fpu
, f000
, f000
);
6152 INSN(fpu
, f200
, ffc0
, CF_FPU
);
6153 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
6154 INSN(fpu
, f200
, ffc0
, FPU
);
6155 INSN(fscc
, f240
, ffc0
, FPU
);
6156 INSN(fbcc
, f280
, ff80
, FPU
);
6157 #if defined(CONFIG_SOFTMMU)
6158 INSN(frestore
, f340
, ffc0
, CF_FPU
);
6159 INSN(fsave
, f300
, ffc0
, CF_FPU
);
6160 INSN(frestore
, f340
, ffc0
, FPU
);
6161 INSN(fsave
, f300
, ffc0
, FPU
);
6162 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
6163 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
6164 INSN(cpush
, f420
, ff20
, M68040
);
6165 INSN(cinv
, f400
, ff20
, M68040
);
6166 INSN(pflush
, f500
, ffe0
, M68040
);
6167 INSN(ptest
, f548
, ffd8
, M68040
);
6168 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
6169 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
6171 INSN(move16_mem
, f600
, ffe0
, M68040
);
6172 INSN(move16_reg
, f620
, fff8
, M68040
);
6176 static void m68k_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cpu
)
6178 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6179 CPUM68KState
*env
= cpu
->env_ptr
;
6182 dc
->pc
= dc
->base
.pc_first
;
6183 dc
->cc_op
= CC_OP_DYNAMIC
;
6184 dc
->cc_op_synced
= 1;
6186 dc
->writeback_mask
= 0;
6187 init_release_array(dc
);
6190 static void m68k_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
6194 static void m68k_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
6196 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6197 tcg_gen_insn_start(dc
->base
.pc_next
, dc
->cc_op
);
6200 static bool m68k_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
6201 const CPUBreakpoint
*bp
)
6203 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6205 gen_exception(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
6207 * The address covered by the breakpoint must be included in
6208 * [tb->pc, tb->pc + tb->size) in order to for it to be
6209 * properly cleared -- thus we increment the PC here so that
6210 * the logic setting tb->size below does the right thing.
6212 dc
->base
.pc_next
+= 2;
6217 static void m68k_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
6219 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6220 CPUM68KState
*env
= cpu
->env_ptr
;
6221 uint16_t insn
= read_im16(env
, dc
);
6223 opcode_table
[insn
](env
, dc
, insn
);
6227 dc
->base
.pc_next
= dc
->pc
;
6229 if (dc
->base
.is_jmp
== DISAS_NEXT
) {
6231 * Stop translation when the next insn might touch a new page.
6232 * This ensures that prefetch aborts at the right place.
6234 * We cannot determine the size of the next insn without
6235 * completely decoding it. However, the maximum insn size
6236 * is 32 bytes, so end if we do not have that much remaining.
6237 * This may produce several small TBs at the end of each page,
6238 * but they will all be linked with goto_tb.
6240 * ??? ColdFire maximum is 4 bytes; MC68000's maximum is also
6241 * smaller than MC68020's.
6243 target_ulong start_page_offset
6244 = dc
->pc
- (dc
->base
.pc_first
& TARGET_PAGE_MASK
);
6246 if (start_page_offset
>= TARGET_PAGE_SIZE
- 32) {
6247 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
6252 static void m68k_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
6254 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6256 switch (dc
->base
.is_jmp
) {
6257 case DISAS_NORETURN
:
6259 case DISAS_TOO_MANY
:
6261 if (is_singlestepping(dc
)) {
6262 tcg_gen_movi_i32(QREG_PC
, dc
->pc
);
6263 gen_raise_exception(EXCP_DEBUG
);
6265 gen_jmp_tb(dc
, 0, dc
->pc
);
6269 /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
6270 if (is_singlestepping(dc
)) {
6271 gen_raise_exception(EXCP_DEBUG
);
6273 tcg_gen_lookup_and_goto_ptr();
6278 * We updated CC_OP and PC in gen_exit_tb, but also modified
6279 * other state that may require returning to the main loop.
6281 if (is_singlestepping(dc
)) {
6282 gen_raise_exception(EXCP_DEBUG
);
6284 tcg_gen_exit_tb(NULL
, 0);
6288 g_assert_not_reached();
6292 static void m68k_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cpu
)
6294 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
6295 log_target_disas(cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
6298 static const TranslatorOps m68k_tr_ops
= {
6299 .init_disas_context
= m68k_tr_init_disas_context
,
6300 .tb_start
= m68k_tr_tb_start
,
6301 .insn_start
= m68k_tr_insn_start
,
6302 .breakpoint_check
= m68k_tr_breakpoint_check
,
6303 .translate_insn
= m68k_tr_translate_insn
,
6304 .tb_stop
= m68k_tr_tb_stop
,
6305 .disas_log
= m68k_tr_disas_log
,
6308 void gen_intermediate_code(CPUState
*cpu
, TranslationBlock
*tb
, int max_insns
)
6311 translator_loop(&m68k_tr_ops
, &dc
.base
, cpu
, tb
, max_insns
);
6314 static double floatx80_to_double(CPUM68KState
*env
, uint16_t high
, uint64_t low
)
6316 floatx80 a
= { .high
= high
, .low
= low
};
6322 u
.f64
= floatx80_to_float64(a
, &env
->fp_status
);
6326 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
6328 M68kCPU
*cpu
= M68K_CPU(cs
);
6329 CPUM68KState
*env
= &cpu
->env
;
6332 for (i
= 0; i
< 8; i
++) {
6333 qemu_fprintf(f
, "D%d = %08x A%d = %08x "
6334 "F%d = %04x %016"PRIx64
" (%12g)\n",
6335 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
6336 i
, env
->fregs
[i
].l
.upper
, env
->fregs
[i
].l
.lower
,
6337 floatx80_to_double(env
, env
->fregs
[i
].l
.upper
,
6338 env
->fregs
[i
].l
.lower
));
6340 qemu_fprintf(f
, "PC = %08x ", env
->pc
);
6341 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
6342 qemu_fprintf(f
, "SR = %04x T:%x I:%x %c%c %c%c%c%c%c\n",
6343 sr
, (sr
& SR_T
) >> SR_T_SHIFT
, (sr
& SR_I
) >> SR_I_SHIFT
,
6344 (sr
& SR_S
) ? 'S' : 'U', (sr
& SR_M
) ? '%' : 'I',
6345 (sr
& CCF_X
) ? 'X' : '-', (sr
& CCF_N
) ? 'N' : '-',
6346 (sr
& CCF_Z
) ? 'Z' : '-', (sr
& CCF_V
) ? 'V' : '-',
6347 (sr
& CCF_C
) ? 'C' : '-');
6348 qemu_fprintf(f
, "FPSR = %08x %c%c%c%c ", env
->fpsr
,
6349 (env
->fpsr
& FPSR_CC_A
) ? 'A' : '-',
6350 (env
->fpsr
& FPSR_CC_I
) ? 'I' : '-',
6351 (env
->fpsr
& FPSR_CC_Z
) ? 'Z' : '-',
6352 (env
->fpsr
& FPSR_CC_N
) ? 'N' : '-');
6353 qemu_fprintf(f
, "\n "
6354 "FPCR = %04x ", env
->fpcr
);
6355 switch (env
->fpcr
& FPCR_PREC_MASK
) {
6357 qemu_fprintf(f
, "X ");
6360 qemu_fprintf(f
, "S ");
6363 qemu_fprintf(f
, "D ");
6366 switch (env
->fpcr
& FPCR_RND_MASK
) {
6368 qemu_fprintf(f
, "RN ");
6371 qemu_fprintf(f
, "RZ ");
6374 qemu_fprintf(f
, "RM ");
6377 qemu_fprintf(f
, "RP ");
6380 qemu_fprintf(f
, "\n");
6381 #ifdef CONFIG_SOFTMMU
6382 qemu_fprintf(f
, "%sA7(MSP) = %08x %sA7(USP) = %08x %sA7(ISP) = %08x\n",
6383 env
->current_sp
== M68K_SSP
? "->" : " ", env
->sp
[M68K_SSP
],
6384 env
->current_sp
== M68K_USP
? "->" : " ", env
->sp
[M68K_USP
],
6385 env
->current_sp
== M68K_ISP
? "->" : " ", env
->sp
[M68K_ISP
]);
6386 qemu_fprintf(f
, "VBR = 0x%08x\n", env
->vbr
);
6387 qemu_fprintf(f
, "SFC = %x DFC %x\n", env
->sfc
, env
->dfc
);
6388 qemu_fprintf(f
, "SSW %08x TCR %08x URP %08x SRP %08x\n",
6389 env
->mmu
.ssw
, env
->mmu
.tcr
, env
->mmu
.urp
, env
->mmu
.srp
);
6390 qemu_fprintf(f
, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n",
6391 env
->mmu
.ttr
[M68K_DTTR0
], env
->mmu
.ttr
[M68K_DTTR1
],
6392 env
->mmu
.ttr
[M68K_ITTR0
], env
->mmu
.ttr
[M68K_ITTR1
]);
6393 qemu_fprintf(f
, "MMUSR %08x, fault at %08x\n",
6394 env
->mmu
.mmusr
, env
->mmu
.ar
);
6398 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,
6401 int cc_op
= data
[1];
6403 if (cc_op
!= CC_OP_DYNAMIC
) {