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cmd: Fix potential memory leak
[qemu/ar7.git] / hw / ac97.c
blob6800af43a46d719621923a5e10b9e56468cfc439
1 /*
2 * Copyright (C) 2006 InnoTek Systemberatung GmbH
3 *
4 * This file is part of VirtualBox Open Source Edition (OSE), as
5 * available from http://www.virtualbox.org. This file is free software;
6 * you can redistribute it and/or modify it under the terms of the GNU
7 * General Public License as published by the Free Software Foundation,
8 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
9 * distribution. VirtualBox OSE is distributed in the hope that it will
10 * be useful, but WITHOUT ANY WARRANTY of any kind.
11 *
12 * If you received this file as part of a commercial VirtualBox
13 * distribution, then only the terms of your commercial VirtualBox
14 * license agreement apply instead of the previous paragraph.
15 */
16
17 #include "hw.h"
18 #include "audiodev.h"
19 #include "audio/audio.h"
20 #include "pci.h"
21 #include "dma.h"
22
23 enum {
24 AC97_Reset = 0x00,
25 AC97_Master_Volume_Mute = 0x02,
26 AC97_Headphone_Volume_Mute = 0x04,
27 AC97_Master_Volume_Mono_Mute = 0x06,
28 AC97_Master_Tone_RL = 0x08,
29 AC97_PC_BEEP_Volume_Mute = 0x0A,
30 AC97_Phone_Volume_Mute = 0x0C,
31 AC97_Mic_Volume_Mute = 0x0E,
32 AC97_Line_In_Volume_Mute = 0x10,
33 AC97_CD_Volume_Mute = 0x12,
34 AC97_Video_Volume_Mute = 0x14,
35 AC97_Aux_Volume_Mute = 0x16,
36 AC97_PCM_Out_Volume_Mute = 0x18,
37 AC97_Record_Select = 0x1A,
38 AC97_Record_Gain_Mute = 0x1C,
39 AC97_Record_Gain_Mic_Mute = 0x1E,
40 AC97_General_Purpose = 0x20,
41 AC97_3D_Control = 0x22,
42 AC97_AC_97_RESERVED = 0x24,
43 AC97_Powerdown_Ctrl_Stat = 0x26,
44 AC97_Extended_Audio_ID = 0x28,
45 AC97_Extended_Audio_Ctrl_Stat = 0x2A,
46 AC97_PCM_Front_DAC_Rate = 0x2C,
47 AC97_PCM_Surround_DAC_Rate = 0x2E,
48 AC97_PCM_LFE_DAC_Rate = 0x30,
49 AC97_PCM_LR_ADC_Rate = 0x32,
50 AC97_MIC_ADC_Rate = 0x34,
51 AC97_6Ch_Vol_C_LFE_Mute = 0x36,
52 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
53 AC97_Vendor_Reserved = 0x58,
54 AC97_Vendor_ID1 = 0x7c,
55 AC97_Vendor_ID2 = 0x7e
56 };
57
58 #define SOFT_VOLUME
59 #define SR_FIFOE 16 /* rwc */
60 #define SR_BCIS 8 /* rwc */
61 #define SR_LVBCI 4 /* rwc */
62 #define SR_CELV 2 /* ro */
63 #define SR_DCH 1 /* ro */
64 #define SR_VALID_MASK ((1 << 5) - 1)
65 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
66 #define SR_RO_MASK (SR_DCH | SR_CELV)
67 #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
68
69 #define CR_IOCE 16 /* rw */
70 #define CR_FEIE 8 /* rw */
71 #define CR_LVBIE 4 /* rw */
72 #define CR_RR 2 /* rw */
73 #define CR_RPBM 1 /* rw */
74 #define CR_VALID_MASK ((1 << 5) - 1)
75 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
76
77 #define GC_WR 4 /* rw */
78 #define GC_CR 2 /* rw */
79 #define GC_VALID_MASK ((1 << 6) - 1)
80
81 #define GS_MD3 (1<<17) /* rw */
82 #define GS_AD3 (1<<16) /* rw */
83 #define GS_RCS (1<<15) /* rwc */
84 #define GS_B3S12 (1<<14) /* ro */
85 #define GS_B2S12 (1<<13) /* ro */
86 #define GS_B1S12 (1<<12) /* ro */
87 #define GS_S1R1 (1<<11) /* rwc */
88 #define GS_S0R1 (1<<10) /* rwc */
89 #define GS_S1CR (1<<9) /* ro */
90 #define GS_S0CR (1<<8) /* ro */
91 #define GS_MINT (1<<7) /* ro */
92 #define GS_POINT (1<<6) /* ro */
93 #define GS_PIINT (1<<5) /* ro */
94 #define GS_RSRVD ((1<<4)|(1<<3))
95 #define GS_MOINT (1<<2) /* ro */
96 #define GS_MIINT (1<<1) /* ro */
97 #define GS_GSCI 1 /* rwc */
98 #define GS_RO_MASK (GS_B3S12| \
99 GS_B2S12| \
100 GS_B1S12| \
101 GS_S1CR| \
102 GS_S0CR| \
103 GS_MINT| \
104 GS_POINT| \
105 GS_PIINT| \
106 GS_RSRVD| \
107 GS_MOINT| \
108 GS_MIINT)
109 #define GS_VALID_MASK ((1 << 18) - 1)
110 #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)
111
112 #define BD_IOC (1<<31)
113 #define BD_BUP (1<<30)
114
115 #define EACS_VRA 1
116 #define EACS_VRM 8
117
118 #define VOL_MASK 0x1f
119 #define MUTE_SHIFT 15
120
121 #define REC_MASK 7
122 enum {
123 REC_MIC = 0,
124 REC_CD,
125 REC_VIDEO,
126 REC_AUX,
127 REC_LINE_IN,
128 REC_STEREO_MIX,
129 REC_MONO_MIX,
130 REC_PHONE
131 };
132
133 typedef struct BD {
134 uint32_t addr;
135 uint32_t ctl_len;
136 } BD;
137
138 typedef struct AC97BusMasterRegs {
139 uint32_t bdbar; /* rw 0 */
140 uint8_t civ; /* ro 0 */
141 uint8_t lvi; /* rw 0 */
142 uint16_t sr; /* rw 1 */
143 uint16_t picb; /* ro 0 */
144 uint8_t piv; /* ro 0 */
145 uint8_t cr; /* rw 0 */
146 unsigned int bd_valid;
147 BD bd;
148 } AC97BusMasterRegs;
149
150 typedef struct AC97LinkState {
151 PCIDevice dev;
152 QEMUSoundCard card;
153 uint32_t glob_cnt;
154 uint32_t glob_sta;
155 uint32_t cas;
156 uint32_t last_samp;
157 AC97BusMasterRegs bm_regs[3];
158 uint8_t mixer_data[256];
159 SWVoiceIn *voice_pi;
160 SWVoiceOut *voice_po;
161 SWVoiceIn *voice_mc;
162 int invalid_freq[3];
163 uint8_t silence[128];
164 int bup_flag;
165 MemoryRegion io_nam;
166 MemoryRegion io_nabm;
167 } AC97LinkState;
168
169 enum {
170 BUP_SET = 1,
171 BUP_LAST = 2
172 };
173
174 #ifdef DEBUG_AC97
175 #define dolog(...) AUD_log ("ac97", __VA_ARGS__)
176 #else
177 #define dolog(...)
178 #endif
179
180 #define MKREGS(prefix, start) \
181 enum { \
182 prefix ## _BDBAR = start, \
183 prefix ## _CIV = start + 4, \
184 prefix ## _LVI = start + 5, \
185 prefix ## _SR = start + 6, \
186 prefix ## _PICB = start + 8, \
187 prefix ## _PIV = start + 10, \
188 prefix ## _CR = start + 11 \
189 }
190
191 enum {
192 PI_INDEX = 0,
193 PO_INDEX,
194 MC_INDEX,
195 LAST_INDEX
196 };
197
198 MKREGS (PI, PI_INDEX * 16);
199 MKREGS (PO, PO_INDEX * 16);
200 MKREGS (MC, MC_INDEX * 16);
201
202 enum {
203 GLOB_CNT = 0x2c,
204 GLOB_STA = 0x30,
205 CAS = 0x34
206 };
207
208 #define GET_BM(index) (((index) >> 4) & 3)
209
210 static void po_callback (void *opaque, int free);
211 static void pi_callback (void *opaque, int avail);
212 static void mc_callback (void *opaque, int avail);
213
214 static void warm_reset (AC97LinkState *s)
215 {
216 (void) s;
217 }
218
219 static void cold_reset (AC97LinkState * s)
220 {
221 (void) s;
222 }
223
224 static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r)
225 {
226 uint8_t b[8];
227
228 pci_dma_read (&s->dev, r->bdbar + r->civ * 8, b, 8);
229 r->bd_valid = 1;
230 r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3;
231 r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]);
232 r->picb = r->bd.ctl_len & 0xffff;
233 dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
234 r->civ, r->bd.addr, r->bd.ctl_len >> 16,
235 r->bd.ctl_len & 0xffff,
236 (r->bd.ctl_len & 0xffff) << 1);
237 }
238
239 static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)
240 {
241 int event = 0;
242 int level = 0;
243 uint32_t new_mask = new_sr & SR_INT_MASK;
244 uint32_t old_mask = r->sr & SR_INT_MASK;
245 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT};
246
247 if (new_mask ^ old_mask) {
248 /** @todo is IRQ deasserted when only one of status bits is cleared? */
249 if (!new_mask) {
250 event = 1;
251 level = 0;
252 }
253 else {
254 if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) {
255 event = 1;
256 level = 1;
257 }
258 if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) {
259 event = 1;
260 level = 1;
261 }
262 }
263 }
264
265 r->sr = new_sr;
266
267 dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n",
268 r->sr & SR_BCIS, r->sr & SR_LVBCI,
269 r->sr,
270 event, level);
271
272 if (!event)
273 return;
274
275 if (level) {
276 s->glob_sta |= masks[r - s->bm_regs];
277 dolog ("set irq level=1\n");
278 qemu_set_irq (s->dev.irq[0], 1);
279 }
280 else {
281 s->glob_sta &= ~masks[r - s->bm_regs];
282 dolog ("set irq level=0\n");
283 qemu_set_irq (s->dev.irq[0], 0);
284 }
285 }
286
287 static void voice_set_active (AC97LinkState *s, int bm_index, int on)
288 {
289 switch (bm_index) {
290 case PI_INDEX:
291 AUD_set_active_in (s->voice_pi, on);
292 break;
293
294 case PO_INDEX:
295 AUD_set_active_out (s->voice_po, on);
296 break;
297
298 case MC_INDEX:
299 AUD_set_active_in (s->voice_mc, on);
300 break;
301
302 default:
303 AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index);
304 break;
305 }
306 }
307
308 static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r)
309 {
310 dolog ("reset_bm_regs\n");
311 r->bdbar = 0;
312 r->civ = 0;
313 r->lvi = 0;
314 /** todo do we need to do that? */
315 update_sr (s, r, SR_DCH);
316 r->picb = 0;
317 r->piv = 0;
318 r->cr = r->cr & CR_DONT_CLEAR_MASK;
319 r->bd_valid = 0;
320
321 voice_set_active (s, r - s->bm_regs, 0);
322 memset (s->silence, 0, sizeof (s->silence));
323 }
324
325 static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v)
326 {
327 if (i + 2 > sizeof (s->mixer_data)) {
328 dolog ("mixer_store: index %d out of bounds %zd\n",
329 i, sizeof (s->mixer_data));
330 return;
331 }
332
333 s->mixer_data[i + 0] = v & 0xff;
334 s->mixer_data[i + 1] = v >> 8;
335 }
336
337 static uint16_t mixer_load (AC97LinkState *s, uint32_t i)
338 {
339 uint16_t val = 0xffff;
340
341 if (i + 2 > sizeof (s->mixer_data)) {
342 dolog ("mixer_store: index %d out of bounds %zd\n",
343 i, sizeof (s->mixer_data));
344 }
345 else {
346 val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8);
347 }
348
349 return val;
350 }
351
352 static void open_voice (AC97LinkState *s, int index, int freq)
353 {
354 struct audsettings as;
355
356 as.freq = freq;
357 as.nchannels = 2;
358 as.fmt = AUD_FMT_S16;
359 as.endianness = 0;
360
361 if (freq > 0) {
362 s->invalid_freq[index] = 0;
363 switch (index) {
364 case PI_INDEX:
365 s->voice_pi = AUD_open_in (
366 &s->card,
367 s->voice_pi,
368 "ac97.pi",
369 s,
370 pi_callback,
371 &as
372 );
373 break;
374
375 case PO_INDEX:
376 s->voice_po = AUD_open_out (
377 &s->card,
378 s->voice_po,
379 "ac97.po",
380 s,
381 po_callback,
382 &as
383 );
384 break;
385
386 case MC_INDEX:
387 s->voice_mc = AUD_open_in (
388 &s->card,
389 s->voice_mc,
390 "ac97.mc",
391 s,
392 mc_callback,
393 &as
394 );
395 break;
396 }
397 }
398 else {
399 s->invalid_freq[index] = freq;
400 switch (index) {
401 case PI_INDEX:
402 AUD_close_in (&s->card, s->voice_pi);
403 s->voice_pi = NULL;
404 break;
405
406 case PO_INDEX:
407 AUD_close_out (&s->card, s->voice_po);
408 s->voice_po = NULL;
409 break;
410
411 case MC_INDEX:
412 AUD_close_in (&s->card, s->voice_mc);
413 s->voice_mc = NULL;
414 break;
415 }
416 }
417 }
418
419 static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX])
420 {
421 uint16_t freq;
422
423 freq = mixer_load (s, AC97_PCM_LR_ADC_Rate);
424 open_voice (s, PI_INDEX, freq);
425 AUD_set_active_in (s->voice_pi, active[PI_INDEX]);
426
427 freq = mixer_load (s, AC97_PCM_Front_DAC_Rate);
428 open_voice (s, PO_INDEX, freq);
429 AUD_set_active_out (s->voice_po, active[PO_INDEX]);
430
431 freq = mixer_load (s, AC97_MIC_ADC_Rate);
432 open_voice (s, MC_INDEX, freq);
433 AUD_set_active_in (s->voice_mc, active[MC_INDEX]);
434 }
435
436 #ifdef USE_MIXER
437 static void set_volume (AC97LinkState *s, int index,
438 audmixerctl_t mt, uint32_t val)
439 {
440 int mute = (val >> MUTE_SHIFT) & 1;
441 uint8_t rvol = VOL_MASK - (val & VOL_MASK);
442 uint8_t lvol = VOL_MASK - ((val >> 8) & VOL_MASK);
443 rvol = 255 * rvol / VOL_MASK;
444 lvol = 255 * lvol / VOL_MASK;
445
446 #ifdef SOFT_VOLUME
447 if (index == AC97_Master_Volume_Mute) {
448 AUD_set_volume_out (s->voice_po, mute, lvol, rvol);
449 }
450 else {
451 AUD_set_volume (mt, &mute, &lvol, &rvol);
452 }
453 #else
454 AUD_set_volume (mt, &mute, &lvol, &rvol);
455 #endif
456
457 rvol = VOL_MASK - ((VOL_MASK * rvol) / 255);
458 lvol = VOL_MASK - ((VOL_MASK * lvol) / 255);
459 mixer_store (s, index, val);
460 }
461
462 static audrecsource_t ac97_to_aud_record_source (uint8_t i)
463 {
464 switch (i) {
465 case REC_MIC:
466 return AUD_REC_MIC;
467
468 case REC_CD:
469 return AUD_REC_CD;
470
471 case REC_VIDEO:
472 return AUD_REC_VIDEO;
473
474 case REC_AUX:
475 return AUD_REC_AUX;
476
477 case REC_LINE_IN:
478 return AUD_REC_LINE_IN;
479
480 case REC_PHONE:
481 return AUD_REC_PHONE;
482
483 default:
484 dolog ("Unknown record source %d, using MIC\n", i);
485 return AUD_REC_MIC;
486 }
487 }
488
489 static uint8_t aud_to_ac97_record_source (audrecsource_t rs)
490 {
491 switch (rs) {
492 case AUD_REC_MIC:
493 return REC_MIC;
494
495 case AUD_REC_CD:
496 return REC_CD;
497
498 case AUD_REC_VIDEO:
499 return REC_VIDEO;
500
501 case AUD_REC_AUX:
502 return REC_AUX;
503
504 case AUD_REC_LINE_IN:
505 return REC_LINE_IN;
506
507 case AUD_REC_PHONE:
508 return REC_PHONE;
509
510 default:
511 dolog ("Unknown audio recording source %d using MIC\n", rs);
512 return REC_MIC;
513 }
514 }
515
516 static void record_select (AC97LinkState *s, uint32_t val)
517 {
518 uint8_t rs = val & REC_MASK;
519 uint8_t ls = (val >> 8) & REC_MASK;
520 audrecsource_t ars = ac97_to_aud_record_source (rs);
521 audrecsource_t als = ac97_to_aud_record_source (ls);
522 AUD_set_record_source (&als, &ars);
523 rs = aud_to_ac97_record_source (ars);
524 ls = aud_to_ac97_record_source (als);
525 mixer_store (s, AC97_Record_Select, rs | (ls << 8));
526 }
527 #endif
528
529 static void mixer_reset (AC97LinkState *s)
530 {
531 uint8_t active[LAST_INDEX];
532
533 dolog ("mixer_reset\n");
534 memset (s->mixer_data, 0, sizeof (s->mixer_data));
535 memset (active, 0, sizeof (active));
536 mixer_store (s, AC97_Reset , 0x0000); /* 6940 */
537 mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x8000);
538 mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000);
539
540 mixer_store (s, AC97_Phone_Volume_Mute , 0x8008);
541 mixer_store (s, AC97_Mic_Volume_Mute , 0x8008);
542 mixer_store (s, AC97_CD_Volume_Mute , 0x8808);
543 mixer_store (s, AC97_Aux_Volume_Mute , 0x8808);
544 mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x8000);
545 mixer_store (s, AC97_General_Purpose , 0x0000);
546 mixer_store (s, AC97_3D_Control , 0x0000);
547 mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f);
548
549 /*
550 * Sigmatel 9700 (STAC9700)
551 */
552 mixer_store (s, AC97_Vendor_ID1 , 0x8384);
553 mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */
554
555 mixer_store (s, AC97_Extended_Audio_ID , 0x0809);
556 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
557 mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80);
558 mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80);
559 mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80);
560 mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80);
561 mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80);
562
563 #ifdef USE_MIXER
564 record_select (s, 0);
565 set_volume (s, AC97_Master_Volume_Mute, AUD_MIXER_VOLUME , 0x8000);
566 set_volume (s, AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM , 0x8808);
567 set_volume (s, AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN, 0x8808);
568 #endif
569 reset_voices (s, active);
570 }
571
572 /**
573 * Native audio mixer
574 * I/O Reads
575 */
576 static uint32_t nam_readb (void *opaque, uint32_t addr)
577 {
578 AC97LinkState *s = opaque;
579 dolog ("U nam readb %#x\n", addr);
580 s->cas = 0;
581 return ~0U;
582 }
583
584 static uint32_t nam_readw (void *opaque, uint32_t addr)
585 {
586 AC97LinkState *s = opaque;
587 uint32_t val = ~0U;
588 uint32_t index = addr;
589 s->cas = 0;
590 val = mixer_load (s, index);
591 return val;
592 }
593
594 static uint32_t nam_readl (void *opaque, uint32_t addr)
595 {
596 AC97LinkState *s = opaque;
597 dolog ("U nam readl %#x\n", addr);
598 s->cas = 0;
599 return ~0U;
600 }
601
602 /**
603 * Native audio mixer
604 * I/O Writes
605 */
606 static void nam_writeb (void *opaque, uint32_t addr, uint32_t val)
607 {
608 AC97LinkState *s = opaque;
609 dolog ("U nam writeb %#x <- %#x\n", addr, val);
610 s->cas = 0;
611 }
612
613 static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
614 {
615 AC97LinkState *s = opaque;
616 uint32_t index = addr;
617 s->cas = 0;
618 switch (index) {
619 case AC97_Reset:
620 mixer_reset (s);
621 break;
622 case AC97_Powerdown_Ctrl_Stat:
623 val &= ~0xf;
624 val |= mixer_load (s, index) & 0xf;
625 mixer_store (s, index, val);
626 break;
627 #ifdef USE_MIXER
628 case AC97_Master_Volume_Mute:
629 set_volume (s, index, AUD_MIXER_VOLUME, val);
630 break;
631 case AC97_PCM_Out_Volume_Mute:
632 set_volume (s, index, AUD_MIXER_PCM, val);
633 break;
634 case AC97_Line_In_Volume_Mute:
635 set_volume (s, index, AUD_MIXER_LINE_IN, val);
636 break;
637 case AC97_Record_Select:
638 record_select (s, val);
639 break;
640 #endif
641 case AC97_Vendor_ID1:
642 case AC97_Vendor_ID2:
643 dolog ("Attempt to write vendor ID to %#x\n", val);
644 break;
645 case AC97_Extended_Audio_ID:
646 dolog ("Attempt to write extended audio ID to %#x\n", val);
647 break;
648 case AC97_Extended_Audio_Ctrl_Stat:
649 if (!(val & EACS_VRA)) {
650 mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80);
651 mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80);
652 open_voice (s, PI_INDEX, 48000);
653 open_voice (s, PO_INDEX, 48000);
654 }
655 if (!(val & EACS_VRM)) {
656 mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80);
657 open_voice (s, MC_INDEX, 48000);
658 }
659 dolog ("Setting extended audio control to %#x\n", val);
660 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val);
661 break;
662 case AC97_PCM_Front_DAC_Rate:
663 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
664 mixer_store (s, index, val);
665 dolog ("Set front DAC rate to %d\n", val);
666 open_voice (s, PO_INDEX, val);
667 }
668 else {
669 dolog ("Attempt to set front DAC rate to %d, "
670 "but VRA is not set\n",
671 val);
672 }
673 break;
674 case AC97_MIC_ADC_Rate:
675 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) {
676 mixer_store (s, index, val);
677 dolog ("Set MIC ADC rate to %d\n", val);
678 open_voice (s, MC_INDEX, val);
679 }
680 else {
681 dolog ("Attempt to set MIC ADC rate to %d, "
682 "but VRM is not set\n",
683 val);
684 }
685 break;
686 case AC97_PCM_LR_ADC_Rate:
687 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
688 mixer_store (s, index, val);
689 dolog ("Set front LR ADC rate to %d\n", val);
690 open_voice (s, PI_INDEX, val);
691 }
692 else {
693 dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n",
694 val);
695 }
696 break;
697 default:
698 dolog ("U nam writew %#x <- %#x\n", addr, val);
699 mixer_store (s, index, val);
700 break;
701 }
702 }
703
704 static void nam_writel (void *opaque, uint32_t addr, uint32_t val)
705 {
706 AC97LinkState *s = opaque;
707 dolog ("U nam writel %#x <- %#x\n", addr, val);
708 s->cas = 0;
709 }
710
711 /**
712 * Native audio bus master
713 * I/O Reads
714 */
715 static uint32_t nabm_readb (void *opaque, uint32_t addr)
716 {
717 AC97LinkState *s = opaque;
718 AC97BusMasterRegs *r = NULL;
719 uint32_t index = addr;
720 uint32_t val = ~0U;
721
722 switch (index) {
723 case CAS:
724 dolog ("CAS %d\n", s->cas);
725 val = s->cas;
726 s->cas = 1;
727 break;
728 case PI_CIV:
729 case PO_CIV:
730 case MC_CIV:
731 r = &s->bm_regs[GET_BM (index)];
732 val = r->civ;
733 dolog ("CIV[%d] -> %#x\n", GET_BM (index), val);
734 break;
735 case PI_LVI:
736 case PO_LVI:
737 case MC_LVI:
738 r = &s->bm_regs[GET_BM (index)];
739 val = r->lvi;
740 dolog ("LVI[%d] -> %#x\n", GET_BM (index), val);
741 break;
742 case PI_PIV:
743 case PO_PIV:
744 case MC_PIV:
745 r = &s->bm_regs[GET_BM (index)];
746 val = r->piv;
747 dolog ("PIV[%d] -> %#x\n", GET_BM (index), val);
748 break;
749 case PI_CR:
750 case PO_CR:
751 case MC_CR:
752 r = &s->bm_regs[GET_BM (index)];
753 val = r->cr;
754 dolog ("CR[%d] -> %#x\n", GET_BM (index), val);
755 break;
756 case PI_SR:
757 case PO_SR:
758 case MC_SR:
759 r = &s->bm_regs[GET_BM (index)];
760 val = r->sr & 0xff;
761 dolog ("SRb[%d] -> %#x\n", GET_BM (index), val);
762 break;
763 default:
764 dolog ("U nabm readb %#x -> %#x\n", addr, val);
765 break;
766 }
767 return val;
768 }
769
770 static uint32_t nabm_readw (void *opaque, uint32_t addr)
771 {
772 AC97LinkState *s = opaque;
773 AC97BusMasterRegs *r = NULL;
774 uint32_t index = addr;
775 uint32_t val = ~0U;
776
777 switch (index) {
778 case PI_SR:
779 case PO_SR:
780 case MC_SR:
781 r = &s->bm_regs[GET_BM (index)];
782 val = r->sr;
783 dolog ("SR[%d] -> %#x\n", GET_BM (index), val);
784 break;
785 case PI_PICB:
786 case PO_PICB:
787 case MC_PICB:
788 r = &s->bm_regs[GET_BM (index)];
789 val = r->picb;
790 dolog ("PICB[%d] -> %#x\n", GET_BM (index), val);
791 break;
792 default:
793 dolog ("U nabm readw %#x -> %#x\n", addr, val);
794 break;
795 }
796 return val;
797 }
798
799 static uint32_t nabm_readl (void *opaque, uint32_t addr)
800 {
801 AC97LinkState *s = opaque;
802 AC97BusMasterRegs *r = NULL;
803 uint32_t index = addr;
804 uint32_t val = ~0U;
805
806 switch (index) {
807 case PI_BDBAR:
808 case PO_BDBAR:
809 case MC_BDBAR:
810 r = &s->bm_regs[GET_BM (index)];
811 val = r->bdbar;
812 dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val);
813 break;
814 case PI_CIV:
815 case PO_CIV:
816 case MC_CIV:
817 r = &s->bm_regs[GET_BM (index)];
818 val = r->civ | (r->lvi << 8) | (r->sr << 16);
819 dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index),
820 r->civ, r->lvi, r->sr);
821 break;
822 case PI_PICB:
823 case PO_PICB:
824 case MC_PICB:
825 r = &s->bm_regs[GET_BM (index)];
826 val = r->picb | (r->piv << 16) | (r->cr << 24);
827 dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index),
828 val, r->picb, r->piv, r->cr);
829 break;
830 case GLOB_CNT:
831 val = s->glob_cnt;
832 dolog ("glob_cnt -> %#x\n", val);
833 break;
834 case GLOB_STA:
835 val = s->glob_sta | GS_S0CR;
836 dolog ("glob_sta -> %#x\n", val);
837 break;
838 default:
839 dolog ("U nabm readl %#x -> %#x\n", addr, val);
840 break;
841 }
842 return val;
843 }
844
845 /**
846 * Native audio bus master
847 * I/O Writes
848 */
849 static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val)
850 {
851 AC97LinkState *s = opaque;
852 AC97BusMasterRegs *r = NULL;
853 uint32_t index = addr;
854 switch (index) {
855 case PI_LVI:
856 case PO_LVI:
857 case MC_LVI:
858 r = &s->bm_regs[GET_BM (index)];
859 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) {
860 r->sr &= ~(SR_DCH | SR_CELV);
861 r->civ = r->piv;
862 r->piv = (r->piv + 1) % 32;
863 fetch_bd (s, r);
864 }
865 r->lvi = val % 32;
866 dolog ("LVI[%d] <- %#x\n", GET_BM (index), val);
867 break;
868 case PI_CR:
869 case PO_CR:
870 case MC_CR:
871 r = &s->bm_regs[GET_BM (index)];
872 if (val & CR_RR) {
873 reset_bm_regs (s, r);
874 }
875 else {
876 r->cr = val & CR_VALID_MASK;
877 if (!(r->cr & CR_RPBM)) {
878 voice_set_active (s, r - s->bm_regs, 0);
879 r->sr |= SR_DCH;
880 }
881 else {
882 r->civ = r->piv;
883 r->piv = (r->piv + 1) % 32;
884 fetch_bd (s, r);
885 r->sr &= ~SR_DCH;
886 voice_set_active (s, r - s->bm_regs, 1);
887 }
888 }
889 dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr);
890 break;
891 case PI_SR:
892 case PO_SR:
893 case MC_SR:
894 r = &s->bm_regs[GET_BM (index)];
895 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
896 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
897 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
898 break;
899 default:
900 dolog ("U nabm writeb %#x <- %#x\n", addr, val);
901 break;
902 }
903 }
904
905 static void nabm_writew (void *opaque, uint32_t addr, uint32_t val)
906 {
907 AC97LinkState *s = opaque;
908 AC97BusMasterRegs *r = NULL;
909 uint32_t index = addr;
910 switch (index) {
911 case PI_SR:
912 case PO_SR:
913 case MC_SR:
914 r = &s->bm_regs[GET_BM (index)];
915 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
916 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
917 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
918 break;
919 default:
920 dolog ("U nabm writew %#x <- %#x\n", addr, val);
921 break;
922 }
923 }
924
925 static void nabm_writel (void *opaque, uint32_t addr, uint32_t val)
926 {
927 AC97LinkState *s = opaque;
928 AC97BusMasterRegs *r = NULL;
929 uint32_t index = addr;
930 switch (index) {
931 case PI_BDBAR:
932 case PO_BDBAR:
933 case MC_BDBAR:
934 r = &s->bm_regs[GET_BM (index)];
935 r->bdbar = val & ~3;
936 dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n",
937 GET_BM (index), val, r->bdbar);
938 break;
939 case GLOB_CNT:
940 if (val & GC_WR)
941 warm_reset (s);
942 if (val & GC_CR)
943 cold_reset (s);
944 if (!(val & (GC_WR | GC_CR)))
945 s->glob_cnt = val & GC_VALID_MASK;
946 dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt);
947 break;
948 case GLOB_STA:
949 s->glob_sta &= ~(val & GS_WCLEAR_MASK);
950 s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;
951 dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta);
952 break;
953 default:
954 dolog ("U nabm writel %#x <- %#x\n", addr, val);
955 break;
956 }
957 }
958
959 static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r,
960 int max, int *stop)
961 {
962 uint8_t tmpbuf[4096];
963 uint32_t addr = r->bd.addr;
964 uint32_t temp = r->picb << 1;
965 uint32_t written = 0;
966 int to_copy = 0;
967 temp = audio_MIN (temp, max);
968
969 if (!temp) {
970 *stop = 1;
971 return 0;
972 }
973
974 while (temp) {
975 int copied;
976 to_copy = audio_MIN (temp, sizeof (tmpbuf));
977 pci_dma_read (&s->dev, addr, tmpbuf, to_copy);
978 copied = AUD_write (s->voice_po, tmpbuf, to_copy);
979 dolog ("write_audio max=%x to_copy=%x copied=%x\n",
980 max, to_copy, copied);
981 if (!copied) {
982 *stop = 1;
983 break;
984 }
985 temp -= copied;
986 addr += copied;
987 written += copied;
988 }
989
990 if (!temp) {
991 if (to_copy < 4) {
992 dolog ("whoops\n");
993 s->last_samp = 0;
994 }
995 else {
996 s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4];
997 }
998 }
999
1000 r->bd.addr = addr;
1001 return written;
1002 }
1003
1004 static void write_bup (AC97LinkState *s, int elapsed)
1005 {
1006 dolog ("write_bup\n");
1007 if (!(s->bup_flag & BUP_SET)) {
1008 if (s->bup_flag & BUP_LAST) {
1009 int i;
1010 uint8_t *p = s->silence;
1011 for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) {
1012 *(uint32_t *) p = s->last_samp;
1013 }
1014 }
1015 else {
1016 memset (s->silence, 0, sizeof (s->silence));
1017 }
1018 s->bup_flag |= BUP_SET;
1019 }
1020
1021 while (elapsed) {
1022 int temp = audio_MIN (elapsed, sizeof (s->silence));
1023 while (temp) {
1024 int copied = AUD_write (s->voice_po, s->silence, temp);
1025 if (!copied)
1026 return;
1027 temp -= copied;
1028 elapsed -= copied;
1029 }
1030 }
1031 }
1032
1033 static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r,
1034 int max, int *stop)
1035 {
1036 uint8_t tmpbuf[4096];
1037 uint32_t addr = r->bd.addr;
1038 uint32_t temp = r->picb << 1;
1039 uint32_t nread = 0;
1040 int to_copy = 0;
1041 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi;
1042
1043 temp = audio_MIN (temp, max);
1044
1045 if (!temp) {
1046 *stop = 1;
1047 return 0;
1048 }
1049
1050 while (temp) {
1051 int acquired;
1052 to_copy = audio_MIN (temp, sizeof (tmpbuf));
1053 acquired = AUD_read (voice, tmpbuf, to_copy);
1054 if (!acquired) {
1055 *stop = 1;
1056 break;
1057 }
1058 pci_dma_write (&s->dev, addr, tmpbuf, acquired);
1059 temp -= acquired;
1060 addr += acquired;
1061 nread += acquired;
1062 }
1063
1064 r->bd.addr = addr;
1065 return nread;
1066 }
1067
1068 static void transfer_audio (AC97LinkState *s, int index, int elapsed)
1069 {
1070 AC97BusMasterRegs *r = &s->bm_regs[index];
1071 int stop = 0;
1072
1073 if (s->invalid_freq[index]) {
1074 AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n",
1075 index, s->invalid_freq[index]);
1076 return;
1077 }
1078
1079 if (r->sr & SR_DCH) {
1080 if (r->cr & CR_RPBM) {
1081 switch (index) {
1082 case PO_INDEX:
1083 write_bup (s, elapsed);
1084 break;
1085 }
1086 }
1087 return;
1088 }
1089
1090 while ((elapsed >> 1) && !stop) {
1091 int temp;
1092
1093 if (!r->bd_valid) {
1094 dolog ("invalid bd\n");
1095 fetch_bd (s, r);
1096 }
1097
1098 if (!r->picb) {
1099 dolog ("fresh bd %d is empty %#x %#x\n",
1100 r->civ, r->bd.addr, r->bd.ctl_len);
1101 if (r->civ == r->lvi) {
1102 r->sr |= SR_DCH; /* CELV? */
1103 s->bup_flag = 0;
1104 break;
1105 }
1106 r->sr &= ~SR_CELV;
1107 r->civ = r->piv;
1108 r->piv = (r->piv + 1) % 32;
1109 fetch_bd (s, r);
1110 return;
1111 }
1112
1113 switch (index) {
1114 case PO_INDEX:
1115 temp = write_audio (s, r, elapsed, &stop);
1116 elapsed -= temp;
1117 r->picb -= (temp >> 1);
1118 break;
1119
1120 case PI_INDEX:
1121 case MC_INDEX:
1122 temp = read_audio (s, r, elapsed, &stop);
1123 elapsed -= temp;
1124 r->picb -= (temp >> 1);
1125 break;
1126 }
1127
1128 if (!r->picb) {
1129 uint32_t new_sr = r->sr & ~SR_CELV;
1130
1131 if (r->bd.ctl_len & BD_IOC) {
1132 new_sr |= SR_BCIS;
1133 }
1134
1135 if (r->civ == r->lvi) {
1136 dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi);
1137
1138 new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
1139 stop = 1;
1140 s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
1141 }
1142 else {
1143 r->civ = r->piv;
1144 r->piv = (r->piv + 1) % 32;
1145 fetch_bd (s, r);
1146 }
1147
1148 update_sr (s, r, new_sr);
1149 }
1150 }
1151 }
1152
1153 static void pi_callback (void *opaque, int avail)
1154 {
1155 transfer_audio (opaque, PI_INDEX, avail);
1156 }
1157
1158 static void mc_callback (void *opaque, int avail)
1159 {
1160 transfer_audio (opaque, MC_INDEX, avail);
1161 }
1162
1163 static void po_callback (void *opaque, int free)
1164 {
1165 transfer_audio (opaque, PO_INDEX, free);
1166 }
1167
1168 static const VMStateDescription vmstate_ac97_bm_regs = {
1169 .name = "ac97_bm_regs",
1170 .version_id = 1,
1171 .minimum_version_id = 1,
1172 .minimum_version_id_old = 1,
1173 .fields = (VMStateField []) {
1174 VMSTATE_UINT32(bdbar, AC97BusMasterRegs),
1175 VMSTATE_UINT8(civ, AC97BusMasterRegs),
1176 VMSTATE_UINT8(lvi, AC97BusMasterRegs),
1177 VMSTATE_UINT16(sr, AC97BusMasterRegs),
1178 VMSTATE_UINT16(picb, AC97BusMasterRegs),
1179 VMSTATE_UINT8(piv, AC97BusMasterRegs),
1180 VMSTATE_UINT8(cr, AC97BusMasterRegs),
1181 VMSTATE_UINT32(bd_valid, AC97BusMasterRegs),
1182 VMSTATE_UINT32(bd.addr, AC97BusMasterRegs),
1183 VMSTATE_UINT32(bd.ctl_len, AC97BusMasterRegs),
1184 VMSTATE_END_OF_LIST()
1185 }
1186 };
1187
1188 static int ac97_post_load (void *opaque, int version_id)
1189 {
1190 uint8_t active[LAST_INDEX];
1191 AC97LinkState *s = opaque;
1192
1193 #ifdef USE_MIXER
1194 record_select (s, mixer_load (s, AC97_Record_Select));
1195 #define V_(a, b) set_volume (s, a, b, mixer_load (s, a))
1196 V_ (AC97_Master_Volume_Mute, AUD_MIXER_VOLUME);
1197 V_ (AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM);
1198 V_ (AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN);
1199 #undef V_
1200 #endif
1201 active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM);
1202 active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM);
1203 active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM);
1204 reset_voices (s, active);
1205
1206 s->bup_flag = 0;
1207 s->last_samp = 0;
1208 return 0;
1209 }
1210
1211 static bool is_version_2 (void *opaque, int version_id)
1212 {
1213 return version_id == 2;
1214 }
1215
1216 static const VMStateDescription vmstate_ac97 = {
1217 .name = "ac97",
1218 .version_id = 3,
1219 .minimum_version_id = 2,
1220 .minimum_version_id_old = 2,
1221 .post_load = ac97_post_load,
1222 .fields = (VMStateField []) {
1223 VMSTATE_PCI_DEVICE(dev, AC97LinkState),
1224 VMSTATE_UINT32(glob_cnt, AC97LinkState),
1225 VMSTATE_UINT32(glob_sta, AC97LinkState),
1226 VMSTATE_UINT32(cas, AC97LinkState),
1227 VMSTATE_STRUCT_ARRAY(bm_regs, AC97LinkState, 3, 1,
1228 vmstate_ac97_bm_regs, AC97BusMasterRegs),
1229 VMSTATE_BUFFER(mixer_data, AC97LinkState),
1230 VMSTATE_UNUSED_TEST(is_version_2, 3),
1231 VMSTATE_END_OF_LIST()
1232 }
1233 };
1234
1235 static const MemoryRegionPortio nam_portio[] = {
1236 { 0, 256 * 1, 1, .read = nam_readb, },
1237 { 0, 256 * 2, 2, .read = nam_readw, },
1238 { 0, 256 * 4, 4, .read = nam_readl, },
1239 { 0, 256 * 1, 1, .write = nam_writeb, },
1240 { 0, 256 * 2, 2, .write = nam_writew, },
1241 { 0, 256 * 4, 4, .write = nam_writel, },
1242 PORTIO_END_OF_LIST(),
1243 };
1244
1245 static const MemoryRegionOps ac97_io_nam_ops = {
1246 .old_portio = nam_portio,
1247 };
1248
1249 static const MemoryRegionPortio nabm_portio[] = {
1250 { 0, 64 * 1, 1, .read = nabm_readb, },
1251 { 0, 64 * 2, 2, .read = nabm_readw, },
1252 { 0, 64 * 4, 4, .read = nabm_readl, },
1253 { 0, 64 * 1, 1, .write = nabm_writeb, },
1254 { 0, 64 * 2, 2, .write = nabm_writew, },
1255 { 0, 64 * 4, 4, .write = nabm_writel, },
1256 PORTIO_END_OF_LIST()
1257 };
1258
1259 static const MemoryRegionOps ac97_io_nabm_ops = {
1260 .old_portio = nabm_portio,
1261 };
1262
1263 static void ac97_on_reset (void *opaque)
1264 {
1265 AC97LinkState *s = opaque;
1266
1267 reset_bm_regs (s, &s->bm_regs[0]);
1268 reset_bm_regs (s, &s->bm_regs[1]);
1269 reset_bm_regs (s, &s->bm_regs[2]);
1270
1271 /*
1272 * Reset the mixer too. The Windows XP driver seems to rely on
1273 * this. At least it wants to read the vendor id before it resets
1274 * the codec manually.
1275 */
1276 mixer_reset (s);
1277 }
1278
1279 static int ac97_initfn (PCIDevice *dev)
1280 {
1281 AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
1282 uint8_t *c = s->dev.config;
1283
1284 /* TODO: no need to override */
1285 c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */
1286 c[PCI_COMMAND + 1] = 0x00;
1287
1288 /* TODO: */
1289 c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
1290 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
1291
1292 c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
1293
1294 /* TODO set when bar is registered. no need to override. */
1295 /* nabmar native audio mixer base address rw */
1296 c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
1297 c[PCI_BASE_ADDRESS_0 + 1] = 0x00;
1298 c[PCI_BASE_ADDRESS_0 + 2] = 0x00;
1299 c[PCI_BASE_ADDRESS_0 + 3] = 0x00;
1300
1301 /* TODO set when bar is registered. no need to override. */
1302 /* nabmbar native audio bus mastering base address rw */
1303 c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO;
1304 c[PCI_BASE_ADDRESS_0 + 5] = 0x00;
1305 c[PCI_BASE_ADDRESS_0 + 6] = 0x00;
1306 c[PCI_BASE_ADDRESS_0 + 7] = 0x00;
1307
1308 c[PCI_SUBSYSTEM_VENDOR_ID] = 0x86; /* svid subsystem vendor id rwo */
1309 c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x80;
1310
1311 c[PCI_SUBSYSTEM_ID] = 0x00; /* sid subsystem id rwo */
1312 c[PCI_SUBSYSTEM_ID + 1] = 0x00;
1313
1314 c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */
1315 c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
1316
1317 memory_region_init_io (&s->io_nam, &ac97_io_nam_ops, s, "ac97-nam", 1024);
1318 memory_region_init_io (&s->io_nabm, &ac97_io_nabm_ops, s, "ac97-nabm", 256);
1319 pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
1320 pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
1321 qemu_register_reset (ac97_on_reset, s);
1322 AUD_register_card ("ac97", &s->card);
1323 ac97_on_reset (s);
1324 return 0;
1325 }
1326
1327 static int ac97_exitfn (PCIDevice *dev)
1328 {
1329 AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
1330
1331 memory_region_destroy (&s->io_nam);
1332 memory_region_destroy (&s->io_nabm);
1333 return 0;
1334 }
1335
1336 int ac97_init (PCIBus *bus)
1337 {
1338 pci_create_simple (bus, -1, "AC97");
1339 return 0;
1340 }
1341
1342 static PCIDeviceInfo ac97_info = {
1343 .qdev.name = "AC97",
1344 .qdev.desc = "Intel 82801AA AC97 Audio",
1345 .qdev.size = sizeof (AC97LinkState),
1346 .qdev.vmsd = &vmstate_ac97,
1347 .init = ac97_initfn,
1348 .exit = ac97_exitfn,
1349 .vendor_id = PCI_VENDOR_ID_INTEL,
1350 .device_id = PCI_DEVICE_ID_INTEL_82801AA_5,
1351 .revision = 0x01,
1352 .class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
1353 };
1354
1355 static void ac97_register (void)
1356 {
1357 pci_qdev_register (&ac97_info);
1358 }
1359 device_init (ac97_register);
1360
AR7 emulation for QEMU