2 * Nokia N-series internet tablets.
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu-common.h"
36 #include "exec-memory.h"
38 /* Nokia N8x0 support */
40 struct omap_mpu_state_s
*cpu
;
42 struct rfbi_chip_s blizzard
;
45 uint32_t (*txrx
)(void *opaque
, uint32_t value
, int len
);
59 #define N8X0_TUSB_ENABLE_GPIO 0
60 #define N800_MMC2_WP_GPIO 8
61 #define N800_UNKNOWN_GPIO0 9 /* out */
62 #define N810_MMC2_VIOSD_GPIO 9
63 #define N810_HEADSET_AMP_GPIO 10
64 #define N800_CAM_TURN_GPIO 12
65 #define N810_GPS_RESET_GPIO 12
66 #define N800_BLIZZARD_POWERDOWN_GPIO 15
67 #define N800_MMC1_WP_GPIO 23
68 #define N810_MMC2_VSD_GPIO 23
69 #define N8X0_ONENAND_GPIO 26
70 #define N810_BLIZZARD_RESET_GPIO 30
71 #define N800_UNKNOWN_GPIO2 53 /* out */
72 #define N8X0_TUSB_INT_GPIO 58
73 #define N8X0_BT_WKUP_GPIO 61
74 #define N8X0_STI_GPIO 62
75 #define N8X0_CBUS_SEL_GPIO 64
76 #define N8X0_CBUS_DAT_GPIO 65
77 #define N8X0_CBUS_CLK_GPIO 66
78 #define N8X0_WLAN_IRQ_GPIO 87
79 #define N8X0_BT_RESET_GPIO 92
80 #define N8X0_TEA5761_CS_GPIO 93
81 #define N800_UNKNOWN_GPIO 94
82 #define N810_TSC_RESET_GPIO 94
83 #define N800_CAM_ACT_GPIO 95
84 #define N810_GPS_WAKEUP_GPIO 95
85 #define N8X0_MMC_CS_GPIO 96
86 #define N8X0_WLAN_PWR_GPIO 97
87 #define N8X0_BT_HOST_WKUP_GPIO 98
88 #define N810_SPEAKER_AMP_GPIO 101
89 #define N810_KB_LOCK_GPIO 102
90 #define N800_TSC_TS_GPIO 103
91 #define N810_TSC_TS_GPIO 106
92 #define N8X0_HEADPHONE_GPIO 107
93 #define N8X0_RETU_GPIO 108
94 #define N800_TSC_KP_IRQ_GPIO 109
95 #define N810_KEYBOARD_GPIO 109
96 #define N800_BAT_COVER_GPIO 110
97 #define N810_SLIDE_GPIO 110
98 #define N8X0_TAHVO_GPIO 111
99 #define N800_UNKNOWN_GPIO4 112 /* out */
100 #define N810_SLEEPX_LED_GPIO 112
101 #define N800_TSC_RESET_GPIO 118 /* ? */
102 #define N810_AIC33_RESET_GPIO 118
103 #define N800_TSC_UNKNOWN_GPIO 119 /* out */
104 #define N8X0_TMP105_GPIO 125
108 #define XLDR_LL_UART 1
110 /* Addresses on the I2C bus 0 */
111 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
112 #define N8X0_TCM825x_ADDR 0x29 /* Camera */
113 #define N810_LP5521_ADDR 0x32 /* LEDs */
114 #define N810_TSL2563_ADDR 0x3d /* Light sensor */
115 #define N810_LM8323_ADDR 0x45 /* Keyboard */
116 /* Addresses on the I2C bus 1 */
117 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
118 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */
120 /* Chipselects on GPMC NOR interface */
121 #define N8X0_ONENAND_CS 0
122 #define N8X0_USB_ASYNC_CS 1
123 #define N8X0_USB_SYNC_CS 4
125 #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
127 static void n800_mmc_cs_cb(void *opaque
, int line
, int level
)
129 /* TODO: this seems to actually be connected to the menelaus, to
130 * which also both MMC slots connect. */
131 omap_mmc_enable((struct omap_mmc_s
*) opaque
, !level
);
133 printf("%s: MMC slot %i active\n", __FUNCTION__
, level
+ 1);
136 static void n8x0_gpio_setup(struct n800_s
*s
)
138 qemu_irq
*mmc_cs
= qemu_allocate_irqs(n800_mmc_cs_cb
, s
->cpu
->mmc
, 1);
139 qdev_connect_gpio_out(s
->cpu
->gpio
, N8X0_MMC_CS_GPIO
, mmc_cs
[0]);
141 qemu_irq_lower(qdev_get_gpio_in(s
->cpu
->gpio
, N800_BAT_COVER_GPIO
));
144 #define MAEMO_CAL_HEADER(...) \
145 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
149 static const uint8_t n8x0_cal_wlan_mac
[] = {
150 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
151 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
152 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
153 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
154 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
155 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
158 static const uint8_t n8x0_cal_bt_id
[] = {
159 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
160 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
161 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
165 static void n8x0_nand_setup(struct n800_s
*s
)
170 s
->nand
= qdev_create(NULL
, "onenand");
171 qdev_prop_set_uint16(s
->nand
, "manufacturer_id", NAND_MFR_SAMSUNG
);
172 /* Either 0x40 or 0x48 are OK for the device ID */
173 qdev_prop_set_uint16(s
->nand
, "device_id", 0x48);
174 qdev_prop_set_uint16(s
->nand
, "version_id", 0);
175 qdev_prop_set_int32(s
->nand
, "shift", 1);
176 dinfo
= drive_get(IF_MTD
, 0, 0);
177 if (dinfo
&& dinfo
->bdrv
) {
178 qdev_prop_set_drive_nofail(s
->nand
, "drive", dinfo
->bdrv
);
180 qdev_init_nofail(s
->nand
);
181 sysbus_connect_irq(sysbus_from_qdev(s
->nand
), 0,
182 qdev_get_gpio_in(s
->cpu
->gpio
, N8X0_ONENAND_GPIO
));
183 omap_gpmc_attach(s
->cpu
->gpmc
, N8X0_ONENAND_CS
,
184 sysbus_mmio_get_region(sysbus_from_qdev(s
->nand
), 0));
185 otp_region
= onenand_raw_otp(s
->nand
);
187 memcpy(otp_region
+ 0x000, n8x0_cal_wlan_mac
, sizeof(n8x0_cal_wlan_mac
));
188 memcpy(otp_region
+ 0x800, n8x0_cal_bt_id
, sizeof(n8x0_cal_bt_id
));
189 /* XXX: in theory should also update the OOB for both pages */
192 static void n8x0_i2c_setup(struct n800_s
*s
)
195 qemu_irq tmp_irq
= qdev_get_gpio_in(s
->cpu
->gpio
, N8X0_TMP105_GPIO
);
196 i2c_bus
*i2c
= omap_i2c_bus(s
->cpu
->i2c
[0]);
198 /* Attach a menelaus PM chip */
199 dev
= i2c_create_slave(i2c
, "twl92230", N8X0_MENELAUS_ADDR
);
200 qdev_connect_gpio_out(dev
, 3,
201 qdev_get_gpio_in(s
->cpu
->ih
[0],
202 OMAP_INT_24XX_SYS_NIRQ
));
204 qemu_system_powerdown
= qdev_get_gpio_in(dev
, 3);
206 /* Attach a TMP105 PM chip (A0 wired to ground) */
207 dev
= i2c_create_slave(i2c
, "tmp105", N8X0_TMP105_ADDR
);
208 qdev_connect_gpio_out(dev
, 0, tmp_irq
);
211 /* Touchscreen and keypad controller */
212 static MouseTransformInfo n800_pointercal
= {
215 .a
= { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
218 static MouseTransformInfo n810_pointercal
= {
221 .a
= { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
224 #define RETU_KEYCODE 61 /* F3 */
226 static void n800_key_event(void *opaque
, int keycode
)
228 struct n800_s
*s
= (struct n800_s
*) opaque
;
229 int code
= s
->keymap
[keycode
& 0x7f];
232 if ((keycode
& 0x7f) == RETU_KEYCODE
)
233 retu_key_event(s
->retu
, !(keycode
& 0x80));
237 tsc210x_key_event(s
->ts
.chip
, code
, !(keycode
& 0x80));
240 static const int n800_keys
[16] = {
254 64, /* FullScreen (F6) */
259 static void n800_tsc_kbd_setup(struct n800_s
*s
)
263 /* XXX: are the three pins inverted inside the chip between the
264 * tsc and the cpu (N4111)? */
265 qemu_irq penirq
= NULL
; /* NC */
266 qemu_irq kbirq
= qdev_get_gpio_in(s
->cpu
->gpio
, N800_TSC_KP_IRQ_GPIO
);
267 qemu_irq dav
= qdev_get_gpio_in(s
->cpu
->gpio
, N800_TSC_TS_GPIO
);
269 s
->ts
.chip
= tsc2301_init(penirq
, kbirq
, dav
);
270 s
->ts
.opaque
= s
->ts
.chip
->opaque
;
271 s
->ts
.txrx
= tsc210x_txrx
;
273 for (i
= 0; i
< 0x80; i
++)
275 for (i
= 0; i
< 0x10; i
++)
276 if (n800_keys
[i
] >= 0)
277 s
->keymap
[n800_keys
[i
]] = i
;
279 qemu_add_kbd_event_handler(n800_key_event
, s
);
281 tsc210x_set_transform(s
->ts
.chip
, &n800_pointercal
);
284 static void n810_tsc_setup(struct n800_s
*s
)
286 qemu_irq pintdav
= qdev_get_gpio_in(s
->cpu
->gpio
, N810_TSC_TS_GPIO
);
288 s
->ts
.opaque
= tsc2005_init(pintdav
);
289 s
->ts
.txrx
= tsc2005_txrx
;
291 tsc2005_set_transform(s
->ts
.opaque
, &n810_pointercal
);
294 /* N810 Keyboard controller */
295 static void n810_key_event(void *opaque
, int keycode
)
297 struct n800_s
*s
= (struct n800_s
*) opaque
;
298 int code
= s
->keymap
[keycode
& 0x7f];
301 if ((keycode
& 0x7f) == RETU_KEYCODE
)
302 retu_key_event(s
->retu
, !(keycode
& 0x80));
306 lm832x_key_event(s
->kbd
, code
, !(keycode
& 0x80));
311 static int n810_keys
[0x80] = {
316 [0x05] = 14, /* Backspace */
326 [0x12] = 62, /* Menu (F4) */
328 [0x14] = 40, /* ' (Apostrophe) */
335 [0x1c] = 42, /* Shift (Left shift) */
336 [0x1f] = 65, /* Zoom+ (F7) */
339 [0x22] = 39, /* ; (Semicolon) */
340 [0x23] = 12, /* - (Minus) */
341 [0x24] = 13, /* = (Equal) */
342 [0x2b] = 56, /* Fn (Left Alt) */
344 [0x2f] = 66, /* Zoom- (F8) */
347 [0x32] = 29 | M
, /* Right Ctrl */
348 [0x34] = 57, /* Space */
349 [0x35] = 51, /* , (Comma) */
350 [0x37] = 72 | M
, /* Up */
351 [0x3c] = 82 | M
, /* Compose (Insert) */
352 [0x3f] = 64, /* FullScreen (F6) */
355 [0x44] = 52, /* . (Dot) */
356 [0x46] = 77 | M
, /* Right */
357 [0x4f] = 63, /* Home (F5) */
359 [0x53] = 80 | M
, /* Down */
360 [0x55] = 28, /* Enter */
361 [0x5f] = 1, /* Cycle (ESC) */
364 [0x64] = 75 | M
, /* Left */
368 [0x75] = 28 | M
, /* KP Enter (KP Enter) */
370 [0x75] = 15, /* KP Enter (Tab) */
376 static void n810_kbd_setup(struct n800_s
*s
)
378 qemu_irq kbd_irq
= qdev_get_gpio_in(s
->cpu
->gpio
, N810_KEYBOARD_GPIO
);
381 for (i
= 0; i
< 0x80; i
++)
383 for (i
= 0; i
< 0x80; i
++)
384 if (n810_keys
[i
] > 0)
385 s
->keymap
[n810_keys
[i
]] = i
;
387 qemu_add_kbd_event_handler(n810_key_event
, s
);
389 /* Attach the LM8322 keyboard to the I2C bus,
390 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
391 s
->kbd
= i2c_create_slave(omap_i2c_bus(s
->cpu
->i2c
[0]),
392 "lm8323", N810_LM8323_ADDR
);
393 qdev_connect_gpio_out(s
->kbd
, 0, kbd_irq
);
396 /* LCD MIPI DBI-C controller (URAL) */
417 static void mipid_reset(struct mipid_s
*s
)
420 fprintf(stderr
, "%s: Display off\n", __FUNCTION__
);
428 (1 << 7) | /* Register loading OK. */
429 (1 << 5) | /* The chip is attached. */
430 (1 << 4); /* Display glass still in one piece. */
440 static uint32_t mipid_txrx(void *opaque
, uint32_t cmd
, int len
)
442 struct mipid_s
*s
= (struct mipid_s
*) opaque
;
446 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__
, len
);
448 if (s
->p
>= ARRAY_SIZE(s
->resp
))
451 ret
= s
->resp
[s
->p
++];
453 s
->param
[s
->pm
] = cmd
;
461 case 0x01: /* SWRESET */
465 case 0x02: /* BSTROFF */
468 case 0x03: /* BSTRON */
472 case 0x04: /* RDDID */
474 s
->resp
[0] = (s
->id
>> 16) & 0xff;
475 s
->resp
[1] = (s
->id
>> 8) & 0xff;
476 s
->resp
[2] = (s
->id
>> 0) & 0xff;
479 case 0x06: /* RD_RED */
480 case 0x07: /* RD_GREEN */
481 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
482 * for the bootloader one needs to change this. */
483 case 0x08: /* RD_BLUE */
485 /* TODO: return first pixel components */
489 case 0x09: /* RDDST */
491 s
->resp
[0] = s
->booster
<< 7;
492 s
->resp
[1] = (5 << 4) | (s
->partial
<< 2) |
493 (s
->sleep
<< 1) | s
->normal
;
494 s
->resp
[2] = (s
->vscr
<< 7) | (s
->invert
<< 5) |
495 (s
->onoff
<< 2) | (s
->te
<< 1) | (s
->gamma
>> 2);
496 s
->resp
[3] = s
->gamma
<< 6;
499 case 0x0a: /* RDDPM */
501 s
->resp
[0] = (s
->onoff
<< 2) | (s
->normal
<< 3) | (s
->sleep
<< 4) |
502 (s
->partial
<< 5) | (s
->sleep
<< 6) | (s
->booster
<< 7);
504 case 0x0b: /* RDDMADCTR */
508 case 0x0c: /* RDDCOLMOD */
510 s
->resp
[0] = 5; /* 65K colours */
512 case 0x0d: /* RDDIM */
514 s
->resp
[0] = (s
->invert
<< 5) | (s
->vscr
<< 7) | s
->gamma
;
516 case 0x0e: /* RDDSM */
518 s
->resp
[0] = s
->te
<< 7;
520 case 0x0f: /* RDDSDR */
522 s
->resp
[0] = s
->selfcheck
;
525 case 0x10: /* SLPIN */
528 case 0x11: /* SLPOUT */
530 s
->selfcheck
^= 1 << 6; /* POFF self-diagnosis Ok */
533 case 0x12: /* PTLON */
538 case 0x13: /* NORON */
544 case 0x20: /* INVOFF */
547 case 0x21: /* INVON */
551 case 0x22: /* APOFF */
552 case 0x23: /* APON */
555 case 0x25: /* WRCNTR */
560 case 0x26: /* GAMSET */
562 s
->gamma
= ffs(s
->param
[0] & 0xf) - 1;
567 case 0x28: /* DISPOFF */
569 fprintf(stderr
, "%s: Display off\n", __FUNCTION__
);
571 case 0x29: /* DISPON */
573 fprintf(stderr
, "%s: Display on\n", __FUNCTION__
);
576 case 0x2a: /* CASET */
577 case 0x2b: /* RASET */
578 case 0x2c: /* RAMWR */
579 case 0x2d: /* RGBSET */
580 case 0x2e: /* RAMRD */
581 case 0x30: /* PTLAR */
582 case 0x33: /* SCRLAR */
585 case 0x34: /* TEOFF */
588 case 0x35: /* TEON */
595 case 0x36: /* MADCTR */
598 case 0x37: /* VSCSAD */
604 case 0x38: /* IDMOFF */
605 case 0x39: /* IDMON */
606 case 0x3a: /* COLMOD */
609 case 0xb0: /* CLKINT / DISCTL */
610 case 0xb1: /* CLKEXT */
615 case 0xb4: /* FRMSEL */
618 case 0xb5: /* FRM8SEL */
619 case 0xb6: /* TMPRNG / INIESC */
620 case 0xb7: /* TMPHIS / NOP2 */
621 case 0xb8: /* TMPREAD / MADCTL */
622 case 0xba: /* DISTCTR */
623 case 0xbb: /* EPVOL */
626 case 0xbd: /* Unknown */
632 case 0xc2: /* IFMOD */
637 case 0xc6: /* PWRCTL */
638 case 0xc7: /* PPWRCTL */
639 case 0xd0: /* EPWROUT */
640 case 0xd1: /* EPWRIN */
641 case 0xd4: /* RDEV */
642 case 0xd5: /* RDRR */
645 case 0xda: /* RDID1 */
647 s
->resp
[0] = (s
->id
>> 16) & 0xff;
649 case 0xdb: /* RDID2 */
651 s
->resp
[0] = (s
->id
>> 8) & 0xff;
653 case 0xdc: /* RDID3 */
655 s
->resp
[0] = (s
->id
>> 0) & 0xff;
660 fprintf(stderr
, "%s: unknown command %02x\n", __FUNCTION__
, s
->cmd
);
667 static void *mipid_init(void)
669 struct mipid_s
*s
= (struct mipid_s
*) g_malloc0(sizeof(*s
));
677 static void n8x0_spi_setup(struct n800_s
*s
)
679 void *tsc
= s
->ts
.opaque
;
680 void *mipid
= mipid_init();
682 omap_mcspi_attach(s
->cpu
->mcspi
[0], s
->ts
.txrx
, tsc
, 0);
683 omap_mcspi_attach(s
->cpu
->mcspi
[0], mipid_txrx
, mipid
, 1);
686 /* This task is normally performed by the bootloader. If we're loading
687 * a kernel directly, we need to enable the Blizzard ourselves. */
688 static void n800_dss_init(struct rfbi_chip_s
*chip
)
692 chip
->write(chip
->opaque
, 0, 0x2a); /* LCD Width register */
693 chip
->write(chip
->opaque
, 1, 0x64);
694 chip
->write(chip
->opaque
, 0, 0x2c); /* LCD HNDP register */
695 chip
->write(chip
->opaque
, 1, 0x1e);
696 chip
->write(chip
->opaque
, 0, 0x2e); /* LCD Height 0 register */
697 chip
->write(chip
->opaque
, 1, 0xe0);
698 chip
->write(chip
->opaque
, 0, 0x30); /* LCD Height 1 register */
699 chip
->write(chip
->opaque
, 1, 0x01);
700 chip
->write(chip
->opaque
, 0, 0x32); /* LCD VNDP register */
701 chip
->write(chip
->opaque
, 1, 0x06);
702 chip
->write(chip
->opaque
, 0, 0x68); /* Display Mode register */
703 chip
->write(chip
->opaque
, 1, 1); /* Enable bit */
705 chip
->write(chip
->opaque
, 0, 0x6c);
706 chip
->write(chip
->opaque
, 1, 0x00); /* Input X Start Position */
707 chip
->write(chip
->opaque
, 1, 0x00); /* Input X Start Position */
708 chip
->write(chip
->opaque
, 1, 0x00); /* Input Y Start Position */
709 chip
->write(chip
->opaque
, 1, 0x00); /* Input Y Start Position */
710 chip
->write(chip
->opaque
, 1, 0x1f); /* Input X End Position */
711 chip
->write(chip
->opaque
, 1, 0x03); /* Input X End Position */
712 chip
->write(chip
->opaque
, 1, 0xdf); /* Input Y End Position */
713 chip
->write(chip
->opaque
, 1, 0x01); /* Input Y End Position */
714 chip
->write(chip
->opaque
, 1, 0x00); /* Output X Start Position */
715 chip
->write(chip
->opaque
, 1, 0x00); /* Output X Start Position */
716 chip
->write(chip
->opaque
, 1, 0x00); /* Output Y Start Position */
717 chip
->write(chip
->opaque
, 1, 0x00); /* Output Y Start Position */
718 chip
->write(chip
->opaque
, 1, 0x1f); /* Output X End Position */
719 chip
->write(chip
->opaque
, 1, 0x03); /* Output X End Position */
720 chip
->write(chip
->opaque
, 1, 0xdf); /* Output Y End Position */
721 chip
->write(chip
->opaque
, 1, 0x01); /* Output Y End Position */
722 chip
->write(chip
->opaque
, 1, 0x01); /* Input Data Format */
723 chip
->write(chip
->opaque
, 1, 0x01); /* Data Source Select */
725 fb_blank
= memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
726 /* Display Memory Data Port */
727 chip
->block(chip
->opaque
, 1, fb_blank
, 800 * 480 * 2, 800);
731 static void n8x0_dss_setup(struct n800_s
*s
)
733 s
->blizzard
.opaque
= s1d13745_init(NULL
);
734 s
->blizzard
.block
= s1d13745_write_block
;
735 s
->blizzard
.write
= s1d13745_write
;
736 s
->blizzard
.read
= s1d13745_read
;
738 omap_rfbi_attach(s
->cpu
->dss
, 0, &s
->blizzard
);
741 static void n8x0_cbus_setup(struct n800_s
*s
)
743 qemu_irq dat_out
= qdev_get_gpio_in(s
->cpu
->gpio
, N8X0_CBUS_DAT_GPIO
);
744 qemu_irq retu_irq
= qdev_get_gpio_in(s
->cpu
->gpio
, N8X0_RETU_GPIO
);
745 qemu_irq tahvo_irq
= qdev_get_gpio_in(s
->cpu
->gpio
, N8X0_TAHVO_GPIO
);
747 CBus
*cbus
= cbus_init(dat_out
);
749 qdev_connect_gpio_out(s
->cpu
->gpio
, N8X0_CBUS_CLK_GPIO
, cbus
->clk
);
750 qdev_connect_gpio_out(s
->cpu
->gpio
, N8X0_CBUS_DAT_GPIO
, cbus
->dat
);
751 qdev_connect_gpio_out(s
->cpu
->gpio
, N8X0_CBUS_SEL_GPIO
, cbus
->sel
);
753 cbus_attach(cbus
, s
->retu
= retu_init(retu_irq
, 1));
754 cbus_attach(cbus
, s
->tahvo
= tahvo_init(tahvo_irq
, 1));
757 static void n8x0_uart_setup(struct n800_s
*s
)
759 CharDriverState
*radio
= uart_hci_init(
760 qdev_get_gpio_in(s
->cpu
->gpio
, N8X0_BT_HOST_WKUP_GPIO
));
762 qdev_connect_gpio_out(s
->cpu
->gpio
, N8X0_BT_RESET_GPIO
,
763 csrhci_pins_get(radio
)[csrhci_pin_reset
]);
764 qdev_connect_gpio_out(s
->cpu
->gpio
, N8X0_BT_WKUP_GPIO
,
765 csrhci_pins_get(radio
)[csrhci_pin_wakeup
]);
767 omap_uart_attach(s
->cpu
->uart
[BT_UART
], radio
);
770 static void n8x0_usb_setup(struct n800_s
*s
)
773 s
->usb
= qdev_create(NULL
, "tusb6010");
774 dev
= sysbus_from_qdev(s
->usb
);
775 qdev_init_nofail(s
->usb
);
776 sysbus_connect_irq(dev
, 0,
777 qdev_get_gpio_in(s
->cpu
->gpio
, N8X0_TUSB_INT_GPIO
));
778 /* Using the NOR interface */
779 omap_gpmc_attach(s
->cpu
->gpmc
, N8X0_USB_ASYNC_CS
,
780 sysbus_mmio_get_region(dev
, 0));
781 omap_gpmc_attach(s
->cpu
->gpmc
, N8X0_USB_SYNC_CS
,
782 sysbus_mmio_get_region(dev
, 1));
783 qdev_connect_gpio_out(s
->cpu
->gpio
, N8X0_TUSB_ENABLE_GPIO
,
784 qdev_get_gpio_in(s
->usb
, 0)); /* tusb_pwr */
787 /* Setup done before the main bootloader starts by some early setup code
788 * - used when we want to run the main bootloader in emulation. This
789 * isn't documented. */
790 static uint32_t n800_pinout
[104] = {
791 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
792 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
793 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
794 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
795 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
796 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
797 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
798 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
799 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
800 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
801 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
802 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
803 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
804 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
805 0x00000000, 0x00000038, 0x00340000, 0x00000000,
806 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
807 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
808 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
809 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
810 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
811 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
812 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
813 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
814 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
815 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
816 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
819 static void n800_setup_nolo_tags(void *sram_base
)
822 uint32_t *p
= sram_base
+ 0x8000;
823 uint32_t *v
= sram_base
+ 0xa000;
825 memset(p
, 0, 0x3000);
827 strcpy((void *) (p
+ 0), "QEMU N800");
829 strcpy((void *) (p
+ 8), "F5");
831 stl_raw(p
+ 10, 0x04f70000);
832 strcpy((void *) (p
+ 9), "RX-34");
834 /* RAM size in MB? */
835 stl_raw(p
+ 12, 0x80);
837 /* Pointer to the list of tags */
838 stl_raw(p
+ 13, OMAP2_SRAM_BASE
+ 0x9000);
840 /* The NOLO tags start here */
841 p
= sram_base
+ 0x9000;
842 #define ADD_TAG(tag, len) \
843 stw_raw((uint16_t *) p + 0, tag); \
844 stw_raw((uint16_t *) p + 1, len); p ++; \
845 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
847 /* OMAP STI console? Pin out settings? */
848 ADD_TAG(0x6e01, 414);
849 for (i
= 0; i
< ARRAY_SIZE(n800_pinout
); i
++)
850 stl_raw(v
++, n800_pinout
[i
]);
852 /* Kernel memsize? */
856 /* NOLO serial console */
858 stl_raw(v
++, XLDR_LL_UART
); /* UART number (1 - 3) */
861 /* CBUS settings (Retu/AVilma) */
863 stw_raw((uint16_t *) v
+ 0, 65); /* CBUS GPIO0 */
864 stw_raw((uint16_t *) v
+ 1, 66); /* CBUS GPIO1 */
865 stw_raw((uint16_t *) v
+ 2, 64); /* CBUS GPIO2 */
869 /* Nokia ASIC BB5 (Retu/Tahvo) */
871 stw_raw((uint16_t *) v
+ 0, 111); /* "Retu" interrupt GPIO */
872 stw_raw((uint16_t *) v
+ 1, 108); /* "Tahvo" interrupt GPIO */
877 stw_raw((uint16_t *) v
+ 0, 30); /* ??? */
878 stw_raw((uint16_t *) v
+ 1, 24); /* ??? */
884 stw_raw((uint16_t *) (v
++), 15); /* ??? */
887 /* I^2C (Menelaus) */
889 stl_raw(v
++, 0x00720000); /* ??? */
893 stw_raw((uint16_t *) v
+ 0, 94); /* ??? */
894 stw_raw((uint16_t *) v
+ 1, 23); /* ??? */
895 stw_raw((uint16_t *) v
+ 2, 0); /* ??? */
898 /* OMAP gpio switch info */
900 strcpy((void *) v
, "bat_cover"); v
+= 3;
901 stw_raw((uint16_t *) v
+ 0, 110); /* GPIO num ??? */
902 stw_raw((uint16_t *) v
+ 1, 1); /* GPIO num ??? */
904 strcpy((void *) v
, "cam_act"); v
+= 3;
905 stw_raw((uint16_t *) v
+ 0, 95); /* GPIO num ??? */
906 stw_raw((uint16_t *) v
+ 1, 32); /* GPIO num ??? */
908 strcpy((void *) v
, "cam_turn"); v
+= 3;
909 stw_raw((uint16_t *) v
+ 0, 12); /* GPIO num ??? */
910 stw_raw((uint16_t *) v
+ 1, 33); /* GPIO num ??? */
912 strcpy((void *) v
, "headphone"); v
+= 3;
913 stw_raw((uint16_t *) v
+ 0, 107); /* GPIO num ??? */
914 stw_raw((uint16_t *) v
+ 1, 17); /* GPIO num ??? */
919 stl_raw(v
++, 0x5c623d01); /* ??? */
920 stl_raw(v
++, 0x00000201); /* ??? */
921 stl_raw(v
++, 0x00000000); /* ??? */
923 /* CX3110x WLAN settings */
925 stl_raw(v
++, 0x00610025); /* ??? */
926 stl_raw(v
++, 0xffff0057); /* ??? */
928 /* MMC host settings */
930 stl_raw(v
++, 0xffff000f); /* ??? */
931 stl_raw(v
++, 0xffffffff); /* ??? */
932 stl_raw(v
++, 0x00000060); /* ??? */
934 /* OneNAND chip select */
936 stl_raw(v
++, 0x00000401); /* ??? */
937 stl_raw(v
++, 0x0002003a); /* ??? */
938 stl_raw(v
++, 0x00000002); /* ??? */
940 /* TEA5761 sensor settings */
942 stl_raw(v
++, 93); /* GPIO num ??? */
948 /* Kernel UART / console */
952 /* End of the list */
953 stl_raw(p
++, 0x00000000);
954 stl_raw(p
++, 0x00000000);
957 /* This task is normally performed by the bootloader. If we're loading
958 * a kernel directly, we need to set up GPMC mappings ourselves. */
959 static void n800_gpmc_init(struct n800_s
*s
)
962 (0xf << 8) | /* MASKADDRESS */
963 (1 << 6) | /* CSVALID */
964 (4 << 0); /* BASEADDRESS */
966 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
967 (void *) &config7
, sizeof(config7
));
970 /* Setup sequence done by the bootloader */
971 static void n8x0_boot_init(void *opaque
)
973 struct n800_s
*s
= (struct n800_s
*) opaque
;
977 #define omap_writel(addr, val) \
979 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
981 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
982 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
983 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
984 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
985 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
986 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
987 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
988 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
989 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
990 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
991 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
992 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
993 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
994 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
995 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
996 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
997 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
998 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
999 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
1000 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
1001 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
1002 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
1003 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
1004 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1005 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1006 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1007 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1008 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1009 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1010 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1011 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1012 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1013 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1014 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1015 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1016 (0x78 << 12) | (6 << 8));
1017 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1023 n800_dss_init(&s
->blizzard
);
1026 s
->cpu
->cpu
->env
.GE
= 0x5;
1028 /* If the machine has a slided keyboard, open it */
1030 qemu_irq_raise(qdev_get_gpio_in(s
->cpu
->gpio
, N810_SLIDE_GPIO
));
1033 #define OMAP_TAG_NOKIA_BT 0x4e01
1034 #define OMAP_TAG_WLAN_CX3110X 0x4e02
1035 #define OMAP_TAG_CBUS 0x4e03
1036 #define OMAP_TAG_EM_ASIC_BB5 0x4e04
1038 static struct omap_gpiosw_info_s
{
1042 } n800_gpiosw_info
[] = {
1044 "bat_cover", N800_BAT_COVER_GPIO
,
1045 OMAP_GPIOSW_TYPE_COVER
| OMAP_GPIOSW_INVERTED
,
1047 "cam_act", N800_CAM_ACT_GPIO
,
1048 OMAP_GPIOSW_TYPE_ACTIVITY
,
1050 "cam_turn", N800_CAM_TURN_GPIO
,
1051 OMAP_GPIOSW_TYPE_ACTIVITY
| OMAP_GPIOSW_INVERTED
,
1053 "headphone", N8X0_HEADPHONE_GPIO
,
1054 OMAP_GPIOSW_TYPE_CONNECTION
| OMAP_GPIOSW_INVERTED
,
1057 }, n810_gpiosw_info
[] = {
1059 "gps_reset", N810_GPS_RESET_GPIO
,
1060 OMAP_GPIOSW_TYPE_ACTIVITY
| OMAP_GPIOSW_OUTPUT
,
1062 "gps_wakeup", N810_GPS_WAKEUP_GPIO
,
1063 OMAP_GPIOSW_TYPE_ACTIVITY
| OMAP_GPIOSW_OUTPUT
,
1065 "headphone", N8X0_HEADPHONE_GPIO
,
1066 OMAP_GPIOSW_TYPE_CONNECTION
| OMAP_GPIOSW_INVERTED
,
1068 "kb_lock", N810_KB_LOCK_GPIO
,
1069 OMAP_GPIOSW_TYPE_COVER
| OMAP_GPIOSW_INVERTED
,
1071 "sleepx_led", N810_SLEEPX_LED_GPIO
,
1072 OMAP_GPIOSW_TYPE_ACTIVITY
| OMAP_GPIOSW_INVERTED
| OMAP_GPIOSW_OUTPUT
,
1074 "slide", N810_SLIDE_GPIO
,
1075 OMAP_GPIOSW_TYPE_COVER
| OMAP_GPIOSW_INVERTED
,
1080 static struct omap_partition_info_s
{
1085 } n800_part_info
[] = {
1086 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1087 { 0x00020000, 0x00060000, 0x0, "config" },
1088 { 0x00080000, 0x00200000, 0x0, "kernel" },
1089 { 0x00280000, 0x00200000, 0x3, "initfs" },
1090 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1093 }, n810_part_info
[] = {
1094 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1095 { 0x00020000, 0x00060000, 0x0, "config" },
1096 { 0x00080000, 0x00220000, 0x0, "kernel" },
1097 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1098 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1103 static bdaddr_t n8x0_bd_addr
= {{ N8X0_BD_ADDR
}};
1105 static int n8x0_atag_setup(void *p
, int model
)
1110 struct omap_gpiosw_info_s
*gpiosw
;
1111 struct omap_partition_info_s
*partition
;
1116 stw_raw(w
++, OMAP_TAG_UART
); /* u16 tag */
1117 stw_raw(w
++, 4); /* u16 len */
1118 stw_raw(w
++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1122 stw_raw(w
++, OMAP_TAG_SERIAL_CONSOLE
); /* u16 tag */
1123 stw_raw(w
++, 4); /* u16 len */
1124 stw_raw(w
++, XLDR_LL_UART
+ 1); /* u8 console_uart */
1125 stw_raw(w
++, 115200); /* u32 console_speed */
1128 stw_raw(w
++, OMAP_TAG_LCD
); /* u16 tag */
1129 stw_raw(w
++, 36); /* u16 len */
1130 strcpy((void *) w
, "QEMU LCD panel"); /* char panel_name[16] */
1132 strcpy((void *) w
, "blizzard"); /* char ctrl_name[16] */
1134 stw_raw(w
++, N810_BLIZZARD_RESET_GPIO
); /* TODO: n800 s16 nreset_gpio */
1135 stw_raw(w
++, 24); /* u8 data_lines */
1137 stw_raw(w
++, OMAP_TAG_CBUS
); /* u16 tag */
1138 stw_raw(w
++, 8); /* u16 len */
1139 stw_raw(w
++, N8X0_CBUS_CLK_GPIO
); /* s16 clk_gpio */
1140 stw_raw(w
++, N8X0_CBUS_DAT_GPIO
); /* s16 dat_gpio */
1141 stw_raw(w
++, N8X0_CBUS_SEL_GPIO
); /* s16 sel_gpio */
1144 stw_raw(w
++, OMAP_TAG_EM_ASIC_BB5
); /* u16 tag */
1145 stw_raw(w
++, 4); /* u16 len */
1146 stw_raw(w
++, N8X0_RETU_GPIO
); /* s16 retu_irq_gpio */
1147 stw_raw(w
++, N8X0_TAHVO_GPIO
); /* s16 tahvo_irq_gpio */
1149 gpiosw
= (model
== 810) ? n810_gpiosw_info
: n800_gpiosw_info
;
1150 for (; gpiosw
->name
; gpiosw
++) {
1151 stw_raw(w
++, OMAP_TAG_GPIO_SWITCH
); /* u16 tag */
1152 stw_raw(w
++, 20); /* u16 len */
1153 strcpy((void *) w
, gpiosw
->name
); /* char name[12] */
1155 stw_raw(w
++, gpiosw
->line
); /* u16 gpio */
1156 stw_raw(w
++, gpiosw
->type
);
1161 stw_raw(w
++, OMAP_TAG_NOKIA_BT
); /* u16 tag */
1162 stw_raw(w
++, 12); /* u16 len */
1164 stb_raw(b
++, 0x01); /* u8 chip_type (CSR) */
1165 stb_raw(b
++, N8X0_BT_WKUP_GPIO
); /* u8 bt_wakeup_gpio */
1166 stb_raw(b
++, N8X0_BT_HOST_WKUP_GPIO
); /* u8 host_wakeup_gpio */
1167 stb_raw(b
++, N8X0_BT_RESET_GPIO
); /* u8 reset_gpio */
1168 stb_raw(b
++, BT_UART
+ 1); /* u8 bt_uart */
1169 memcpy(b
, &n8x0_bd_addr
, 6); /* u8 bd_addr[6] */
1171 stb_raw(b
++, 0x02); /* u8 bt_sysclk (38.4) */
1174 stw_raw(w
++, OMAP_TAG_WLAN_CX3110X
); /* u16 tag */
1175 stw_raw(w
++, 8); /* u16 len */
1176 stw_raw(w
++, 0x25); /* u8 chip_type */
1177 stw_raw(w
++, N8X0_WLAN_PWR_GPIO
); /* s16 power_gpio */
1178 stw_raw(w
++, N8X0_WLAN_IRQ_GPIO
); /* s16 irq_gpio */
1179 stw_raw(w
++, -1); /* s16 spi_cs_gpio */
1181 stw_raw(w
++, OMAP_TAG_MMC
); /* u16 tag */
1182 stw_raw(w
++, 16); /* u16 len */
1184 stw_raw(w
++, 0x23f); /* unsigned flags */
1185 stw_raw(w
++, -1); /* s16 power_pin */
1186 stw_raw(w
++, -1); /* s16 switch_pin */
1187 stw_raw(w
++, -1); /* s16 wp_pin */
1188 stw_raw(w
++, 0x240); /* unsigned flags */
1189 stw_raw(w
++, 0xc000); /* s16 power_pin */
1190 stw_raw(w
++, 0x0248); /* s16 switch_pin */
1191 stw_raw(w
++, 0xc000); /* s16 wp_pin */
1193 stw_raw(w
++, 0xf); /* unsigned flags */
1194 stw_raw(w
++, -1); /* s16 power_pin */
1195 stw_raw(w
++, -1); /* s16 switch_pin */
1196 stw_raw(w
++, -1); /* s16 wp_pin */
1197 stw_raw(w
++, 0); /* unsigned flags */
1198 stw_raw(w
++, 0); /* s16 power_pin */
1199 stw_raw(w
++, 0); /* s16 switch_pin */
1200 stw_raw(w
++, 0); /* s16 wp_pin */
1203 stw_raw(w
++, OMAP_TAG_TEA5761
); /* u16 tag */
1204 stw_raw(w
++, 4); /* u16 len */
1205 stw_raw(w
++, N8X0_TEA5761_CS_GPIO
); /* u16 enable_gpio */
1208 partition
= (model
== 810) ? n810_part_info
: n800_part_info
;
1209 for (; partition
->name
; partition
++) {
1210 stw_raw(w
++, OMAP_TAG_PARTITION
); /* u16 tag */
1211 stw_raw(w
++, 28); /* u16 len */
1212 strcpy((void *) w
, partition
->name
); /* char name[16] */
1213 l
= (void *) (w
+ 8);
1214 stl_raw(l
++, partition
->size
); /* unsigned int size */
1215 stl_raw(l
++, partition
->offset
); /* unsigned int offset */
1216 stl_raw(l
++, partition
->mask
); /* unsigned int mask_flags */
1220 stw_raw(w
++, OMAP_TAG_BOOT_REASON
); /* u16 tag */
1221 stw_raw(w
++, 12); /* u16 len */
1223 strcpy((void *) w
, "por"); /* char reason_str[12] */
1224 strcpy((void *) w
, "charger"); /* char reason_str[12] */
1225 strcpy((void *) w
, "32wd_to"); /* char reason_str[12] */
1226 strcpy((void *) w
, "sw_rst"); /* char reason_str[12] */
1227 strcpy((void *) w
, "mbus"); /* char reason_str[12] */
1228 strcpy((void *) w
, "unknown"); /* char reason_str[12] */
1229 strcpy((void *) w
, "swdg_to"); /* char reason_str[12] */
1230 strcpy((void *) w
, "sec_vio"); /* char reason_str[12] */
1231 strcpy((void *) w
, "pwr_key"); /* char reason_str[12] */
1232 strcpy((void *) w
, "rtc_alarm"); /* char reason_str[12] */
1234 strcpy((void *) w
, "pwr_key"); /* char reason_str[12] */
1238 tag
= (model
== 810) ? "RX-44" : "RX-34";
1239 stw_raw(w
++, OMAP_TAG_VERSION_STR
); /* u16 tag */
1240 stw_raw(w
++, 24); /* u16 len */
1241 strcpy((void *) w
, "product"); /* char component[12] */
1243 strcpy((void *) w
, tag
); /* char version[12] */
1246 stw_raw(w
++, OMAP_TAG_VERSION_STR
); /* u16 tag */
1247 stw_raw(w
++, 24); /* u16 len */
1248 strcpy((void *) w
, "hw-build"); /* char component[12] */
1250 strcpy((void *) w
, "QEMU " QEMU_VERSION
); /* char version[12] */
1253 tag
= (model
== 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1254 stw_raw(w
++, OMAP_TAG_VERSION_STR
); /* u16 tag */
1255 stw_raw(w
++, 24); /* u16 len */
1256 strcpy((void *) w
, "nolo"); /* char component[12] */
1258 strcpy((void *) w
, tag
); /* char version[12] */
1261 return (void *) w
- p
;
1264 static int n800_atag_setup(const struct arm_boot_info
*info
, void *p
)
1266 return n8x0_atag_setup(p
, 800);
1269 static int n810_atag_setup(const struct arm_boot_info
*info
, void *p
)
1271 return n8x0_atag_setup(p
, 810);
1274 static void n8x0_init(ram_addr_t ram_size
, const char *boot_device
,
1275 const char *kernel_filename
,
1276 const char *kernel_cmdline
, const char *initrd_filename
,
1277 const char *cpu_model
, struct arm_boot_info
*binfo
, int model
)
1279 MemoryRegion
*sysmem
= get_system_memory();
1280 struct n800_s
*s
= (struct n800_s
*) g_malloc0(sizeof(*s
));
1281 int sdram_size
= binfo
->ram_size
;
1284 s
->cpu
= omap2420_mpu_init(sysmem
, sdram_size
, cpu_model
);
1286 /* Setup peripherals
1288 * Believed external peripherals layout in the N810:
1293 * Conexant cx3110x (WLAN)
1294 * optional: pc2400m (WiMAX)
1296 * TLV320AIC33 (audio codec)
1297 * TCM825x (camera by Toshiba)
1298 * lp5521 (clever LEDs)
1299 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1300 * lm8323 (keypad, manf 00, rev 04)
1302 * tmp105 (temperature sensor, hwmon)
1304 * (somewhere on i2c - maybe N800-only)
1305 * tea5761 (FM tuner)
1308 * (some serial port)
1309 * csr41814 (Bluetooth)
1315 n800_tsc_kbd_setup(s
);
1316 else if (model
== 810) {
1327 if (kernel_filename
) {
1328 /* Or at the linux loader. */
1329 binfo
->kernel_filename
= kernel_filename
;
1330 binfo
->kernel_cmdline
= kernel_cmdline
;
1331 binfo
->initrd_filename
= initrd_filename
;
1332 arm_load_kernel(&s
->cpu
->cpu
->env
, binfo
);
1334 qemu_register_reset(n8x0_boot_init
, s
);
1337 if (option_rom
[0].name
&& (boot_device
[0] == 'n' || !kernel_filename
)) {
1339 uint8_t nolo_tags
[0x10000];
1340 /* No, wait, better start at the ROM. */
1341 s
->cpu
->cpu
->env
.regs
[15] = OMAP2_Q2_BASE
+ 0x400000;
1343 /* This is intended for loading the `secondary.bin' program from
1344 * Nokia images (the NOLO bootloader). The entry point seems
1345 * to be at OMAP2_Q2_BASE + 0x400000.
1347 * The `2nd.bin' files contain some kind of earlier boot code and
1348 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1350 * The code above is for loading the `zImage' file from Nokia
1352 rom_size
= load_image_targphys(option_rom
[0].name
,
1353 OMAP2_Q2_BASE
+ 0x400000,
1354 sdram_size
- 0x400000);
1355 printf("%i bytes of image loaded\n", rom_size
);
1357 n800_setup_nolo_tags(nolo_tags
);
1358 cpu_physical_memory_write(OMAP2_SRAM_BASE
, nolo_tags
, 0x10000);
1360 /* FIXME: We shouldn't really be doing this here. The LCD controller
1361 will set the size once configured, so this just sets an initial
1362 size until the guest activates the display. */
1363 ds
= get_displaystate();
1364 ds
->surface
= qemu_resize_displaysurface(ds
, 800, 480);
1368 static struct arm_boot_info n800_binfo
= {
1369 .loader_start
= OMAP2_Q2_BASE
,
1370 /* Actually two chips of 0x4000000 bytes each */
1371 .ram_size
= 0x08000000,
1373 .atag_board
= n800_atag_setup
,
1376 static struct arm_boot_info n810_binfo
= {
1377 .loader_start
= OMAP2_Q2_BASE
,
1378 /* Actually two chips of 0x4000000 bytes each */
1379 .ram_size
= 0x08000000,
1380 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1381 * used by some older versions of the bootloader and 5555 is used
1382 * instead (including versions that shipped with many devices). */
1384 .atag_board
= n810_atag_setup
,
1387 static void n800_init(ram_addr_t ram_size
,
1388 const char *boot_device
,
1389 const char *kernel_filename
, const char *kernel_cmdline
,
1390 const char *initrd_filename
, const char *cpu_model
)
1392 return n8x0_init(ram_size
, boot_device
,
1393 kernel_filename
, kernel_cmdline
, initrd_filename
,
1394 cpu_model
, &n800_binfo
, 800);
1397 static void n810_init(ram_addr_t ram_size
,
1398 const char *boot_device
,
1399 const char *kernel_filename
, const char *kernel_cmdline
,
1400 const char *initrd_filename
, const char *cpu_model
)
1402 return n8x0_init(ram_size
, boot_device
,
1403 kernel_filename
, kernel_cmdline
, initrd_filename
,
1404 cpu_model
, &n810_binfo
, 810);
1407 static QEMUMachine n800_machine
= {
1409 .desc
= "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1413 static QEMUMachine n810_machine
= {
1415 .desc
= "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1419 static void nseries_machine_init(void)
1421 qemu_register_machine(&n800_machine
);
1422 qemu_register_machine(&n810_machine
);
1425 machine_init(nseries_machine_init
);