2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012-2014 Imagination Technologies Ltd.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include "qemu/osdep.h"
13 #include <sys/ioctl.h>
15 #include <linux/kvm.h>
17 #include "qemu-common.h"
19 #include "qemu/error-report.h"
20 #include "qemu/timer.h"
21 #include "sysemu/sysemu.h"
22 #include "sysemu/kvm.h"
23 #include "sysemu/cpus.h"
25 #include "exec/memattrs.h"
29 #define DPRINTF(fmt, ...) \
30 do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
32 static int kvm_mips_fpu_cap
;
33 static int kvm_mips_msa_cap
;
35 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
39 static void kvm_mips_update_state(void *opaque
, int running
, RunState state
);
41 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
46 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
48 /* MIPS has 128 signals */
49 kvm_set_sigmask_len(s
, 16);
51 kvm_mips_fpu_cap
= kvm_check_extension(s
, KVM_CAP_MIPS_FPU
);
52 kvm_mips_msa_cap
= kvm_check_extension(s
, KVM_CAP_MIPS_MSA
);
54 DPRINTF("%s\n", __func__
);
58 int kvm_arch_irqchip_create(MachineState
*ms
, KVMState
*s
)
63 int kvm_arch_init_vcpu(CPUState
*cs
)
65 MIPSCPU
*cpu
= MIPS_CPU(cs
);
66 CPUMIPSState
*env
= &cpu
->env
;
69 qemu_add_vm_change_state_handler(kvm_mips_update_state
, cs
);
71 if (kvm_mips_fpu_cap
&& env
->CP0_Config1
& (1 << CP0C1_FP
)) {
72 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_MIPS_FPU
, 0, 0);
74 /* mark unsupported so it gets disabled on reset */
80 if (kvm_mips_msa_cap
&& env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
81 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_MIPS_MSA
, 0, 0);
83 /* mark unsupported so it gets disabled on reset */
89 DPRINTF("%s\n", __func__
);
93 void kvm_mips_reset_vcpu(MIPSCPU
*cpu
)
95 CPUMIPSState
*env
= &cpu
->env
;
97 if (!kvm_mips_fpu_cap
&& env
->CP0_Config1
& (1 << CP0C1_FP
)) {
98 fprintf(stderr
, "Warning: KVM does not support FPU, disabling\n");
99 env
->CP0_Config1
&= ~(1 << CP0C1_FP
);
101 if (!kvm_mips_msa_cap
&& env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
102 fprintf(stderr
, "Warning: KVM does not support MSA, disabling\n");
103 env
->CP0_Config3
&= ~(1 << CP0C3_MSAP
);
106 DPRINTF("%s\n", __func__
);
109 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
111 DPRINTF("%s\n", __func__
);
115 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
117 DPRINTF("%s\n", __func__
);
121 static inline int cpu_mips_io_interrupts_pending(MIPSCPU
*cpu
)
123 CPUMIPSState
*env
= &cpu
->env
;
125 return env
->CP0_Cause
& (0x1 << (2 + CP0Ca_IP
));
129 void kvm_arch_pre_run(CPUState
*cs
, struct kvm_run
*run
)
131 MIPSCPU
*cpu
= MIPS_CPU(cs
);
133 struct kvm_mips_interrupt intr
;
135 qemu_mutex_lock_iothread();
137 if ((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
138 cpu_mips_io_interrupts_pending(cpu
)) {
141 r
= kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
143 error_report("%s: cpu %d: failed to inject IRQ %x",
144 __func__
, cs
->cpu_index
, intr
.irq
);
148 qemu_mutex_unlock_iothread();
151 MemTxAttrs
kvm_arch_post_run(CPUState
*cs
, struct kvm_run
*run
)
153 return MEMTXATTRS_UNSPECIFIED
;
156 int kvm_arch_process_async_events(CPUState
*cs
)
161 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
165 DPRINTF("%s\n", __func__
);
166 switch (run
->exit_reason
) {
168 error_report("%s: unknown exit reason %d",
169 __func__
, run
->exit_reason
);
177 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
179 DPRINTF("%s\n", __func__
);
183 int kvm_arch_on_sigbus_vcpu(CPUState
*cs
, int code
, void *addr
)
185 DPRINTF("%s\n", __func__
);
189 int kvm_arch_on_sigbus(int code
, void *addr
)
191 DPRINTF("%s\n", __func__
);
195 void kvm_arch_init_irq_routing(KVMState
*s
)
199 int kvm_mips_set_interrupt(MIPSCPU
*cpu
, int irq
, int level
)
201 CPUState
*cs
= CPU(cpu
);
202 struct kvm_mips_interrupt intr
;
204 if (!kvm_enabled()) {
216 kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
221 int kvm_mips_set_ipi_interrupt(MIPSCPU
*cpu
, int irq
, int level
)
223 CPUState
*cs
= current_cpu
;
224 CPUState
*dest_cs
= CPU(cpu
);
225 struct kvm_mips_interrupt intr
;
227 if (!kvm_enabled()) {
231 intr
.cpu
= dest_cs
->cpu_index
;
239 DPRINTF("%s: CPU %d, IRQ: %d\n", __func__
, intr
.cpu
, intr
.irq
);
241 kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
246 #define MIPS_CP0_32(_R, _S) \
247 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
249 #define MIPS_CP0_64(_R, _S) \
250 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
252 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
253 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
254 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
255 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
256 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
257 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
258 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
259 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
260 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
261 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
262 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
263 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
264 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
265 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
266 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
267 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
268 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
269 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
270 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
271 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
272 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
274 static inline int kvm_mips_put_one_reg(CPUState
*cs
, uint64_t reg_id
,
277 struct kvm_one_reg cp0reg
= {
279 .addr
= (uintptr_t)addr
282 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
285 static inline int kvm_mips_put_one_ureg(CPUState
*cs
, uint64_t reg_id
,
288 struct kvm_one_reg cp0reg
= {
290 .addr
= (uintptr_t)addr
293 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
296 static inline int kvm_mips_put_one_ulreg(CPUState
*cs
, uint64_t reg_id
,
299 uint64_t val64
= *addr
;
300 struct kvm_one_reg cp0reg
= {
302 .addr
= (uintptr_t)&val64
305 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
308 static inline int kvm_mips_put_one_reg64(CPUState
*cs
, uint64_t reg_id
,
311 struct kvm_one_reg cp0reg
= {
313 .addr
= (uintptr_t)addr
316 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
319 static inline int kvm_mips_put_one_ureg64(CPUState
*cs
, uint64_t reg_id
,
322 struct kvm_one_reg cp0reg
= {
324 .addr
= (uintptr_t)addr
327 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
330 static inline int kvm_mips_get_one_reg(CPUState
*cs
, uint64_t reg_id
,
333 struct kvm_one_reg cp0reg
= {
335 .addr
= (uintptr_t)addr
338 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
341 static inline int kvm_mips_get_one_ureg(CPUState
*cs
, uint64_t reg_id
,
344 struct kvm_one_reg cp0reg
= {
346 .addr
= (uintptr_t)addr
349 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
352 static inline int kvm_mips_get_one_ulreg(CPUState
*cs
, uint64_t reg_id
,
357 struct kvm_one_reg cp0reg
= {
359 .addr
= (uintptr_t)&val64
362 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
369 static inline int kvm_mips_get_one_reg64(CPUState
*cs
, uint64_t reg_id
,
372 struct kvm_one_reg cp0reg
= {
374 .addr
= (uintptr_t)addr
377 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
380 static inline int kvm_mips_get_one_ureg64(CPUState
*cs
, uint64_t reg_id
,
383 struct kvm_one_reg cp0reg
= {
385 .addr
= (uintptr_t)addr
388 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
391 #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M)
392 #define KVM_REG_MIPS_CP0_CONFIG1_MASK ((1U << CP0C1_M) | \
394 #define KVM_REG_MIPS_CP0_CONFIG2_MASK (1U << CP0C2_M)
395 #define KVM_REG_MIPS_CP0_CONFIG3_MASK ((1U << CP0C3_M) | \
397 #define KVM_REG_MIPS_CP0_CONFIG4_MASK (1U << CP0C4_M)
398 #define KVM_REG_MIPS_CP0_CONFIG5_MASK ((1U << CP0C5_MSAEn) | \
399 (1U << CP0C5_UFE) | \
400 (1U << CP0C5_FRE) | \
403 static inline int kvm_mips_change_one_reg(CPUState
*cs
, uint64_t reg_id
,
404 int32_t *addr
, int32_t mask
)
409 err
= kvm_mips_get_one_reg(cs
, reg_id
, &tmp
);
414 /* only change bits in mask */
415 change
= (*addr
^ tmp
) & mask
;
421 return kvm_mips_put_one_reg(cs
, reg_id
, &tmp
);
425 * We freeze the KVM timer when either the VM clock is stopped or the state is
426 * saved (the state is dirty).
430 * Save the state of the KVM timer when VM clock is stopped or state is synced
433 static int kvm_mips_save_count(CPUState
*cs
)
435 MIPSCPU
*cpu
= MIPS_CPU(cs
);
436 CPUMIPSState
*env
= &cpu
->env
;
440 /* freeze KVM timer */
441 err
= kvm_mips_get_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
443 DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__
, err
);
445 } else if (!(count_ctl
& KVM_REG_MIPS_COUNT_CTL_DC
)) {
446 count_ctl
|= KVM_REG_MIPS_COUNT_CTL_DC
;
447 err
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
449 DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__
, err
);
455 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CAUSE
, &env
->CP0_Cause
);
457 DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__
, err
);
462 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_COUNT
, &env
->CP0_Count
);
464 DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__
, err
);
472 * Restore the state of the KVM timer when VM clock is restarted or state is
475 static int kvm_mips_restore_count(CPUState
*cs
)
477 MIPSCPU
*cpu
= MIPS_CPU(cs
);
478 CPUMIPSState
*env
= &cpu
->env
;
480 int err_dc
, err
, ret
= 0;
482 /* check the timer is frozen */
483 err_dc
= kvm_mips_get_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
485 DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__
, err_dc
);
487 } else if (!(count_ctl
& KVM_REG_MIPS_COUNT_CTL_DC
)) {
488 /* freeze timer (sets COUNT_RESUME for us) */
489 count_ctl
|= KVM_REG_MIPS_COUNT_CTL_DC
;
490 err
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
492 DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__
, err
);
498 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_CAUSE
, &env
->CP0_Cause
);
500 DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__
, err
);
505 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_COUNT
, &env
->CP0_Count
);
507 DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__
, err
);
511 /* resume KVM timer */
513 count_ctl
&= ~KVM_REG_MIPS_COUNT_CTL_DC
;
514 err
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
516 DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__
, err
);
525 * Handle the VM clock being started or stopped
527 static void kvm_mips_update_state(void *opaque
, int running
, RunState state
)
529 CPUState
*cs
= opaque
;
531 uint64_t count_resume
;
534 * If state is already dirty (synced to QEMU) then the KVM timer state is
535 * already saved and can be restored when it is synced back to KVM.
538 if (!cs
->kvm_vcpu_dirty
) {
539 ret
= kvm_mips_save_count(cs
);
541 fprintf(stderr
, "Failed saving count\n");
545 /* Set clock restore time to now */
546 count_resume
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
547 ret
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_COUNT_RESUME
,
550 fprintf(stderr
, "Failed setting COUNT_RESUME\n");
554 if (!cs
->kvm_vcpu_dirty
) {
555 ret
= kvm_mips_restore_count(cs
);
557 fprintf(stderr
, "Failed restoring count\n");
563 static int kvm_mips_put_fpu_registers(CPUState
*cs
, int level
)
565 MIPSCPU
*cpu
= MIPS_CPU(cs
);
566 CPUMIPSState
*env
= &cpu
->env
;
570 /* Only put FPU state if we're emulating a CPU with an FPU */
571 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
572 /* FPU Control Registers */
573 if (level
== KVM_PUT_FULL_STATE
) {
574 err
= kvm_mips_put_one_ureg(cs
, KVM_REG_MIPS_FCR_IR
,
575 &env
->active_fpu
.fcr0
);
577 DPRINTF("%s: Failed to put FCR_IR (%d)\n", __func__
, err
);
581 err
= kvm_mips_put_one_ureg(cs
, KVM_REG_MIPS_FCR_CSR
,
582 &env
->active_fpu
.fcr31
);
584 DPRINTF("%s: Failed to put FCR_CSR (%d)\n", __func__
, err
);
589 * FPU register state is a subset of MSA vector state, so don't put FPU
590 * registers if we're emulating a CPU with MSA.
592 if (!(env
->CP0_Config3
& (1 << CP0C3_MSAP
))) {
593 /* Floating point registers */
594 for (i
= 0; i
< 32; ++i
) {
595 if (env
->CP0_Status
& (1 << CP0St_FR
)) {
596 err
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_FPR_64(i
),
597 &env
->active_fpu
.fpr
[i
].d
);
599 err
= kvm_mips_get_one_ureg(cs
, KVM_REG_MIPS_FPR_32(i
),
600 &env
->active_fpu
.fpr
[i
].w
[FP_ENDIAN_IDX
]);
603 DPRINTF("%s: Failed to put FPR%u (%d)\n", __func__
, i
, err
);
610 /* Only put MSA state if we're emulating a CPU with MSA */
611 if (env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
612 /* MSA Control Registers */
613 if (level
== KVM_PUT_FULL_STATE
) {
614 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_MSA_IR
,
617 DPRINTF("%s: Failed to put MSA_IR (%d)\n", __func__
, err
);
621 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_MSA_CSR
,
622 &env
->active_tc
.msacsr
);
624 DPRINTF("%s: Failed to put MSA_CSR (%d)\n", __func__
, err
);
628 /* Vector registers (includes FP registers) */
629 for (i
= 0; i
< 32; ++i
) {
630 /* Big endian MSA not supported by QEMU yet anyway */
631 err
= kvm_mips_put_one_reg64(cs
, KVM_REG_MIPS_VEC_128(i
),
632 env
->active_fpu
.fpr
[i
].wr
.d
);
634 DPRINTF("%s: Failed to put VEC%u (%d)\n", __func__
, i
, err
);
643 static int kvm_mips_get_fpu_registers(CPUState
*cs
)
645 MIPSCPU
*cpu
= MIPS_CPU(cs
);
646 CPUMIPSState
*env
= &cpu
->env
;
650 /* Only get FPU state if we're emulating a CPU with an FPU */
651 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
652 /* FPU Control Registers */
653 err
= kvm_mips_get_one_ureg(cs
, KVM_REG_MIPS_FCR_IR
,
654 &env
->active_fpu
.fcr0
);
656 DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__
, err
);
659 err
= kvm_mips_get_one_ureg(cs
, KVM_REG_MIPS_FCR_CSR
,
660 &env
->active_fpu
.fcr31
);
662 DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__
, err
);
665 restore_fp_status(env
);
669 * FPU register state is a subset of MSA vector state, so don't save FPU
670 * registers if we're emulating a CPU with MSA.
672 if (!(env
->CP0_Config3
& (1 << CP0C3_MSAP
))) {
673 /* Floating point registers */
674 for (i
= 0; i
< 32; ++i
) {
675 if (env
->CP0_Status
& (1 << CP0St_FR
)) {
676 err
= kvm_mips_get_one_ureg64(cs
, KVM_REG_MIPS_FPR_64(i
),
677 &env
->active_fpu
.fpr
[i
].d
);
679 err
= kvm_mips_get_one_ureg(cs
, KVM_REG_MIPS_FPR_32(i
),
680 &env
->active_fpu
.fpr
[i
].w
[FP_ENDIAN_IDX
]);
683 DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__
, i
, err
);
690 /* Only get MSA state if we're emulating a CPU with MSA */
691 if (env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
692 /* MSA Control Registers */
693 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_MSA_IR
,
696 DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__
, err
);
699 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_MSA_CSR
,
700 &env
->active_tc
.msacsr
);
702 DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__
, err
);
705 restore_msa_fp_status(env
);
708 /* Vector registers (includes FP registers) */
709 for (i
= 0; i
< 32; ++i
) {
710 /* Big endian MSA not supported by QEMU yet anyway */
711 err
= kvm_mips_get_one_reg64(cs
, KVM_REG_MIPS_VEC_128(i
),
712 env
->active_fpu
.fpr
[i
].wr
.d
);
714 DPRINTF("%s: Failed to get VEC%u (%d)\n", __func__
, i
, err
);
724 static int kvm_mips_put_cp0_registers(CPUState
*cs
, int level
)
726 MIPSCPU
*cpu
= MIPS_CPU(cs
);
727 CPUMIPSState
*env
= &cpu
->env
;
732 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_INDEX
, &env
->CP0_Index
);
734 DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__
, err
);
737 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_CONTEXT
,
740 DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__
, err
);
743 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_USERLOCAL
,
744 &env
->active_tc
.CP0_UserLocal
);
746 DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__
, err
);
749 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_PAGEMASK
,
752 DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__
, err
);
755 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_WIRED
, &env
->CP0_Wired
);
757 DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__
, err
);
760 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_HWRENA
, &env
->CP0_HWREna
);
762 DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__
, err
);
765 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_BADVADDR
,
768 DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__
, err
);
772 /* If VM clock stopped then state will be restored when it is restarted */
773 if (runstate_is_running()) {
774 err
= kvm_mips_restore_count(cs
);
780 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_ENTRYHI
,
783 DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__
, err
);
786 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_COMPARE
,
789 DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__
, err
);
792 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_STATUS
, &env
->CP0_Status
);
794 DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__
, err
);
797 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_EPC
, &env
->CP0_EPC
);
799 DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__
, err
);
802 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_PRID
, &env
->CP0_PRid
);
804 DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__
, err
);
807 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG
,
809 KVM_REG_MIPS_CP0_CONFIG_MASK
);
811 DPRINTF("%s: Failed to change CP0_CONFIG (%d)\n", __func__
, err
);
814 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG1
,
816 KVM_REG_MIPS_CP0_CONFIG1_MASK
);
818 DPRINTF("%s: Failed to change CP0_CONFIG1 (%d)\n", __func__
, err
);
821 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG2
,
823 KVM_REG_MIPS_CP0_CONFIG2_MASK
);
825 DPRINTF("%s: Failed to change CP0_CONFIG2 (%d)\n", __func__
, err
);
828 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG3
,
830 KVM_REG_MIPS_CP0_CONFIG3_MASK
);
832 DPRINTF("%s: Failed to change CP0_CONFIG3 (%d)\n", __func__
, err
);
835 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG4
,
837 KVM_REG_MIPS_CP0_CONFIG4_MASK
);
839 DPRINTF("%s: Failed to change CP0_CONFIG4 (%d)\n", __func__
, err
);
842 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG5
,
844 KVM_REG_MIPS_CP0_CONFIG5_MASK
);
846 DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__
, err
);
849 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_ERROREPC
,
852 DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__
, err
);
859 static int kvm_mips_get_cp0_registers(CPUState
*cs
)
861 MIPSCPU
*cpu
= MIPS_CPU(cs
);
862 CPUMIPSState
*env
= &cpu
->env
;
865 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_INDEX
, &env
->CP0_Index
);
867 DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__
, err
);
870 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_CONTEXT
,
873 DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__
, err
);
876 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_USERLOCAL
,
877 &env
->active_tc
.CP0_UserLocal
);
879 DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__
, err
);
882 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_PAGEMASK
,
885 DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__
, err
);
888 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_WIRED
, &env
->CP0_Wired
);
890 DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__
, err
);
893 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_HWRENA
, &env
->CP0_HWREna
);
895 DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__
, err
);
898 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_BADVADDR
,
901 DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__
, err
);
904 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_ENTRYHI
,
907 DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__
, err
);
910 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_COMPARE
,
913 DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__
, err
);
916 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_STATUS
, &env
->CP0_Status
);
918 DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__
, err
);
922 /* If VM clock stopped then state was already saved when it was stopped */
923 if (runstate_is_running()) {
924 err
= kvm_mips_save_count(cs
);
930 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_EPC
, &env
->CP0_EPC
);
932 DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__
, err
);
935 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_PRID
, &env
->CP0_PRid
);
937 DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__
, err
);
940 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG
, &env
->CP0_Config0
);
942 DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__
, err
);
945 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG1
, &env
->CP0_Config1
);
947 DPRINTF("%s: Failed to get CP0_CONFIG1 (%d)\n", __func__
, err
);
950 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG2
, &env
->CP0_Config2
);
952 DPRINTF("%s: Failed to get CP0_CONFIG2 (%d)\n", __func__
, err
);
955 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG3
, &env
->CP0_Config3
);
957 DPRINTF("%s: Failed to get CP0_CONFIG3 (%d)\n", __func__
, err
);
960 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG4
, &env
->CP0_Config4
);
962 DPRINTF("%s: Failed to get CP0_CONFIG4 (%d)\n", __func__
, err
);
965 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG5
, &env
->CP0_Config5
);
967 DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__
, err
);
970 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_ERROREPC
,
973 DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__
, err
);
980 int kvm_arch_put_registers(CPUState
*cs
, int level
)
982 MIPSCPU
*cpu
= MIPS_CPU(cs
);
983 CPUMIPSState
*env
= &cpu
->env
;
984 struct kvm_regs regs
;
988 /* Set the registers based on QEMU's view of things */
989 for (i
= 0; i
< 32; i
++) {
990 regs
.gpr
[i
] = (int64_t)(target_long
)env
->active_tc
.gpr
[i
];
993 regs
.hi
= (int64_t)(target_long
)env
->active_tc
.HI
[0];
994 regs
.lo
= (int64_t)(target_long
)env
->active_tc
.LO
[0];
995 regs
.pc
= (int64_t)(target_long
)env
->active_tc
.PC
;
997 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_REGS
, ®s
);
1003 ret
= kvm_mips_put_cp0_registers(cs
, level
);
1008 ret
= kvm_mips_put_fpu_registers(cs
, level
);
1016 int kvm_arch_get_registers(CPUState
*cs
)
1018 MIPSCPU
*cpu
= MIPS_CPU(cs
);
1019 CPUMIPSState
*env
= &cpu
->env
;
1021 struct kvm_regs regs
;
1024 /* Get the current register set as KVM seems it */
1025 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
1031 for (i
= 0; i
< 32; i
++) {
1032 env
->active_tc
.gpr
[i
] = regs
.gpr
[i
];
1035 env
->active_tc
.HI
[0] = regs
.hi
;
1036 env
->active_tc
.LO
[0] = regs
.lo
;
1037 env
->active_tc
.PC
= regs
.pc
;
1039 kvm_mips_get_cp0_registers(cs
);
1040 kvm_mips_get_fpu_registers(cs
);
1045 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
1046 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
1051 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
1052 int vector
, PCIDevice
*dev
)
1057 int kvm_arch_release_virq_post(int virq
)
1062 int kvm_arch_msi_data_to_gsi(uint32_t data
)