include/hw/pci-host/apb.h

   1 #ifndef PCI_HOST_APB_H
   2 #define PCI_HOST_APB_H
   3
   4 #include "qemu-common.h"
   5 #include "hw/pci/pci_host.h"
   6
   7 #define IOMMU_NREGS             3
   8
   9 #define IOMMU_PAGE_SIZE_8K      (1ULL << 13)
  10 #define IOMMU_PAGE_MASK_8K      (~(IOMMU_PAGE_SIZE_8K - 1))
  11 #define IOMMU_PAGE_SIZE_64K     (1ULL << 16)
  12 #define IOMMU_PAGE_MASK_64K     (~(IOMMU_PAGE_SIZE_64K - 1))
  13
  14 #define IOMMU_CTRL              0x0
  15 #define IOMMU_CTRL_TBW_SIZE     (1ULL << 2)
  16 #define IOMMU_CTRL_MMU_EN       (1ULL)
  17
  18 #define IOMMU_CTRL_TSB_SHIFT    16
  19
  20 #define IOMMU_BASE              0x8
  21 #define IOMMU_FLUSH             0x10
  22
  23 #define IOMMU_TTE_DATA_V        (1ULL << 63)
  24 #define IOMMU_TTE_DATA_SIZE     (1ULL << 61)
  25 #define IOMMU_TTE_DATA_W        (1ULL << 1)
  26
  27 #define IOMMU_TTE_PHYS_MASK_8K  0x1ffffffe000ULL
  28 #define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
  29
  30 #define IOMMU_TSB_8K_OFFSET_MASK_8M    0x00000000007fe000ULL
  31 #define IOMMU_TSB_8K_OFFSET_MASK_16M   0x0000000000ffe000ULL
  32 #define IOMMU_TSB_8K_OFFSET_MASK_32M   0x0000000001ffe000ULL
  33 #define IOMMU_TSB_8K_OFFSET_MASK_64M   0x0000000003ffe000ULL
  34 #define IOMMU_TSB_8K_OFFSET_MASK_128M  0x0000000007ffe000ULL
  35 #define IOMMU_TSB_8K_OFFSET_MASK_256M  0x000000000fffe000ULL
  36 #define IOMMU_TSB_8K_OFFSET_MASK_512M  0x000000001fffe000ULL
  37 #define IOMMU_TSB_8K_OFFSET_MASK_1G    0x000000003fffe000ULL
  38
  39 #define IOMMU_TSB_64K_OFFSET_MASK_64M  0x0000000003ff0000ULL
  40 #define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
  41 #define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
  42 #define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
  43 #define IOMMU_TSB_64K_OFFSET_MASK_1G   0x000000003fff0000ULL
  44 #define IOMMU_TSB_64K_OFFSET_MASK_2G   0x000000007fff0000ULL
  45
  46 typedef struct IOMMUState {
  47     AddressSpace iommu_as;
  48     IOMMUMemoryRegion iommu;
  49
  50     uint64_t regs[IOMMU_NREGS];
  51 } IOMMUState;
  52
  53 #define MAX_IVEC 0x40
  54
  55 #define TYPE_APB "pbm"
  56
  57 #define APB_DEVICE(obj) \
  58     OBJECT_CHECK(APBState, (obj), TYPE_APB)
  59
  60 #define TYPE_APB_IOMMU_MEMORY_REGION "pbm-iommu-memory-region"
  61
  62 typedef struct APBState {
  63     PCIHostState parent_obj;
  64
  65     MemoryRegion apb_config;
  66     MemoryRegion pci_config;
  67     MemoryRegion pci_mmio;
  68     MemoryRegion pci_ioport;
  69     uint64_t pci_irq_in;
  70     IOMMUState iommu;
  71     PCIBridge *bridgeA;
  72     PCIBridge *bridgeB;
  73     uint32_t pci_control[16];
  74     uint32_t pci_irq_map[8];
  75     uint32_t pci_err_irq_map[4];
  76     uint32_t obio_irq_map[32];
  77     qemu_irq *pbm_irqs;
  78     qemu_irq ivec_irqs[MAX_IVEC];
  79     unsigned int irq_request;
  80     uint32_t reset_control;
  81     unsigned int nr_resets;
  82 } APBState;
  83
  84 typedef struct PBMPCIBridge {
  85     /*< private >*/
  86     PCIBridge parent_obj;
  87
  88     /* Is this busA with in-built devices (ebus)? */
  89     bool busA;
  90 } PBMPCIBridge;
  91
  92 #define TYPE_PBM_PCI_BRIDGE "pbm-bridge"
  93 #define PBM_PCI_BRIDGE(obj) \
  94     OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
  95
  96 APBState *pci_apb_init(hwaddr special_base,
  97                        hwaddr mem_base);
  98 #endif