4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
7 * Copyright 2016 IBM Corp.
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
16 #include "exec/address-spaces.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
21 #include "qemu/module.h"
22 #include "qemu/error-report.h"
23 #include "hw/i2c/aspeed_i2c.h"
25 #include "sysemu/sysemu.h"
27 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
29 static const hwaddr aspeed_soc_ast2400_memmap
[] = {
30 [ASPEED_IOMEM
] = 0x1E600000,
31 [ASPEED_FMC
] = 0x1E620000,
32 [ASPEED_SPI1
] = 0x1E630000,
33 [ASPEED_VIC
] = 0x1E6C0000,
34 [ASPEED_SDMC
] = 0x1E6E0000,
35 [ASPEED_SCU
] = 0x1E6E2000,
36 [ASPEED_XDMA
] = 0x1E6E7000,
37 [ASPEED_ADC
] = 0x1E6E9000,
38 [ASPEED_SRAM
] = 0x1E720000,
39 [ASPEED_GPIO
] = 0x1E780000,
40 [ASPEED_RTC
] = 0x1E781000,
41 [ASPEED_TIMER1
] = 0x1E782000,
42 [ASPEED_WDT
] = 0x1E785000,
43 [ASPEED_PWM
] = 0x1E786000,
44 [ASPEED_LPC
] = 0x1E789000,
45 [ASPEED_IBT
] = 0x1E789140,
46 [ASPEED_I2C
] = 0x1E78A000,
47 [ASPEED_ETH1
] = 0x1E660000,
48 [ASPEED_ETH2
] = 0x1E680000,
49 [ASPEED_UART1
] = 0x1E783000,
50 [ASPEED_UART5
] = 0x1E784000,
51 [ASPEED_VUART
] = 0x1E787000,
52 [ASPEED_SDRAM
] = 0x40000000,
55 static const hwaddr aspeed_soc_ast2500_memmap
[] = {
56 [ASPEED_IOMEM
] = 0x1E600000,
57 [ASPEED_FMC
] = 0x1E620000,
58 [ASPEED_SPI1
] = 0x1E630000,
59 [ASPEED_SPI2
] = 0x1E631000,
60 [ASPEED_VIC
] = 0x1E6C0000,
61 [ASPEED_SDMC
] = 0x1E6E0000,
62 [ASPEED_SCU
] = 0x1E6E2000,
63 [ASPEED_XDMA
] = 0x1E6E7000,
64 [ASPEED_ADC
] = 0x1E6E9000,
65 [ASPEED_SRAM
] = 0x1E720000,
66 [ASPEED_GPIO
] = 0x1E780000,
67 [ASPEED_RTC
] = 0x1E781000,
68 [ASPEED_TIMER1
] = 0x1E782000,
69 [ASPEED_WDT
] = 0x1E785000,
70 [ASPEED_PWM
] = 0x1E786000,
71 [ASPEED_LPC
] = 0x1E789000,
72 [ASPEED_IBT
] = 0x1E789140,
73 [ASPEED_I2C
] = 0x1E78A000,
74 [ASPEED_ETH1
] = 0x1E660000,
75 [ASPEED_ETH2
] = 0x1E680000,
76 [ASPEED_UART1
] = 0x1E783000,
77 [ASPEED_UART5
] = 0x1E784000,
78 [ASPEED_VUART
] = 0x1E787000,
79 [ASPEED_SDRAM
] = 0x80000000,
82 static const int aspeed_soc_ast2400_irqmap
[] = {
100 [ASPEED_TIMER6
] = 37,
101 [ASPEED_TIMER7
] = 38,
102 [ASPEED_TIMER8
] = 39,
106 [ASPEED_IBT
] = 8, /* LPC */
113 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
115 static const AspeedSoCInfo aspeed_socs
[] = {
117 .name
= "ast2400-a1",
118 .cpu_type
= ARM_CPU_TYPE_NAME("arm926"),
119 .silicon_rev
= AST2400_A1_SILICON_REV
,
123 .irqmap
= aspeed_soc_ast2400_irqmap
,
124 .memmap
= aspeed_soc_ast2400_memmap
,
127 .name
= "ast2500-a1",
128 .cpu_type
= ARM_CPU_TYPE_NAME("arm1176"),
129 .silicon_rev
= AST2500_A1_SILICON_REV
,
133 .irqmap
= aspeed_soc_ast2500_irqmap
,
134 .memmap
= aspeed_soc_ast2500_memmap
,
139 static qemu_irq
aspeed_soc_get_irq(AspeedSoCState
*s
, int ctrl
)
141 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
143 return qdev_get_gpio_in(DEVICE(&s
->vic
), sc
->info
->irqmap
[ctrl
]);
146 static void aspeed_soc_init(Object
*obj
)
148 AspeedSoCState
*s
= ASPEED_SOC(obj
);
149 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
154 if (sscanf(sc
->info
->name
, "%7s", socname
) != 1) {
155 g_assert_not_reached();
158 for (i
= 0; i
< sc
->info
->num_cpus
; i
++) {
159 object_initialize_child(obj
, "cpu[*]", OBJECT(&s
->cpu
[i
]),
160 sizeof(s
->cpu
[i
]), sc
->info
->cpu_type
,
164 snprintf(typename
, sizeof(typename
), "aspeed.scu-%s", socname
);
165 sysbus_init_child_obj(obj
, "scu", OBJECT(&s
->scu
), sizeof(s
->scu
),
167 qdev_prop_set_uint32(DEVICE(&s
->scu
), "silicon-rev",
168 sc
->info
->silicon_rev
);
169 object_property_add_alias(obj
, "hw-strap1", OBJECT(&s
->scu
),
170 "hw-strap1", &error_abort
);
171 object_property_add_alias(obj
, "hw-strap2", OBJECT(&s
->scu
),
172 "hw-strap2", &error_abort
);
173 object_property_add_alias(obj
, "hw-prot-key", OBJECT(&s
->scu
),
174 "hw-prot-key", &error_abort
);
176 sysbus_init_child_obj(obj
, "vic", OBJECT(&s
->vic
), sizeof(s
->vic
),
179 sysbus_init_child_obj(obj
, "rtc", OBJECT(&s
->rtc
), sizeof(s
->rtc
),
182 sysbus_init_child_obj(obj
, "timerctrl", OBJECT(&s
->timerctrl
),
183 sizeof(s
->timerctrl
), TYPE_ASPEED_TIMER
);
184 object_property_add_const_link(OBJECT(&s
->timerctrl
), "scu",
185 OBJECT(&s
->scu
), &error_abort
);
187 sysbus_init_child_obj(obj
, "i2c", OBJECT(&s
->i2c
), sizeof(s
->i2c
),
190 snprintf(typename
, sizeof(typename
), "aspeed.fmc-%s", socname
);
191 sysbus_init_child_obj(obj
, "fmc", OBJECT(&s
->fmc
), sizeof(s
->fmc
),
193 object_property_add_alias(obj
, "num-cs", OBJECT(&s
->fmc
), "num-cs",
195 object_property_add_alias(obj
, "dram", OBJECT(&s
->fmc
), "dram",
198 for (i
= 0; i
< sc
->info
->spis_num
; i
++) {
199 snprintf(typename
, sizeof(typename
), "aspeed.spi%d-%s", i
+ 1, socname
);
200 sysbus_init_child_obj(obj
, "spi[*]", OBJECT(&s
->spi
[i
]),
201 sizeof(s
->spi
[i
]), typename
);
204 sysbus_init_child_obj(obj
, "sdmc", OBJECT(&s
->sdmc
), sizeof(s
->sdmc
),
206 qdev_prop_set_uint32(DEVICE(&s
->sdmc
), "silicon-rev",
207 sc
->info
->silicon_rev
);
208 object_property_add_alias(obj
, "ram-size", OBJECT(&s
->sdmc
),
209 "ram-size", &error_abort
);
210 object_property_add_alias(obj
, "max-ram-size", OBJECT(&s
->sdmc
),
211 "max-ram-size", &error_abort
);
213 for (i
= 0; i
< sc
->info
->wdts_num
; i
++) {
214 sysbus_init_child_obj(obj
, "wdt[*]", OBJECT(&s
->wdt
[i
]),
215 sizeof(s
->wdt
[i
]), TYPE_ASPEED_WDT
);
216 qdev_prop_set_uint32(DEVICE(&s
->wdt
[i
]), "silicon-rev",
217 sc
->info
->silicon_rev
);
218 object_property_add_const_link(OBJECT(&s
->wdt
[i
]), "scu",
219 OBJECT(&s
->scu
), &error_abort
);
222 for (i
= 0; i
< ASPEED_MACS_NUM
; i
++) {
223 sysbus_init_child_obj(obj
, "ftgmac100[*]", OBJECT(&s
->ftgmac100
[i
]),
224 sizeof(s
->ftgmac100
[i
]), TYPE_FTGMAC100
);
227 sysbus_init_child_obj(obj
, "xdma", OBJECT(&s
->xdma
), sizeof(s
->xdma
),
230 snprintf(typename
, sizeof(typename
), "aspeed.gpio-%s", socname
);
231 sysbus_init_child_obj(obj
, "gpio", OBJECT(&s
->gpio
), sizeof(s
->gpio
),
235 static void aspeed_soc_realize(DeviceState
*dev
, Error
**errp
)
238 AspeedSoCState
*s
= ASPEED_SOC(dev
);
239 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
240 Error
*err
= NULL
, *local_err
= NULL
;
243 create_unimplemented_device("aspeed_soc.io", sc
->info
->memmap
[ASPEED_IOMEM
],
244 ASPEED_SOC_IOMEM_SIZE
);
246 if (s
->num_cpus
> sc
->info
->num_cpus
) {
247 warn_report("%s: invalid number of CPUs %d, using default %d",
248 sc
->info
->name
, s
->num_cpus
, sc
->info
->num_cpus
);
249 s
->num_cpus
= sc
->info
->num_cpus
;
253 for (i
= 0; i
< s
->num_cpus
; i
++) {
254 object_property_set_bool(OBJECT(&s
->cpu
[i
]), true, "realized", &err
);
256 error_propagate(errp
, err
);
262 memory_region_init_ram(&s
->sram
, OBJECT(dev
), "aspeed.sram",
263 sc
->info
->sram_size
, &err
);
265 error_propagate(errp
, err
);
268 memory_region_add_subregion(get_system_memory(),
269 sc
->info
->memmap
[ASPEED_SRAM
], &s
->sram
);
272 object_property_set_bool(OBJECT(&s
->scu
), true, "realized", &err
);
274 error_propagate(errp
, err
);
277 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->scu
), 0, sc
->info
->memmap
[ASPEED_SCU
]);
280 object_property_set_bool(OBJECT(&s
->vic
), true, "realized", &err
);
282 error_propagate(errp
, err
);
285 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->vic
), 0, sc
->info
->memmap
[ASPEED_VIC
]);
286 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 0,
287 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_IRQ
));
288 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 1,
289 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_FIQ
));
292 object_property_set_bool(OBJECT(&s
->rtc
), true, "realized", &err
);
294 error_propagate(errp
, err
);
297 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->rtc
), 0, sc
->info
->memmap
[ASPEED_RTC
]);
298 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->rtc
), 0,
299 aspeed_soc_get_irq(s
, ASPEED_RTC
));
302 object_property_set_bool(OBJECT(&s
->timerctrl
), true, "realized", &err
);
304 error_propagate(errp
, err
);
307 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->timerctrl
), 0,
308 sc
->info
->memmap
[ASPEED_TIMER1
]);
309 for (i
= 0; i
< ASPEED_TIMER_NR_TIMERS
; i
++) {
310 qemu_irq irq
= aspeed_soc_get_irq(s
, ASPEED_TIMER1
+ i
);
311 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timerctrl
), i
, irq
);
314 /* UART - attach an 8250 to the IO space as our UART5 */
316 qemu_irq uart5
= aspeed_soc_get_irq(s
, ASPEED_UART5
);
317 serial_mm_init(get_system_memory(), sc
->info
->memmap
[ASPEED_UART5
], 2,
318 uart5
, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN
);
322 object_property_set_bool(OBJECT(&s
->i2c
), true, "realized", &err
);
324 error_propagate(errp
, err
);
327 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
), 0, sc
->info
->memmap
[ASPEED_I2C
]);
328 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
), 0,
329 aspeed_soc_get_irq(s
, ASPEED_I2C
));
331 /* FMC, The number of CS is set at the board level */
332 object_property_set_int(OBJECT(&s
->fmc
), sc
->info
->memmap
[ASPEED_SDRAM
],
335 error_propagate(errp
, err
);
338 object_property_set_bool(OBJECT(&s
->fmc
), true, "realized", &err
);
340 error_propagate(errp
, err
);
343 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 0, sc
->info
->memmap
[ASPEED_FMC
]);
344 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 1,
345 s
->fmc
.ctrl
->flash_window_base
);
346 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->fmc
), 0,
347 aspeed_soc_get_irq(s
, ASPEED_FMC
));
350 for (i
= 0; i
< sc
->info
->spis_num
; i
++) {
351 object_property_set_int(OBJECT(&s
->spi
[i
]), 1, "num-cs", &err
);
352 object_property_set_bool(OBJECT(&s
->spi
[i
]), true, "realized",
354 error_propagate(&err
, local_err
);
356 error_propagate(errp
, err
);
359 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
360 sc
->info
->memmap
[ASPEED_SPI1
+ i
]);
361 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 1,
362 s
->spi
[i
].ctrl
->flash_window_base
);
365 /* SDMC - SDRAM Memory Controller */
366 object_property_set_bool(OBJECT(&s
->sdmc
), true, "realized", &err
);
368 error_propagate(errp
, err
);
371 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdmc
), 0, sc
->info
->memmap
[ASPEED_SDMC
]);
374 for (i
= 0; i
< sc
->info
->wdts_num
; i
++) {
375 object_property_set_bool(OBJECT(&s
->wdt
[i
]), true, "realized", &err
);
377 error_propagate(errp
, err
);
380 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0,
381 sc
->info
->memmap
[ASPEED_WDT
] + i
* 0x20);
385 for (i
= 0; i
< nb_nics
; i
++) {
386 qdev_set_nic_properties(DEVICE(&s
->ftgmac100
[i
]), &nd_table
[i
]);
387 object_property_set_bool(OBJECT(&s
->ftgmac100
[i
]), true, "aspeed",
389 object_property_set_bool(OBJECT(&s
->ftgmac100
[i
]), true, "realized",
391 error_propagate(&err
, local_err
);
393 error_propagate(errp
, err
);
396 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
397 sc
->info
->memmap
[ASPEED_ETH1
+ i
]);
398 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
399 aspeed_soc_get_irq(s
, ASPEED_ETH1
+ i
));
403 object_property_set_bool(OBJECT(&s
->xdma
), true, "realized", &err
);
405 error_propagate(errp
, err
);
408 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->xdma
), 0,
409 sc
->info
->memmap
[ASPEED_XDMA
]);
410 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->xdma
), 0,
411 aspeed_soc_get_irq(s
, ASPEED_XDMA
));
414 object_property_set_bool(OBJECT(&s
->gpio
), true, "realized", &err
);
416 error_propagate(errp
, err
);
419 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
), 0, sc
->info
->memmap
[ASPEED_GPIO
]);
420 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
), 0,
421 aspeed_soc_get_irq(s
, ASPEED_GPIO
));
423 static Property aspeed_soc_properties
[] = {
424 DEFINE_PROP_UINT32("num-cpus", AspeedSoCState
, num_cpus
, 0),
425 DEFINE_PROP_END_OF_LIST(),
428 static void aspeed_soc_class_init(ObjectClass
*oc
, void *data
)
430 DeviceClass
*dc
= DEVICE_CLASS(oc
);
431 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
433 sc
->info
= (AspeedSoCInfo
*) data
;
434 dc
->realize
= aspeed_soc_realize
;
435 /* Reason: Uses serial_hds and nd_table in realize() directly */
436 dc
->user_creatable
= false;
437 dc
->props
= aspeed_soc_properties
;
440 static const TypeInfo aspeed_soc_type_info
= {
441 .name
= TYPE_ASPEED_SOC
,
442 .parent
= TYPE_DEVICE
,
443 .instance_init
= aspeed_soc_init
,
444 .instance_size
= sizeof(AspeedSoCState
),
445 .class_size
= sizeof(AspeedSoCClass
),
449 static void aspeed_soc_register_types(void)
453 type_register_static(&aspeed_soc_type_info
);
454 for (i
= 0; i
< ARRAY_SIZE(aspeed_socs
); ++i
) {
456 .name
= aspeed_socs
[i
].name
,
457 .parent
= TYPE_ASPEED_SOC
,
458 .class_init
= aspeed_soc_class_init
,
459 .class_data
= (void *) &aspeed_socs
[i
],
465 type_init(aspeed_soc_register_types
)