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virtio-scsi: dataplane: fail setup gracefully
[qemu/ar7.git] / hw / display / cirrus_vga.c
blob8a5b76c4038259b0098757c47189c7ddeec08fb5
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw/hw.h"
30 #include "hw/pci/pci.h"
31 #include "ui/console.h"
32 #include "ui/pixel_ops.h"
33 #include "vga_int.h"
34 #include "hw/loader.h"
35
36 /*
37 * TODO:
38 * - destination write mask support not complete (bits 5..7)
39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
43 //#define DEBUG_CIRRUS
44 //#define DEBUG_BITBLT
45
46 /***************************************
47 *
48 * definitions
49 *
50 ***************************************/
51
52 // ID
53 #define CIRRUS_ID_CLGD5422 (0x23<<2)
54 #define CIRRUS_ID_CLGD5426 (0x24<<2)
55 #define CIRRUS_ID_CLGD5424 (0x25<<2)
56 #define CIRRUS_ID_CLGD5428 (0x26<<2)
57 #define CIRRUS_ID_CLGD5430 (0x28<<2)
58 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
59 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
60 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
61
62 // sequencer 0x07
63 #define CIRRUS_SR7_BPP_VGA 0x00
64 #define CIRRUS_SR7_BPP_SVGA 0x01
65 #define CIRRUS_SR7_BPP_MASK 0x0e
66 #define CIRRUS_SR7_BPP_8 0x00
67 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
68 #define CIRRUS_SR7_BPP_24 0x04
69 #define CIRRUS_SR7_BPP_16 0x06
70 #define CIRRUS_SR7_BPP_32 0x08
71 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
72
73 // sequencer 0x0f
74 #define CIRRUS_MEMSIZE_512k 0x08
75 #define CIRRUS_MEMSIZE_1M 0x10
76 #define CIRRUS_MEMSIZE_2M 0x18
77 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
78
79 // sequencer 0x12
80 #define CIRRUS_CURSOR_SHOW 0x01
81 #define CIRRUS_CURSOR_HIDDENPEL 0x02
82 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
83
84 // sequencer 0x17
85 #define CIRRUS_BUSTYPE_VLBFAST 0x10
86 #define CIRRUS_BUSTYPE_PCI 0x20
87 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
88 #define CIRRUS_BUSTYPE_ISA 0x38
89 #define CIRRUS_MMIO_ENABLE 0x04
90 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
91 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
92
93 // control 0x0b
94 #define CIRRUS_BANKING_DUAL 0x01
95 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
96
97 // control 0x30
98 #define CIRRUS_BLTMODE_BACKWARDS 0x01
99 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
100 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
101 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
102 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
103 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
104 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
105 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
106 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
107 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
108 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
109
110 // control 0x31
111 #define CIRRUS_BLT_BUSY 0x01
112 #define CIRRUS_BLT_START 0x02
113 #define CIRRUS_BLT_RESET 0x04
114 #define CIRRUS_BLT_FIFOUSED 0x10
115 #define CIRRUS_BLT_AUTOSTART 0x80
116
117 // control 0x32
118 #define CIRRUS_ROP_0 0x00
119 #define CIRRUS_ROP_SRC_AND_DST 0x05
120 #define CIRRUS_ROP_NOP 0x06
121 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
122 #define CIRRUS_ROP_NOTDST 0x0b
123 #define CIRRUS_ROP_SRC 0x0d
124 #define CIRRUS_ROP_1 0x0e
125 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
126 #define CIRRUS_ROP_SRC_XOR_DST 0x59
127 #define CIRRUS_ROP_SRC_OR_DST 0x6d
128 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
129 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
130 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
131 #define CIRRUS_ROP_NOTSRC 0xd0
132 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
133 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
134
135 #define CIRRUS_ROP_NOP_INDEX 2
136 #define CIRRUS_ROP_SRC_INDEX 5
137
138 // control 0x33
139 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
140 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
141 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
142
143 // memory-mapped IO
144 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
145 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
146 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
147 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
148 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
149 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
150 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
151 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
152 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
153 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
154 #define CIRRUS_MMIO_BLTROP 0x1a // byte
155 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
156 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
157 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
158 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
159 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
160 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
161 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
162 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
163 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
166 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
167 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
168 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
169 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
170 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
171 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
172 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
173
174 #define CIRRUS_PNPMMIO_SIZE 0x1000
175
176 #define BLTUNSAFE(s) \
177 ( \
178 ( /* check dst is within bounds */ \
179 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
180 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
181 (s)->vga.vram_size \
182 ) || \
183 ( /* check src is within bounds */ \
184 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
185 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
186 (s)->vga.vram_size \
187 ) \
188 )
189
190 struct CirrusVGAState;
191 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
192 uint8_t * dst, const uint8_t * src,
193 int dstpitch, int srcpitch,
194 int bltwidth, int bltheight);
195 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
196 uint8_t *dst, int dst_pitch, int width, int height);
197
198 typedef struct CirrusVGAState {
199 VGACommonState vga;
200
201 MemoryRegion cirrus_vga_io;
202 MemoryRegion cirrus_linear_io;
203 MemoryRegion cirrus_linear_bitblt_io;
204 MemoryRegion cirrus_mmio_io;
205 MemoryRegion pci_bar;
206 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
207 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
208 MemoryRegion low_mem; /* always mapped, overridden by: */
209 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
210 uint32_t cirrus_addr_mask;
211 uint32_t linear_mmio_mask;
212 uint8_t cirrus_shadow_gr0;
213 uint8_t cirrus_shadow_gr1;
214 uint8_t cirrus_hidden_dac_lockindex;
215 uint8_t cirrus_hidden_dac_data;
216 uint32_t cirrus_bank_base[2];
217 uint32_t cirrus_bank_limit[2];
218 uint8_t cirrus_hidden_palette[48];
219 uint32_t hw_cursor_x;
220 uint32_t hw_cursor_y;
221 int cirrus_blt_pixelwidth;
222 int cirrus_blt_width;
223 int cirrus_blt_height;
224 int cirrus_blt_dstpitch;
225 int cirrus_blt_srcpitch;
226 uint32_t cirrus_blt_fgcol;
227 uint32_t cirrus_blt_bgcol;
228 uint32_t cirrus_blt_dstaddr;
229 uint32_t cirrus_blt_srcaddr;
230 uint8_t cirrus_blt_mode;
231 uint8_t cirrus_blt_modeext;
232 cirrus_bitblt_rop_t cirrus_rop;
233 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
234 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
235 uint8_t *cirrus_srcptr;
236 uint8_t *cirrus_srcptr_end;
237 uint32_t cirrus_srccounter;
238 /* hwcursor display state */
239 int last_hw_cursor_size;
240 int last_hw_cursor_x;
241 int last_hw_cursor_y;
242 int last_hw_cursor_y_start;
243 int last_hw_cursor_y_end;
244 int real_vram_size; /* XXX: suppress that */
245 int device_id;
246 int bustype;
247 } CirrusVGAState;
248
249 typedef struct PCICirrusVGAState {
250 PCIDevice dev;
251 CirrusVGAState cirrus_vga;
252 } PCICirrusVGAState;
253
254 #define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga"
255 #define ISA_CIRRUS_VGA(obj) \
256 OBJECT_CHECK(ISACirrusVGAState, (obj), TYPE_ISA_CIRRUS_VGA)
257
258 typedef struct ISACirrusVGAState {
259 ISADevice parent_obj;
260
261 CirrusVGAState cirrus_vga;
262 } ISACirrusVGAState;
263
264 static uint8_t rop_to_index[256];
265
266 /***************************************
267 *
268 * prototypes.
269 *
270 ***************************************/
271
272
273 static void cirrus_bitblt_reset(CirrusVGAState *s);
274 static void cirrus_update_memory_access(CirrusVGAState *s);
275
276 /***************************************
277 *
278 * raster operations
279 *
280 ***************************************/
281
282 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
283 uint8_t *dst,const uint8_t *src,
284 int dstpitch,int srcpitch,
285 int bltwidth,int bltheight)
286 {
287 }
288
289 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
290 uint8_t *dst,
291 int dstpitch, int bltwidth,int bltheight)
292 {
293 }
294
295 #define ROP_NAME 0
296 #define ROP_FN(d, s) 0
297 #include "cirrus_vga_rop.h"
298
299 #define ROP_NAME src_and_dst
300 #define ROP_FN(d, s) (s) & (d)
301 #include "cirrus_vga_rop.h"
302
303 #define ROP_NAME src_and_notdst
304 #define ROP_FN(d, s) (s) & (~(d))
305 #include "cirrus_vga_rop.h"
306
307 #define ROP_NAME notdst
308 #define ROP_FN(d, s) ~(d)
309 #include "cirrus_vga_rop.h"
310
311 #define ROP_NAME src
312 #define ROP_FN(d, s) s
313 #include "cirrus_vga_rop.h"
314
315 #define ROP_NAME 1
316 #define ROP_FN(d, s) ~0
317 #include "cirrus_vga_rop.h"
318
319 #define ROP_NAME notsrc_and_dst
320 #define ROP_FN(d, s) (~(s)) & (d)
321 #include "cirrus_vga_rop.h"
322
323 #define ROP_NAME src_xor_dst
324 #define ROP_FN(d, s) (s) ^ (d)
325 #include "cirrus_vga_rop.h"
326
327 #define ROP_NAME src_or_dst
328 #define ROP_FN(d, s) (s) | (d)
329 #include "cirrus_vga_rop.h"
330
331 #define ROP_NAME notsrc_or_notdst
332 #define ROP_FN(d, s) (~(s)) | (~(d))
333 #include "cirrus_vga_rop.h"
334
335 #define ROP_NAME src_notxor_dst
336 #define ROP_FN(d, s) ~((s) ^ (d))
337 #include "cirrus_vga_rop.h"
338
339 #define ROP_NAME src_or_notdst
340 #define ROP_FN(d, s) (s) | (~(d))
341 #include "cirrus_vga_rop.h"
342
343 #define ROP_NAME notsrc
344 #define ROP_FN(d, s) (~(s))
345 #include "cirrus_vga_rop.h"
346
347 #define ROP_NAME notsrc_or_dst
348 #define ROP_FN(d, s) (~(s)) | (d)
349 #include "cirrus_vga_rop.h"
350
351 #define ROP_NAME notsrc_and_notdst
352 #define ROP_FN(d, s) (~(s)) & (~(d))
353 #include "cirrus_vga_rop.h"
354
355 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
356 cirrus_bitblt_rop_fwd_0,
357 cirrus_bitblt_rop_fwd_src_and_dst,
358 cirrus_bitblt_rop_nop,
359 cirrus_bitblt_rop_fwd_src_and_notdst,
360 cirrus_bitblt_rop_fwd_notdst,
361 cirrus_bitblt_rop_fwd_src,
362 cirrus_bitblt_rop_fwd_1,
363 cirrus_bitblt_rop_fwd_notsrc_and_dst,
364 cirrus_bitblt_rop_fwd_src_xor_dst,
365 cirrus_bitblt_rop_fwd_src_or_dst,
366 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
367 cirrus_bitblt_rop_fwd_src_notxor_dst,
368 cirrus_bitblt_rop_fwd_src_or_notdst,
369 cirrus_bitblt_rop_fwd_notsrc,
370 cirrus_bitblt_rop_fwd_notsrc_or_dst,
371 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
372 };
373
374 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
375 cirrus_bitblt_rop_bkwd_0,
376 cirrus_bitblt_rop_bkwd_src_and_dst,
377 cirrus_bitblt_rop_nop,
378 cirrus_bitblt_rop_bkwd_src_and_notdst,
379 cirrus_bitblt_rop_bkwd_notdst,
380 cirrus_bitblt_rop_bkwd_src,
381 cirrus_bitblt_rop_bkwd_1,
382 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
383 cirrus_bitblt_rop_bkwd_src_xor_dst,
384 cirrus_bitblt_rop_bkwd_src_or_dst,
385 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
386 cirrus_bitblt_rop_bkwd_src_notxor_dst,
387 cirrus_bitblt_rop_bkwd_src_or_notdst,
388 cirrus_bitblt_rop_bkwd_notsrc,
389 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
390 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
391 };
392
393 #define TRANSP_ROP(name) {\
394 name ## _8,\
395 name ## _16,\
396 }
397 #define TRANSP_NOP(func) {\
398 func,\
399 func,\
400 }
401
402 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
405 TRANSP_NOP(cirrus_bitblt_rop_nop),
406 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
407 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
408 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
409 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
410 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
411 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
412 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
413 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
414 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
415 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
416 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
417 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
418 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
419 };
420
421 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
424 TRANSP_NOP(cirrus_bitblt_rop_nop),
425 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
426 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
427 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
428 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
429 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
430 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
431 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
432 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
433 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
434 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
435 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
436 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
437 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
438 };
439
440 #define ROP2(name) {\
441 name ## _8,\
442 name ## _16,\
443 name ## _24,\
444 name ## _32,\
445 }
446
447 #define ROP_NOP2(func) {\
448 func,\
449 func,\
450 func,\
451 func,\
452 }
453
454 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
455 ROP2(cirrus_patternfill_0),
456 ROP2(cirrus_patternfill_src_and_dst),
457 ROP_NOP2(cirrus_bitblt_rop_nop),
458 ROP2(cirrus_patternfill_src_and_notdst),
459 ROP2(cirrus_patternfill_notdst),
460 ROP2(cirrus_patternfill_src),
461 ROP2(cirrus_patternfill_1),
462 ROP2(cirrus_patternfill_notsrc_and_dst),
463 ROP2(cirrus_patternfill_src_xor_dst),
464 ROP2(cirrus_patternfill_src_or_dst),
465 ROP2(cirrus_patternfill_notsrc_or_notdst),
466 ROP2(cirrus_patternfill_src_notxor_dst),
467 ROP2(cirrus_patternfill_src_or_notdst),
468 ROP2(cirrus_patternfill_notsrc),
469 ROP2(cirrus_patternfill_notsrc_or_dst),
470 ROP2(cirrus_patternfill_notsrc_and_notdst),
471 };
472
473 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
474 ROP2(cirrus_colorexpand_transp_0),
475 ROP2(cirrus_colorexpand_transp_src_and_dst),
476 ROP_NOP2(cirrus_bitblt_rop_nop),
477 ROP2(cirrus_colorexpand_transp_src_and_notdst),
478 ROP2(cirrus_colorexpand_transp_notdst),
479 ROP2(cirrus_colorexpand_transp_src),
480 ROP2(cirrus_colorexpand_transp_1),
481 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
482 ROP2(cirrus_colorexpand_transp_src_xor_dst),
483 ROP2(cirrus_colorexpand_transp_src_or_dst),
484 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
485 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
486 ROP2(cirrus_colorexpand_transp_src_or_notdst),
487 ROP2(cirrus_colorexpand_transp_notsrc),
488 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
489 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
490 };
491
492 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
493 ROP2(cirrus_colorexpand_0),
494 ROP2(cirrus_colorexpand_src_and_dst),
495 ROP_NOP2(cirrus_bitblt_rop_nop),
496 ROP2(cirrus_colorexpand_src_and_notdst),
497 ROP2(cirrus_colorexpand_notdst),
498 ROP2(cirrus_colorexpand_src),
499 ROP2(cirrus_colorexpand_1),
500 ROP2(cirrus_colorexpand_notsrc_and_dst),
501 ROP2(cirrus_colorexpand_src_xor_dst),
502 ROP2(cirrus_colorexpand_src_or_dst),
503 ROP2(cirrus_colorexpand_notsrc_or_notdst),
504 ROP2(cirrus_colorexpand_src_notxor_dst),
505 ROP2(cirrus_colorexpand_src_or_notdst),
506 ROP2(cirrus_colorexpand_notsrc),
507 ROP2(cirrus_colorexpand_notsrc_or_dst),
508 ROP2(cirrus_colorexpand_notsrc_and_notdst),
509 };
510
511 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
512 ROP2(cirrus_colorexpand_pattern_transp_0),
513 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
514 ROP_NOP2(cirrus_bitblt_rop_nop),
515 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
516 ROP2(cirrus_colorexpand_pattern_transp_notdst),
517 ROP2(cirrus_colorexpand_pattern_transp_src),
518 ROP2(cirrus_colorexpand_pattern_transp_1),
519 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
520 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
521 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
522 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
523 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
524 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
525 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
526 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
527 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
528 };
529
530 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
531 ROP2(cirrus_colorexpand_pattern_0),
532 ROP2(cirrus_colorexpand_pattern_src_and_dst),
533 ROP_NOP2(cirrus_bitblt_rop_nop),
534 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
535 ROP2(cirrus_colorexpand_pattern_notdst),
536 ROP2(cirrus_colorexpand_pattern_src),
537 ROP2(cirrus_colorexpand_pattern_1),
538 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
539 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
540 ROP2(cirrus_colorexpand_pattern_src_or_dst),
541 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
542 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
543 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
544 ROP2(cirrus_colorexpand_pattern_notsrc),
545 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
546 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
547 };
548
549 static const cirrus_fill_t cirrus_fill[16][4] = {
550 ROP2(cirrus_fill_0),
551 ROP2(cirrus_fill_src_and_dst),
552 ROP_NOP2(cirrus_bitblt_fill_nop),
553 ROP2(cirrus_fill_src_and_notdst),
554 ROP2(cirrus_fill_notdst),
555 ROP2(cirrus_fill_src),
556 ROP2(cirrus_fill_1),
557 ROP2(cirrus_fill_notsrc_and_dst),
558 ROP2(cirrus_fill_src_xor_dst),
559 ROP2(cirrus_fill_src_or_dst),
560 ROP2(cirrus_fill_notsrc_or_notdst),
561 ROP2(cirrus_fill_src_notxor_dst),
562 ROP2(cirrus_fill_src_or_notdst),
563 ROP2(cirrus_fill_notsrc),
564 ROP2(cirrus_fill_notsrc_or_dst),
565 ROP2(cirrus_fill_notsrc_and_notdst),
566 };
567
568 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
569 {
570 unsigned int color;
571 switch (s->cirrus_blt_pixelwidth) {
572 case 1:
573 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
574 break;
575 case 2:
576 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
577 s->cirrus_blt_fgcol = le16_to_cpu(color);
578 break;
579 case 3:
580 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
581 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
582 break;
583 default:
584 case 4:
585 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
586 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
587 s->cirrus_blt_fgcol = le32_to_cpu(color);
588 break;
589 }
590 }
591
592 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
593 {
594 unsigned int color;
595 switch (s->cirrus_blt_pixelwidth) {
596 case 1:
597 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
598 break;
599 case 2:
600 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
601 s->cirrus_blt_bgcol = le16_to_cpu(color);
602 break;
603 case 3:
604 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
605 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
606 break;
607 default:
608 case 4:
609 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
610 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
611 s->cirrus_blt_bgcol = le32_to_cpu(color);
612 break;
613 }
614 }
615
616 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
617 int off_pitch, int bytesperline,
618 int lines)
619 {
620 int y;
621 int off_cur;
622 int off_cur_end;
623
624 for (y = 0; y < lines; y++) {
625 off_cur = off_begin;
626 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
627 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
628 off_begin += off_pitch;
629 }
630 }
631
632 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
633 const uint8_t * src)
634 {
635 uint8_t *dst;
636
637 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
638
639 if (BLTUNSAFE(s))
640 return 0;
641
642 (*s->cirrus_rop) (s, dst, src,
643 s->cirrus_blt_dstpitch, 0,
644 s->cirrus_blt_width, s->cirrus_blt_height);
645 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
646 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
647 s->cirrus_blt_height);
648 return 1;
649 }
650
651 /* fill */
652
653 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
654 {
655 cirrus_fill_t rop_func;
656
657 if (BLTUNSAFE(s))
658 return 0;
659 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
660 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
661 s->cirrus_blt_dstpitch,
662 s->cirrus_blt_width, s->cirrus_blt_height);
663 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
664 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
665 s->cirrus_blt_height);
666 cirrus_bitblt_reset(s);
667 return 1;
668 }
669
670 /***************************************
671 *
672 * bitblt (video-to-video)
673 *
674 ***************************************/
675
676 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
677 {
678 return cirrus_bitblt_common_patterncopy(s,
679 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
680 s->cirrus_addr_mask));
681 }
682
683 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
684 {
685 int sx = 0, sy = 0;
686 int dx = 0, dy = 0;
687 int depth = 0;
688 int notify = 0;
689
690 /* make sure to only copy if it's a plain copy ROP */
691 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
692 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
693
694 int width, height;
695
696 depth = s->vga.get_bpp(&s->vga) / 8;
697 s->vga.get_resolution(&s->vga, &width, &height);
698
699 /* extra x, y */
700 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
701 sy = (src / ABS(s->cirrus_blt_srcpitch));
702 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
703 dy = (dst / ABS(s->cirrus_blt_dstpitch));
704
705 /* normalize width */
706 w /= depth;
707
708 /* if we're doing a backward copy, we have to adjust
709 our x/y to be the upper left corner (instead of the lower
710 right corner) */
711 if (s->cirrus_blt_dstpitch < 0) {
712 sx -= (s->cirrus_blt_width / depth) - 1;
713 dx -= (s->cirrus_blt_width / depth) - 1;
714 sy -= s->cirrus_blt_height - 1;
715 dy -= s->cirrus_blt_height - 1;
716 }
717
718 /* are we in the visible portion of memory? */
719 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
720 (sx + w) <= width && (sy + h) <= height &&
721 (dx + w) <= width && (dy + h) <= height) {
722 notify = 1;
723 }
724 }
725
726 /* we have to flush all pending changes so that the copy
727 is generated at the appropriate moment in time */
728 if (notify)
729 graphic_hw_update(s->vga.con);
730
731 (*s->cirrus_rop) (s, s->vga.vram_ptr +
732 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
733 s->vga.vram_ptr +
734 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
735 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
736 s->cirrus_blt_width, s->cirrus_blt_height);
737
738 if (notify) {
739 qemu_console_copy(s->vga.con,
740 sx, sy, dx, dy,
741 s->cirrus_blt_width / depth,
742 s->cirrus_blt_height);
743 }
744
745 /* we don't have to notify the display that this portion has
746 changed since qemu_console_copy implies this */
747
748 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
749 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
750 s->cirrus_blt_height);
751 }
752
753 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
754 {
755 if (BLTUNSAFE(s))
756 return 0;
757
758 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
759 s->cirrus_blt_srcaddr - s->vga.start_addr,
760 s->cirrus_blt_width, s->cirrus_blt_height);
761
762 return 1;
763 }
764
765 /***************************************
766 *
767 * bitblt (cpu-to-video)
768 *
769 ***************************************/
770
771 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
772 {
773 int copy_count;
774 uint8_t *end_ptr;
775
776 if (s->cirrus_srccounter > 0) {
777 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
778 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
779 the_end:
780 s->cirrus_srccounter = 0;
781 cirrus_bitblt_reset(s);
782 } else {
783 /* at least one scan line */
784 do {
785 (*s->cirrus_rop)(s, s->vga.vram_ptr +
786 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
787 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
788 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
789 s->cirrus_blt_width, 1);
790 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
791 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
792 if (s->cirrus_srccounter <= 0)
793 goto the_end;
794 /* more bytes than needed can be transferred because of
795 word alignment, so we keep them for the next line */
796 /* XXX: keep alignment to speed up transfer */
797 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
798 copy_count = s->cirrus_srcptr_end - end_ptr;
799 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
800 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
801 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
802 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
803 }
804 }
805 }
806
807 /***************************************
808 *
809 * bitblt wrapper
810 *
811 ***************************************/
812
813 static void cirrus_bitblt_reset(CirrusVGAState * s)
814 {
815 int need_update;
816
817 s->vga.gr[0x31] &=
818 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
819 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
820 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
821 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
822 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
823 s->cirrus_srccounter = 0;
824 if (!need_update)
825 return;
826 cirrus_update_memory_access(s);
827 }
828
829 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
830 {
831 int w;
832
833 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
834 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
835 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
836
837 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
838 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
839 s->cirrus_blt_srcpitch = 8;
840 } else {
841 /* XXX: check for 24 bpp */
842 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
843 }
844 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
845 } else {
846 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
847 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
848 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
849 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
850 else
851 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
852 } else {
853 /* always align input size to 32 bits */
854 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
855 }
856 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
857 }
858 s->cirrus_srcptr = s->cirrus_bltbuf;
859 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
860 cirrus_update_memory_access(s);
861 return 1;
862 }
863
864 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
865 {
866 /* XXX */
867 #ifdef DEBUG_BITBLT
868 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
869 #endif
870 return 0;
871 }
872
873 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
874 {
875 int ret;
876
877 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
878 ret = cirrus_bitblt_videotovideo_patterncopy(s);
879 } else {
880 ret = cirrus_bitblt_videotovideo_copy(s);
881 }
882 if (ret)
883 cirrus_bitblt_reset(s);
884 return ret;
885 }
886
887 static void cirrus_bitblt_start(CirrusVGAState * s)
888 {
889 uint8_t blt_rop;
890
891 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
892
893 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
894 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
895 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
896 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
897 s->cirrus_blt_dstaddr =
898 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
899 s->cirrus_blt_srcaddr =
900 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
901 s->cirrus_blt_mode = s->vga.gr[0x30];
902 s->cirrus_blt_modeext = s->vga.gr[0x33];
903 blt_rop = s->vga.gr[0x32];
904
905 #ifdef DEBUG_BITBLT
906 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
907 blt_rop,
908 s->cirrus_blt_mode,
909 s->cirrus_blt_modeext,
910 s->cirrus_blt_width,
911 s->cirrus_blt_height,
912 s->cirrus_blt_dstpitch,
913 s->cirrus_blt_srcpitch,
914 s->cirrus_blt_dstaddr,
915 s->cirrus_blt_srcaddr,
916 s->vga.gr[0x2f]);
917 #endif
918
919 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
920 case CIRRUS_BLTMODE_PIXELWIDTH8:
921 s->cirrus_blt_pixelwidth = 1;
922 break;
923 case CIRRUS_BLTMODE_PIXELWIDTH16:
924 s->cirrus_blt_pixelwidth = 2;
925 break;
926 case CIRRUS_BLTMODE_PIXELWIDTH24:
927 s->cirrus_blt_pixelwidth = 3;
928 break;
929 case CIRRUS_BLTMODE_PIXELWIDTH32:
930 s->cirrus_blt_pixelwidth = 4;
931 break;
932 default:
933 #ifdef DEBUG_BITBLT
934 printf("cirrus: bitblt - pixel width is unknown\n");
935 #endif
936 goto bitblt_ignore;
937 }
938 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
939
940 if ((s->
941 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
942 CIRRUS_BLTMODE_MEMSYSDEST))
943 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
944 #ifdef DEBUG_BITBLT
945 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
946 #endif
947 goto bitblt_ignore;
948 }
949
950 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
951 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
952 CIRRUS_BLTMODE_TRANSPARENTCOMP |
953 CIRRUS_BLTMODE_PATTERNCOPY |
954 CIRRUS_BLTMODE_COLOREXPAND)) ==
955 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
956 cirrus_bitblt_fgcol(s);
957 cirrus_bitblt_solidfill(s, blt_rop);
958 } else {
959 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
960 CIRRUS_BLTMODE_PATTERNCOPY)) ==
961 CIRRUS_BLTMODE_COLOREXPAND) {
962
963 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
964 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
965 cirrus_bitblt_bgcol(s);
966 else
967 cirrus_bitblt_fgcol(s);
968 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
969 } else {
970 cirrus_bitblt_fgcol(s);
971 cirrus_bitblt_bgcol(s);
972 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
973 }
974 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
975 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
976 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
977 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
978 cirrus_bitblt_bgcol(s);
979 else
980 cirrus_bitblt_fgcol(s);
981 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
982 } else {
983 cirrus_bitblt_fgcol(s);
984 cirrus_bitblt_bgcol(s);
985 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
986 }
987 } else {
988 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
989 }
990 } else {
991 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
992 if (s->cirrus_blt_pixelwidth > 2) {
993 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
994 goto bitblt_ignore;
995 }
996 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
997 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
998 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
999 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1000 } else {
1001 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1002 }
1003 } else {
1004 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1005 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1006 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1007 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1008 } else {
1009 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1010 }
1011 }
1012 }
1013 // setup bitblt engine.
1014 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1015 if (!cirrus_bitblt_cputovideo(s))
1016 goto bitblt_ignore;
1017 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1018 if (!cirrus_bitblt_videotocpu(s))
1019 goto bitblt_ignore;
1020 } else {
1021 if (!cirrus_bitblt_videotovideo(s))
1022 goto bitblt_ignore;
1023 }
1024 }
1025 return;
1026 bitblt_ignore:;
1027 cirrus_bitblt_reset(s);
1028 }
1029
1030 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1031 {
1032 unsigned old_value;
1033
1034 old_value = s->vga.gr[0x31];
1035 s->vga.gr[0x31] = reg_value;
1036
1037 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1038 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1039 cirrus_bitblt_reset(s);
1040 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1041 ((reg_value & CIRRUS_BLT_START) != 0)) {
1042 cirrus_bitblt_start(s);
1043 }
1044 }
1045
1046
1047 /***************************************
1048 *
1049 * basic parameters
1050 *
1051 ***************************************/
1052
1053 static void cirrus_get_offsets(VGACommonState *s1,
1054 uint32_t *pline_offset,
1055 uint32_t *pstart_addr,
1056 uint32_t *pline_compare)
1057 {
1058 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1059 uint32_t start_addr, line_offset, line_compare;
1060
1061 line_offset = s->vga.cr[0x13]
1062 | ((s->vga.cr[0x1b] & 0x10) << 4);
1063 line_offset <<= 3;
1064 *pline_offset = line_offset;
1065
1066 start_addr = (s->vga.cr[0x0c] << 8)
1067 | s->vga.cr[0x0d]
1068 | ((s->vga.cr[0x1b] & 0x01) << 16)
1069 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1070 | ((s->vga.cr[0x1d] & 0x80) << 12);
1071 *pstart_addr = start_addr;
1072
1073 line_compare = s->vga.cr[0x18] |
1074 ((s->vga.cr[0x07] & 0x10) << 4) |
1075 ((s->vga.cr[0x09] & 0x40) << 3);
1076 *pline_compare = line_compare;
1077 }
1078
1079 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1080 {
1081 uint32_t ret = 16;
1082
1083 switch (s->cirrus_hidden_dac_data & 0xf) {
1084 case 0:
1085 ret = 15;
1086 break; /* Sierra HiColor */
1087 case 1:
1088 ret = 16;
1089 break; /* XGA HiColor */
1090 default:
1091 #ifdef DEBUG_CIRRUS
1092 printf("cirrus: invalid DAC value %x in 16bpp\n",
1093 (s->cirrus_hidden_dac_data & 0xf));
1094 #endif
1095 ret = 15; /* XXX */
1096 break;
1097 }
1098 return ret;
1099 }
1100
1101 static int cirrus_get_bpp(VGACommonState *s1)
1102 {
1103 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1104 uint32_t ret = 8;
1105
1106 if ((s->vga.sr[0x07] & 0x01) != 0) {
1107 /* Cirrus SVGA */
1108 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1109 case CIRRUS_SR7_BPP_8:
1110 ret = 8;
1111 break;
1112 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1113 ret = cirrus_get_bpp16_depth(s);
1114 break;
1115 case CIRRUS_SR7_BPP_24:
1116 ret = 24;
1117 break;
1118 case CIRRUS_SR7_BPP_16:
1119 ret = cirrus_get_bpp16_depth(s);
1120 break;
1121 case CIRRUS_SR7_BPP_32:
1122 ret = 32;
1123 break;
1124 default:
1125 #ifdef DEBUG_CIRRUS
1126 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1127 #endif
1128 ret = 8;
1129 break;
1130 }
1131 } else {
1132 /* VGA */
1133 ret = 0;
1134 }
1135
1136 return ret;
1137 }
1138
1139 static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1140 {
1141 int width, height;
1142
1143 width = (s->cr[0x01] + 1) * 8;
1144 height = s->cr[0x12] |
1145 ((s->cr[0x07] & 0x02) << 7) |
1146 ((s->cr[0x07] & 0x40) << 3);
1147 height = (height + 1);
1148 /* interlace support */
1149 if (s->cr[0x1a] & 0x01)
1150 height = height * 2;
1151 *pwidth = width;
1152 *pheight = height;
1153 }
1154
1155 /***************************************
1156 *
1157 * bank memory
1158 *
1159 ***************************************/
1160
1161 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1162 {
1163 unsigned offset;
1164 unsigned limit;
1165
1166 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1167 offset = s->vga.gr[0x09 + bank_index];
1168 else /* single bank */
1169 offset = s->vga.gr[0x09];
1170
1171 if ((s->vga.gr[0x0b] & 0x20) != 0)
1172 offset <<= 14;
1173 else
1174 offset <<= 12;
1175
1176 if (s->real_vram_size <= offset)
1177 limit = 0;
1178 else
1179 limit = s->real_vram_size - offset;
1180
1181 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1182 if (limit > 0x8000) {
1183 offset += 0x8000;
1184 limit -= 0x8000;
1185 } else {
1186 limit = 0;
1187 }
1188 }
1189
1190 if (limit > 0) {
1191 s->cirrus_bank_base[bank_index] = offset;
1192 s->cirrus_bank_limit[bank_index] = limit;
1193 } else {
1194 s->cirrus_bank_base[bank_index] = 0;
1195 s->cirrus_bank_limit[bank_index] = 0;
1196 }
1197 }
1198
1199 /***************************************
1200 *
1201 * I/O access between 0x3c4-0x3c5
1202 *
1203 ***************************************/
1204
1205 static int cirrus_vga_read_sr(CirrusVGAState * s)
1206 {
1207 switch (s->vga.sr_index) {
1208 case 0x00: // Standard VGA
1209 case 0x01: // Standard VGA
1210 case 0x02: // Standard VGA
1211 case 0x03: // Standard VGA
1212 case 0x04: // Standard VGA
1213 return s->vga.sr[s->vga.sr_index];
1214 case 0x06: // Unlock Cirrus extensions
1215 return s->vga.sr[s->vga.sr_index];
1216 case 0x10:
1217 case 0x30:
1218 case 0x50:
1219 case 0x70: // Graphics Cursor X
1220 case 0x90:
1221 case 0xb0:
1222 case 0xd0:
1223 case 0xf0: // Graphics Cursor X
1224 return s->vga.sr[0x10];
1225 case 0x11:
1226 case 0x31:
1227 case 0x51:
1228 case 0x71: // Graphics Cursor Y
1229 case 0x91:
1230 case 0xb1:
1231 case 0xd1:
1232 case 0xf1: // Graphics Cursor Y
1233 return s->vga.sr[0x11];
1234 case 0x05: // ???
1235 case 0x07: // Extended Sequencer Mode
1236 case 0x08: // EEPROM Control
1237 case 0x09: // Scratch Register 0
1238 case 0x0a: // Scratch Register 1
1239 case 0x0b: // VCLK 0
1240 case 0x0c: // VCLK 1
1241 case 0x0d: // VCLK 2
1242 case 0x0e: // VCLK 3
1243 case 0x0f: // DRAM Control
1244 case 0x12: // Graphics Cursor Attribute
1245 case 0x13: // Graphics Cursor Pattern Address
1246 case 0x14: // Scratch Register 2
1247 case 0x15: // Scratch Register 3
1248 case 0x16: // Performance Tuning Register
1249 case 0x17: // Configuration Readback and Extended Control
1250 case 0x18: // Signature Generator Control
1251 case 0x19: // Signal Generator Result
1252 case 0x1a: // Signal Generator Result
1253 case 0x1b: // VCLK 0 Denominator & Post
1254 case 0x1c: // VCLK 1 Denominator & Post
1255 case 0x1d: // VCLK 2 Denominator & Post
1256 case 0x1e: // VCLK 3 Denominator & Post
1257 case 0x1f: // BIOS Write Enable and MCLK select
1258 #ifdef DEBUG_CIRRUS
1259 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
1260 #endif
1261 return s->vga.sr[s->vga.sr_index];
1262 default:
1263 #ifdef DEBUG_CIRRUS
1264 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
1265 #endif
1266 return 0xff;
1267 break;
1268 }
1269 }
1270
1271 static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
1272 {
1273 switch (s->vga.sr_index) {
1274 case 0x00: // Standard VGA
1275 case 0x01: // Standard VGA
1276 case 0x02: // Standard VGA
1277 case 0x03: // Standard VGA
1278 case 0x04: // Standard VGA
1279 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1280 if (s->vga.sr_index == 1)
1281 s->vga.update_retrace_info(&s->vga);
1282 break;
1283 case 0x06: // Unlock Cirrus extensions
1284 val &= 0x17;
1285 if (val == 0x12) {
1286 s->vga.sr[s->vga.sr_index] = 0x12;
1287 } else {
1288 s->vga.sr[s->vga.sr_index] = 0x0f;
1289 }
1290 break;
1291 case 0x10:
1292 case 0x30:
1293 case 0x50:
1294 case 0x70: // Graphics Cursor X
1295 case 0x90:
1296 case 0xb0:
1297 case 0xd0:
1298 case 0xf0: // Graphics Cursor X
1299 s->vga.sr[0x10] = val;
1300 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
1301 break;
1302 case 0x11:
1303 case 0x31:
1304 case 0x51:
1305 case 0x71: // Graphics Cursor Y
1306 case 0x91:
1307 case 0xb1:
1308 case 0xd1:
1309 case 0xf1: // Graphics Cursor Y
1310 s->vga.sr[0x11] = val;
1311 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
1312 break;
1313 case 0x07: // Extended Sequencer Mode
1314 cirrus_update_memory_access(s);
1315 case 0x08: // EEPROM Control
1316 case 0x09: // Scratch Register 0
1317 case 0x0a: // Scratch Register 1
1318 case 0x0b: // VCLK 0
1319 case 0x0c: // VCLK 1
1320 case 0x0d: // VCLK 2
1321 case 0x0e: // VCLK 3
1322 case 0x0f: // DRAM Control
1323 case 0x12: // Graphics Cursor Attribute
1324 case 0x13: // Graphics Cursor Pattern Address
1325 case 0x14: // Scratch Register 2
1326 case 0x15: // Scratch Register 3
1327 case 0x16: // Performance Tuning Register
1328 case 0x18: // Signature Generator Control
1329 case 0x19: // Signature Generator Result
1330 case 0x1a: // Signature Generator Result
1331 case 0x1b: // VCLK 0 Denominator & Post
1332 case 0x1c: // VCLK 1 Denominator & Post
1333 case 0x1d: // VCLK 2 Denominator & Post
1334 case 0x1e: // VCLK 3 Denominator & Post
1335 case 0x1f: // BIOS Write Enable and MCLK select
1336 s->vga.sr[s->vga.sr_index] = val;
1337 #ifdef DEBUG_CIRRUS
1338 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1339 s->vga.sr_index, val);
1340 #endif
1341 break;
1342 case 0x17: // Configuration Readback and Extended Control
1343 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1344 | (val & 0xc7);
1345 cirrus_update_memory_access(s);
1346 break;
1347 default:
1348 #ifdef DEBUG_CIRRUS
1349 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1350 s->vga.sr_index, val);
1351 #endif
1352 break;
1353 }
1354 }
1355
1356 /***************************************
1357 *
1358 * I/O access at 0x3c6
1359 *
1360 ***************************************/
1361
1362 static int cirrus_read_hidden_dac(CirrusVGAState * s)
1363 {
1364 if (++s->cirrus_hidden_dac_lockindex == 5) {
1365 s->cirrus_hidden_dac_lockindex = 0;
1366 return s->cirrus_hidden_dac_data;
1367 }
1368 return 0xff;
1369 }
1370
1371 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1372 {
1373 if (s->cirrus_hidden_dac_lockindex == 4) {
1374 s->cirrus_hidden_dac_data = reg_value;
1375 #if defined(DEBUG_CIRRUS)
1376 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1377 #endif
1378 }
1379 s->cirrus_hidden_dac_lockindex = 0;
1380 }
1381
1382 /***************************************
1383 *
1384 * I/O access at 0x3c9
1385 *
1386 ***************************************/
1387
1388 static int cirrus_vga_read_palette(CirrusVGAState * s)
1389 {
1390 int val;
1391
1392 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1393 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1394 s->vga.dac_sub_index];
1395 } else {
1396 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1397 }
1398 if (++s->vga.dac_sub_index == 3) {
1399 s->vga.dac_sub_index = 0;
1400 s->vga.dac_read_index++;
1401 }
1402 return val;
1403 }
1404
1405 static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
1406 {
1407 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1408 if (++s->vga.dac_sub_index == 3) {
1409 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1410 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1411 s->vga.dac_cache, 3);
1412 } else {
1413 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1414 }
1415 /* XXX update cursor */
1416 s->vga.dac_sub_index = 0;
1417 s->vga.dac_write_index++;
1418 }
1419 }
1420
1421 /***************************************
1422 *
1423 * I/O access between 0x3ce-0x3cf
1424 *
1425 ***************************************/
1426
1427 static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
1428 {
1429 switch (reg_index) {
1430 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1431 return s->cirrus_shadow_gr0;
1432 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1433 return s->cirrus_shadow_gr1;
1434 case 0x02: // Standard VGA
1435 case 0x03: // Standard VGA
1436 case 0x04: // Standard VGA
1437 case 0x06: // Standard VGA
1438 case 0x07: // Standard VGA
1439 case 0x08: // Standard VGA
1440 return s->vga.gr[s->vga.gr_index];
1441 case 0x05: // Standard VGA, Cirrus extended mode
1442 default:
1443 break;
1444 }
1445
1446 if (reg_index < 0x3a) {
1447 return s->vga.gr[reg_index];
1448 } else {
1449 #ifdef DEBUG_CIRRUS
1450 printf("cirrus: inport gr_index %02x\n", reg_index);
1451 #endif
1452 return 0xff;
1453 }
1454 }
1455
1456 static void
1457 cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1458 {
1459 #if defined(DEBUG_BITBLT) && 0
1460 printf("gr%02x: %02x\n", reg_index, reg_value);
1461 #endif
1462 switch (reg_index) {
1463 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1464 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1465 s->cirrus_shadow_gr0 = reg_value;
1466 break;
1467 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1468 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1469 s->cirrus_shadow_gr1 = reg_value;
1470 break;
1471 case 0x02: // Standard VGA
1472 case 0x03: // Standard VGA
1473 case 0x04: // Standard VGA
1474 case 0x06: // Standard VGA
1475 case 0x07: // Standard VGA
1476 case 0x08: // Standard VGA
1477 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1478 break;
1479 case 0x05: // Standard VGA, Cirrus extended mode
1480 s->vga.gr[reg_index] = reg_value & 0x7f;
1481 cirrus_update_memory_access(s);
1482 break;
1483 case 0x09: // bank offset #0
1484 case 0x0A: // bank offset #1
1485 s->vga.gr[reg_index] = reg_value;
1486 cirrus_update_bank_ptr(s, 0);
1487 cirrus_update_bank_ptr(s, 1);
1488 cirrus_update_memory_access(s);
1489 break;
1490 case 0x0B:
1491 s->vga.gr[reg_index] = reg_value;
1492 cirrus_update_bank_ptr(s, 0);
1493 cirrus_update_bank_ptr(s, 1);
1494 cirrus_update_memory_access(s);
1495 break;
1496 case 0x10: // BGCOLOR 0x0000ff00
1497 case 0x11: // FGCOLOR 0x0000ff00
1498 case 0x12: // BGCOLOR 0x00ff0000
1499 case 0x13: // FGCOLOR 0x00ff0000
1500 case 0x14: // BGCOLOR 0xff000000
1501 case 0x15: // FGCOLOR 0xff000000
1502 case 0x20: // BLT WIDTH 0x0000ff
1503 case 0x22: // BLT HEIGHT 0x0000ff
1504 case 0x24: // BLT DEST PITCH 0x0000ff
1505 case 0x26: // BLT SRC PITCH 0x0000ff
1506 case 0x28: // BLT DEST ADDR 0x0000ff
1507 case 0x29: // BLT DEST ADDR 0x00ff00
1508 case 0x2c: // BLT SRC ADDR 0x0000ff
1509 case 0x2d: // BLT SRC ADDR 0x00ff00
1510 case 0x2f: // BLT WRITEMASK
1511 case 0x30: // BLT MODE
1512 case 0x32: // RASTER OP
1513 case 0x33: // BLT MODEEXT
1514 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1515 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1516 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1517 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1518 s->vga.gr[reg_index] = reg_value;
1519 break;
1520 case 0x21: // BLT WIDTH 0x001f00
1521 case 0x23: // BLT HEIGHT 0x001f00
1522 case 0x25: // BLT DEST PITCH 0x001f00
1523 case 0x27: // BLT SRC PITCH 0x001f00
1524 s->vga.gr[reg_index] = reg_value & 0x1f;
1525 break;
1526 case 0x2a: // BLT DEST ADDR 0x3f0000
1527 s->vga.gr[reg_index] = reg_value & 0x3f;
1528 /* if auto start mode, starts bit blt now */
1529 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1530 cirrus_bitblt_start(s);
1531 }
1532 break;
1533 case 0x2e: // BLT SRC ADDR 0x3f0000
1534 s->vga.gr[reg_index] = reg_value & 0x3f;
1535 break;
1536 case 0x31: // BLT STATUS/START
1537 cirrus_write_bitblt(s, reg_value);
1538 break;
1539 default:
1540 #ifdef DEBUG_CIRRUS
1541 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1542 reg_value);
1543 #endif
1544 break;
1545 }
1546 }
1547
1548 /***************************************
1549 *
1550 * I/O access between 0x3d4-0x3d5
1551 *
1552 ***************************************/
1553
1554 static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
1555 {
1556 switch (reg_index) {
1557 case 0x00: // Standard VGA
1558 case 0x01: // Standard VGA
1559 case 0x02: // Standard VGA
1560 case 0x03: // Standard VGA
1561 case 0x04: // Standard VGA
1562 case 0x05: // Standard VGA
1563 case 0x06: // Standard VGA
1564 case 0x07: // Standard VGA
1565 case 0x08: // Standard VGA
1566 case 0x09: // Standard VGA
1567 case 0x0a: // Standard VGA
1568 case 0x0b: // Standard VGA
1569 case 0x0c: // Standard VGA
1570 case 0x0d: // Standard VGA
1571 case 0x0e: // Standard VGA
1572 case 0x0f: // Standard VGA
1573 case 0x10: // Standard VGA
1574 case 0x11: // Standard VGA
1575 case 0x12: // Standard VGA
1576 case 0x13: // Standard VGA
1577 case 0x14: // Standard VGA
1578 case 0x15: // Standard VGA
1579 case 0x16: // Standard VGA
1580 case 0x17: // Standard VGA
1581 case 0x18: // Standard VGA
1582 return s->vga.cr[s->vga.cr_index];
1583 case 0x24: // Attribute Controller Toggle Readback (R)
1584 return (s->vga.ar_flip_flop << 7);
1585 case 0x19: // Interlace End
1586 case 0x1a: // Miscellaneous Control
1587 case 0x1b: // Extended Display Control
1588 case 0x1c: // Sync Adjust and Genlock
1589 case 0x1d: // Overlay Extended Control
1590 case 0x22: // Graphics Data Latches Readback (R)
1591 case 0x25: // Part Status
1592 case 0x27: // Part ID (R)
1593 return s->vga.cr[s->vga.cr_index];
1594 case 0x26: // Attribute Controller Index Readback (R)
1595 return s->vga.ar_index & 0x3f;
1596 break;
1597 default:
1598 #ifdef DEBUG_CIRRUS
1599 printf("cirrus: inport cr_index %02x\n", reg_index);
1600 #endif
1601 return 0xff;
1602 }
1603 }
1604
1605 static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
1606 {
1607 switch (s->vga.cr_index) {
1608 case 0x00: // Standard VGA
1609 case 0x01: // Standard VGA
1610 case 0x02: // Standard VGA
1611 case 0x03: // Standard VGA
1612 case 0x04: // Standard VGA
1613 case 0x05: // Standard VGA
1614 case 0x06: // Standard VGA
1615 case 0x07: // Standard VGA
1616 case 0x08: // Standard VGA
1617 case 0x09: // Standard VGA
1618 case 0x0a: // Standard VGA
1619 case 0x0b: // Standard VGA
1620 case 0x0c: // Standard VGA
1621 case 0x0d: // Standard VGA
1622 case 0x0e: // Standard VGA
1623 case 0x0f: // Standard VGA
1624 case 0x10: // Standard VGA
1625 case 0x11: // Standard VGA
1626 case 0x12: // Standard VGA
1627 case 0x13: // Standard VGA
1628 case 0x14: // Standard VGA
1629 case 0x15: // Standard VGA
1630 case 0x16: // Standard VGA
1631 case 0x17: // Standard VGA
1632 case 0x18: // Standard VGA
1633 /* handle CR0-7 protection */
1634 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1635 /* can always write bit 4 of CR7 */
1636 if (s->vga.cr_index == 7)
1637 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1638 return;
1639 }
1640 s->vga.cr[s->vga.cr_index] = reg_value;
1641 switch(s->vga.cr_index) {
1642 case 0x00:
1643 case 0x04:
1644 case 0x05:
1645 case 0x06:
1646 case 0x07:
1647 case 0x11:
1648 case 0x17:
1649 s->vga.update_retrace_info(&s->vga);
1650 break;
1651 }
1652 break;
1653 case 0x19: // Interlace End
1654 case 0x1a: // Miscellaneous Control
1655 case 0x1b: // Extended Display Control
1656 case 0x1c: // Sync Adjust and Genlock
1657 case 0x1d: // Overlay Extended Control
1658 s->vga.cr[s->vga.cr_index] = reg_value;
1659 #ifdef DEBUG_CIRRUS
1660 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1661 s->vga.cr_index, reg_value);
1662 #endif
1663 break;
1664 case 0x22: // Graphics Data Latches Readback (R)
1665 case 0x24: // Attribute Controller Toggle Readback (R)
1666 case 0x26: // Attribute Controller Index Readback (R)
1667 case 0x27: // Part ID (R)
1668 break;
1669 case 0x25: // Part Status
1670 default:
1671 #ifdef DEBUG_CIRRUS
1672 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1673 s->vga.cr_index, reg_value);
1674 #endif
1675 break;
1676 }
1677 }
1678
1679 /***************************************
1680 *
1681 * memory-mapped I/O (bitblt)
1682 *
1683 ***************************************/
1684
1685 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1686 {
1687 int value = 0xff;
1688
1689 switch (address) {
1690 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1691 value = cirrus_vga_read_gr(s, 0x00);
1692 break;
1693 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1694 value = cirrus_vga_read_gr(s, 0x10);
1695 break;
1696 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1697 value = cirrus_vga_read_gr(s, 0x12);
1698 break;
1699 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1700 value = cirrus_vga_read_gr(s, 0x14);
1701 break;
1702 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1703 value = cirrus_vga_read_gr(s, 0x01);
1704 break;
1705 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1706 value = cirrus_vga_read_gr(s, 0x11);
1707 break;
1708 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1709 value = cirrus_vga_read_gr(s, 0x13);
1710 break;
1711 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1712 value = cirrus_vga_read_gr(s, 0x15);
1713 break;
1714 case (CIRRUS_MMIO_BLTWIDTH + 0):
1715 value = cirrus_vga_read_gr(s, 0x20);
1716 break;
1717 case (CIRRUS_MMIO_BLTWIDTH + 1):
1718 value = cirrus_vga_read_gr(s, 0x21);
1719 break;
1720 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1721 value = cirrus_vga_read_gr(s, 0x22);
1722 break;
1723 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1724 value = cirrus_vga_read_gr(s, 0x23);
1725 break;
1726 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1727 value = cirrus_vga_read_gr(s, 0x24);
1728 break;
1729 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1730 value = cirrus_vga_read_gr(s, 0x25);
1731 break;
1732 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1733 value = cirrus_vga_read_gr(s, 0x26);
1734 break;
1735 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1736 value = cirrus_vga_read_gr(s, 0x27);
1737 break;
1738 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1739 value = cirrus_vga_read_gr(s, 0x28);
1740 break;
1741 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1742 value = cirrus_vga_read_gr(s, 0x29);
1743 break;
1744 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1745 value = cirrus_vga_read_gr(s, 0x2a);
1746 break;
1747 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1748 value = cirrus_vga_read_gr(s, 0x2c);
1749 break;
1750 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1751 value = cirrus_vga_read_gr(s, 0x2d);
1752 break;
1753 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1754 value = cirrus_vga_read_gr(s, 0x2e);
1755 break;
1756 case CIRRUS_MMIO_BLTWRITEMASK:
1757 value = cirrus_vga_read_gr(s, 0x2f);
1758 break;
1759 case CIRRUS_MMIO_BLTMODE:
1760 value = cirrus_vga_read_gr(s, 0x30);
1761 break;
1762 case CIRRUS_MMIO_BLTROP:
1763 value = cirrus_vga_read_gr(s, 0x32);
1764 break;
1765 case CIRRUS_MMIO_BLTMODEEXT:
1766 value = cirrus_vga_read_gr(s, 0x33);
1767 break;
1768 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1769 value = cirrus_vga_read_gr(s, 0x34);
1770 break;
1771 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1772 value = cirrus_vga_read_gr(s, 0x35);
1773 break;
1774 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1775 value = cirrus_vga_read_gr(s, 0x38);
1776 break;
1777 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1778 value = cirrus_vga_read_gr(s, 0x39);
1779 break;
1780 case CIRRUS_MMIO_BLTSTATUS:
1781 value = cirrus_vga_read_gr(s, 0x31);
1782 break;
1783 default:
1784 #ifdef DEBUG_CIRRUS
1785 printf("cirrus: mmio read - address 0x%04x\n", address);
1786 #endif
1787 break;
1788 }
1789
1790 return (uint8_t) value;
1791 }
1792
1793 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1794 uint8_t value)
1795 {
1796 switch (address) {
1797 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1798 cirrus_vga_write_gr(s, 0x00, value);
1799 break;
1800 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1801 cirrus_vga_write_gr(s, 0x10, value);
1802 break;
1803 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1804 cirrus_vga_write_gr(s, 0x12, value);
1805 break;
1806 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1807 cirrus_vga_write_gr(s, 0x14, value);
1808 break;
1809 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1810 cirrus_vga_write_gr(s, 0x01, value);
1811 break;
1812 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1813 cirrus_vga_write_gr(s, 0x11, value);
1814 break;
1815 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1816 cirrus_vga_write_gr(s, 0x13, value);
1817 break;
1818 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1819 cirrus_vga_write_gr(s, 0x15, value);
1820 break;
1821 case (CIRRUS_MMIO_BLTWIDTH + 0):
1822 cirrus_vga_write_gr(s, 0x20, value);
1823 break;
1824 case (CIRRUS_MMIO_BLTWIDTH + 1):
1825 cirrus_vga_write_gr(s, 0x21, value);
1826 break;
1827 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1828 cirrus_vga_write_gr(s, 0x22, value);
1829 break;
1830 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1831 cirrus_vga_write_gr(s, 0x23, value);
1832 break;
1833 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1834 cirrus_vga_write_gr(s, 0x24, value);
1835 break;
1836 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1837 cirrus_vga_write_gr(s, 0x25, value);
1838 break;
1839 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1840 cirrus_vga_write_gr(s, 0x26, value);
1841 break;
1842 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1843 cirrus_vga_write_gr(s, 0x27, value);
1844 break;
1845 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1846 cirrus_vga_write_gr(s, 0x28, value);
1847 break;
1848 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1849 cirrus_vga_write_gr(s, 0x29, value);
1850 break;
1851 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1852 cirrus_vga_write_gr(s, 0x2a, value);
1853 break;
1854 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1855 /* ignored */
1856 break;
1857 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1858 cirrus_vga_write_gr(s, 0x2c, value);
1859 break;
1860 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1861 cirrus_vga_write_gr(s, 0x2d, value);
1862 break;
1863 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1864 cirrus_vga_write_gr(s, 0x2e, value);
1865 break;
1866 case CIRRUS_MMIO_BLTWRITEMASK:
1867 cirrus_vga_write_gr(s, 0x2f, value);
1868 break;
1869 case CIRRUS_MMIO_BLTMODE:
1870 cirrus_vga_write_gr(s, 0x30, value);
1871 break;
1872 case CIRRUS_MMIO_BLTROP:
1873 cirrus_vga_write_gr(s, 0x32, value);
1874 break;
1875 case CIRRUS_MMIO_BLTMODEEXT:
1876 cirrus_vga_write_gr(s, 0x33, value);
1877 break;
1878 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1879 cirrus_vga_write_gr(s, 0x34, value);
1880 break;
1881 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1882 cirrus_vga_write_gr(s, 0x35, value);
1883 break;
1884 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1885 cirrus_vga_write_gr(s, 0x38, value);
1886 break;
1887 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1888 cirrus_vga_write_gr(s, 0x39, value);
1889 break;
1890 case CIRRUS_MMIO_BLTSTATUS:
1891 cirrus_vga_write_gr(s, 0x31, value);
1892 break;
1893 default:
1894 #ifdef DEBUG_CIRRUS
1895 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1896 address, value);
1897 #endif
1898 break;
1899 }
1900 }
1901
1902 /***************************************
1903 *
1904 * write mode 4/5
1905 *
1906 ***************************************/
1907
1908 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1909 unsigned mode,
1910 unsigned offset,
1911 uint32_t mem_value)
1912 {
1913 int x;
1914 unsigned val = mem_value;
1915 uint8_t *dst;
1916
1917 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1918 for (x = 0; x < 8; x++) {
1919 if (val & 0x80) {
1920 *dst = s->cirrus_shadow_gr1;
1921 } else if (mode == 5) {
1922 *dst = s->cirrus_shadow_gr0;
1923 }
1924 val <<= 1;
1925 dst++;
1926 }
1927 memory_region_set_dirty(&s->vga.vram, offset, 8);
1928 }
1929
1930 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1931 unsigned mode,
1932 unsigned offset,
1933 uint32_t mem_value)
1934 {
1935 int x;
1936 unsigned val = mem_value;
1937 uint8_t *dst;
1938
1939 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1940 for (x = 0; x < 8; x++) {
1941 if (val & 0x80) {
1942 *dst = s->cirrus_shadow_gr1;
1943 *(dst + 1) = s->vga.gr[0x11];
1944 } else if (mode == 5) {
1945 *dst = s->cirrus_shadow_gr0;
1946 *(dst + 1) = s->vga.gr[0x10];
1947 }
1948 val <<= 1;
1949 dst += 2;
1950 }
1951 memory_region_set_dirty(&s->vga.vram, offset, 16);
1952 }
1953
1954 /***************************************
1955 *
1956 * memory access between 0xa0000-0xbffff
1957 *
1958 ***************************************/
1959
1960 static uint64_t cirrus_vga_mem_read(void *opaque,
1961 hwaddr addr,
1962 uint32_t size)
1963 {
1964 CirrusVGAState *s = opaque;
1965 unsigned bank_index;
1966 unsigned bank_offset;
1967 uint32_t val;
1968
1969 if ((s->vga.sr[0x07] & 0x01) == 0) {
1970 return vga_mem_readb(&s->vga, addr);
1971 }
1972
1973 if (addr < 0x10000) {
1974 /* XXX handle bitblt */
1975 /* video memory */
1976 bank_index = addr >> 15;
1977 bank_offset = addr & 0x7fff;
1978 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1979 bank_offset += s->cirrus_bank_base[bank_index];
1980 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
1981 bank_offset <<= 4;
1982 } else if (s->vga.gr[0x0B] & 0x02) {
1983 bank_offset <<= 3;
1984 }
1985 bank_offset &= s->cirrus_addr_mask;
1986 val = *(s->vga.vram_ptr + bank_offset);
1987 } else
1988 val = 0xff;
1989 } else if (addr >= 0x18000 && addr < 0x18100) {
1990 /* memory-mapped I/O */
1991 val = 0xff;
1992 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
1993 val = cirrus_mmio_blt_read(s, addr & 0xff);
1994 }
1995 } else {
1996 val = 0xff;
1997 #ifdef DEBUG_CIRRUS
1998 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
1999 #endif
2000 }
2001 return val;
2002 }
2003
2004 static void cirrus_vga_mem_write(void *opaque,
2005 hwaddr addr,
2006 uint64_t mem_value,
2007 uint32_t size)
2008 {
2009 CirrusVGAState *s = opaque;
2010 unsigned bank_index;
2011 unsigned bank_offset;
2012 unsigned mode;
2013
2014 if ((s->vga.sr[0x07] & 0x01) == 0) {
2015 vga_mem_writeb(&s->vga, addr, mem_value);
2016 return;
2017 }
2018
2019 if (addr < 0x10000) {
2020 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2021 /* bitblt */
2022 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2023 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2024 cirrus_bitblt_cputovideo_next(s);
2025 }
2026 } else {
2027 /* video memory */
2028 bank_index = addr >> 15;
2029 bank_offset = addr & 0x7fff;
2030 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2031 bank_offset += s->cirrus_bank_base[bank_index];
2032 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2033 bank_offset <<= 4;
2034 } else if (s->vga.gr[0x0B] & 0x02) {
2035 bank_offset <<= 3;
2036 }
2037 bank_offset &= s->cirrus_addr_mask;
2038 mode = s->vga.gr[0x05] & 0x7;
2039 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2040 *(s->vga.vram_ptr + bank_offset) = mem_value;
2041 memory_region_set_dirty(&s->vga.vram, bank_offset,
2042 sizeof(mem_value));
2043 } else {
2044 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2045 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2046 bank_offset,
2047 mem_value);
2048 } else {
2049 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2050 bank_offset,
2051 mem_value);
2052 }
2053 }
2054 }
2055 }
2056 } else if (addr >= 0x18000 && addr < 0x18100) {
2057 /* memory-mapped I/O */
2058 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2059 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2060 }
2061 } else {
2062 #ifdef DEBUG_CIRRUS
2063 printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr,
2064 mem_value);
2065 #endif
2066 }
2067 }
2068
2069 static const MemoryRegionOps cirrus_vga_mem_ops = {
2070 .read = cirrus_vga_mem_read,
2071 .write = cirrus_vga_mem_write,
2072 .endianness = DEVICE_LITTLE_ENDIAN,
2073 .impl = {
2074 .min_access_size = 1,
2075 .max_access_size = 1,
2076 },
2077 };
2078
2079 /***************************************
2080 *
2081 * hardware cursor
2082 *
2083 ***************************************/
2084
2085 static inline void invalidate_cursor1(CirrusVGAState *s)
2086 {
2087 if (s->last_hw_cursor_size) {
2088 vga_invalidate_scanlines(&s->vga,
2089 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2090 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2091 }
2092 }
2093
2094 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2095 {
2096 const uint8_t *src;
2097 uint32_t content;
2098 int y, y_min, y_max;
2099
2100 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2101 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2102 src += (s->vga.sr[0x13] & 0x3c) * 256;
2103 y_min = 64;
2104 y_max = -1;
2105 for(y = 0; y < 64; y++) {
2106 content = ((uint32_t *)src)[0] |
2107 ((uint32_t *)src)[1] |
2108 ((uint32_t *)src)[2] |
2109 ((uint32_t *)src)[3];
2110 if (content) {
2111 if (y < y_min)
2112 y_min = y;
2113 if (y > y_max)
2114 y_max = y;
2115 }
2116 src += 16;
2117 }
2118 } else {
2119 src += (s->vga.sr[0x13] & 0x3f) * 256;
2120 y_min = 32;
2121 y_max = -1;
2122 for(y = 0; y < 32; y++) {
2123 content = ((uint32_t *)src)[0] |
2124 ((uint32_t *)(src + 128))[0];
2125 if (content) {
2126 if (y < y_min)
2127 y_min = y;
2128 if (y > y_max)
2129 y_max = y;
2130 }
2131 src += 4;
2132 }
2133 }
2134 if (y_min > y_max) {
2135 s->last_hw_cursor_y_start = 0;
2136 s->last_hw_cursor_y_end = 0;
2137 } else {
2138 s->last_hw_cursor_y_start = y_min;
2139 s->last_hw_cursor_y_end = y_max + 1;
2140 }
2141 }
2142
2143 /* NOTE: we do not currently handle the cursor bitmap change, so we
2144 update the cursor only if it moves. */
2145 static void cirrus_cursor_invalidate(VGACommonState *s1)
2146 {
2147 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2148 int size;
2149
2150 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2151 size = 0;
2152 } else {
2153 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2154 size = 64;
2155 else
2156 size = 32;
2157 }
2158 /* invalidate last cursor and new cursor if any change */
2159 if (s->last_hw_cursor_size != size ||
2160 s->last_hw_cursor_x != s->hw_cursor_x ||
2161 s->last_hw_cursor_y != s->hw_cursor_y) {
2162
2163 invalidate_cursor1(s);
2164
2165 s->last_hw_cursor_size = size;
2166 s->last_hw_cursor_x = s->hw_cursor_x;
2167 s->last_hw_cursor_y = s->hw_cursor_y;
2168 /* compute the real cursor min and max y */
2169 cirrus_cursor_compute_yrange(s);
2170 invalidate_cursor1(s);
2171 }
2172 }
2173
2174 static void vga_draw_cursor_line(uint8_t *d1,
2175 const uint8_t *src1,
2176 int poffset, int w,
2177 unsigned int color0,
2178 unsigned int color1,
2179 unsigned int color_xor)
2180 {
2181 const uint8_t *plane0, *plane1;
2182 int x, b0, b1;
2183 uint8_t *d;
2184
2185 d = d1;
2186 plane0 = src1;
2187 plane1 = src1 + poffset;
2188 for (x = 0; x < w; x++) {
2189 b0 = (plane0[x >> 3] >> (7 - (x & 7))) & 1;
2190 b1 = (plane1[x >> 3] >> (7 - (x & 7))) & 1;
2191 switch (b0 | (b1 << 1)) {
2192 case 0:
2193 break;
2194 case 1:
2195 ((uint32_t *)d)[0] ^= color_xor;
2196 break;
2197 case 2:
2198 ((uint32_t *)d)[0] = color0;
2199 break;
2200 case 3:
2201 ((uint32_t *)d)[0] = color1;
2202 break;
2203 }
2204 d += 4;
2205 }
2206 }
2207
2208 static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
2209 {
2210 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2211 int w, h, x1, x2, poffset;
2212 unsigned int color0, color1;
2213 const uint8_t *palette, *src;
2214 uint32_t content;
2215
2216 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2217 return;
2218 /* fast test to see if the cursor intersects with the scan line */
2219 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2220 h = 64;
2221 } else {
2222 h = 32;
2223 }
2224 if (scr_y < s->hw_cursor_y ||
2225 scr_y >= (s->hw_cursor_y + h))
2226 return;
2227
2228 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2229 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2230 src += (s->vga.sr[0x13] & 0x3c) * 256;
2231 src += (scr_y - s->hw_cursor_y) * 16;
2232 poffset = 8;
2233 content = ((uint32_t *)src)[0] |
2234 ((uint32_t *)src)[1] |
2235 ((uint32_t *)src)[2] |
2236 ((uint32_t *)src)[3];
2237 } else {
2238 src += (s->vga.sr[0x13] & 0x3f) * 256;
2239 src += (scr_y - s->hw_cursor_y) * 4;
2240
2241
2242 poffset = 128;
2243 content = ((uint32_t *)src)[0] |
2244 ((uint32_t *)(src + 128))[0];
2245 }
2246 /* if nothing to draw, no need to continue */
2247 if (!content)
2248 return;
2249 w = h;
2250
2251 x1 = s->hw_cursor_x;
2252 if (x1 >= s->vga.last_scr_width)
2253 return;
2254 x2 = s->hw_cursor_x + w;
2255 if (x2 > s->vga.last_scr_width)
2256 x2 = s->vga.last_scr_width;
2257 w = x2 - x1;
2258 palette = s->cirrus_hidden_palette;
2259 color0 = rgb_to_pixel32(c6_to_8(palette[0x0 * 3]),
2260 c6_to_8(palette[0x0 * 3 + 1]),
2261 c6_to_8(palette[0x0 * 3 + 2]));
2262 color1 = rgb_to_pixel32(c6_to_8(palette[0xf * 3]),
2263 c6_to_8(palette[0xf * 3 + 1]),
2264 c6_to_8(palette[0xf * 3 + 2]));
2265 d1 += x1 * 4;
2266 vga_draw_cursor_line(d1, src, poffset, w, color0, color1, 0xffffff);
2267 }
2268
2269 /***************************************
2270 *
2271 * LFB memory access
2272 *
2273 ***************************************/
2274
2275 static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
2276 unsigned size)
2277 {
2278 CirrusVGAState *s = opaque;
2279 uint32_t ret;
2280
2281 addr &= s->cirrus_addr_mask;
2282
2283 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2284 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2285 /* memory-mapped I/O */
2286 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2287 } else if (0) {
2288 /* XXX handle bitblt */
2289 ret = 0xff;
2290 } else {
2291 /* video memory */
2292 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2293 addr <<= 4;
2294 } else if (s->vga.gr[0x0B] & 0x02) {
2295 addr <<= 3;
2296 }
2297 addr &= s->cirrus_addr_mask;
2298 ret = *(s->vga.vram_ptr + addr);
2299 }
2300
2301 return ret;
2302 }
2303
2304 static void cirrus_linear_write(void *opaque, hwaddr addr,
2305 uint64_t val, unsigned size)
2306 {
2307 CirrusVGAState *s = opaque;
2308 unsigned mode;
2309
2310 addr &= s->cirrus_addr_mask;
2311
2312 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2313 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2314 /* memory-mapped I/O */
2315 cirrus_mmio_blt_write(s, addr & 0xff, val);
2316 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2317 /* bitblt */
2318 *s->cirrus_srcptr++ = (uint8_t) val;
2319 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2320 cirrus_bitblt_cputovideo_next(s);
2321 }
2322 } else {
2323 /* video memory */
2324 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2325 addr <<= 4;
2326 } else if (s->vga.gr[0x0B] & 0x02) {
2327 addr <<= 3;
2328 }
2329 addr &= s->cirrus_addr_mask;
2330
2331 mode = s->vga.gr[0x05] & 0x7;
2332 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2333 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2334 memory_region_set_dirty(&s->vga.vram, addr, 1);
2335 } else {
2336 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2337 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2338 } else {
2339 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2340 }
2341 }
2342 }
2343 }
2344
2345 /***************************************
2346 *
2347 * system to screen memory access
2348 *
2349 ***************************************/
2350
2351
2352 static uint64_t cirrus_linear_bitblt_read(void *opaque,
2353 hwaddr addr,
2354 unsigned size)
2355 {
2356 CirrusVGAState *s = opaque;
2357 uint32_t ret;
2358
2359 /* XXX handle bitblt */
2360 (void)s;
2361 ret = 0xff;
2362 return ret;
2363 }
2364
2365 static void cirrus_linear_bitblt_write(void *opaque,
2366 hwaddr addr,
2367 uint64_t val,
2368 unsigned size)
2369 {
2370 CirrusVGAState *s = opaque;
2371
2372 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2373 /* bitblt */
2374 *s->cirrus_srcptr++ = (uint8_t) val;
2375 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2376 cirrus_bitblt_cputovideo_next(s);
2377 }
2378 }
2379 }
2380
2381 static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2382 .read = cirrus_linear_bitblt_read,
2383 .write = cirrus_linear_bitblt_write,
2384 .endianness = DEVICE_LITTLE_ENDIAN,
2385 .impl = {
2386 .min_access_size = 1,
2387 .max_access_size = 1,
2388 },
2389 };
2390
2391 static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2392 {
2393 MemoryRegion *mr = &s->cirrus_bank[bank];
2394 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2395 && !((s->vga.sr[0x07] & 0x01) == 0)
2396 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2397 && !(s->vga.gr[0x0B] & 0x02);
2398
2399 memory_region_set_enabled(mr, enabled);
2400 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
2401 }
2402
2403 static void map_linear_vram(CirrusVGAState *s)
2404 {
2405 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
2406 s->linear_vram = true;
2407 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2408 }
2409 map_linear_vram_bank(s, 0);
2410 map_linear_vram_bank(s, 1);
2411 }
2412
2413 static void unmap_linear_vram(CirrusVGAState *s)
2414 {
2415 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
2416 s->linear_vram = false;
2417 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
2418 }
2419 memory_region_set_enabled(&s->cirrus_bank[0], false);
2420 memory_region_set_enabled(&s->cirrus_bank[1], false);
2421 }
2422
2423 /* Compute the memory access functions */
2424 static void cirrus_update_memory_access(CirrusVGAState *s)
2425 {
2426 unsigned mode;
2427
2428 memory_region_transaction_begin();
2429 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2430 goto generic_io;
2431 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2432 goto generic_io;
2433 } else {
2434 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2435 goto generic_io;
2436 } else if (s->vga.gr[0x0B] & 0x02) {
2437 goto generic_io;
2438 }
2439
2440 mode = s->vga.gr[0x05] & 0x7;
2441 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2442 map_linear_vram(s);
2443 } else {
2444 generic_io:
2445 unmap_linear_vram(s);
2446 }
2447 }
2448 memory_region_transaction_commit();
2449 }
2450
2451
2452 /* I/O ports */
2453
2454 static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
2455 unsigned size)
2456 {
2457 CirrusVGAState *c = opaque;
2458 VGACommonState *s = &c->vga;
2459 int val, index;
2460
2461 addr += 0x3b0;
2462
2463 if (vga_ioport_invalid(s, addr)) {
2464 val = 0xff;
2465 } else {
2466 switch (addr) {
2467 case 0x3c0:
2468 if (s->ar_flip_flop == 0) {
2469 val = s->ar_index;
2470 } else {
2471 val = 0;
2472 }
2473 break;
2474 case 0x3c1:
2475 index = s->ar_index & 0x1f;
2476 if (index < 21)
2477 val = s->ar[index];
2478 else
2479 val = 0;
2480 break;
2481 case 0x3c2:
2482 val = s->st00;
2483 break;
2484 case 0x3c4:
2485 val = s->sr_index;
2486 break;
2487 case 0x3c5:
2488 val = cirrus_vga_read_sr(c);
2489 break;
2490 #ifdef DEBUG_VGA_REG
2491 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2492 #endif
2493 break;
2494 case 0x3c6:
2495 val = cirrus_read_hidden_dac(c);
2496 break;
2497 case 0x3c7:
2498 val = s->dac_state;
2499 break;
2500 case 0x3c8:
2501 val = s->dac_write_index;
2502 c->cirrus_hidden_dac_lockindex = 0;
2503 break;
2504 case 0x3c9:
2505 val = cirrus_vga_read_palette(c);
2506 break;
2507 case 0x3ca:
2508 val = s->fcr;
2509 break;
2510 case 0x3cc:
2511 val = s->msr;
2512 break;
2513 case 0x3ce:
2514 val = s->gr_index;
2515 break;
2516 case 0x3cf:
2517 val = cirrus_vga_read_gr(c, s->gr_index);
2518 #ifdef DEBUG_VGA_REG
2519 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2520 #endif
2521 break;
2522 case 0x3b4:
2523 case 0x3d4:
2524 val = s->cr_index;
2525 break;
2526 case 0x3b5:
2527 case 0x3d5:
2528 val = cirrus_vga_read_cr(c, s->cr_index);
2529 #ifdef DEBUG_VGA_REG
2530 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2531 #endif
2532 break;
2533 case 0x3ba:
2534 case 0x3da:
2535 /* just toggle to fool polling */
2536 val = s->st01 = s->retrace(s);
2537 s->ar_flip_flop = 0;
2538 break;
2539 default:
2540 val = 0x00;
2541 break;
2542 }
2543 }
2544 #if defined(DEBUG_VGA)
2545 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2546 #endif
2547 return val;
2548 }
2549
2550 static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
2551 unsigned size)
2552 {
2553 CirrusVGAState *c = opaque;
2554 VGACommonState *s = &c->vga;
2555 int index;
2556
2557 addr += 0x3b0;
2558
2559 /* check port range access depending on color/monochrome mode */
2560 if (vga_ioport_invalid(s, addr)) {
2561 return;
2562 }
2563 #ifdef DEBUG_VGA
2564 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2565 #endif
2566
2567 switch (addr) {
2568 case 0x3c0:
2569 if (s->ar_flip_flop == 0) {
2570 val &= 0x3f;
2571 s->ar_index = val;
2572 } else {
2573 index = s->ar_index & 0x1f;
2574 switch (index) {
2575 case 0x00 ... 0x0f:
2576 s->ar[index] = val & 0x3f;
2577 break;
2578 case 0x10:
2579 s->ar[index] = val & ~0x10;
2580 break;
2581 case 0x11:
2582 s->ar[index] = val;
2583 break;
2584 case 0x12:
2585 s->ar[index] = val & ~0xc0;
2586 break;
2587 case 0x13:
2588 s->ar[index] = val & ~0xf0;
2589 break;
2590 case 0x14:
2591 s->ar[index] = val & ~0xf0;
2592 break;
2593 default:
2594 break;
2595 }
2596 }
2597 s->ar_flip_flop ^= 1;
2598 break;
2599 case 0x3c2:
2600 s->msr = val & ~0x10;
2601 s->update_retrace_info(s);
2602 break;
2603 case 0x3c4:
2604 s->sr_index = val;
2605 break;
2606 case 0x3c5:
2607 #ifdef DEBUG_VGA_REG
2608 printf("vga: write SR%x = 0x%02" PRIu64 "\n", s->sr_index, val);
2609 #endif
2610 cirrus_vga_write_sr(c, val);
2611 break;
2612 case 0x3c6:
2613 cirrus_write_hidden_dac(c, val);
2614 break;
2615 case 0x3c7:
2616 s->dac_read_index = val;
2617 s->dac_sub_index = 0;
2618 s->dac_state = 3;
2619 break;
2620 case 0x3c8:
2621 s->dac_write_index = val;
2622 s->dac_sub_index = 0;
2623 s->dac_state = 0;
2624 break;
2625 case 0x3c9:
2626 cirrus_vga_write_palette(c, val);
2627 break;
2628 case 0x3ce:
2629 s->gr_index = val;
2630 break;
2631 case 0x3cf:
2632 #ifdef DEBUG_VGA_REG
2633 printf("vga: write GR%x = 0x%02" PRIu64 "\n", s->gr_index, val);
2634 #endif
2635 cirrus_vga_write_gr(c, s->gr_index, val);
2636 break;
2637 case 0x3b4:
2638 case 0x3d4:
2639 s->cr_index = val;
2640 break;
2641 case 0x3b5:
2642 case 0x3d5:
2643 #ifdef DEBUG_VGA_REG
2644 printf("vga: write CR%x = 0x%02"PRIu64"\n", s->cr_index, val);
2645 #endif
2646 cirrus_vga_write_cr(c, val);
2647 break;
2648 case 0x3ba:
2649 case 0x3da:
2650 s->fcr = val & 0x10;
2651 break;
2652 }
2653 }
2654
2655 /***************************************
2656 *
2657 * memory-mapped I/O access
2658 *
2659 ***************************************/
2660
2661 static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
2662 unsigned size)
2663 {
2664 CirrusVGAState *s = opaque;
2665
2666 if (addr >= 0x100) {
2667 return cirrus_mmio_blt_read(s, addr - 0x100);
2668 } else {
2669 return cirrus_vga_ioport_read(s, addr + 0x10, size);
2670 }
2671 }
2672
2673 static void cirrus_mmio_write(void *opaque, hwaddr addr,
2674 uint64_t val, unsigned size)
2675 {
2676 CirrusVGAState *s = opaque;
2677
2678 if (addr >= 0x100) {
2679 cirrus_mmio_blt_write(s, addr - 0x100, val);
2680 } else {
2681 cirrus_vga_ioport_write(s, addr + 0x10, val, size);
2682 }
2683 }
2684
2685 static const MemoryRegionOps cirrus_mmio_io_ops = {
2686 .read = cirrus_mmio_read,
2687 .write = cirrus_mmio_write,
2688 .endianness = DEVICE_LITTLE_ENDIAN,
2689 .impl = {
2690 .min_access_size = 1,
2691 .max_access_size = 1,
2692 },
2693 };
2694
2695 /* load/save state */
2696
2697 static int cirrus_post_load(void *opaque, int version_id)
2698 {
2699 CirrusVGAState *s = opaque;
2700
2701 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2702 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2703
2704 cirrus_update_memory_access(s);
2705 /* force refresh */
2706 s->vga.graphic_mode = -1;
2707 cirrus_update_bank_ptr(s, 0);
2708 cirrus_update_bank_ptr(s, 1);
2709 return 0;
2710 }
2711
2712 static const VMStateDescription vmstate_cirrus_vga = {
2713 .name = "cirrus_vga",
2714 .version_id = 2,
2715 .minimum_version_id = 1,
2716 .post_load = cirrus_post_load,
2717 .fields = (VMStateField[]) {
2718 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2719 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2720 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2721 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2722 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2723 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2724 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2725 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2726 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2727 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2728 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2729 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2730 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2731 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2732 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2733 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2734 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2735 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2736 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2737 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2738 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2739 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2740 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2741 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2742 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2743 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
2744 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
2745 /* XXX: we do not save the bitblt state - we assume we do not save
2746 the state when the blitter is active */
2747 VMSTATE_END_OF_LIST()
2748 }
2749 };
2750
2751 static const VMStateDescription vmstate_pci_cirrus_vga = {
2752 .name = "cirrus_vga",
2753 .version_id = 2,
2754 .minimum_version_id = 2,
2755 .fields = (VMStateField[]) {
2756 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2757 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2758 vmstate_cirrus_vga, CirrusVGAState),
2759 VMSTATE_END_OF_LIST()
2760 }
2761 };
2762
2763 /***************************************
2764 *
2765 * initialize
2766 *
2767 ***************************************/
2768
2769 static void cirrus_reset(void *opaque)
2770 {
2771 CirrusVGAState *s = opaque;
2772
2773 vga_common_reset(&s->vga);
2774 unmap_linear_vram(s);
2775 s->vga.sr[0x06] = 0x0f;
2776 if (s->device_id == CIRRUS_ID_CLGD5446) {
2777 /* 4MB 64 bit memory config, always PCI */
2778 s->vga.sr[0x1F] = 0x2d; // MemClock
2779 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2780 s->vga.sr[0x0f] = 0x98;
2781 s->vga.sr[0x17] = 0x20;
2782 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2783 } else {
2784 s->vga.sr[0x1F] = 0x22; // MemClock
2785 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2786 s->vga.sr[0x17] = s->bustype;
2787 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2788 }
2789 s->vga.cr[0x27] = s->device_id;
2790
2791 s->cirrus_hidden_dac_lockindex = 5;
2792 s->cirrus_hidden_dac_data = 0;
2793 }
2794
2795 static const MemoryRegionOps cirrus_linear_io_ops = {
2796 .read = cirrus_linear_read,
2797 .write = cirrus_linear_write,
2798 .endianness = DEVICE_LITTLE_ENDIAN,
2799 .impl = {
2800 .min_access_size = 1,
2801 .max_access_size = 1,
2802 },
2803 };
2804
2805 static const MemoryRegionOps cirrus_vga_io_ops = {
2806 .read = cirrus_vga_ioport_read,
2807 .write = cirrus_vga_ioport_write,
2808 .endianness = DEVICE_LITTLE_ENDIAN,
2809 .impl = {
2810 .min_access_size = 1,
2811 .max_access_size = 1,
2812 },
2813 };
2814
2815 static void cirrus_init_common(CirrusVGAState *s, Object *owner,
2816 int device_id, int is_pci,
2817 MemoryRegion *system_memory,
2818 MemoryRegion *system_io)
2819 {
2820 int i;
2821 static int inited;
2822
2823 if (!inited) {
2824 inited = 1;
2825 for(i = 0;i < 256; i++)
2826 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2827 rop_to_index[CIRRUS_ROP_0] = 0;
2828 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2829 rop_to_index[CIRRUS_ROP_NOP] = 2;
2830 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2831 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2832 rop_to_index[CIRRUS_ROP_SRC] = 5;
2833 rop_to_index[CIRRUS_ROP_1] = 6;
2834 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2835 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2836 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2837 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2838 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2839 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2840 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2841 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2842 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2843 s->device_id = device_id;
2844 if (is_pci)
2845 s->bustype = CIRRUS_BUSTYPE_PCI;
2846 else
2847 s->bustype = CIRRUS_BUSTYPE_ISA;
2848 }
2849
2850 /* Register ioport 0x3b0 - 0x3df */
2851 memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s,
2852 "cirrus-io", 0x30);
2853 memory_region_set_flush_coalesced(&s->cirrus_vga_io);
2854 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
2855
2856 memory_region_init(&s->low_mem_container, owner,
2857 "cirrus-lowmem-container",
2858 0x20000);
2859
2860 memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s,
2861 "cirrus-low-memory", 0x20000);
2862 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
2863 for (i = 0; i < 2; ++i) {
2864 static const char *names[] = { "vga.bank0", "vga.bank1" };
2865 MemoryRegion *bank = &s->cirrus_bank[i];
2866 memory_region_init_alias(bank, owner, names[i], &s->vga.vram,
2867 0, 0x8000);
2868 memory_region_set_enabled(bank, false);
2869 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2870 bank, 1);
2871 }
2872 memory_region_add_subregion_overlap(system_memory,
2873 isa_mem_base + 0x000a0000,
2874 &s->low_mem_container,
2875 1);
2876 memory_region_set_coalescing(&s->low_mem);
2877
2878 /* I/O handler for LFB */
2879 memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s,
2880 "cirrus-linear-io", s->vga.vram_size_mb
2881 * 1024 * 1024);
2882 memory_region_set_flush_coalesced(&s->cirrus_linear_io);
2883
2884 /* I/O handler for LFB */
2885 memory_region_init_io(&s->cirrus_linear_bitblt_io, owner,
2886 &cirrus_linear_bitblt_io_ops,
2887 s,
2888 "cirrus-bitblt-mmio",
2889 0x400000);
2890 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
2891
2892 /* I/O handler for memory-mapped I/O */
2893 memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s,
2894 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
2895 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
2896
2897 s->real_vram_size =
2898 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2899
2900 /* XXX: s->vga.vram_size must be a power of two */
2901 s->cirrus_addr_mask = s->real_vram_size - 1;
2902 s->linear_mmio_mask = s->real_vram_size - 256;
2903
2904 s->vga.get_bpp = cirrus_get_bpp;
2905 s->vga.get_offsets = cirrus_get_offsets;
2906 s->vga.get_resolution = cirrus_get_resolution;
2907 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2908 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
2909
2910 qemu_register_reset(cirrus_reset, s);
2911 }
2912
2913 /***************************************
2914 *
2915 * ISA bus support
2916 *
2917 ***************************************/
2918
2919 static void isa_cirrus_vga_realizefn(DeviceState *dev, Error **errp)
2920 {
2921 ISADevice *isadev = ISA_DEVICE(dev);
2922 ISACirrusVGAState *d = ISA_CIRRUS_VGA(dev);
2923 VGACommonState *s = &d->cirrus_vga.vga;
2924
2925 /* follow real hardware, cirrus card emulated has 4 MB video memory.
2926 Also accept 8 MB/16 MB for backward compatibility. */
2927 if (s->vram_size_mb != 4 && s->vram_size_mb != 8 &&
2928 s->vram_size_mb != 16) {
2929 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
2930 s->vram_size_mb);
2931 return;
2932 }
2933 vga_common_init(s, OBJECT(dev), true);
2934 cirrus_init_common(&d->cirrus_vga, OBJECT(dev), CIRRUS_ID_CLGD5430, 0,
2935 isa_address_space(isadev),
2936 isa_address_space_io(isadev));
2937 s->con = graphic_console_init(dev, 0, s->hw_ops, s);
2938 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
2939 /* XXX ISA-LFB support */
2940 /* FIXME not qdev yet */
2941 }
2942
2943 static Property isa_cirrus_vga_properties[] = {
2944 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState,
2945 cirrus_vga.vga.vram_size_mb, 8),
2946 DEFINE_PROP_END_OF_LIST(),
2947 };
2948
2949 static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data)
2950 {
2951 DeviceClass *dc = DEVICE_CLASS(klass);
2952
2953 dc->vmsd = &vmstate_cirrus_vga;
2954 dc->realize = isa_cirrus_vga_realizefn;
2955 dc->props = isa_cirrus_vga_properties;
2956 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2957 }
2958
2959 static const TypeInfo isa_cirrus_vga_info = {
2960 .name = TYPE_ISA_CIRRUS_VGA,
2961 .parent = TYPE_ISA_DEVICE,
2962 .instance_size = sizeof(ISACirrusVGAState),
2963 .class_init = isa_cirrus_vga_class_init,
2964 };
2965
2966 /***************************************
2967 *
2968 * PCI bus support
2969 *
2970 ***************************************/
2971
2972 static int pci_cirrus_vga_initfn(PCIDevice *dev)
2973 {
2974 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
2975 CirrusVGAState *s = &d->cirrus_vga;
2976 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2977 int16_t device_id = pc->device_id;
2978
2979 /* follow real hardware, cirrus card emulated has 4 MB video memory.
2980 Also accept 8 MB/16 MB for backward compatibility. */
2981 if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 &&
2982 s->vga.vram_size_mb != 16) {
2983 error_report("Invalid cirrus_vga ram size '%u'",
2984 s->vga.vram_size_mb);
2985 return -1;
2986 }
2987 /* setup VGA */
2988 vga_common_init(&s->vga, OBJECT(dev), true);
2989 cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
2990 pci_address_space_io(dev));
2991 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga);
2992
2993 /* setup PCI */
2994
2995 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000);
2996
2997 /* XXX: add byte swapping apertures */
2998 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
2999 memory_region_add_subregion(&s->pci_bar, 0x1000000,
3000 &s->cirrus_linear_bitblt_io);
3001
3002 /* setup memory space */
3003 /* memory #0 LFB */
3004 /* memory #1 memory-mapped I/O */
3005 /* XXX: s->vga.vram_size must be a power of two */
3006 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
3007 if (device_id == CIRRUS_ID_CLGD5446) {
3008 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
3009 }
3010 return 0;
3011 }
3012
3013 static Property pci_vga_cirrus_properties[] = {
3014 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
3015 cirrus_vga.vga.vram_size_mb, 8),
3016 DEFINE_PROP_END_OF_LIST(),
3017 };
3018
3019 static void cirrus_vga_class_init(ObjectClass *klass, void *data)
3020 {
3021 DeviceClass *dc = DEVICE_CLASS(klass);
3022 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3023
3024 k->init = pci_cirrus_vga_initfn;
3025 k->romfile = VGABIOS_CIRRUS_FILENAME;
3026 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
3027 k->device_id = CIRRUS_ID_CLGD5446;
3028 k->class_id = PCI_CLASS_DISPLAY_VGA;
3029 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
3030 dc->desc = "Cirrus CLGD 54xx VGA";
3031 dc->vmsd = &vmstate_pci_cirrus_vga;
3032 dc->props = pci_vga_cirrus_properties;
3033 dc->hotpluggable = false;
3034 }
3035
3036 static const TypeInfo cirrus_vga_info = {
3037 .name = "cirrus-vga",
3038 .parent = TYPE_PCI_DEVICE,
3039 .instance_size = sizeof(PCICirrusVGAState),
3040 .class_init = cirrus_vga_class_init,
3041 };
3042
3043 static void cirrus_vga_register_types(void)
3044 {
3045 type_register_static(&isa_cirrus_vga_info);
3046 type_register_static(&cirrus_vga_info);
3047 }
3048
3049 type_init(cirrus_vga_register_types)
AR7 emulation for QEMU