4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
23 #include "exec/helper-proto.h"
24 #include "internals.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
28 #define SIGNBIT (uint32_t)0x80000000
29 #define SIGNBIT64 ((uint64_t)1 << 63)
31 static void raise_exception(CPUARMState
*env
, uint32_t excp
,
32 uint32_t syndrome
, uint32_t target_el
)
34 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
36 assert(!excp_is_internal(excp
));
37 cs
->exception_index
= excp
;
38 env
->exception
.syndrome
= syndrome
;
39 env
->exception
.target_el
= target_el
;
43 static int exception_target_el(CPUARMState
*env
)
45 int target_el
= MAX(1, arm_current_el(env
));
47 /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL
48 * to EL3 in this case.
50 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3) && target_el
== 1) {
57 uint32_t HELPER(neon_tbl
)(uint32_t ireg
, uint32_t def
, void *vn
,
64 for (shift
= 0; shift
< 32; shift
+= 8) {
65 uint32_t index
= (ireg
>> shift
) & 0xff;
66 if (index
< maxindex
) {
67 uint32_t tmp
= (table
[index
>> 3] >> ((index
& 7) << 3)) & 0xff;
70 val
|= def
& (0xff << shift
);
76 #if !defined(CONFIG_USER_ONLY)
78 static inline uint32_t merge_syn_data_abort(uint32_t template_syn
,
79 unsigned int target_el
,
80 bool same_el
, bool ea
,
81 bool s1ptw
, bool is_write
,
86 /* ISV is only set for data aborts routed to EL2 and
87 * never for stage-1 page table walks faulting on stage 2.
89 * Furthermore, ISV is only set for certain kinds of load/stores.
90 * If the template syndrome does not have ISV set, we should leave
93 * See ARMv8 specs, D7-1974:
94 * ISS encoding for an exception from a Data Abort, the
97 if (!(template_syn
& ARM_EL_ISV
) || target_el
!= 2 || s1ptw
) {
98 syn
= syn_data_abort_no_iss(same_el
,
99 ea
, 0, s1ptw
, is_write
, fsc
);
101 /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
102 * syndrome created at translation time.
103 * Now we create the runtime syndrome with the remaining fields.
105 syn
= syn_data_abort_with_iss(same_el
,
107 ea
, 0, s1ptw
, is_write
, fsc
,
109 /* Merge the runtime syndrome with the template syndrome. */
115 static void deliver_fault(ARMCPU
*cpu
, vaddr addr
, MMUAccessType access_type
,
116 int mmu_idx
, ARMMMUFaultInfo
*fi
)
118 CPUARMState
*env
= &cpu
->env
;
121 uint32_t syn
, exc
, fsr
, fsc
;
122 ARMMMUIdx arm_mmu_idx
= core_to_arm_mmu_idx(env
, mmu_idx
);
124 target_el
= exception_target_el(env
);
127 env
->cp15
.hpfar_el2
= extract64(fi
->s2addr
, 12, 47) << 4;
129 same_el
= (arm_current_el(env
) == target_el
);
131 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
132 arm_s1_regime_using_lpae_format(env
, arm_mmu_idx
)) {
133 /* LPAE format fault status register : bottom 6 bits are
134 * status code in the same form as needed for syndrome
136 fsr
= arm_fi_to_lfsc(fi
);
137 fsc
= extract32(fsr
, 0, 6);
139 fsr
= arm_fi_to_sfsc(fi
);
140 /* Short format FSR : this fault will never actually be reported
141 * to an EL that uses a syndrome register. Use a (currently)
142 * reserved FSR code in case the constructed syndrome does leak
143 * into the guest somehow.
148 if (access_type
== MMU_INST_FETCH
) {
149 syn
= syn_insn_abort(same_el
, fi
->ea
, fi
->s1ptw
, fsc
);
150 exc
= EXCP_PREFETCH_ABORT
;
152 syn
= merge_syn_data_abort(env
->exception
.syndrome
, target_el
,
153 same_el
, fi
->ea
, fi
->s1ptw
,
154 access_type
== MMU_DATA_STORE
,
156 if (access_type
== MMU_DATA_STORE
157 && arm_feature(env
, ARM_FEATURE_V6
)) {
160 exc
= EXCP_DATA_ABORT
;
163 env
->exception
.vaddress
= addr
;
164 env
->exception
.fsr
= fsr
;
165 raise_exception(env
, exc
, syn
, target_el
);
168 /* try to fill the TLB and return an exception if error. If retaddr is
169 * NULL, it means that the function was called in C code (i.e. not
170 * from generated code or from helper.c)
172 void tlb_fill(CPUState
*cs
, target_ulong addr
, int size
,
173 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
176 ARMMMUFaultInfo fi
= {};
178 ret
= arm_tlb_fill(cs
, addr
, access_type
, mmu_idx
, &fi
);
180 ARMCPU
*cpu
= ARM_CPU(cs
);
182 /* now we have a real cpu fault */
183 cpu_restore_state(cs
, retaddr
, true);
185 deliver_fault(cpu
, addr
, access_type
, mmu_idx
, &fi
);
189 /* Raise a data fault alignment exception for the specified virtual address */
190 void arm_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
191 MMUAccessType access_type
,
192 int mmu_idx
, uintptr_t retaddr
)
194 ARMCPU
*cpu
= ARM_CPU(cs
);
195 ARMMMUFaultInfo fi
= {};
197 /* now we have a real cpu fault */
198 cpu_restore_state(cs
, retaddr
, true);
200 fi
.type
= ARMFault_Alignment
;
201 deliver_fault(cpu
, vaddr
, access_type
, mmu_idx
, &fi
);
204 /* arm_cpu_do_transaction_failed: handle a memory system error response
205 * (eg "no device/memory present at address") by raising an external abort
208 void arm_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
209 vaddr addr
, unsigned size
,
210 MMUAccessType access_type
,
211 int mmu_idx
, MemTxAttrs attrs
,
212 MemTxResult response
, uintptr_t retaddr
)
214 ARMCPU
*cpu
= ARM_CPU(cs
);
215 ARMMMUFaultInfo fi
= {};
217 /* now we have a real cpu fault */
218 cpu_restore_state(cs
, retaddr
, true);
220 fi
.ea
= arm_extabort_type(response
);
221 fi
.type
= ARMFault_SyncExternal
;
222 deliver_fault(cpu
, addr
, access_type
, mmu_idx
, &fi
);
225 #endif /* !defined(CONFIG_USER_ONLY) */
227 uint32_t HELPER(add_setq
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
229 uint32_t res
= a
+ b
;
230 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
))
235 uint32_t HELPER(add_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
237 uint32_t res
= a
+ b
;
238 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
)) {
240 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
245 uint32_t HELPER(sub_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
247 uint32_t res
= a
- b
;
248 if (((res
^ a
) & SIGNBIT
) && ((a
^ b
) & SIGNBIT
)) {
250 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
255 uint32_t HELPER(double_saturate
)(CPUARMState
*env
, int32_t val
)
258 if (val
>= 0x40000000) {
261 } else if (val
<= (int32_t)0xc0000000) {
270 uint32_t HELPER(add_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
272 uint32_t res
= a
+ b
;
280 uint32_t HELPER(sub_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
282 uint32_t res
= a
- b
;
290 /* Signed saturation. */
291 static inline uint32_t do_ssat(CPUARMState
*env
, int32_t val
, int shift
)
297 mask
= (1u << shift
) - 1;
301 } else if (top
< -1) {
308 /* Unsigned saturation. */
309 static inline uint32_t do_usat(CPUARMState
*env
, int32_t val
, int shift
)
313 max
= (1u << shift
) - 1;
317 } else if (val
> max
) {
324 /* Signed saturate. */
325 uint32_t HELPER(ssat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
327 return do_ssat(env
, x
, shift
);
330 /* Dual halfword signed saturate. */
331 uint32_t HELPER(ssat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
335 res
= (uint16_t)do_ssat(env
, (int16_t)x
, shift
);
336 res
|= do_ssat(env
, ((int32_t)x
) >> 16, shift
) << 16;
340 /* Unsigned saturate. */
341 uint32_t HELPER(usat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
343 return do_usat(env
, x
, shift
);
346 /* Dual halfword unsigned saturate. */
347 uint32_t HELPER(usat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
351 res
= (uint16_t)do_usat(env
, (int16_t)x
, shift
);
352 res
|= do_usat(env
, ((int32_t)x
) >> 16, shift
) << 16;
356 void HELPER(setend
)(CPUARMState
*env
)
358 env
->uncached_cpsr
^= CPSR_E
;
361 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
362 * The function returns the target EL (1-3) if the instruction is to be trapped;
363 * otherwise it returns 0 indicating it is not trapped.
365 static inline int check_wfx_trap(CPUARMState
*env
, bool is_wfe
)
367 int cur_el
= arm_current_el(env
);
370 if (arm_feature(env
, ARM_FEATURE_M
)) {
371 /* M profile cores can never trap WFI/WFE. */
375 /* If we are currently in EL0 then we need to check if SCTLR is set up for
376 * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
378 if (cur_el
< 1 && arm_feature(env
, ARM_FEATURE_V8
)) {
381 mask
= is_wfe
? SCTLR_nTWE
: SCTLR_nTWI
;
382 if (arm_is_secure_below_el3(env
) && !arm_el_is_aa64(env
, 3)) {
383 /* Secure EL0 and Secure PL1 is at EL3 */
389 if (!(env
->cp15
.sctlr_el
[target_el
] & mask
)) {
394 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
395 * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
396 * bits will be zero indicating no trap.
398 if (cur_el
< 2 && !arm_is_secure(env
)) {
399 mask
= (is_wfe
) ? HCR_TWE
: HCR_TWI
;
400 if (env
->cp15
.hcr_el2
& mask
) {
405 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
407 mask
= (is_wfe
) ? SCR_TWE
: SCR_TWI
;
408 if (env
->cp15
.scr_el3
& mask
) {
416 void HELPER(wfi
)(CPUARMState
*env
, uint32_t insn_len
)
418 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
419 int target_el
= check_wfx_trap(env
, false);
421 if (cpu_has_work(cs
)) {
422 /* Don't bother to go into our "low power state" if
423 * we would just wake up immediately.
430 raise_exception(env
, EXCP_UDEF
, syn_wfx(1, 0xe, 0, insn_len
== 2),
434 cs
->exception_index
= EXCP_HLT
;
439 void HELPER(wfe
)(CPUARMState
*env
)
441 /* This is a hint instruction that is semantically different
442 * from YIELD even though we currently implement it identically.
443 * Don't actually halt the CPU, just yield back to top
444 * level loop. This is not going into a "low power state"
445 * (ie halting until some event occurs), so we never take
446 * a configurable trap to a different exception level.
451 void HELPER(yield
)(CPUARMState
*env
)
453 ARMCPU
*cpu
= arm_env_get_cpu(env
);
454 CPUState
*cs
= CPU(cpu
);
456 /* This is a non-trappable hint instruction that generally indicates
457 * that the guest is currently busy-looping. Yield control back to the
458 * top level loop so that a more deserving VCPU has a chance to run.
460 cs
->exception_index
= EXCP_YIELD
;
464 /* Raise an internal-to-QEMU exception. This is limited to only
465 * those EXCP values which are special cases for QEMU to interrupt
466 * execution and not to be used for exceptions which are passed to
467 * the guest (those must all have syndrome information and thus should
468 * use exception_with_syndrome).
470 void HELPER(exception_internal
)(CPUARMState
*env
, uint32_t excp
)
472 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
474 assert(excp_is_internal(excp
));
475 cs
->exception_index
= excp
;
479 /* Raise an exception with the specified syndrome register value */
480 void HELPER(exception_with_syndrome
)(CPUARMState
*env
, uint32_t excp
,
481 uint32_t syndrome
, uint32_t target_el
)
483 raise_exception(env
, excp
, syndrome
, target_el
);
486 /* Raise an EXCP_BKPT with the specified syndrome register value,
487 * targeting the correct exception level for debug exceptions.
489 void HELPER(exception_bkpt_insn
)(CPUARMState
*env
, uint32_t syndrome
)
491 /* FSR will only be used if the debug target EL is AArch32. */
492 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
493 /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
494 * values to the guest that it shouldn't be able to see at its
495 * exception/security level.
497 env
->exception
.vaddress
= 0;
498 raise_exception(env
, EXCP_BKPT
, syndrome
, arm_debug_target_el(env
));
501 uint32_t HELPER(cpsr_read
)(CPUARMState
*env
)
503 return cpsr_read(env
) & ~(CPSR_EXEC
| CPSR_RESERVED
);
506 void HELPER(cpsr_write
)(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
508 cpsr_write(env
, val
, mask
, CPSRWriteByInstr
);
511 /* Write the CPSR for a 32-bit exception return */
512 void HELPER(cpsr_write_eret
)(CPUARMState
*env
, uint32_t val
)
514 qemu_mutex_lock_iothread();
515 arm_call_pre_el_change_hook(arm_env_get_cpu(env
));
516 qemu_mutex_unlock_iothread();
518 cpsr_write(env
, val
, CPSR_ERET_MASK
, CPSRWriteExceptionReturn
);
520 /* Generated code has already stored the new PC value, but
521 * without masking out its low bits, because which bits need
522 * masking depends on whether we're returning to Thumb or ARM
523 * state. Do the masking now.
525 env
->regs
[15] &= (env
->thumb
? ~1 : ~3);
527 qemu_mutex_lock_iothread();
528 arm_call_el_change_hook(arm_env_get_cpu(env
));
529 qemu_mutex_unlock_iothread();
532 /* Access to user mode registers from privileged modes. */
533 uint32_t HELPER(get_user_reg
)(CPUARMState
*env
, uint32_t regno
)
538 val
= env
->banked_r13
[BANK_USRSYS
];
539 } else if (regno
== 14) {
540 val
= env
->banked_r14
[BANK_USRSYS
];
541 } else if (regno
>= 8
542 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
543 val
= env
->usr_regs
[regno
- 8];
545 val
= env
->regs
[regno
];
550 void HELPER(set_user_reg
)(CPUARMState
*env
, uint32_t regno
, uint32_t val
)
553 env
->banked_r13
[BANK_USRSYS
] = val
;
554 } else if (regno
== 14) {
555 env
->banked_r14
[BANK_USRSYS
] = val
;
556 } else if (regno
>= 8
557 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
558 env
->usr_regs
[regno
- 8] = val
;
560 env
->regs
[regno
] = val
;
564 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
566 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
569 env
->banked_r13
[bank_number(mode
)] = val
;
573 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
575 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_SYS
) {
576 /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
577 * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
579 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
580 exception_target_el(env
));
583 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
584 return env
->regs
[13];
586 return env
->banked_r13
[bank_number(mode
)];
590 static void msr_mrs_banked_exc_checks(CPUARMState
*env
, uint32_t tgtmode
,
593 /* Raise an exception if the requested access is one of the UNPREDICTABLE
594 * cases; otherwise return. This broadly corresponds to the pseudocode
595 * BankedRegisterAccessValid() and SPSRAccessValid(),
596 * except that we have already handled some cases at translate time.
598 int curmode
= env
->uncached_cpsr
& CPSR_M
;
600 if (curmode
== tgtmode
) {
604 if (tgtmode
== ARM_CPU_MODE_USR
) {
607 if (curmode
!= ARM_CPU_MODE_FIQ
) {
612 if (curmode
== ARM_CPU_MODE_SYS
) {
617 if (curmode
== ARM_CPU_MODE_HYP
|| curmode
== ARM_CPU_MODE_SYS
) {
626 if (tgtmode
== ARM_CPU_MODE_HYP
) {
628 case 17: /* ELR_Hyp */
629 if (curmode
!= ARM_CPU_MODE_HYP
&& curmode
!= ARM_CPU_MODE_MON
) {
634 if (curmode
!= ARM_CPU_MODE_MON
) {
644 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
645 exception_target_el(env
));
648 void HELPER(msr_banked
)(CPUARMState
*env
, uint32_t value
, uint32_t tgtmode
,
651 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
655 env
->banked_spsr
[bank_number(tgtmode
)] = value
;
657 case 17: /* ELR_Hyp */
658 env
->elr_el
[2] = value
;
661 env
->banked_r13
[bank_number(tgtmode
)] = value
;
664 env
->banked_r14
[bank_number(tgtmode
)] = value
;
668 case ARM_CPU_MODE_USR
:
669 env
->usr_regs
[regno
- 8] = value
;
671 case ARM_CPU_MODE_FIQ
:
672 env
->fiq_regs
[regno
- 8] = value
;
675 g_assert_not_reached();
679 g_assert_not_reached();
683 uint32_t HELPER(mrs_banked
)(CPUARMState
*env
, uint32_t tgtmode
, uint32_t regno
)
685 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
689 return env
->banked_spsr
[bank_number(tgtmode
)];
690 case 17: /* ELR_Hyp */
691 return env
->elr_el
[2];
693 return env
->banked_r13
[bank_number(tgtmode
)];
695 return env
->banked_r14
[bank_number(tgtmode
)];
698 case ARM_CPU_MODE_USR
:
699 return env
->usr_regs
[regno
- 8];
700 case ARM_CPU_MODE_FIQ
:
701 return env
->fiq_regs
[regno
- 8];
703 g_assert_not_reached();
706 g_assert_not_reached();
710 void HELPER(access_check_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t syndrome
,
713 const ARMCPRegInfo
*ri
= rip
;
716 if (arm_feature(env
, ARM_FEATURE_XSCALE
) && ri
->cp
< 14
717 && extract32(env
->cp15
.c15_cpar
, ri
->cp
, 1) == 0) {
718 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
725 switch (ri
->accessfn(env
, ri
, isread
)) {
729 target_el
= exception_target_el(env
);
731 case CP_ACCESS_TRAP_EL2
:
732 /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
733 * a bug in the access function.
735 assert(!arm_is_secure(env
) && arm_current_el(env
) != 3);
738 case CP_ACCESS_TRAP_EL3
:
741 case CP_ACCESS_TRAP_UNCATEGORIZED
:
742 target_el
= exception_target_el(env
);
743 syndrome
= syn_uncategorized();
745 case CP_ACCESS_TRAP_UNCATEGORIZED_EL2
:
747 syndrome
= syn_uncategorized();
749 case CP_ACCESS_TRAP_UNCATEGORIZED_EL3
:
751 syndrome
= syn_uncategorized();
753 case CP_ACCESS_TRAP_FP_EL2
:
755 /* Since we are an implementation that takes exceptions on a trapped
756 * conditional insn only if the insn has passed its condition code
757 * check, we take the IMPDEF choice to always report CV=1 COND=0xe
758 * (which is also the required value for AArch64 traps).
760 syndrome
= syn_fp_access_trap(1, 0xe, false);
762 case CP_ACCESS_TRAP_FP_EL3
:
764 syndrome
= syn_fp_access_trap(1, 0xe, false);
767 g_assert_not_reached();
770 raise_exception(env
, EXCP_UDEF
, syndrome
, target_el
);
773 void HELPER(set_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t value
)
775 const ARMCPRegInfo
*ri
= rip
;
777 if (ri
->type
& ARM_CP_IO
) {
778 qemu_mutex_lock_iothread();
779 ri
->writefn(env
, ri
, value
);
780 qemu_mutex_unlock_iothread();
782 ri
->writefn(env
, ri
, value
);
786 uint32_t HELPER(get_cp_reg
)(CPUARMState
*env
, void *rip
)
788 const ARMCPRegInfo
*ri
= rip
;
791 if (ri
->type
& ARM_CP_IO
) {
792 qemu_mutex_lock_iothread();
793 res
= ri
->readfn(env
, ri
);
794 qemu_mutex_unlock_iothread();
796 res
= ri
->readfn(env
, ri
);
802 void HELPER(set_cp_reg64
)(CPUARMState
*env
, void *rip
, uint64_t value
)
804 const ARMCPRegInfo
*ri
= rip
;
806 if (ri
->type
& ARM_CP_IO
) {
807 qemu_mutex_lock_iothread();
808 ri
->writefn(env
, ri
, value
);
809 qemu_mutex_unlock_iothread();
811 ri
->writefn(env
, ri
, value
);
815 uint64_t HELPER(get_cp_reg64
)(CPUARMState
*env
, void *rip
)
817 const ARMCPRegInfo
*ri
= rip
;
820 if (ri
->type
& ARM_CP_IO
) {
821 qemu_mutex_lock_iothread();
822 res
= ri
->readfn(env
, ri
);
823 qemu_mutex_unlock_iothread();
825 res
= ri
->readfn(env
, ri
);
831 void HELPER(msr_i_pstate
)(CPUARMState
*env
, uint32_t op
, uint32_t imm
)
833 /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
834 * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
835 * to catch that case at translate time.
837 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
838 uint32_t syndrome
= syn_aa64_sysregtrap(0, extract32(op
, 0, 3),
839 extract32(op
, 3, 3), 4,
841 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
845 case 0x05: /* SPSel */
846 update_spsel(env
, imm
);
848 case 0x1e: /* DAIFSet */
849 env
->daif
|= (imm
<< 6) & PSTATE_DAIF
;
851 case 0x1f: /* DAIFClear */
852 env
->daif
&= ~((imm
<< 6) & PSTATE_DAIF
);
855 g_assert_not_reached();
859 void HELPER(clear_pstate_ss
)(CPUARMState
*env
)
861 env
->pstate
&= ~PSTATE_SS
;
864 void HELPER(pre_hvc
)(CPUARMState
*env
)
866 ARMCPU
*cpu
= arm_env_get_cpu(env
);
867 int cur_el
= arm_current_el(env
);
868 /* FIXME: Use actual secure state. */
872 if (arm_is_psci_call(cpu
, EXCP_HVC
)) {
873 /* If PSCI is enabled and this looks like a valid PSCI call then
874 * that overrides the architecturally mandated HVC behaviour.
879 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
880 /* If EL2 doesn't exist, HVC always UNDEFs */
882 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
883 /* EL3.HCE has priority over EL2.HCD. */
884 undef
= !(env
->cp15
.scr_el3
& SCR_HCE
);
886 undef
= env
->cp15
.hcr_el2
& HCR_HCD
;
889 /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
890 * For ARMv8/AArch64, HVC is allowed in EL3.
891 * Note that we've already trapped HVC from EL0 at translation
894 if (secure
&& (!is_a64(env
) || cur_el
== 1)) {
899 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
900 exception_target_el(env
));
904 void HELPER(pre_smc
)(CPUARMState
*env
, uint32_t syndrome
)
906 ARMCPU
*cpu
= arm_env_get_cpu(env
);
907 int cur_el
= arm_current_el(env
);
908 bool secure
= arm_is_secure(env
);
909 bool smd
= env
->cp15
.scr_el3
& SCR_SMD
;
910 /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
911 * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
912 * extensions, SMD only applies to NS state.
913 * On ARMv7 without the Virtualization extensions, the SMD bit
914 * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
915 * so we need not special case this here.
917 bool undef
= arm_feature(env
, ARM_FEATURE_AARCH64
) ? smd
: smd
&& !secure
;
919 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
920 cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
921 /* If we have no EL3 then SMC always UNDEFs and can't be
922 * trapped to EL2. PSCI-via-SMC is a sort of ersatz EL3
923 * firmware within QEMU, and we want an EL2 guest to be able
924 * to forbid its EL1 from making PSCI calls into QEMU's
925 * "firmware" via HCR.TSC, so for these purposes treat
926 * PSCI-via-SMC as implying an EL3.
929 } else if (!secure
&& cur_el
== 1 && (env
->cp15
.hcr_el2
& HCR_TSC
)) {
930 /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
931 * We also want an EL2 guest to be able to forbid its EL1 from
932 * making PSCI calls into QEMU's "firmware" via HCR.TSC.
934 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);
937 /* If PSCI is enabled and this looks like a valid PSCI call then
938 * suppress the UNDEF -- we'll catch the SMC exception and
939 * implement the PSCI call behaviour there.
941 if (undef
&& !arm_is_psci_call(cpu
, EXCP_SMC
)) {
942 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
943 exception_target_el(env
));
947 static int el_from_spsr(uint32_t spsr
)
949 /* Return the exception level that this SPSR is requesting a return to,
950 * or -1 if it is invalid (an illegal return)
952 if (spsr
& PSTATE_nRW
) {
953 switch (spsr
& CPSR_M
) {
954 case ARM_CPU_MODE_USR
:
956 case ARM_CPU_MODE_HYP
:
958 case ARM_CPU_MODE_FIQ
:
959 case ARM_CPU_MODE_IRQ
:
960 case ARM_CPU_MODE_SVC
:
961 case ARM_CPU_MODE_ABT
:
962 case ARM_CPU_MODE_UND
:
963 case ARM_CPU_MODE_SYS
:
965 case ARM_CPU_MODE_MON
:
966 /* Returning to Mon from AArch64 is never possible,
967 * so this is an illegal return.
973 if (extract32(spsr
, 1, 1)) {
974 /* Return with reserved M[1] bit set */
977 if (extract32(spsr
, 0, 4) == 1) {
978 /* return to EL0 with M[0] bit set */
981 return extract32(spsr
, 2, 2);
985 void HELPER(exception_return
)(CPUARMState
*env
)
987 int cur_el
= arm_current_el(env
);
988 unsigned int spsr_idx
= aarch64_banked_spsr_index(cur_el
);
989 uint32_t spsr
= env
->banked_spsr
[spsr_idx
];
991 bool return_to_aa64
= (spsr
& PSTATE_nRW
) == 0;
993 aarch64_save_sp(env
, cur_el
);
995 arm_clear_exclusive(env
);
997 /* We must squash the PSTATE.SS bit to zero unless both of the
999 * 1. debug exceptions are currently disabled
1000 * 2. singlestep will be active in the EL we return to
1001 * We check 1 here and 2 after we've done the pstate/cpsr write() to
1002 * transition to the EL we're going to.
1004 if (arm_generate_debug_exceptions(env
)) {
1008 new_el
= el_from_spsr(spsr
);
1010 goto illegal_return
;
1013 || (new_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
))) {
1014 /* Disallow return to an EL which is unimplemented or higher
1015 * than the current one.
1017 goto illegal_return
;
1020 if (new_el
!= 0 && arm_el_is_aa64(env
, new_el
) != return_to_aa64
) {
1021 /* Return to an EL which is configured for a different register width */
1022 goto illegal_return
;
1025 if (new_el
== 2 && arm_is_secure_below_el3(env
)) {
1026 /* Return to the non-existent secure-EL2 */
1027 goto illegal_return
;
1030 if (new_el
== 1 && (env
->cp15
.hcr_el2
& HCR_TGE
)
1031 && !arm_is_secure_below_el3(env
)) {
1032 goto illegal_return
;
1035 qemu_mutex_lock_iothread();
1036 arm_call_pre_el_change_hook(arm_env_get_cpu(env
));
1037 qemu_mutex_unlock_iothread();
1039 if (!return_to_aa64
) {
1041 /* We do a raw CPSR write because aarch64_sync_64_to_32()
1042 * will sort the register banks out for us, and we've already
1043 * caught all the bad-mode cases in el_from_spsr().
1045 cpsr_write(env
, spsr
, ~0, CPSRWriteRaw
);
1046 if (!arm_singlestep_active(env
)) {
1047 env
->uncached_cpsr
&= ~PSTATE_SS
;
1049 aarch64_sync_64_to_32(env
);
1051 if (spsr
& CPSR_T
) {
1052 env
->regs
[15] = env
->elr_el
[cur_el
] & ~0x1;
1054 env
->regs
[15] = env
->elr_el
[cur_el
] & ~0x3;
1056 qemu_log_mask(CPU_LOG_INT
, "Exception return from AArch64 EL%d to "
1057 "AArch32 EL%d PC 0x%" PRIx32
"\n",
1058 cur_el
, new_el
, env
->regs
[15]);
1061 pstate_write(env
, spsr
);
1062 if (!arm_singlestep_active(env
)) {
1063 env
->pstate
&= ~PSTATE_SS
;
1065 aarch64_restore_sp(env
, new_el
);
1066 env
->pc
= env
->elr_el
[cur_el
];
1067 qemu_log_mask(CPU_LOG_INT
, "Exception return from AArch64 EL%d to "
1068 "AArch64 EL%d PC 0x%" PRIx64
"\n",
1069 cur_el
, new_el
, env
->pc
);
1072 qemu_mutex_lock_iothread();
1073 arm_call_el_change_hook(arm_env_get_cpu(env
));
1074 qemu_mutex_unlock_iothread();
1079 /* Illegal return events of various kinds have architecturally
1080 * mandated behaviour:
1081 * restore NZCV and DAIF from SPSR_ELx
1083 * restore PC from ELR_ELx
1084 * no change to exception level, execution state or stack pointer
1086 env
->pstate
|= PSTATE_IL
;
1087 env
->pc
= env
->elr_el
[cur_el
];
1088 spsr
&= PSTATE_NZCV
| PSTATE_DAIF
;
1089 spsr
|= pstate_read(env
) & ~(PSTATE_NZCV
| PSTATE_DAIF
);
1090 pstate_write(env
, spsr
);
1091 if (!arm_singlestep_active(env
)) {
1092 env
->pstate
&= ~PSTATE_SS
;
1094 qemu_log_mask(LOG_GUEST_ERROR
, "Illegal exception return at EL%d: "
1095 "resuming execution at 0x%" PRIx64
"\n", cur_el
, env
->pc
);
1098 /* Return true if the linked breakpoint entry lbn passes its checks */
1099 static bool linked_bp_matches(ARMCPU
*cpu
, int lbn
)
1101 CPUARMState
*env
= &cpu
->env
;
1102 uint64_t bcr
= env
->cp15
.dbgbcr
[lbn
];
1103 int brps
= extract32(cpu
->dbgdidr
, 24, 4);
1104 int ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
1106 uint32_t contextidr
;
1108 /* Links to unimplemented or non-context aware breakpoints are
1109 * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
1110 * as if linked to an UNKNOWN context-aware breakpoint (in which
1111 * case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
1112 * We choose the former.
1114 if (lbn
> brps
|| lbn
< (brps
- ctx_cmps
)) {
1118 bcr
= env
->cp15
.dbgbcr
[lbn
];
1120 if (extract64(bcr
, 0, 1) == 0) {
1121 /* Linked breakpoint disabled : generate no events */
1125 bt
= extract64(bcr
, 20, 4);
1127 /* We match the whole register even if this is AArch32 using the
1128 * short descriptor format (in which case it holds both PROCID and ASID),
1129 * since we don't implement the optional v7 context ID masking.
1131 contextidr
= extract64(env
->cp15
.contextidr_el
[1], 0, 32);
1134 case 3: /* linked context ID match */
1135 if (arm_current_el(env
) > 1) {
1136 /* Context matches never fire in EL2 or (AArch64) EL3 */
1139 return (contextidr
== extract64(env
->cp15
.dbgbvr
[lbn
], 0, 32));
1140 case 5: /* linked address mismatch (reserved in AArch64) */
1141 case 9: /* linked VMID match (reserved if no EL2) */
1142 case 11: /* linked context ID and VMID match (reserved if no EL2) */
1144 /* Links to Unlinked context breakpoints must generate no
1145 * events; we choose to do the same for reserved values too.
1153 static bool bp_wp_matches(ARMCPU
*cpu
, int n
, bool is_wp
)
1155 CPUARMState
*env
= &cpu
->env
;
1157 int pac
, hmc
, ssc
, wt
, lbn
;
1158 /* Note that for watchpoints the check is against the CPU security
1159 * state, not the S/NS attribute on the offending data access.
1161 bool is_secure
= arm_is_secure(env
);
1162 int access_el
= arm_current_el(env
);
1165 CPUWatchpoint
*wp
= env
->cpu_watchpoint
[n
];
1167 if (!wp
|| !(wp
->flags
& BP_WATCHPOINT_HIT
)) {
1170 cr
= env
->cp15
.dbgwcr
[n
];
1171 if (wp
->hitattrs
.user
) {
1172 /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
1173 * match watchpoints as if they were accesses done at EL0, even if
1174 * the CPU is at EL1 or higher.
1179 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1181 if (!env
->cpu_breakpoint
[n
] || env
->cpu_breakpoint
[n
]->pc
!= pc
) {
1184 cr
= env
->cp15
.dbgbcr
[n
];
1186 /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
1187 * enabled and that the address and access type match; for breakpoints
1188 * we know the address matched; check the remaining fields, including
1189 * linked breakpoints. We rely on WCR and BCR having the same layout
1190 * for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
1191 * Note that some combinations of {PAC, HMC, SSC} are reserved and
1192 * must act either like some valid combination or as if the watchpoint
1193 * were disabled. We choose the former, and use this together with
1194 * the fact that EL3 must always be Secure and EL2 must always be
1195 * Non-Secure to simplify the code slightly compared to the full
1196 * table in the ARM ARM.
1198 pac
= extract64(cr
, 1, 2);
1199 hmc
= extract64(cr
, 13, 1);
1200 ssc
= extract64(cr
, 14, 2);
1218 switch (access_el
) {
1226 if (extract32(pac
, 0, 1) == 0) {
1231 if (extract32(pac
, 1, 1) == 0) {
1236 g_assert_not_reached();
1239 wt
= extract64(cr
, 20, 1);
1240 lbn
= extract64(cr
, 16, 4);
1242 if (wt
&& !linked_bp_matches(cpu
, lbn
)) {
1249 static bool check_watchpoints(ARMCPU
*cpu
)
1251 CPUARMState
*env
= &cpu
->env
;
1254 /* If watchpoints are disabled globally or we can't take debug
1255 * exceptions here then watchpoint firings are ignored.
1257 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1258 || !arm_generate_debug_exceptions(env
)) {
1262 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_watchpoint
); n
++) {
1263 if (bp_wp_matches(cpu
, n
, true)) {
1270 static bool check_breakpoints(ARMCPU
*cpu
)
1272 CPUARMState
*env
= &cpu
->env
;
1275 /* If breakpoints are disabled globally or we can't take debug
1276 * exceptions here then breakpoint firings are ignored.
1278 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1279 || !arm_generate_debug_exceptions(env
)) {
1283 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_breakpoint
); n
++) {
1284 if (bp_wp_matches(cpu
, n
, false)) {
1291 void HELPER(check_breakpoints
)(CPUARMState
*env
)
1293 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1295 if (check_breakpoints(cpu
)) {
1296 HELPER(exception_internal(env
, EXCP_DEBUG
));
1300 bool arm_debug_check_watchpoint(CPUState
*cs
, CPUWatchpoint
*wp
)
1302 /* Called by core code when a CPU watchpoint fires; need to check if this
1303 * is also an architectural watchpoint match.
1305 ARMCPU
*cpu
= ARM_CPU(cs
);
1307 return check_watchpoints(cpu
);
1310 vaddr
arm_adjust_watchpoint_address(CPUState
*cs
, vaddr addr
, int len
)
1312 ARMCPU
*cpu
= ARM_CPU(cs
);
1313 CPUARMState
*env
= &cpu
->env
;
1315 /* In BE32 system mode, target memory is stored byteswapped (on a
1316 * little-endian host system), and by the time we reach here (via an
1317 * opcode helper) the addresses of subword accesses have been adjusted
1318 * to account for that, which means that watchpoints will not match.
1319 * Undo the adjustment here.
1321 if (arm_sctlr_b(env
)) {
1324 } else if (len
== 2) {
1332 void arm_debug_excp_handler(CPUState
*cs
)
1334 /* Called by core code when a watchpoint or breakpoint fires;
1335 * need to check which one and raise the appropriate exception.
1337 ARMCPU
*cpu
= ARM_CPU(cs
);
1338 CPUARMState
*env
= &cpu
->env
;
1339 CPUWatchpoint
*wp_hit
= cs
->watchpoint_hit
;
1342 if (wp_hit
->flags
& BP_CPU
) {
1343 bool wnr
= (wp_hit
->flags
& BP_WATCHPOINT_HIT_WRITE
) != 0;
1344 bool same_el
= arm_debug_target_el(env
) == arm_current_el(env
);
1346 cs
->watchpoint_hit
= NULL
;
1348 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
1349 env
->exception
.vaddress
= wp_hit
->hitaddr
;
1350 raise_exception(env
, EXCP_DATA_ABORT
,
1351 syn_watchpoint(same_el
, 0, wnr
),
1352 arm_debug_target_el(env
));
1355 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1356 bool same_el
= (arm_debug_target_el(env
) == arm_current_el(env
));
1358 /* (1) GDB breakpoints should be handled first.
1359 * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
1360 * since singlestep is also done by generating a debug internal
1363 if (cpu_breakpoint_test(cs
, pc
, BP_GDB
)
1364 || !cpu_breakpoint_test(cs
, pc
, BP_CPU
)) {
1368 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
1369 /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
1370 * values to the guest that it shouldn't be able to see at its
1371 * exception/security level.
1373 env
->exception
.vaddress
= 0;
1374 raise_exception(env
, EXCP_PREFETCH_ABORT
,
1375 syn_breakpoint(same_el
),
1376 arm_debug_target_el(env
));
1380 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
1381 The only way to do that in TCG is a conditional branch, which clobbers
1382 all our temporaries. For now implement these as helper functions. */
1384 /* Similarly for variable shift instructions. */
1386 uint32_t HELPER(shl_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1388 int shift
= i
& 0xff;
1395 } else if (shift
!= 0) {
1396 env
->CF
= (x
>> (32 - shift
)) & 1;
1402 uint32_t HELPER(shr_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1404 int shift
= i
& 0xff;
1407 env
->CF
= (x
>> 31) & 1;
1411 } else if (shift
!= 0) {
1412 env
->CF
= (x
>> (shift
- 1)) & 1;
1418 uint32_t HELPER(sar_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1420 int shift
= i
& 0xff;
1422 env
->CF
= (x
>> 31) & 1;
1423 return (int32_t)x
>> 31;
1424 } else if (shift
!= 0) {
1425 env
->CF
= (x
>> (shift
- 1)) & 1;
1426 return (int32_t)x
>> shift
;
1431 uint32_t HELPER(ror_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1435 shift
= shift1
& 0x1f;
1438 env
->CF
= (x
>> 31) & 1;
1441 env
->CF
= (x
>> (shift
- 1)) & 1;
1442 return ((uint32_t)x
>> shift
) | (x
<< (32 - shift
));