ati-vga: Fix check for blt outside vram
[qemu/ar7.git] / tests / pnv-xscom-test.c
blob63d464048d538aec21e04c76f74157ac869d8eb0
1 /*
2 * QTest testcase for PowerNV XSCOM bus
4 * Copyright (c) 2016, IBM Corporation.
6 * This work is licensed under the terms of the GNU GPL, version 2 or
7 * later. See the COPYING file in the top-level directory.
8 */
9 #include "qemu/osdep.h"
11 #include "libqtest.h"
13 typedef enum PnvChipType {
14 PNV_CHIP_POWER8E, /* AKA Murano (default) */
15 PNV_CHIP_POWER8, /* AKA Venice */
16 PNV_CHIP_POWER8NVL, /* AKA Naples */
17 PNV_CHIP_POWER9, /* AKA Nimbus */
18 } PnvChipType;
20 typedef struct PnvChip {
21 PnvChipType chip_type;
22 const char *cpu_model;
23 uint64_t xscom_base;
24 uint64_t cfam_id;
25 uint32_t first_core;
26 } PnvChip;
28 static const PnvChip pnv_chips[] = {
30 .chip_type = PNV_CHIP_POWER8,
31 .cpu_model = "POWER8",
32 .xscom_base = 0x0003fc0000000000ull,
33 .cfam_id = 0x220ea04980000000ull,
34 .first_core = 0x1,
35 }, {
36 .chip_type = PNV_CHIP_POWER8NVL,
37 .cpu_model = "POWER8NVL",
38 .xscom_base = 0x0003fc0000000000ull,
39 .cfam_id = 0x120d304980000000ull,
40 .first_core = 0x1,
43 .chip_type = PNV_CHIP_POWER9,
44 .cpu_model = "POWER9",
45 .xscom_base = 0x000603fc00000000ull,
46 .cfam_id = 0x220d104900008000ull,
47 .first_core = 0x0,
51 static uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba)
53 uint64_t addr = chip->xscom_base;
55 if (chip->chip_type == PNV_CHIP_POWER9) {
56 addr |= ((uint64_t) pcba << 3);
57 } else {
58 addr |= (((uint64_t) pcba << 4) & ~0xffull) |
59 (((uint64_t) pcba << 3) & 0x78);
61 return addr;
64 static uint64_t pnv_xscom_read(QTestState *qts, const PnvChip *chip,
65 uint32_t pcba)
67 return qtest_readq(qts, pnv_xscom_addr(chip, pcba));
70 static void test_xscom_cfam_id(QTestState *qts, const PnvChip *chip)
72 uint64_t f000f = pnv_xscom_read(qts, chip, 0xf000f);
74 g_assert_cmphex(f000f, ==, chip->cfam_id);
77 static void test_cfam_id(const void *data)
79 const PnvChip *chip = data;
80 QTestState *qts;
82 qts = qtest_initf("-M powernv,accel=tcg -cpu %s", chip->cpu_model);
83 test_xscom_cfam_id(qts, chip);
84 qtest_quit(qts);
88 #define PNV_XSCOM_EX_CORE_BASE 0x10000000ull
89 #define PNV_XSCOM_EX_BASE(core) \
90 (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
91 #define PNV_XSCOM_P9_EC_BASE(core) \
92 ((uint64_t)(((core) & 0x1F) + 0x20) << 24)
94 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000
96 static void test_xscom_core(QTestState *qts, const PnvChip *chip)
98 uint32_t first_core_dts0 = PNV_XSCOM_EX_DTS_RESULT0;
99 uint64_t dts0;
101 if (chip->chip_type != PNV_CHIP_POWER9) {
102 first_core_dts0 |= PNV_XSCOM_EX_BASE(chip->first_core);
103 } else {
104 first_core_dts0 |= PNV_XSCOM_P9_EC_BASE(chip->first_core);
107 dts0 = pnv_xscom_read(qts, chip, first_core_dts0);
109 g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull);
112 static void test_core(const void *data)
114 const PnvChip *chip = data;
115 QTestState *qts;
117 qts = qtest_initf("-M powernv,accel=tcg -cpu %s", chip->cpu_model);
118 test_xscom_core(qts, chip);
119 qtest_quit(qts);
122 static void add_test(const char *name, void (*test)(const void *data))
124 int i;
126 for (i = 0; i < ARRAY_SIZE(pnv_chips); i++) {
127 char *tname = g_strdup_printf("pnv-xscom/%s/%s", name,
128 pnv_chips[i].cpu_model);
129 qtest_add_data_func(tname, &pnv_chips[i], test);
130 g_free(tname);
134 int main(int argc, char **argv)
136 g_test_init(&argc, &argv, NULL);
138 add_test("cfam_id", test_cfam_id);
139 add_test("core", test_core);
140 return g_test_run();