hw/dma/bcm2835_dma.c

   1 /*
   2  * Raspberry Pi emulation (c) 2012 Gregory Estrade
   3  * This code is licensed under the GNU GPLv2 and later.
   4  */
   5
   6 #include "qemu/osdep.h"
   7 #include "hw/dma/bcm2835_dma.h"
   8
   9 /* DMA CS Control and Status bits */
  10 #define BCM2708_DMA_ACTIVE      (1 << 0)
  11 #define BCM2708_DMA_END         (1 << 1) /* GE */
  12 #define BCM2708_DMA_INT         (1 << 2)
  13 #define BCM2708_DMA_ISPAUSED    (1 << 4)  /* Pause requested or not active */
  14 #define BCM2708_DMA_ISHELD      (1 << 5)  /* Is held by DREQ flow control */
  15 #define BCM2708_DMA_ERR         (1 << 8)
  16 #define BCM2708_DMA_ABORT       (1 << 30) /* stop current CB, go to next, WO */
  17 #define BCM2708_DMA_RESET       (1 << 31) /* WO, self clearing */
  18
  19 /* DMA control block "info" field bits */
  20 #define BCM2708_DMA_INT_EN      (1 << 0)
  21 #define BCM2708_DMA_TDMODE      (1 << 1)
  22 #define BCM2708_DMA_WAIT_RESP   (1 << 3)
  23 #define BCM2708_DMA_D_INC       (1 << 4)
  24 #define BCM2708_DMA_D_WIDTH     (1 << 5)
  25 #define BCM2708_DMA_D_DREQ      (1 << 6)
  26 #define BCM2708_DMA_D_IGNORE    (1 << 7)
  27 #define BCM2708_DMA_S_INC       (1 << 8)
  28 #define BCM2708_DMA_S_WIDTH     (1 << 9)
  29 #define BCM2708_DMA_S_DREQ      (1 << 10)
  30 #define BCM2708_DMA_S_IGNORE    (1 << 11)
  31
  32 /* Register offsets */
  33 #define BCM2708_DMA_CS          0x00 /* Control and Status */
  34 #define BCM2708_DMA_ADDR        0x04 /* Control block address */
  35 /* the current control block appears in the following registers - read only */
  36 #define BCM2708_DMA_INFO        0x08
  37 #define BCM2708_DMA_SOURCE_AD   0x0c
  38 #define BCM2708_DMA_DEST_AD     0x10
  39 #define BCM2708_DMA_TXFR_LEN    0x14
  40 #define BCM2708_DMA_STRIDE      0x18
  41 #define BCM2708_DMA_NEXTCB      0x1C
  42 #define BCM2708_DMA_DEBUG       0x20
  43
  44 #define BCM2708_DMA_INT_STATUS  0xfe0 /* Interrupt status of each channel */
  45 #define BCM2708_DMA_ENABLE      0xff0 /* Global enable bits for each channel */
  46
  47 #define BCM2708_DMA_CS_RW_MASK  0x30ff0001 /* All RW bits in DMA_CS */
  48
  49 static void bcm2835_dma_update(BCM2835DMAState *s, unsigned c)
  50 {
  51     BCM2835DMAChan *ch = &s->chan[c];
  52     uint32_t data, xlen, ylen;
  53     int16_t dst_stride, src_stride;
  54
  55     if (!(s->enable & (1 << c))) {
  56         return;
  57     }
  58
  59     while ((s->enable & (1 << c)) && (ch->conblk_ad != 0)) {
  60         /* CB fetch */
  61         ch->ti = ldl_le_phys(&s->dma_as, ch->conblk_ad);
  62         ch->source_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 4);
  63         ch->dest_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 8);
  64         ch->txfr_len = ldl_le_phys(&s->dma_as, ch->conblk_ad + 12);
  65         ch->stride = ldl_le_phys(&s->dma_as, ch->conblk_ad + 16);
  66         ch->nextconbk = ldl_le_phys(&s->dma_as, ch->conblk_ad + 20);
  67
  68         if (ch->ti & BCM2708_DMA_TDMODE) {
  69             /* 2D transfer mode */
  70             ylen = (ch->txfr_len >> 16) & 0x3fff;
  71             xlen = ch->txfr_len & 0xffff;
  72             dst_stride = ch->stride >> 16;
  73             src_stride = ch->stride & 0xffff;
  74         } else {
  75             ylen = 1;
  76             xlen = ch->txfr_len;
  77             dst_stride = 0;
  78             src_stride = 0;
  79         }
  80
  81         while (ylen != 0) {
  82             /* Normal transfer mode */
  83             while (xlen != 0) {
  84                 if (ch->ti & BCM2708_DMA_S_IGNORE) {
  85                     /* Ignore reads */
  86                     data = 0;
  87                 } else {
  88                     data = ldl_le_phys(&s->dma_as, ch->source_ad);
  89                 }
  90                 if (ch->ti & BCM2708_DMA_S_INC) {
  91                     ch->source_ad += 4;
  92                 }
  93
  94                 if (ch->ti & BCM2708_DMA_D_IGNORE) {
  95                     /* Ignore writes */
  96                 } else {
  97                     stl_le_phys(&s->dma_as, ch->dest_ad, data);
  98                 }
  99                 if (ch->ti & BCM2708_DMA_D_INC) {
 100                     ch->dest_ad += 4;
 101                 }
 102
 103                 /* update remaining transfer length */
 104                 xlen -= 4;
 105                 if (ch->ti & BCM2708_DMA_TDMODE) {
 106                     ch->txfr_len = (ylen << 16) | xlen;
 107                 } else {
 108                     ch->txfr_len = xlen;
 109                 }
 110             }
 111
 112             if (--ylen != 0) {
 113                 ch->source_ad += src_stride;
 114                 ch->dest_ad += dst_stride;
 115             }
 116         }
 117         ch->cs |= BCM2708_DMA_END;
 118         if (ch->ti & BCM2708_DMA_INT_EN) {
 119             ch->cs |= BCM2708_DMA_INT;
 120             s->int_status |= (1 << c);
 121             qemu_set_irq(ch->irq, 1);
 122         }
 123
 124         /* Process next CB */
 125         ch->conblk_ad = ch->nextconbk;
 126     }
 127
 128     ch->cs &= ~BCM2708_DMA_ACTIVE;
 129     ch->cs |= BCM2708_DMA_ISPAUSED;
 130 }
 131
 132 static void bcm2835_dma_chan_reset(BCM2835DMAChan *ch)
 133 {
 134     ch->cs = 0;
 135     ch->conblk_ad = 0;
 136 }
 137
 138 static uint64_t bcm2835_dma_read(BCM2835DMAState *s, hwaddr offset,
 139                                  unsigned size, unsigned c)
 140 {
 141     BCM2835DMAChan *ch;
 142     uint32_t res = 0;
 143
 144     assert(size == 4);
 145     assert(c < BCM2835_DMA_NCHANS);
 146
 147     ch = &s->chan[c];
 148
 149     switch (offset) {
 150     case BCM2708_DMA_CS:
 151         res = ch->cs;
 152         break;
 153     case BCM2708_DMA_ADDR:
 154         res = ch->conblk_ad;
 155         break;
 156     case BCM2708_DMA_INFO:
 157         res = ch->ti;
 158         break;
 159     case BCM2708_DMA_SOURCE_AD:
 160         res = ch->source_ad;
 161         break;
 162     case BCM2708_DMA_DEST_AD:
 163         res = ch->dest_ad;
 164         break;
 165     case BCM2708_DMA_TXFR_LEN:
 166         res = ch->txfr_len;
 167         break;
 168     case BCM2708_DMA_STRIDE:
 169         res = ch->stride;
 170         break;
 171     case BCM2708_DMA_NEXTCB:
 172         res = ch->nextconbk;
 173         break;
 174     case BCM2708_DMA_DEBUG:
 175         res = ch->debug;
 176         break;
 177     default:
 178         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 179                       __func__, offset);
 180         break;
 181     }
 182     return res;
 183 }
 184
 185 static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset,
 186                               uint64_t value, unsigned size, unsigned c)
 187 {
 188     BCM2835DMAChan *ch;
 189     uint32_t oldcs;
 190
 191     assert(size == 4);
 192     assert(c < BCM2835_DMA_NCHANS);
 193
 194     ch = &s->chan[c];
 195
 196     switch (offset) {
 197     case BCM2708_DMA_CS:
 198         oldcs = ch->cs;
 199         if (value & BCM2708_DMA_RESET) {
 200             bcm2835_dma_chan_reset(ch);
 201         }
 202         if (value & BCM2708_DMA_ABORT) {
 203             /* abort is a no-op, since we always run to completion */
 204         }
 205         if (value & BCM2708_DMA_END) {
 206             ch->cs &= ~BCM2708_DMA_END;
 207         }
 208         if (value & BCM2708_DMA_INT) {
 209             ch->cs &= ~BCM2708_DMA_INT;
 210             s->int_status &= ~(1 << c);
 211             qemu_set_irq(ch->irq, 0);
 212         }
 213         ch->cs &= ~BCM2708_DMA_CS_RW_MASK;
 214         ch->cs |= (value & BCM2708_DMA_CS_RW_MASK);
 215         if (!(oldcs & BCM2708_DMA_ACTIVE) && (ch->cs & BCM2708_DMA_ACTIVE)) {
 216             bcm2835_dma_update(s, c);
 217         }
 218         break;
 219     case BCM2708_DMA_ADDR:
 220         ch->conblk_ad = value;
 221         break;
 222     case BCM2708_DMA_DEBUG:
 223         ch->debug = value;
 224         break;
 225     default:
 226         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 227                       __func__, offset);
 228         break;
 229     }
 230 }
 231
 232 static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned size)
 233 {
 234     BCM2835DMAState *s = opaque;
 235
 236     if (offset < 0xf00) {
 237         return bcm2835_dma_read(s, (offset & 0xff), size, (offset >> 8) & 0xf);
 238     } else {
 239         switch (offset) {
 240         case BCM2708_DMA_INT_STATUS:
 241             return s->int_status;
 242         case BCM2708_DMA_ENABLE:
 243             return s->enable;
 244         default:
 245             qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 246                           __func__, offset);
 247             return 0;
 248         }
 249     }
 250 }
 251
 252 static uint64_t bcm2835_dma15_read(void *opaque, hwaddr offset, unsigned size)
 253 {
 254     return bcm2835_dma_read(opaque, (offset & 0xff), size, 15);
 255 }
 256
 257 static void bcm2835_dma0_write(void *opaque, hwaddr offset, uint64_t value,
 258                                unsigned size)
 259 {
 260     BCM2835DMAState *s = opaque;
 261
 262     if (offset < 0xf00) {
 263         bcm2835_dma_write(s, (offset & 0xff), value, size, (offset >> 8) & 0xf);
 264     } else {
 265         switch (offset) {
 266         case BCM2708_DMA_INT_STATUS:
 267             break;
 268         case BCM2708_DMA_ENABLE:
 269             s->enable = (value & 0xffff);
 270             break;
 271         default:
 272             qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 273                           __func__, offset);
 274         }
 275     }
 276
 277 }
 278
 279 static void bcm2835_dma15_write(void *opaque, hwaddr offset, uint64_t value,
 280                                 unsigned size)
 281 {
 282     bcm2835_dma_write(opaque, (offset & 0xff), value, size, 15);
 283 }
 284
 285 static const MemoryRegionOps bcm2835_dma0_ops = {
 286     .read = bcm2835_dma0_read,
 287     .write = bcm2835_dma0_write,
 288     .endianness = DEVICE_NATIVE_ENDIAN,
 289     .valid.min_access_size = 4,
 290     .valid.max_access_size = 4,
 291 };
 292
 293 static const MemoryRegionOps bcm2835_dma15_ops = {
 294     .read = bcm2835_dma15_read,
 295     .write = bcm2835_dma15_write,
 296     .endianness = DEVICE_NATIVE_ENDIAN,
 297     .valid.min_access_size = 4,
 298     .valid.max_access_size = 4,
 299 };
 300
 301 static const VMStateDescription vmstate_bcm2835_dma_chan = {
 302     .name = TYPE_BCM2835_DMA "-chan",
 303     .version_id = 1,
 304     .minimum_version_id = 1,
 305     .fields = (VMStateField[]) {
 306         VMSTATE_UINT32(cs, BCM2835DMAChan),
 307         VMSTATE_UINT32(conblk_ad, BCM2835DMAChan),
 308         VMSTATE_UINT32(ti, BCM2835DMAChan),
 309         VMSTATE_UINT32(source_ad, BCM2835DMAChan),
 310         VMSTATE_UINT32(dest_ad, BCM2835DMAChan),
 311         VMSTATE_UINT32(txfr_len, BCM2835DMAChan),
 312         VMSTATE_UINT32(stride, BCM2835DMAChan),
 313         VMSTATE_UINT32(nextconbk, BCM2835DMAChan),
 314         VMSTATE_UINT32(debug, BCM2835DMAChan),
 315         VMSTATE_END_OF_LIST()
 316     }
 317 };
 318
 319 static const VMStateDescription vmstate_bcm2835_dma = {
 320     .name = TYPE_BCM2835_DMA,
 321     .version_id = 1,
 322     .minimum_version_id = 1,
 323     .fields = (VMStateField[]) {
 324         VMSTATE_STRUCT_ARRAY(chan, BCM2835DMAState, BCM2835_DMA_NCHANS, 1,
 325                              vmstate_bcm2835_dma_chan, BCM2835DMAChan),
 326         VMSTATE_UINT32(int_status, BCM2835DMAState),
 327         VMSTATE_UINT32(enable, BCM2835DMAState),
 328         VMSTATE_END_OF_LIST()
 329     }
 330 };
 331
 332 static void bcm2835_dma_init(Object *obj)
 333 {
 334     BCM2835DMAState *s = BCM2835_DMA(obj);
 335     int n;
 336
 337     /* DMA channels 0-14 occupy a contiguous block of IO memory, along
 338      * with the global enable and interrupt status bits. Channel 15
 339      * has the same register map, but is mapped at a discontiguous
 340      * address in a separate IO block.
 341      */
 342     memory_region_init_io(&s->iomem0, OBJECT(s), &bcm2835_dma0_ops, s,
 343                           TYPE_BCM2835_DMA, 0x1000);
 344     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem0);
 345
 346     memory_region_init_io(&s->iomem15, OBJECT(s), &bcm2835_dma15_ops, s,
 347                           TYPE_BCM2835_DMA "-chan15", 0x100);
 348     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem15);
 349
 350     for (n = 0; n < 16; n++) {
 351         sysbus_init_irq(SYS_BUS_DEVICE(s), &s->chan[n].irq);
 352     }
 353 }
 354
 355 static void bcm2835_dma_reset(DeviceState *dev)
 356 {
 357     BCM2835DMAState *s = BCM2835_DMA(dev);
 358     int n;
 359
 360     s->enable = 0xffff;
 361     s->int_status = 0;
 362     for (n = 0; n < BCM2835_DMA_NCHANS; n++) {
 363         bcm2835_dma_chan_reset(&s->chan[n]);
 364     }
 365 }
 366
 367 static void bcm2835_dma_realize(DeviceState *dev, Error **errp)
 368 {
 369     BCM2835DMAState *s = BCM2835_DMA(dev);
 370     Error *err = NULL;
 371     Object *obj;
 372
 373     obj = object_property_get_link(OBJECT(dev), "dma-mr", &err);
 374     if (obj == NULL) {
 375         error_setg(errp, "%s: required dma-mr link not found: %s",
 376                    __func__, error_get_pretty(err));
 377         return;
 378     }
 379
 380     s->dma_mr = MEMORY_REGION(obj);
 381     address_space_init(&s->dma_as, s->dma_mr, NULL);
 382
 383     bcm2835_dma_reset(dev);
 384 }
 385
 386 static void bcm2835_dma_class_init(ObjectClass *klass, void *data)
 387 {
 388     DeviceClass *dc = DEVICE_CLASS(klass);
 389
 390     dc->realize = bcm2835_dma_realize;
 391     dc->reset = bcm2835_dma_reset;
 392     dc->vmsd = &vmstate_bcm2835_dma;
 393 }
 394
 395 static TypeInfo bcm2835_dma_info = {
 396     .name          = TYPE_BCM2835_DMA,
 397     .parent        = TYPE_SYS_BUS_DEVICE,
 398     .instance_size = sizeof(BCM2835DMAState),
 399     .class_init    = bcm2835_dma_class_init,
 400     .instance_init = bcm2835_dma_init,
 401 };
 402
 403 static void bcm2835_dma_register_types(void)
 404 {
 405     type_register_static(&bcm2835_dma_info);
 406 }
 407
 408 type_init(bcm2835_dma_register_types)