2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "qemu-common.h"
30 #include "hw/sysbus.h"
31 #include "qemu/error-report.h"
32 #include "qemu/timer.h"
33 #include "hw/sparc/sun4m_iommu.h"
34 #include "hw/rtc/m48t59.h"
35 #include "migration/vmstate.h"
36 #include "hw/sparc/sparc32_dma.h"
37 #include "hw/block/fdc.h"
38 #include "sysemu/reset.h"
39 #include "sysemu/runstate.h"
40 #include "sysemu/sysemu.h"
42 #include "hw/boards.h"
43 #include "hw/scsi/esp.h"
44 #include "hw/nvram/sun_nvram.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/nvram/chrp_nvram.h"
47 #include "hw/nvram/fw_cfg.h"
48 #include "hw/char/escc.h"
49 #include "hw/misc/empty_slot.h"
50 #include "hw/misc/unimp.h"
52 #include "hw/loader.h"
57 * Sun4m architecture was used in the following machines:
59 * SPARCserver 6xxMP/xx
60 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
61 * SPARCclassic X (4/10)
62 * SPARCstation LX/ZX (4/30)
63 * SPARCstation Voyager
64 * SPARCstation 10/xx, SPARCserver 10/xx
65 * SPARCstation 5, SPARCserver 5
66 * SPARCstation 20/xx, SPARCserver 20
69 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 #define KERNEL_LOAD_ADDR 0x00004000
73 #define CMDLINE_ADDR 0x007ff000
74 #define INITRD_LOAD_ADDR 0x00800000
75 #define PROM_SIZE_MAX (1 * MiB)
76 #define PROM_VADDR 0xffd00000
77 #define PROM_FILENAME "openbios-sparc32"
78 #define CFG_ADDR 0xd00000510ULL
79 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
80 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
81 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
87 #define ESCC_CLOCK 4915200
90 hwaddr iommu_base
, iommu_pad_base
, iommu_pad_len
, slavio_base
;
91 hwaddr intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
92 hwaddr serial_base
, fd_base
;
93 hwaddr afx_base
, idreg_base
, dma_base
, esp_base
, le_base
;
94 hwaddr tcx_base
, cs_base
, apc_base
, aux1_base
, aux2_base
;
95 hwaddr bpp_base
, dbri_base
, sx_base
;
97 hwaddr reg_base
, vram_base
;
101 uint32_t ecc_version
;
102 uint32_t iommu_version
;
104 uint8_t nvram_machine_id
;
107 const char *fw_cfg_arch_key_name(uint16_t key
)
109 static const struct {
112 } fw_cfg_arch_wellknown_keys
[] = {
113 {FW_CFG_SUN4M_DEPTH
, "depth"},
114 {FW_CFG_SUN4M_WIDTH
, "width"},
115 {FW_CFG_SUN4M_HEIGHT
, "height"},
118 for (size_t i
= 0; i
< ARRAY_SIZE(fw_cfg_arch_wellknown_keys
); i
++) {
119 if (fw_cfg_arch_wellknown_keys
[i
].key
== key
) {
120 return fw_cfg_arch_wellknown_keys
[i
].name
;
126 static void fw_cfg_boot_set(void *opaque
, const char *boot_device
,
129 fw_cfg_modify_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
132 static void nvram_init(Nvram
*nvram
, uint8_t *macaddr
,
133 const char *cmdline
, const char *boot_devices
,
134 ram_addr_t RAM_size
, uint32_t kernel_size
,
135 int width
, int height
, int depth
,
136 int nvram_machine_id
, const char *arch
)
140 uint8_t image
[0x1ff0];
141 NvramClass
*k
= NVRAM_GET_CLASS(nvram
);
143 memset(image
, '\0', sizeof(image
));
145 /* OpenBIOS nvram variables partition */
146 sysp_end
= chrp_nvram_create_system_partition(image
, 0, 0x1fd0);
148 /* Free space partition */
149 chrp_nvram_create_free_partition(&image
[sysp_end
], 0x1fd0 - sysp_end
);
151 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
,
154 for (i
= 0; i
< sizeof(image
); i
++) {
155 (k
->write
)(nvram
, i
, image
[i
]);
159 void cpu_check_irqs(CPUSPARCState
*env
)
163 /* We should be holding the BQL before we mess with IRQs */
164 g_assert(qemu_mutex_iothread_locked());
166 if (env
->pil_in
&& (env
->interrupt_index
== 0 ||
167 (env
->interrupt_index
& ~15) == TT_EXTINT
)) {
170 for (i
= 15; i
> 0; i
--) {
171 if (env
->pil_in
& (1 << i
)) {
172 int old_interrupt
= env
->interrupt_index
;
174 env
->interrupt_index
= TT_EXTINT
| i
;
175 if (old_interrupt
!= env
->interrupt_index
) {
177 trace_sun4m_cpu_interrupt(i
);
178 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
183 } else if (!env
->pil_in
&& (env
->interrupt_index
& ~15) == TT_EXTINT
) {
185 trace_sun4m_cpu_reset_interrupt(env
->interrupt_index
& 15);
186 env
->interrupt_index
= 0;
187 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
191 static void cpu_kick_irq(SPARCCPU
*cpu
)
193 CPUSPARCState
*env
= &cpu
->env
;
194 CPUState
*cs
= CPU(cpu
);
201 static void cpu_set_irq(void *opaque
, int irq
, int level
)
203 SPARCCPU
*cpu
= opaque
;
204 CPUSPARCState
*env
= &cpu
->env
;
207 trace_sun4m_cpu_set_irq_raise(irq
);
208 env
->pil_in
|= 1 << irq
;
211 trace_sun4m_cpu_set_irq_lower(irq
);
212 env
->pil_in
&= ~(1 << irq
);
217 static void dummy_cpu_set_irq(void *opaque
, int irq
, int level
)
221 static void sun4m_cpu_reset(void *opaque
)
223 SPARCCPU
*cpu
= opaque
;
224 CPUState
*cs
= CPU(cpu
);
229 static void cpu_halt_signal(void *opaque
, int irq
, int level
)
231 if (level
&& current_cpu
) {
232 cpu_interrupt(current_cpu
, CPU_INTERRUPT_HALT
);
236 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
238 return addr
- 0xf0000000ULL
;
241 static unsigned long sun4m_load_kernel(const char *kernel_filename
,
242 const char *initrd_filename
,
244 uint32_t *initrd_size
)
251 linux_boot
= (kernel_filename
!= NULL
);
262 kernel_size
= load_elf(kernel_filename
, NULL
,
263 translate_kernel_address
, NULL
,
264 NULL
, NULL
, NULL
, NULL
, 1, EM_SPARC
, 0, 0);
266 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
267 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
270 kernel_size
= load_image_targphys(kernel_filename
,
272 RAM_size
- KERNEL_LOAD_ADDR
);
273 if (kernel_size
< 0) {
274 error_report("could not load kernel '%s'", kernel_filename
);
280 if (initrd_filename
) {
281 *initrd_size
= load_image_targphys(initrd_filename
,
283 RAM_size
- INITRD_LOAD_ADDR
);
284 if ((int)*initrd_size
< 0) {
285 error_report("could not load initial ram disk '%s'",
290 if (*initrd_size
> 0) {
291 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
292 ptr
= rom_ptr(KERNEL_LOAD_ADDR
+ i
, 24);
293 if (ptr
&& ldl_p(ptr
) == 0x48647253) { /* HdrS */
294 stl_p(ptr
+ 16, INITRD_LOAD_ADDR
);
295 stl_p(ptr
+ 20, *initrd_size
);
304 static void *iommu_init(hwaddr addr
, uint32_t version
, qemu_irq irq
)
309 dev
= qdev_new(TYPE_SUN4M_IOMMU
);
310 qdev_prop_set_uint32(dev
, "version", version
);
311 s
= SYS_BUS_DEVICE(dev
);
312 sysbus_realize_and_unref(s
, &error_fatal
);
313 sysbus_connect_irq(s
, 0, irq
);
314 sysbus_mmio_map(s
, 0, addr
);
319 static void *sparc32_dma_init(hwaddr dma_base
,
320 hwaddr esp_base
, qemu_irq espdma_irq
,
321 hwaddr le_base
, qemu_irq ledma_irq
)
324 ESPDMADeviceState
*espdma
;
325 LEDMADeviceState
*ledma
;
327 SysBusPCNetState
*lance
;
329 dma
= qdev_new(TYPE_SPARC32_DMA
);
330 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma
), &error_fatal
);
331 sysbus_mmio_map(SYS_BUS_DEVICE(dma
), 0, dma_base
);
333 espdma
= SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
334 OBJECT(dma
), "espdma"));
335 sysbus_connect_irq(SYS_BUS_DEVICE(espdma
), 0, espdma_irq
);
337 esp
= ESP_STATE(object_resolve_path_component(OBJECT(espdma
), "esp"));
338 sysbus_mmio_map(SYS_BUS_DEVICE(esp
), 0, esp_base
);
339 scsi_bus_legacy_handle_cmdline(&esp
->esp
.bus
);
341 ledma
= SPARC32_LEDMA_DEVICE(object_resolve_path_component(
342 OBJECT(dma
), "ledma"));
343 sysbus_connect_irq(SYS_BUS_DEVICE(ledma
), 0, ledma_irq
);
345 lance
= SYSBUS_PCNET(object_resolve_path_component(
346 OBJECT(ledma
), "lance"));
347 sysbus_mmio_map(SYS_BUS_DEVICE(lance
), 0, le_base
);
352 static DeviceState
*slavio_intctl_init(hwaddr addr
,
354 qemu_irq
**parent_irq
)
360 dev
= qdev_new("slavio_intctl");
362 s
= SYS_BUS_DEVICE(dev
);
363 sysbus_realize_and_unref(s
, &error_fatal
);
365 for (i
= 0; i
< MAX_CPUS
; i
++) {
366 for (j
= 0; j
< MAX_PILS
; j
++) {
367 sysbus_connect_irq(s
, i
* MAX_PILS
+ j
, parent_irq
[i
][j
]);
370 sysbus_mmio_map(s
, 0, addrg
);
371 for (i
= 0; i
< MAX_CPUS
; i
++) {
372 sysbus_mmio_map(s
, i
+ 1, addr
+ i
* TARGET_PAGE_SIZE
);
378 #define SYS_TIMER_OFFSET 0x10000ULL
379 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
381 static void slavio_timer_init_all(hwaddr addr
, qemu_irq master_irq
,
382 qemu_irq
*cpu_irqs
, unsigned int num_cpus
)
388 dev
= qdev_new("slavio_timer");
389 qdev_prop_set_uint32(dev
, "num_cpus", num_cpus
);
390 s
= SYS_BUS_DEVICE(dev
);
391 sysbus_realize_and_unref(s
, &error_fatal
);
392 sysbus_connect_irq(s
, 0, master_irq
);
393 sysbus_mmio_map(s
, 0, addr
+ SYS_TIMER_OFFSET
);
395 for (i
= 0; i
< MAX_CPUS
; i
++) {
396 sysbus_mmio_map(s
, i
+ 1, addr
+ (hwaddr
)CPU_TIMER_OFFSET(i
));
397 sysbus_connect_irq(s
, i
+ 1, cpu_irqs
[i
]);
401 static qemu_irq slavio_system_powerdown
;
403 static void slavio_powerdown_req(Notifier
*n
, void *opaque
)
405 qemu_irq_raise(slavio_system_powerdown
);
408 static Notifier slavio_system_powerdown_notifier
= {
409 .notify
= slavio_powerdown_req
412 #define MISC_LEDS 0x01600000
413 #define MISC_CFG 0x01800000
414 #define MISC_DIAG 0x01a00000
415 #define MISC_MDM 0x01b00000
416 #define MISC_SYS 0x01f00000
418 static void slavio_misc_init(hwaddr base
,
420 hwaddr aux2_base
, qemu_irq irq
,
426 dev
= qdev_new("slavio_misc");
427 s
= SYS_BUS_DEVICE(dev
);
428 sysbus_realize_and_unref(s
, &error_fatal
);
430 /* 8 bit registers */
432 sysbus_mmio_map(s
, 0, base
+ MISC_CFG
);
434 sysbus_mmio_map(s
, 1, base
+ MISC_DIAG
);
436 sysbus_mmio_map(s
, 2, base
+ MISC_MDM
);
437 /* 16 bit registers */
438 /* ss600mp diag LEDs */
439 sysbus_mmio_map(s
, 3, base
+ MISC_LEDS
);
440 /* 32 bit registers */
442 sysbus_mmio_map(s
, 4, base
+ MISC_SYS
);
445 /* AUX 1 (Misc System Functions) */
446 sysbus_mmio_map(s
, 5, aux1_base
);
449 /* AUX 2 (Software Powerdown Control) */
450 sysbus_mmio_map(s
, 6, aux2_base
);
452 sysbus_connect_irq(s
, 0, irq
);
453 sysbus_connect_irq(s
, 1, fdc_tc
);
454 slavio_system_powerdown
= qdev_get_gpio_in(dev
, 0);
455 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier
);
458 static void ecc_init(hwaddr base
, qemu_irq irq
, uint32_t version
)
463 dev
= qdev_new("eccmemctl");
464 qdev_prop_set_uint32(dev
, "version", version
);
465 s
= SYS_BUS_DEVICE(dev
);
466 sysbus_realize_and_unref(s
, &error_fatal
);
467 sysbus_connect_irq(s
, 0, irq
);
468 sysbus_mmio_map(s
, 0, base
);
469 if (version
== 0) { // SS-600MP only
470 sysbus_mmio_map(s
, 1, base
+ 0x1000);
474 static void apc_init(hwaddr power_base
, qemu_irq cpu_halt
)
479 dev
= qdev_new("apc");
480 s
= SYS_BUS_DEVICE(dev
);
481 sysbus_realize_and_unref(s
, &error_fatal
);
482 /* Power management (APC) XXX: not a Slavio device */
483 sysbus_mmio_map(s
, 0, power_base
);
484 sysbus_connect_irq(s
, 0, cpu_halt
);
487 static void tcx_init(hwaddr addr
, qemu_irq irq
, int vram_size
, int width
,
488 int height
, int depth
)
493 dev
= qdev_new("SUNW,tcx");
494 qdev_prop_set_uint32(dev
, "vram_size", vram_size
);
495 qdev_prop_set_uint16(dev
, "width", width
);
496 qdev_prop_set_uint16(dev
, "height", height
);
497 qdev_prop_set_uint16(dev
, "depth", depth
);
498 s
= SYS_BUS_DEVICE(dev
);
499 sysbus_realize_and_unref(s
, &error_fatal
);
501 /* 10/ROM : FCode ROM */
502 sysbus_mmio_map(s
, 0, addr
);
503 /* 2/STIP : Stipple */
504 sysbus_mmio_map(s
, 1, addr
+ 0x04000000ULL
);
505 /* 3/BLIT : Blitter */
506 sysbus_mmio_map(s
, 2, addr
+ 0x06000000ULL
);
507 /* 5/RSTIP : Raw Stipple */
508 sysbus_mmio_map(s
, 3, addr
+ 0x0c000000ULL
);
509 /* 6/RBLIT : Raw Blitter */
510 sysbus_mmio_map(s
, 4, addr
+ 0x0e000000ULL
);
511 /* 7/TEC : Transform Engine */
512 sysbus_mmio_map(s
, 5, addr
+ 0x00700000ULL
);
514 sysbus_mmio_map(s
, 6, addr
+ 0x00200000ULL
);
517 sysbus_mmio_map(s
, 7, addr
+ 0x00300000ULL
);
519 sysbus_mmio_map(s
, 7, addr
+ 0x00301000ULL
);
522 sysbus_mmio_map(s
, 8, addr
+ 0x00240000ULL
);
524 sysbus_mmio_map(s
, 9, addr
+ 0x00280000ULL
);
525 /* 0/DFB8 : 8-bit plane */
526 sysbus_mmio_map(s
, 10, addr
+ 0x00800000ULL
);
527 /* 1/DFB24 : 24bit plane */
528 sysbus_mmio_map(s
, 11, addr
+ 0x02000000ULL
);
529 /* 4/RDFB32: Raw framebuffer. Control plane */
530 sysbus_mmio_map(s
, 12, addr
+ 0x0a000000ULL
);
531 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
533 sysbus_mmio_map(s
, 13, addr
+ 0x00301000ULL
);
536 sysbus_connect_irq(s
, 0, irq
);
539 static void cg3_init(hwaddr addr
, qemu_irq irq
, int vram_size
, int width
,
540 int height
, int depth
)
545 dev
= qdev_new("cgthree");
546 qdev_prop_set_uint32(dev
, "vram-size", vram_size
);
547 qdev_prop_set_uint16(dev
, "width", width
);
548 qdev_prop_set_uint16(dev
, "height", height
);
549 qdev_prop_set_uint16(dev
, "depth", depth
);
550 s
= SYS_BUS_DEVICE(dev
);
551 sysbus_realize_and_unref(s
, &error_fatal
);
554 sysbus_mmio_map(s
, 0, addr
);
556 sysbus_mmio_map(s
, 1, addr
+ 0x400000ULL
);
558 sysbus_mmio_map(s
, 2, addr
+ 0x800000ULL
);
560 sysbus_connect_irq(s
, 0, irq
);
563 /* NCR89C100/MACIO Internal ID register */
565 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
567 static const uint8_t idreg_data
[] = { 0xfe, 0x81, 0x01, 0x03 };
569 static void idreg_init(hwaddr addr
)
574 dev
= qdev_new(TYPE_MACIO_ID_REGISTER
);
575 s
= SYS_BUS_DEVICE(dev
);
576 sysbus_realize_and_unref(s
, &error_fatal
);
578 sysbus_mmio_map(s
, 0, addr
);
579 address_space_write_rom(&address_space_memory
, addr
,
580 MEMTXATTRS_UNSPECIFIED
,
581 idreg_data
, sizeof(idreg_data
));
584 #define MACIO_ID_REGISTER(obj) \
585 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
587 typedef struct IDRegState
{
588 SysBusDevice parent_obj
;
593 static void idreg_realize(DeviceState
*ds
, Error
**errp
)
595 IDRegState
*s
= MACIO_ID_REGISTER(ds
);
596 SysBusDevice
*dev
= SYS_BUS_DEVICE(ds
);
597 Error
*local_err
= NULL
;
599 memory_region_init_ram_nomigrate(&s
->mem
, OBJECT(ds
), "sun4m.idreg",
600 sizeof(idreg_data
), &local_err
);
602 error_propagate(errp
, local_err
);
606 vmstate_register_ram_global(&s
->mem
);
607 memory_region_set_readonly(&s
->mem
, true);
608 sysbus_init_mmio(dev
, &s
->mem
);
611 static void idreg_class_init(ObjectClass
*oc
, void *data
)
613 DeviceClass
*dc
= DEVICE_CLASS(oc
);
615 dc
->realize
= idreg_realize
;
618 static const TypeInfo idreg_info
= {
619 .name
= TYPE_MACIO_ID_REGISTER
,
620 .parent
= TYPE_SYS_BUS_DEVICE
,
621 .instance_size
= sizeof(IDRegState
),
622 .class_init
= idreg_class_init
,
625 #define TYPE_TCX_AFX "tcx_afx"
626 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
628 typedef struct AFXState
{
629 SysBusDevice parent_obj
;
634 /* SS-5 TCX AFX register */
635 static void afx_init(hwaddr addr
)
640 dev
= qdev_new(TYPE_TCX_AFX
);
641 s
= SYS_BUS_DEVICE(dev
);
642 sysbus_realize_and_unref(s
, &error_fatal
);
644 sysbus_mmio_map(s
, 0, addr
);
647 static void afx_realize(DeviceState
*ds
, Error
**errp
)
649 AFXState
*s
= TCX_AFX(ds
);
650 SysBusDevice
*dev
= SYS_BUS_DEVICE(ds
);
651 Error
*local_err
= NULL
;
653 memory_region_init_ram_nomigrate(&s
->mem
, OBJECT(ds
), "sun4m.afx", 4,
656 error_propagate(errp
, local_err
);
660 vmstate_register_ram_global(&s
->mem
);
661 sysbus_init_mmio(dev
, &s
->mem
);
664 static void afx_class_init(ObjectClass
*oc
, void *data
)
666 DeviceClass
*dc
= DEVICE_CLASS(oc
);
668 dc
->realize
= afx_realize
;
671 static const TypeInfo afx_info
= {
672 .name
= TYPE_TCX_AFX
,
673 .parent
= TYPE_SYS_BUS_DEVICE
,
674 .instance_size
= sizeof(AFXState
),
675 .class_init
= afx_class_init
,
678 #define TYPE_OPENPROM "openprom"
679 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
681 typedef struct PROMState
{
682 SysBusDevice parent_obj
;
687 /* Boot PROM (OpenBIOS) */
688 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
690 hwaddr
*base_addr
= (hwaddr
*)opaque
;
691 return addr
+ *base_addr
- PROM_VADDR
;
694 static void prom_init(hwaddr addr
, const char *bios_name
)
701 dev
= qdev_new(TYPE_OPENPROM
);
702 s
= SYS_BUS_DEVICE(dev
);
703 sysbus_realize_and_unref(s
, &error_fatal
);
705 sysbus_mmio_map(s
, 0, addr
);
708 if (bios_name
== NULL
) {
709 bios_name
= PROM_FILENAME
;
711 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
713 ret
= load_elf(filename
, NULL
,
714 translate_prom_address
, &addr
, NULL
,
715 NULL
, NULL
, NULL
, 1, EM_SPARC
, 0, 0);
716 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
717 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
723 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
724 error_report("could not load prom '%s'", bios_name
);
729 static void prom_realize(DeviceState
*ds
, Error
**errp
)
731 PROMState
*s
= OPENPROM(ds
);
732 SysBusDevice
*dev
= SYS_BUS_DEVICE(ds
);
733 Error
*local_err
= NULL
;
735 memory_region_init_ram_nomigrate(&s
->prom
, OBJECT(ds
), "sun4m.prom",
736 PROM_SIZE_MAX
, &local_err
);
738 error_propagate(errp
, local_err
);
742 vmstate_register_ram_global(&s
->prom
);
743 memory_region_set_readonly(&s
->prom
, true);
744 sysbus_init_mmio(dev
, &s
->prom
);
747 static Property prom_properties
[] = {
748 {/* end of property list */},
751 static void prom_class_init(ObjectClass
*klass
, void *data
)
753 DeviceClass
*dc
= DEVICE_CLASS(klass
);
755 device_class_set_props(dc
, prom_properties
);
756 dc
->realize
= prom_realize
;
759 static const TypeInfo prom_info
= {
760 .name
= TYPE_OPENPROM
,
761 .parent
= TYPE_SYS_BUS_DEVICE
,
762 .instance_size
= sizeof(PROMState
),
763 .class_init
= prom_class_init
,
766 #define TYPE_SUN4M_MEMORY "memory"
767 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
769 typedef struct RamDevice
{
770 SysBusDevice parent_obj
;
771 HostMemoryBackend
*memdev
;
775 static void ram_realize(DeviceState
*dev
, Error
**errp
)
777 RamDevice
*d
= SUN4M_RAM(dev
);
778 MemoryRegion
*ram
= host_memory_backend_get_memory(d
->memdev
);
780 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), ram
);
783 static void ram_initfn(Object
*obj
)
785 RamDevice
*d
= SUN4M_RAM(obj
);
786 object_property_add_link(obj
, "memdev", TYPE_MEMORY_BACKEND
,
787 (Object
**)&d
->memdev
,
788 object_property_allow_set_link
,
789 OBJ_PROP_LINK_STRONG
);
790 object_property_set_description(obj
, "memdev", "Set RAM backend"
791 "Valid value is ID of a hostmem backend");
794 static void ram_class_init(ObjectClass
*klass
, void *data
)
796 DeviceClass
*dc
= DEVICE_CLASS(klass
);
798 dc
->realize
= ram_realize
;
801 static const TypeInfo ram_info
= {
802 .name
= TYPE_SUN4M_MEMORY
,
803 .parent
= TYPE_SYS_BUS_DEVICE
,
804 .instance_size
= sizeof(RamDevice
),
805 .instance_init
= ram_initfn
,
806 .class_init
= ram_class_init
,
809 static void cpu_devinit(const char *cpu_type
, unsigned int id
,
810 uint64_t prom_addr
, qemu_irq
**cpu_irqs
)
815 cpu
= SPARC_CPU(object_new(cpu_type
));
818 cpu_sparc_set_id(env
, id
);
819 qemu_register_reset(sun4m_cpu_reset
, cpu
);
820 object_property_set_bool(OBJECT(cpu
), "start-powered-off", id
!= 0,
822 qdev_realize_and_unref(DEVICE(cpu
), NULL
, &error_fatal
);
823 *cpu_irqs
= qemu_allocate_irqs(cpu_set_irq
, cpu
, MAX_PILS
);
824 env
->prom_addr
= prom_addr
;
827 static void dummy_fdc_tc(void *opaque
, int irq
, int level
)
831 static void sun4m_hw_init(const struct sun4m_hwdef
*hwdef
,
832 MachineState
*machine
)
834 DeviceState
*slavio_intctl
;
837 qemu_irq
*cpu_irqs
[MAX_CPUS
], slavio_irq
[32], slavio_cpu_irq
[MAX_CPUS
];
839 unsigned long kernel_size
;
840 uint32_t initrd_size
;
841 DriveInfo
*fd
[MAX_FD
];
845 unsigned int smp_cpus
= machine
->smp
.cpus
;
846 unsigned int max_cpus
= machine
->smp
.max_cpus
;
847 Object
*ram_memdev
= object_resolve_path_type(machine
->ram_memdev_id
,
848 TYPE_MEMORY_BACKEND
, NULL
);
850 if (machine
->ram_size
> hwdef
->max_mem
) {
851 error_report("Too much memory for this machine: %" PRId64
","
853 machine
->ram_size
/ MiB
, hwdef
->max_mem
/ MiB
);
858 for(i
= 0; i
< smp_cpus
; i
++) {
859 cpu_devinit(machine
->cpu_type
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
862 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
863 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
865 /* Create and map RAM frontend */
866 dev
= qdev_new("memory");
867 object_property_set_link(OBJECT(dev
), "memdev", ram_memdev
, &error_fatal
);
868 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
869 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0);
871 /* models without ECC don't trap when missing ram is accessed */
872 if (!hwdef
->ecc_base
) {
873 empty_slot_init("ecc", machine
->ram_size
,
874 hwdef
->max_mem
- machine
->ram_size
);
877 prom_init(hwdef
->slavio_base
, bios_name
);
879 slavio_intctl
= slavio_intctl_init(hwdef
->intctl_base
,
880 hwdef
->intctl_base
+ 0x10000ULL
,
883 for (i
= 0; i
< 32; i
++) {
884 slavio_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, i
);
886 for (i
= 0; i
< MAX_CPUS
; i
++) {
887 slavio_cpu_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, 32 + i
);
890 if (hwdef
->idreg_base
) {
891 idreg_init(hwdef
->idreg_base
);
894 if (hwdef
->afx_base
) {
895 afx_init(hwdef
->afx_base
);
898 iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
, slavio_irq
[30]);
900 if (hwdef
->iommu_pad_base
) {
901 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
902 Software shouldn't use aliased addresses, neither should it crash
903 when does. Using empty_slot instead of aliasing can help with
904 debugging such accesses */
905 empty_slot_init("iommu.alias",
906 hwdef
->iommu_pad_base
, hwdef
->iommu_pad_len
);
909 sparc32_dma_init(hwdef
->dma_base
,
910 hwdef
->esp_base
, slavio_irq
[18],
911 hwdef
->le_base
, slavio_irq
[16]);
913 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
914 error_report("Unsupported depth: %d", graphic_depth
);
917 if (vga_interface_type
!= VGA_NONE
) {
918 if (vga_interface_type
== VGA_CG3
) {
919 if (graphic_depth
!= 8) {
920 error_report("Unsupported depth: %d", graphic_depth
);
924 if (!(graphic_width
== 1024 && graphic_height
== 768) &&
925 !(graphic_width
== 1152 && graphic_height
== 900)) {
926 error_report("Unsupported resolution: %d x %d", graphic_width
,
932 cg3_init(hwdef
->tcx_base
, slavio_irq
[11], 0x00100000,
933 graphic_width
, graphic_height
, graphic_depth
);
935 /* If no display specified, default to TCX */
936 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
937 error_report("Unsupported depth: %d", graphic_depth
);
941 if (!(graphic_width
== 1024 && graphic_height
== 768)) {
942 error_report("Unsupported resolution: %d x %d",
943 graphic_width
, graphic_height
);
947 tcx_init(hwdef
->tcx_base
, slavio_irq
[11], 0x00100000,
948 graphic_width
, graphic_height
, graphic_depth
);
952 for (i
= 0; i
< MAX_VSIMMS
; i
++) {
953 /* vsimm registers probed by OBP */
954 if (hwdef
->vsimm
[i
].reg_base
) {
955 char *name
= g_strdup_printf("vsimm[%d]", i
);
956 empty_slot_init(name
, hwdef
->vsimm
[i
].reg_base
, 0x2000);
961 if (hwdef
->sx_base
) {
962 create_unimplemented_device("SUNW,sx", hwdef
->sx_base
, 0x2000);
965 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 1968, 8);
967 slavio_timer_init_all(hwdef
->counter_base
, slavio_irq
[19], slavio_cpu_irq
, smp_cpus
);
969 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
970 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
971 dev
= qdev_new(TYPE_ESCC
);
972 qdev_prop_set_uint32(dev
, "disabled", !machine
->enable_graphics
);
973 qdev_prop_set_uint32(dev
, "frequency", ESCC_CLOCK
);
974 qdev_prop_set_uint32(dev
, "it_shift", 1);
975 qdev_prop_set_chr(dev
, "chrB", NULL
);
976 qdev_prop_set_chr(dev
, "chrA", NULL
);
977 qdev_prop_set_uint32(dev
, "chnBtype", escc_mouse
);
978 qdev_prop_set_uint32(dev
, "chnAtype", escc_kbd
);
979 s
= SYS_BUS_DEVICE(dev
);
980 sysbus_realize_and_unref(s
, &error_fatal
);
981 sysbus_connect_irq(s
, 0, slavio_irq
[14]);
982 sysbus_connect_irq(s
, 1, slavio_irq
[14]);
983 sysbus_mmio_map(s
, 0, hwdef
->ms_kb_base
);
985 dev
= qdev_new(TYPE_ESCC
);
986 qdev_prop_set_uint32(dev
, "disabled", 0);
987 qdev_prop_set_uint32(dev
, "frequency", ESCC_CLOCK
);
988 qdev_prop_set_uint32(dev
, "it_shift", 1);
989 qdev_prop_set_chr(dev
, "chrB", serial_hd(1));
990 qdev_prop_set_chr(dev
, "chrA", serial_hd(0));
991 qdev_prop_set_uint32(dev
, "chnBtype", escc_serial
);
992 qdev_prop_set_uint32(dev
, "chnAtype", escc_serial
);
994 s
= SYS_BUS_DEVICE(dev
);
995 sysbus_realize_and_unref(s
, &error_fatal
);
996 sysbus_connect_irq(s
, 0, slavio_irq
[15]);
997 sysbus_connect_irq(s
, 1, slavio_irq
[15]);
998 sysbus_mmio_map(s
, 0, hwdef
->serial_base
);
1000 if (hwdef
->apc_base
) {
1001 apc_init(hwdef
->apc_base
, qemu_allocate_irq(cpu_halt_signal
, NULL
, 0));
1004 if (hwdef
->fd_base
) {
1005 /* there is zero or one floppy drive */
1006 memset(fd
, 0, sizeof(fd
));
1007 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
1008 sun4m_fdctrl_init(slavio_irq
[22], hwdef
->fd_base
, fd
,
1011 fdc_tc
= qemu_allocate_irq(dummy_fdc_tc
, NULL
, 0);
1014 slavio_misc_init(hwdef
->slavio_base
, hwdef
->aux1_base
, hwdef
->aux2_base
,
1015 slavio_irq
[30], fdc_tc
);
1017 if (hwdef
->cs_base
) {
1018 sysbus_create_simple("SUNW,CS4231", hwdef
->cs_base
,
1022 if (hwdef
->dbri_base
) {
1023 /* ISDN chip with attached CS4215 audio codec */
1025 create_unimplemented_device("SUNW,DBRI.prom",
1026 hwdef
->dbri_base
+ 0x1000, 0x30);
1028 create_unimplemented_device("SUNW,DBRI",
1029 hwdef
->dbri_base
+ 0x10000, 0x100);
1032 if (hwdef
->bpp_base
) {
1034 create_unimplemented_device("SUNW,bpp", hwdef
->bpp_base
, 0x20);
1038 kernel_size
= sun4m_load_kernel(machine
->kernel_filename
,
1039 machine
->initrd_filename
,
1040 machine
->ram_size
, &initrd_size
);
1042 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, machine
->kernel_cmdline
,
1043 machine
->boot_order
, machine
->ram_size
, kernel_size
,
1044 graphic_width
, graphic_height
, graphic_depth
,
1045 hwdef
->nvram_machine_id
, "Sun4m");
1047 if (hwdef
->ecc_base
)
1048 ecc_init(hwdef
->ecc_base
, slavio_irq
[28],
1049 hwdef
->ecc_version
);
1051 dev
= qdev_new(TYPE_FW_CFG_MEM
);
1052 fw_cfg
= FW_CFG(dev
);
1053 qdev_prop_set_uint32(dev
, "data_width", 1);
1054 qdev_prop_set_bit(dev
, "dma_enabled", false);
1055 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG
,
1057 s
= SYS_BUS_DEVICE(dev
);
1058 sysbus_realize_and_unref(s
, &error_fatal
);
1059 sysbus_mmio_map(s
, 0, CFG_ADDR
);
1060 sysbus_mmio_map(s
, 1, CFG_ADDR
+ 2);
1062 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)smp_cpus
);
1063 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)max_cpus
);
1064 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)machine
->ram_size
);
1065 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1066 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1067 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_WIDTH
, graphic_width
);
1068 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_HEIGHT
, graphic_height
);
1069 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1070 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1071 if (machine
->kernel_cmdline
) {
1072 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1073 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
,
1074 machine
->kernel_cmdline
);
1075 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, machine
->kernel_cmdline
);
1076 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
1077 strlen(machine
->kernel_cmdline
) + 1);
1079 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1080 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
1082 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1083 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
1084 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, machine
->boot_order
[0]);
1085 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1100 static const struct sun4m_hwdef sun4m_hwdefs
[] = {
1103 .iommu_base
= 0x10000000,
1104 .iommu_pad_base
= 0x10004000,
1105 .iommu_pad_len
= 0x0fffb000,
1106 .tcx_base
= 0x50000000,
1107 .cs_base
= 0x6c000000,
1108 .slavio_base
= 0x70000000,
1109 .ms_kb_base
= 0x71000000,
1110 .serial_base
= 0x71100000,
1111 .nvram_base
= 0x71200000,
1112 .fd_base
= 0x71400000,
1113 .counter_base
= 0x71d00000,
1114 .intctl_base
= 0x71e00000,
1115 .idreg_base
= 0x78000000,
1116 .dma_base
= 0x78400000,
1117 .esp_base
= 0x78800000,
1118 .le_base
= 0x78c00000,
1119 .apc_base
= 0x6a000000,
1120 .afx_base
= 0x6e000000,
1121 .aux1_base
= 0x71900000,
1122 .aux2_base
= 0x71910000,
1123 .nvram_machine_id
= 0x80,
1124 .machine_id
= ss5_id
,
1125 .iommu_version
= 0x05000000,
1126 .max_mem
= 0x10000000,
1130 .iommu_base
= 0xfe0000000ULL
,
1131 .tcx_base
= 0xe20000000ULL
,
1132 .slavio_base
= 0xff0000000ULL
,
1133 .ms_kb_base
= 0xff1000000ULL
,
1134 .serial_base
= 0xff1100000ULL
,
1135 .nvram_base
= 0xff1200000ULL
,
1136 .fd_base
= 0xff1700000ULL
,
1137 .counter_base
= 0xff1300000ULL
,
1138 .intctl_base
= 0xff1400000ULL
,
1139 .idreg_base
= 0xef0000000ULL
,
1140 .dma_base
= 0xef0400000ULL
,
1141 .esp_base
= 0xef0800000ULL
,
1142 .le_base
= 0xef0c00000ULL
,
1143 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1144 .aux1_base
= 0xff1800000ULL
,
1145 .aux2_base
= 0xff1a01000ULL
,
1146 .ecc_base
= 0xf00000000ULL
,
1147 .ecc_version
= 0x10000000, // version 0, implementation 1
1148 .nvram_machine_id
= 0x72,
1149 .machine_id
= ss10_id
,
1150 .iommu_version
= 0x03000000,
1151 .max_mem
= 0xf00000000ULL
,
1155 .iommu_base
= 0xfe0000000ULL
,
1156 .tcx_base
= 0xe20000000ULL
,
1157 .slavio_base
= 0xff0000000ULL
,
1158 .ms_kb_base
= 0xff1000000ULL
,
1159 .serial_base
= 0xff1100000ULL
,
1160 .nvram_base
= 0xff1200000ULL
,
1161 .counter_base
= 0xff1300000ULL
,
1162 .intctl_base
= 0xff1400000ULL
,
1163 .dma_base
= 0xef0081000ULL
,
1164 .esp_base
= 0xef0080000ULL
,
1165 .le_base
= 0xef0060000ULL
,
1166 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1167 .aux1_base
= 0xff1800000ULL
,
1168 .aux2_base
= 0xff1a01000ULL
, // XXX should not exist
1169 .ecc_base
= 0xf00000000ULL
,
1170 .ecc_version
= 0x00000000, // version 0, implementation 0
1171 .nvram_machine_id
= 0x71,
1172 .machine_id
= ss600mp_id
,
1173 .iommu_version
= 0x01000000,
1174 .max_mem
= 0xf00000000ULL
,
1178 .iommu_base
= 0xfe0000000ULL
,
1179 .tcx_base
= 0xe20000000ULL
,
1180 .slavio_base
= 0xff0000000ULL
,
1181 .ms_kb_base
= 0xff1000000ULL
,
1182 .serial_base
= 0xff1100000ULL
,
1183 .nvram_base
= 0xff1200000ULL
,
1184 .fd_base
= 0xff1700000ULL
,
1185 .counter_base
= 0xff1300000ULL
,
1186 .intctl_base
= 0xff1400000ULL
,
1187 .idreg_base
= 0xef0000000ULL
,
1188 .dma_base
= 0xef0400000ULL
,
1189 .esp_base
= 0xef0800000ULL
,
1190 .le_base
= 0xef0c00000ULL
,
1191 .bpp_base
= 0xef4800000ULL
,
1192 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1193 .aux1_base
= 0xff1800000ULL
,
1194 .aux2_base
= 0xff1a01000ULL
,
1195 .dbri_base
= 0xee0000000ULL
,
1196 .sx_base
= 0xf80000000ULL
,
1199 .reg_base
= 0x9c000000ULL
,
1200 .vram_base
= 0xfc000000ULL
1202 .reg_base
= 0x90000000ULL
,
1203 .vram_base
= 0xf0000000ULL
1205 .reg_base
= 0x94000000ULL
1207 .reg_base
= 0x98000000ULL
1210 .ecc_base
= 0xf00000000ULL
,
1211 .ecc_version
= 0x20000000, // version 0, implementation 2
1212 .nvram_machine_id
= 0x72,
1213 .machine_id
= ss20_id
,
1214 .iommu_version
= 0x13000000,
1215 .max_mem
= 0xf00000000ULL
,
1219 .iommu_base
= 0x10000000,
1220 .tcx_base
= 0x50000000,
1221 .slavio_base
= 0x70000000,
1222 .ms_kb_base
= 0x71000000,
1223 .serial_base
= 0x71100000,
1224 .nvram_base
= 0x71200000,
1225 .fd_base
= 0x71400000,
1226 .counter_base
= 0x71d00000,
1227 .intctl_base
= 0x71e00000,
1228 .idreg_base
= 0x78000000,
1229 .dma_base
= 0x78400000,
1230 .esp_base
= 0x78800000,
1231 .le_base
= 0x78c00000,
1232 .apc_base
= 0x71300000, // pmc
1233 .aux1_base
= 0x71900000,
1234 .aux2_base
= 0x71910000,
1235 .nvram_machine_id
= 0x80,
1236 .machine_id
= vger_id
,
1237 .iommu_version
= 0x05000000,
1238 .max_mem
= 0x10000000,
1242 .iommu_base
= 0x10000000,
1243 .iommu_pad_base
= 0x10004000,
1244 .iommu_pad_len
= 0x0fffb000,
1245 .tcx_base
= 0x50000000,
1246 .slavio_base
= 0x70000000,
1247 .ms_kb_base
= 0x71000000,
1248 .serial_base
= 0x71100000,
1249 .nvram_base
= 0x71200000,
1250 .fd_base
= 0x71400000,
1251 .counter_base
= 0x71d00000,
1252 .intctl_base
= 0x71e00000,
1253 .idreg_base
= 0x78000000,
1254 .dma_base
= 0x78400000,
1255 .esp_base
= 0x78800000,
1256 .le_base
= 0x78c00000,
1257 .aux1_base
= 0x71900000,
1258 .aux2_base
= 0x71910000,
1259 .nvram_machine_id
= 0x80,
1260 .machine_id
= lx_id
,
1261 .iommu_version
= 0x04000000,
1262 .max_mem
= 0x10000000,
1266 .iommu_base
= 0x10000000,
1267 .tcx_base
= 0x50000000,
1268 .cs_base
= 0x6c000000,
1269 .slavio_base
= 0x70000000,
1270 .ms_kb_base
= 0x71000000,
1271 .serial_base
= 0x71100000,
1272 .nvram_base
= 0x71200000,
1273 .fd_base
= 0x71400000,
1274 .counter_base
= 0x71d00000,
1275 .intctl_base
= 0x71e00000,
1276 .idreg_base
= 0x78000000,
1277 .dma_base
= 0x78400000,
1278 .esp_base
= 0x78800000,
1279 .le_base
= 0x78c00000,
1280 .apc_base
= 0x6a000000,
1281 .aux1_base
= 0x71900000,
1282 .aux2_base
= 0x71910000,
1283 .nvram_machine_id
= 0x80,
1284 .machine_id
= ss4_id
,
1285 .iommu_version
= 0x05000000,
1286 .max_mem
= 0x10000000,
1290 .iommu_base
= 0x10000000,
1291 .tcx_base
= 0x50000000,
1292 .slavio_base
= 0x70000000,
1293 .ms_kb_base
= 0x71000000,
1294 .serial_base
= 0x71100000,
1295 .nvram_base
= 0x71200000,
1296 .fd_base
= 0x71400000,
1297 .counter_base
= 0x71d00000,
1298 .intctl_base
= 0x71e00000,
1299 .idreg_base
= 0x78000000,
1300 .dma_base
= 0x78400000,
1301 .esp_base
= 0x78800000,
1302 .le_base
= 0x78c00000,
1303 .apc_base
= 0x6a000000,
1304 .aux1_base
= 0x71900000,
1305 .aux2_base
= 0x71910000,
1306 .nvram_machine_id
= 0x80,
1307 .machine_id
= scls_id
,
1308 .iommu_version
= 0x05000000,
1309 .max_mem
= 0x10000000,
1313 .iommu_base
= 0x10000000,
1314 .tcx_base
= 0x50000000, // XXX
1315 .slavio_base
= 0x70000000,
1316 .ms_kb_base
= 0x71000000,
1317 .serial_base
= 0x71100000,
1318 .nvram_base
= 0x71200000,
1319 .fd_base
= 0x71400000,
1320 .counter_base
= 0x71d00000,
1321 .intctl_base
= 0x71e00000,
1322 .idreg_base
= 0x78000000,
1323 .dma_base
= 0x78400000,
1324 .esp_base
= 0x78800000,
1325 .le_base
= 0x78c00000,
1326 .apc_base
= 0x6a000000,
1327 .aux1_base
= 0x71900000,
1328 .aux2_base
= 0x71910000,
1329 .nvram_machine_id
= 0x80,
1330 .machine_id
= sbook_id
,
1331 .iommu_version
= 0x05000000,
1332 .max_mem
= 0x10000000,
1336 /* SPARCstation 5 hardware initialisation */
1337 static void ss5_init(MachineState
*machine
)
1339 sun4m_hw_init(&sun4m_hwdefs
[0], machine
);
1342 /* SPARCstation 10 hardware initialisation */
1343 static void ss10_init(MachineState
*machine
)
1345 sun4m_hw_init(&sun4m_hwdefs
[1], machine
);
1348 /* SPARCserver 600MP hardware initialisation */
1349 static void ss600mp_init(MachineState
*machine
)
1351 sun4m_hw_init(&sun4m_hwdefs
[2], machine
);
1354 /* SPARCstation 20 hardware initialisation */
1355 static void ss20_init(MachineState
*machine
)
1357 sun4m_hw_init(&sun4m_hwdefs
[3], machine
);
1360 /* SPARCstation Voyager hardware initialisation */
1361 static void vger_init(MachineState
*machine
)
1363 sun4m_hw_init(&sun4m_hwdefs
[4], machine
);
1366 /* SPARCstation LX hardware initialisation */
1367 static void ss_lx_init(MachineState
*machine
)
1369 sun4m_hw_init(&sun4m_hwdefs
[5], machine
);
1372 /* SPARCstation 4 hardware initialisation */
1373 static void ss4_init(MachineState
*machine
)
1375 sun4m_hw_init(&sun4m_hwdefs
[6], machine
);
1378 /* SPARCClassic hardware initialisation */
1379 static void scls_init(MachineState
*machine
)
1381 sun4m_hw_init(&sun4m_hwdefs
[7], machine
);
1384 /* SPARCbook hardware initialisation */
1385 static void sbook_init(MachineState
*machine
)
1387 sun4m_hw_init(&sun4m_hwdefs
[8], machine
);
1390 static void ss5_class_init(ObjectClass
*oc
, void *data
)
1392 MachineClass
*mc
= MACHINE_CLASS(oc
);
1394 mc
->desc
= "Sun4m platform, SPARCstation 5";
1395 mc
->init
= ss5_init
;
1396 mc
->block_default_type
= IF_SCSI
;
1397 mc
->is_default
= true;
1398 mc
->default_boot_order
= "c";
1399 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1400 mc
->default_display
= "tcx";
1401 mc
->default_ram_id
= "sun4m.ram";
1404 static const TypeInfo ss5_type
= {
1405 .name
= MACHINE_TYPE_NAME("SS-5"),
1406 .parent
= TYPE_MACHINE
,
1407 .class_init
= ss5_class_init
,
1410 static void ss10_class_init(ObjectClass
*oc
, void *data
)
1412 MachineClass
*mc
= MACHINE_CLASS(oc
);
1414 mc
->desc
= "Sun4m platform, SPARCstation 10";
1415 mc
->init
= ss10_init
;
1416 mc
->block_default_type
= IF_SCSI
;
1418 mc
->default_boot_order
= "c";
1419 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1420 mc
->default_display
= "tcx";
1421 mc
->default_ram_id
= "sun4m.ram";
1424 static const TypeInfo ss10_type
= {
1425 .name
= MACHINE_TYPE_NAME("SS-10"),
1426 .parent
= TYPE_MACHINE
,
1427 .class_init
= ss10_class_init
,
1430 static void ss600mp_class_init(ObjectClass
*oc
, void *data
)
1432 MachineClass
*mc
= MACHINE_CLASS(oc
);
1434 mc
->desc
= "Sun4m platform, SPARCserver 600MP";
1435 mc
->init
= ss600mp_init
;
1436 mc
->block_default_type
= IF_SCSI
;
1438 mc
->default_boot_order
= "c";
1439 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1440 mc
->default_display
= "tcx";
1441 mc
->default_ram_id
= "sun4m.ram";
1444 static const TypeInfo ss600mp_type
= {
1445 .name
= MACHINE_TYPE_NAME("SS-600MP"),
1446 .parent
= TYPE_MACHINE
,
1447 .class_init
= ss600mp_class_init
,
1450 static void ss20_class_init(ObjectClass
*oc
, void *data
)
1452 MachineClass
*mc
= MACHINE_CLASS(oc
);
1454 mc
->desc
= "Sun4m platform, SPARCstation 20";
1455 mc
->init
= ss20_init
;
1456 mc
->block_default_type
= IF_SCSI
;
1458 mc
->default_boot_order
= "c";
1459 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1460 mc
->default_display
= "tcx";
1461 mc
->default_ram_id
= "sun4m.ram";
1464 static const TypeInfo ss20_type
= {
1465 .name
= MACHINE_TYPE_NAME("SS-20"),
1466 .parent
= TYPE_MACHINE
,
1467 .class_init
= ss20_class_init
,
1470 static void voyager_class_init(ObjectClass
*oc
, void *data
)
1472 MachineClass
*mc
= MACHINE_CLASS(oc
);
1474 mc
->desc
= "Sun4m platform, SPARCstation Voyager";
1475 mc
->init
= vger_init
;
1476 mc
->block_default_type
= IF_SCSI
;
1477 mc
->default_boot_order
= "c";
1478 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1479 mc
->default_display
= "tcx";
1480 mc
->default_ram_id
= "sun4m.ram";
1483 static const TypeInfo voyager_type
= {
1484 .name
= MACHINE_TYPE_NAME("Voyager"),
1485 .parent
= TYPE_MACHINE
,
1486 .class_init
= voyager_class_init
,
1489 static void ss_lx_class_init(ObjectClass
*oc
, void *data
)
1491 MachineClass
*mc
= MACHINE_CLASS(oc
);
1493 mc
->desc
= "Sun4m platform, SPARCstation LX";
1494 mc
->init
= ss_lx_init
;
1495 mc
->block_default_type
= IF_SCSI
;
1496 mc
->default_boot_order
= "c";
1497 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1498 mc
->default_display
= "tcx";
1499 mc
->default_ram_id
= "sun4m.ram";
1502 static const TypeInfo ss_lx_type
= {
1503 .name
= MACHINE_TYPE_NAME("LX"),
1504 .parent
= TYPE_MACHINE
,
1505 .class_init
= ss_lx_class_init
,
1508 static void ss4_class_init(ObjectClass
*oc
, void *data
)
1510 MachineClass
*mc
= MACHINE_CLASS(oc
);
1512 mc
->desc
= "Sun4m platform, SPARCstation 4";
1513 mc
->init
= ss4_init
;
1514 mc
->block_default_type
= IF_SCSI
;
1515 mc
->default_boot_order
= "c";
1516 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1517 mc
->default_display
= "tcx";
1518 mc
->default_ram_id
= "sun4m.ram";
1521 static const TypeInfo ss4_type
= {
1522 .name
= MACHINE_TYPE_NAME("SS-4"),
1523 .parent
= TYPE_MACHINE
,
1524 .class_init
= ss4_class_init
,
1527 static void scls_class_init(ObjectClass
*oc
, void *data
)
1529 MachineClass
*mc
= MACHINE_CLASS(oc
);
1531 mc
->desc
= "Sun4m platform, SPARCClassic";
1532 mc
->init
= scls_init
;
1533 mc
->block_default_type
= IF_SCSI
;
1534 mc
->default_boot_order
= "c";
1535 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1536 mc
->default_display
= "tcx";
1537 mc
->default_ram_id
= "sun4m.ram";
1540 static const TypeInfo scls_type
= {
1541 .name
= MACHINE_TYPE_NAME("SPARCClassic"),
1542 .parent
= TYPE_MACHINE
,
1543 .class_init
= scls_class_init
,
1546 static void sbook_class_init(ObjectClass
*oc
, void *data
)
1548 MachineClass
*mc
= MACHINE_CLASS(oc
);
1550 mc
->desc
= "Sun4m platform, SPARCbook";
1551 mc
->init
= sbook_init
;
1552 mc
->block_default_type
= IF_SCSI
;
1553 mc
->default_boot_order
= "c";
1554 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1555 mc
->default_display
= "tcx";
1556 mc
->default_ram_id
= "sun4m.ram";
1559 static const TypeInfo sbook_type
= {
1560 .name
= MACHINE_TYPE_NAME("SPARCbook"),
1561 .parent
= TYPE_MACHINE
,
1562 .class_init
= sbook_class_init
,
1565 static void sun4m_register_types(void)
1567 type_register_static(&idreg_info
);
1568 type_register_static(&afx_info
);
1569 type_register_static(&prom_info
);
1570 type_register_static(&ram_info
);
1572 type_register_static(&ss5_type
);
1573 type_register_static(&ss10_type
);
1574 type_register_static(&ss600mp_type
);
1575 type_register_static(&ss20_type
);
1576 type_register_static(&voyager_type
);
1577 type_register_static(&ss_lx_type
);
1578 type_register_static(&ss4_type
);
1579 type_register_static(&scls_type
);
1580 type_register_static(&sbook_type
);
1583 type_init(sun4m_register_types
)