Merge remote-tracking branch 'remotes/armbru/tags/pull-build-2019-07-02-v2' into...
[qemu/ar7.git] / exec.c
blobe7622d195619f5a64423eeb3ad79bee34b53b594
1 /*
2 * Virtual page mapping
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
24 #include "qemu/cutils.h"
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "exec/target_page.h"
28 #include "tcg.h"
29 #include "hw/qdev-core.h"
30 #include "hw/qdev-properties.h"
31 #if !defined(CONFIG_USER_ONLY)
32 #include "hw/boards.h"
33 #include "hw/xen/xen.h"
34 #endif
35 #include "sysemu/kvm.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "qemu/timer.h"
39 #include "qemu/config-file.h"
40 #include "qemu/error-report.h"
41 #include "qemu/qemu-print.h"
42 #if defined(CONFIG_USER_ONLY)
43 #include "qemu.h"
44 #else /* !CONFIG_USER_ONLY */
45 #include "hw/hw.h"
46 #include "exec/memory.h"
47 #include "exec/ioport.h"
48 #include "sysemu/dma.h"
49 #include "sysemu/numa.h"
50 #include "sysemu/hw_accel.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/xen-mapcache.h"
53 #include "trace-root.h"
55 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
56 #include <linux/falloc.h>
57 #endif
59 #endif
60 #include "qemu/rcu_queue.h"
61 #include "qemu/main-loop.h"
62 #include "translate-all.h"
63 #include "sysemu/replay.h"
65 #include "exec/memory-internal.h"
66 #include "exec/ram_addr.h"
67 #include "exec/log.h"
69 #include "migration/vmstate.h"
71 #include "qemu/range.h"
72 #ifndef _WIN32
73 #include "qemu/mmap-alloc.h"
74 #endif
76 #include "monitor/monitor.h"
78 //#define DEBUG_SUBPAGE
80 #if !defined(CONFIG_USER_ONLY)
81 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
82 * are protected by the ramlist lock.
84 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
86 static MemoryRegion *system_memory;
87 static MemoryRegion *system_io;
89 AddressSpace address_space_io;
90 AddressSpace address_space_memory;
92 MemoryRegion io_mem_rom, io_mem_notdirty;
93 static MemoryRegion io_mem_unassigned;
94 #endif
96 #ifdef TARGET_PAGE_BITS_VARY
97 int target_page_bits;
98 bool target_page_bits_decided;
99 #endif
101 CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
103 /* current CPU in the current thread. It is only valid inside
104 cpu_exec() */
105 __thread CPUState *current_cpu;
106 /* 0 = Do not count executed instructions.
107 1 = Precise instruction counting.
108 2 = Adaptive rate instruction counting. */
109 int use_icount;
111 uintptr_t qemu_host_page_size;
112 intptr_t qemu_host_page_mask;
114 bool set_preferred_target_page_bits(int bits)
116 /* The target page size is the lowest common denominator for all
117 * the CPUs in the system, so we can only make it smaller, never
118 * larger. And we can't make it smaller once we've committed to
119 * a particular size.
121 #ifdef TARGET_PAGE_BITS_VARY
122 assert(bits >= TARGET_PAGE_BITS_MIN);
123 if (target_page_bits == 0 || target_page_bits > bits) {
124 if (target_page_bits_decided) {
125 return false;
127 target_page_bits = bits;
129 #endif
130 return true;
133 #if !defined(CONFIG_USER_ONLY)
135 static void finalize_target_page_bits(void)
137 #ifdef TARGET_PAGE_BITS_VARY
138 if (target_page_bits == 0) {
139 target_page_bits = TARGET_PAGE_BITS_MIN;
141 target_page_bits_decided = true;
142 #endif
145 typedef struct PhysPageEntry PhysPageEntry;
147 struct PhysPageEntry {
148 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
149 uint32_t skip : 6;
150 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
151 uint32_t ptr : 26;
154 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
156 /* Size of the L2 (and L3, etc) page tables. */
157 #define ADDR_SPACE_BITS 64
159 #define P_L2_BITS 9
160 #define P_L2_SIZE (1 << P_L2_BITS)
162 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
164 typedef PhysPageEntry Node[P_L2_SIZE];
166 typedef struct PhysPageMap {
167 struct rcu_head rcu;
169 unsigned sections_nb;
170 unsigned sections_nb_alloc;
171 unsigned nodes_nb;
172 unsigned nodes_nb_alloc;
173 Node *nodes;
174 MemoryRegionSection *sections;
175 } PhysPageMap;
177 struct AddressSpaceDispatch {
178 MemoryRegionSection *mru_section;
179 /* This is a multi-level map on the physical address space.
180 * The bottom level has pointers to MemoryRegionSections.
182 PhysPageEntry phys_map;
183 PhysPageMap map;
186 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
187 typedef struct subpage_t {
188 MemoryRegion iomem;
189 FlatView *fv;
190 hwaddr base;
191 uint16_t sub_section[];
192 } subpage_t;
194 #define PHYS_SECTION_UNASSIGNED 0
195 #define PHYS_SECTION_NOTDIRTY 1
196 #define PHYS_SECTION_ROM 2
197 #define PHYS_SECTION_WATCH 3
199 static void io_mem_init(void);
200 static void memory_map_init(void);
201 static void tcg_commit(MemoryListener *listener);
203 static MemoryRegion io_mem_watch;
206 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
207 * @cpu: the CPU whose AddressSpace this is
208 * @as: the AddressSpace itself
209 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
210 * @tcg_as_listener: listener for tracking changes to the AddressSpace
212 struct CPUAddressSpace {
213 CPUState *cpu;
214 AddressSpace *as;
215 struct AddressSpaceDispatch *memory_dispatch;
216 MemoryListener tcg_as_listener;
219 struct DirtyBitmapSnapshot {
220 ram_addr_t start;
221 ram_addr_t end;
222 unsigned long dirty[];
225 #endif
227 #if !defined(CONFIG_USER_ONLY)
229 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
231 static unsigned alloc_hint = 16;
232 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
233 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
234 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
235 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
236 alloc_hint = map->nodes_nb_alloc;
240 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
242 unsigned i;
243 uint32_t ret;
244 PhysPageEntry e;
245 PhysPageEntry *p;
247 ret = map->nodes_nb++;
248 p = map->nodes[ret];
249 assert(ret != PHYS_MAP_NODE_NIL);
250 assert(ret != map->nodes_nb_alloc);
252 e.skip = leaf ? 0 : 1;
253 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
254 for (i = 0; i < P_L2_SIZE; ++i) {
255 memcpy(&p[i], &e, sizeof(e));
257 return ret;
260 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
261 hwaddr *index, hwaddr *nb, uint16_t leaf,
262 int level)
264 PhysPageEntry *p;
265 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
267 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
268 lp->ptr = phys_map_node_alloc(map, level == 0);
270 p = map->nodes[lp->ptr];
271 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
273 while (*nb && lp < &p[P_L2_SIZE]) {
274 if ((*index & (step - 1)) == 0 && *nb >= step) {
275 lp->skip = 0;
276 lp->ptr = leaf;
277 *index += step;
278 *nb -= step;
279 } else {
280 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
282 ++lp;
286 static void phys_page_set(AddressSpaceDispatch *d,
287 hwaddr index, hwaddr nb,
288 uint16_t leaf)
290 /* Wildly overreserve - it doesn't matter much. */
291 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
293 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
296 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
297 * and update our entry so we can skip it and go directly to the destination.
299 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
301 unsigned valid_ptr = P_L2_SIZE;
302 int valid = 0;
303 PhysPageEntry *p;
304 int i;
306 if (lp->ptr == PHYS_MAP_NODE_NIL) {
307 return;
310 p = nodes[lp->ptr];
311 for (i = 0; i < P_L2_SIZE; i++) {
312 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
313 continue;
316 valid_ptr = i;
317 valid++;
318 if (p[i].skip) {
319 phys_page_compact(&p[i], nodes);
323 /* We can only compress if there's only one child. */
324 if (valid != 1) {
325 return;
328 assert(valid_ptr < P_L2_SIZE);
330 /* Don't compress if it won't fit in the # of bits we have. */
331 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
332 return;
335 lp->ptr = p[valid_ptr].ptr;
336 if (!p[valid_ptr].skip) {
337 /* If our only child is a leaf, make this a leaf. */
338 /* By design, we should have made this node a leaf to begin with so we
339 * should never reach here.
340 * But since it's so simple to handle this, let's do it just in case we
341 * change this rule.
343 lp->skip = 0;
344 } else {
345 lp->skip += p[valid_ptr].skip;
349 void address_space_dispatch_compact(AddressSpaceDispatch *d)
351 if (d->phys_map.skip) {
352 phys_page_compact(&d->phys_map, d->map.nodes);
356 static inline bool section_covers_addr(const MemoryRegionSection *section,
357 hwaddr addr)
359 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
360 * the section must cover the entire address space.
362 return int128_gethi(section->size) ||
363 range_covers_byte(section->offset_within_address_space,
364 int128_getlo(section->size), addr);
367 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
369 PhysPageEntry lp = d->phys_map, *p;
370 Node *nodes = d->map.nodes;
371 MemoryRegionSection *sections = d->map.sections;
372 hwaddr index = addr >> TARGET_PAGE_BITS;
373 int i;
375 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
376 if (lp.ptr == PHYS_MAP_NODE_NIL) {
377 return &sections[PHYS_SECTION_UNASSIGNED];
379 p = nodes[lp.ptr];
380 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
383 if (section_covers_addr(&sections[lp.ptr], addr)) {
384 return &sections[lp.ptr];
385 } else {
386 return &sections[PHYS_SECTION_UNASSIGNED];
390 /* Called from RCU critical section */
391 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
392 hwaddr addr,
393 bool resolve_subpage)
395 MemoryRegionSection *section = atomic_read(&d->mru_section);
396 subpage_t *subpage;
398 if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
399 !section_covers_addr(section, addr)) {
400 section = phys_page_find(d, addr);
401 atomic_set(&d->mru_section, section);
403 if (resolve_subpage && section->mr->subpage) {
404 subpage = container_of(section->mr, subpage_t, iomem);
405 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
407 return section;
410 /* Called from RCU critical section */
411 static MemoryRegionSection *
412 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
413 hwaddr *plen, bool resolve_subpage)
415 MemoryRegionSection *section;
416 MemoryRegion *mr;
417 Int128 diff;
419 section = address_space_lookup_region(d, addr, resolve_subpage);
420 /* Compute offset within MemoryRegionSection */
421 addr -= section->offset_within_address_space;
423 /* Compute offset within MemoryRegion */
424 *xlat = addr + section->offset_within_region;
426 mr = section->mr;
428 /* MMIO registers can be expected to perform full-width accesses based only
429 * on their address, without considering adjacent registers that could
430 * decode to completely different MemoryRegions. When such registers
431 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
432 * regions overlap wildly. For this reason we cannot clamp the accesses
433 * here.
435 * If the length is small (as is the case for address_space_ldl/stl),
436 * everything works fine. If the incoming length is large, however,
437 * the caller really has to do the clamping through memory_access_size.
439 if (memory_region_is_ram(mr)) {
440 diff = int128_sub(section->size, int128_make64(addr));
441 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
443 return section;
447 * address_space_translate_iommu - translate an address through an IOMMU
448 * memory region and then through the target address space.
450 * @iommu_mr: the IOMMU memory region that we start the translation from
451 * @addr: the address to be translated through the MMU
452 * @xlat: the translated address offset within the destination memory region.
453 * It cannot be %NULL.
454 * @plen_out: valid read/write length of the translated address. It
455 * cannot be %NULL.
456 * @page_mask_out: page mask for the translated address. This
457 * should only be meaningful for IOMMU translated
458 * addresses, since there may be huge pages that this bit
459 * would tell. It can be %NULL if we don't care about it.
460 * @is_write: whether the translation operation is for write
461 * @is_mmio: whether this can be MMIO, set true if it can
462 * @target_as: the address space targeted by the IOMMU
463 * @attrs: transaction attributes
465 * This function is called from RCU critical section. It is the common
466 * part of flatview_do_translate and address_space_translate_cached.
468 static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr,
469 hwaddr *xlat,
470 hwaddr *plen_out,
471 hwaddr *page_mask_out,
472 bool is_write,
473 bool is_mmio,
474 AddressSpace **target_as,
475 MemTxAttrs attrs)
477 MemoryRegionSection *section;
478 hwaddr page_mask = (hwaddr)-1;
480 do {
481 hwaddr addr = *xlat;
482 IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
483 int iommu_idx = 0;
484 IOMMUTLBEntry iotlb;
486 if (imrc->attrs_to_index) {
487 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
490 iotlb = imrc->translate(iommu_mr, addr, is_write ?
491 IOMMU_WO : IOMMU_RO, iommu_idx);
493 if (!(iotlb.perm & (1 << is_write))) {
494 goto unassigned;
497 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
498 | (addr & iotlb.addr_mask));
499 page_mask &= iotlb.addr_mask;
500 *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1);
501 *target_as = iotlb.target_as;
503 section = address_space_translate_internal(
504 address_space_to_dispatch(iotlb.target_as), addr, xlat,
505 plen_out, is_mmio);
507 iommu_mr = memory_region_get_iommu(section->mr);
508 } while (unlikely(iommu_mr));
510 if (page_mask_out) {
511 *page_mask_out = page_mask;
513 return *section;
515 unassigned:
516 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
520 * flatview_do_translate - translate an address in FlatView
522 * @fv: the flat view that we want to translate on
523 * @addr: the address to be translated in above address space
524 * @xlat: the translated address offset within memory region. It
525 * cannot be @NULL.
526 * @plen_out: valid read/write length of the translated address. It
527 * can be @NULL when we don't care about it.
528 * @page_mask_out: page mask for the translated address. This
529 * should only be meaningful for IOMMU translated
530 * addresses, since there may be huge pages that this bit
531 * would tell. It can be @NULL if we don't care about it.
532 * @is_write: whether the translation operation is for write
533 * @is_mmio: whether this can be MMIO, set true if it can
534 * @target_as: the address space targeted by the IOMMU
535 * @attrs: memory transaction attributes
537 * This function is called from RCU critical section
539 static MemoryRegionSection flatview_do_translate(FlatView *fv,
540 hwaddr addr,
541 hwaddr *xlat,
542 hwaddr *plen_out,
543 hwaddr *page_mask_out,
544 bool is_write,
545 bool is_mmio,
546 AddressSpace **target_as,
547 MemTxAttrs attrs)
549 MemoryRegionSection *section;
550 IOMMUMemoryRegion *iommu_mr;
551 hwaddr plen = (hwaddr)(-1);
553 if (!plen_out) {
554 plen_out = &plen;
557 section = address_space_translate_internal(
558 flatview_to_dispatch(fv), addr, xlat,
559 plen_out, is_mmio);
561 iommu_mr = memory_region_get_iommu(section->mr);
562 if (unlikely(iommu_mr)) {
563 return address_space_translate_iommu(iommu_mr, xlat,
564 plen_out, page_mask_out,
565 is_write, is_mmio,
566 target_as, attrs);
568 if (page_mask_out) {
569 /* Not behind an IOMMU, use default page size. */
570 *page_mask_out = ~TARGET_PAGE_MASK;
573 return *section;
576 /* Called from RCU critical section */
577 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
578 bool is_write, MemTxAttrs attrs)
580 MemoryRegionSection section;
581 hwaddr xlat, page_mask;
584 * This can never be MMIO, and we don't really care about plen,
585 * but page mask.
587 section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
588 NULL, &page_mask, is_write, false, &as,
589 attrs);
591 /* Illegal translation */
592 if (section.mr == &io_mem_unassigned) {
593 goto iotlb_fail;
596 /* Convert memory region offset into address space offset */
597 xlat += section.offset_within_address_space -
598 section.offset_within_region;
600 return (IOMMUTLBEntry) {
601 .target_as = as,
602 .iova = addr & ~page_mask,
603 .translated_addr = xlat & ~page_mask,
604 .addr_mask = page_mask,
605 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
606 .perm = IOMMU_RW,
609 iotlb_fail:
610 return (IOMMUTLBEntry) {0};
613 /* Called from RCU critical section */
614 MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
615 hwaddr *plen, bool is_write,
616 MemTxAttrs attrs)
618 MemoryRegion *mr;
619 MemoryRegionSection section;
620 AddressSpace *as = NULL;
622 /* This can be MMIO, so setup MMIO bit. */
623 section = flatview_do_translate(fv, addr, xlat, plen, NULL,
624 is_write, true, &as, attrs);
625 mr = section.mr;
627 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
628 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
629 *plen = MIN(page, *plen);
632 return mr;
635 typedef struct TCGIOMMUNotifier {
636 IOMMUNotifier n;
637 MemoryRegion *mr;
638 CPUState *cpu;
639 int iommu_idx;
640 bool active;
641 } TCGIOMMUNotifier;
643 static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb)
645 TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n);
647 if (!notifier->active) {
648 return;
650 tlb_flush(notifier->cpu);
651 notifier->active = false;
652 /* We leave the notifier struct on the list to avoid reallocating it later.
653 * Generally the number of IOMMUs a CPU deals with will be small.
654 * In any case we can't unregister the iommu notifier from a notify
655 * callback.
659 static void tcg_register_iommu_notifier(CPUState *cpu,
660 IOMMUMemoryRegion *iommu_mr,
661 int iommu_idx)
663 /* Make sure this CPU has an IOMMU notifier registered for this
664 * IOMMU/IOMMU index combination, so that we can flush its TLB
665 * when the IOMMU tells us the mappings we've cached have changed.
667 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
668 TCGIOMMUNotifier *notifier;
669 int i;
671 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
672 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
673 if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) {
674 break;
677 if (i == cpu->iommu_notifiers->len) {
678 /* Not found, add a new entry at the end of the array */
679 cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1);
680 notifier = g_new0(TCGIOMMUNotifier, 1);
681 g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i) = notifier;
683 notifier->mr = mr;
684 notifier->iommu_idx = iommu_idx;
685 notifier->cpu = cpu;
686 /* Rather than trying to register interest in the specific part
687 * of the iommu's address space that we've accessed and then
688 * expand it later as subsequent accesses touch more of it, we
689 * just register interest in the whole thing, on the assumption
690 * that iommu reconfiguration will be rare.
692 iommu_notifier_init(&notifier->n,
693 tcg_iommu_unmap_notify,
694 IOMMU_NOTIFIER_UNMAP,
696 HWADDR_MAX,
697 iommu_idx);
698 memory_region_register_iommu_notifier(notifier->mr, &notifier->n);
701 if (!notifier->active) {
702 notifier->active = true;
706 static void tcg_iommu_free_notifier_list(CPUState *cpu)
708 /* Destroy the CPU's notifier list */
709 int i;
710 TCGIOMMUNotifier *notifier;
712 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
713 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
714 memory_region_unregister_iommu_notifier(notifier->mr, &notifier->n);
715 g_free(notifier);
717 g_array_free(cpu->iommu_notifiers, true);
720 /* Called from RCU critical section */
721 MemoryRegionSection *
722 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
723 hwaddr *xlat, hwaddr *plen,
724 MemTxAttrs attrs, int *prot)
726 MemoryRegionSection *section;
727 IOMMUMemoryRegion *iommu_mr;
728 IOMMUMemoryRegionClass *imrc;
729 IOMMUTLBEntry iotlb;
730 int iommu_idx;
731 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
733 for (;;) {
734 section = address_space_translate_internal(d, addr, &addr, plen, false);
736 iommu_mr = memory_region_get_iommu(section->mr);
737 if (!iommu_mr) {
738 break;
741 imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
743 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
744 tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx);
745 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
746 * doesn't short-cut its translation table walk.
748 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx);
749 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
750 | (addr & iotlb.addr_mask));
751 /* Update the caller's prot bits to remove permissions the IOMMU
752 * is giving us a failure response for. If we get down to no
753 * permissions left at all we can give up now.
755 if (!(iotlb.perm & IOMMU_RO)) {
756 *prot &= ~(PAGE_READ | PAGE_EXEC);
758 if (!(iotlb.perm & IOMMU_WO)) {
759 *prot &= ~PAGE_WRITE;
762 if (!*prot) {
763 goto translate_fail;
766 d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as));
769 assert(!memory_region_is_iommu(section->mr));
770 *xlat = addr;
771 return section;
773 translate_fail:
774 return &d->map.sections[PHYS_SECTION_UNASSIGNED];
776 #endif
778 #if !defined(CONFIG_USER_ONLY)
780 static int cpu_common_post_load(void *opaque, int version_id)
782 CPUState *cpu = opaque;
784 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
785 version_id is increased. */
786 cpu->interrupt_request &= ~0x01;
787 tlb_flush(cpu);
789 /* loadvm has just updated the content of RAM, bypassing the
790 * usual mechanisms that ensure we flush TBs for writes to
791 * memory we've translated code from. So we must flush all TBs,
792 * which will now be stale.
794 tb_flush(cpu);
796 return 0;
799 static int cpu_common_pre_load(void *opaque)
801 CPUState *cpu = opaque;
803 cpu->exception_index = -1;
805 return 0;
808 static bool cpu_common_exception_index_needed(void *opaque)
810 CPUState *cpu = opaque;
812 return tcg_enabled() && cpu->exception_index != -1;
815 static const VMStateDescription vmstate_cpu_common_exception_index = {
816 .name = "cpu_common/exception_index",
817 .version_id = 1,
818 .minimum_version_id = 1,
819 .needed = cpu_common_exception_index_needed,
820 .fields = (VMStateField[]) {
821 VMSTATE_INT32(exception_index, CPUState),
822 VMSTATE_END_OF_LIST()
826 static bool cpu_common_crash_occurred_needed(void *opaque)
828 CPUState *cpu = opaque;
830 return cpu->crash_occurred;
833 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
834 .name = "cpu_common/crash_occurred",
835 .version_id = 1,
836 .minimum_version_id = 1,
837 .needed = cpu_common_crash_occurred_needed,
838 .fields = (VMStateField[]) {
839 VMSTATE_BOOL(crash_occurred, CPUState),
840 VMSTATE_END_OF_LIST()
844 const VMStateDescription vmstate_cpu_common = {
845 .name = "cpu_common",
846 .version_id = 1,
847 .minimum_version_id = 1,
848 .pre_load = cpu_common_pre_load,
849 .post_load = cpu_common_post_load,
850 .fields = (VMStateField[]) {
851 VMSTATE_UINT32(halted, CPUState),
852 VMSTATE_UINT32(interrupt_request, CPUState),
853 VMSTATE_END_OF_LIST()
855 .subsections = (const VMStateDescription*[]) {
856 &vmstate_cpu_common_exception_index,
857 &vmstate_cpu_common_crash_occurred,
858 NULL
862 #endif
864 CPUState *qemu_get_cpu(int index)
866 CPUState *cpu;
868 CPU_FOREACH(cpu) {
869 if (cpu->cpu_index == index) {
870 return cpu;
874 return NULL;
877 #if !defined(CONFIG_USER_ONLY)
878 void cpu_address_space_init(CPUState *cpu, int asidx,
879 const char *prefix, MemoryRegion *mr)
881 CPUAddressSpace *newas;
882 AddressSpace *as = g_new0(AddressSpace, 1);
883 char *as_name;
885 assert(mr);
886 as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index);
887 address_space_init(as, mr, as_name);
888 g_free(as_name);
890 /* Target code should have set num_ases before calling us */
891 assert(asidx < cpu->num_ases);
893 if (asidx == 0) {
894 /* address space 0 gets the convenience alias */
895 cpu->as = as;
898 /* KVM cannot currently support multiple address spaces. */
899 assert(asidx == 0 || !kvm_enabled());
901 if (!cpu->cpu_ases) {
902 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
905 newas = &cpu->cpu_ases[asidx];
906 newas->cpu = cpu;
907 newas->as = as;
908 if (tcg_enabled()) {
909 newas->tcg_as_listener.commit = tcg_commit;
910 memory_listener_register(&newas->tcg_as_listener, as);
914 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
916 /* Return the AddressSpace corresponding to the specified index */
917 return cpu->cpu_ases[asidx].as;
919 #endif
921 void cpu_exec_unrealizefn(CPUState *cpu)
923 CPUClass *cc = CPU_GET_CLASS(cpu);
925 cpu_list_remove(cpu);
927 if (cc->vmsd != NULL) {
928 vmstate_unregister(NULL, cc->vmsd, cpu);
930 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
931 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
933 #ifndef CONFIG_USER_ONLY
934 tcg_iommu_free_notifier_list(cpu);
935 #endif
938 Property cpu_common_props[] = {
939 #ifndef CONFIG_USER_ONLY
940 /* Create a memory property for softmmu CPU object,
941 * so users can wire up its memory. (This can't go in qom/cpu.c
942 * because that file is compiled only once for both user-mode
943 * and system builds.) The default if no link is set up is to use
944 * the system address space.
946 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
947 MemoryRegion *),
948 #endif
949 DEFINE_PROP_END_OF_LIST(),
952 void cpu_exec_initfn(CPUState *cpu)
954 cpu->as = NULL;
955 cpu->num_ases = 0;
957 #ifndef CONFIG_USER_ONLY
958 cpu->thread_id = qemu_get_thread_id();
959 cpu->memory = system_memory;
960 object_ref(OBJECT(cpu->memory));
961 #endif
964 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
966 CPUClass *cc = CPU_GET_CLASS(cpu);
967 static bool tcg_target_initialized;
969 cpu_list_add(cpu);
971 if (tcg_enabled() && !tcg_target_initialized) {
972 tcg_target_initialized = true;
973 cc->tcg_initialize();
975 tlb_init(cpu);
977 #ifndef CONFIG_USER_ONLY
978 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
979 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
981 if (cc->vmsd != NULL) {
982 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
985 cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *));
986 #endif
989 const char *parse_cpu_option(const char *cpu_option)
991 ObjectClass *oc;
992 CPUClass *cc;
993 gchar **model_pieces;
994 const char *cpu_type;
996 model_pieces = g_strsplit(cpu_option, ",", 2);
997 if (!model_pieces[0]) {
998 error_report("-cpu option cannot be empty");
999 exit(1);
1002 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
1003 if (oc == NULL) {
1004 error_report("unable to find CPU model '%s'", model_pieces[0]);
1005 g_strfreev(model_pieces);
1006 exit(EXIT_FAILURE);
1009 cpu_type = object_class_get_name(oc);
1010 cc = CPU_CLASS(oc);
1011 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
1012 g_strfreev(model_pieces);
1013 return cpu_type;
1016 #if defined(CONFIG_USER_ONLY)
1017 void tb_invalidate_phys_addr(target_ulong addr)
1019 mmap_lock();
1020 tb_invalidate_phys_page_range(addr, addr + 1, 0);
1021 mmap_unlock();
1024 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
1026 tb_invalidate_phys_addr(pc);
1028 #else
1029 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
1031 ram_addr_t ram_addr;
1032 MemoryRegion *mr;
1033 hwaddr l = 1;
1035 if (!tcg_enabled()) {
1036 return;
1039 rcu_read_lock();
1040 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
1041 if (!(memory_region_is_ram(mr)
1042 || memory_region_is_romd(mr))) {
1043 rcu_read_unlock();
1044 return;
1046 ram_addr = memory_region_get_ram_addr(mr) + addr;
1047 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
1048 rcu_read_unlock();
1051 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
1053 MemTxAttrs attrs;
1054 hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
1055 int asidx = cpu_asidx_from_attrs(cpu, attrs);
1056 if (phys != -1) {
1057 /* Locks grabbed by tb_invalidate_phys_addr */
1058 tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
1059 phys | (pc & ~TARGET_PAGE_MASK), attrs);
1062 #endif
1064 #if defined(CONFIG_USER_ONLY)
1065 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1070 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
1071 int flags)
1073 return -ENOSYS;
1076 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
1080 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1081 int flags, CPUWatchpoint **watchpoint)
1083 return -ENOSYS;
1085 #else
1086 /* Add a watchpoint. */
1087 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1088 int flags, CPUWatchpoint **watchpoint)
1090 CPUWatchpoint *wp;
1092 /* forbid ranges which are empty or run off the end of the address space */
1093 if (len == 0 || (addr + len - 1) < addr) {
1094 error_report("tried to set invalid watchpoint at %"
1095 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
1096 return -EINVAL;
1098 wp = g_malloc(sizeof(*wp));
1100 wp->vaddr = addr;
1101 wp->len = len;
1102 wp->flags = flags;
1104 /* keep all GDB-injected watchpoints in front */
1105 if (flags & BP_GDB) {
1106 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
1107 } else {
1108 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
1111 tlb_flush_page(cpu, addr);
1113 if (watchpoint)
1114 *watchpoint = wp;
1115 return 0;
1118 /* Remove a specific watchpoint. */
1119 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
1120 int flags)
1122 CPUWatchpoint *wp;
1124 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1125 if (addr == wp->vaddr && len == wp->len
1126 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
1127 cpu_watchpoint_remove_by_ref(cpu, wp);
1128 return 0;
1131 return -ENOENT;
1134 /* Remove a specific watchpoint by reference. */
1135 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
1137 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
1139 tlb_flush_page(cpu, watchpoint->vaddr);
1141 g_free(watchpoint);
1144 /* Remove all matching watchpoints. */
1145 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1147 CPUWatchpoint *wp, *next;
1149 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
1150 if (wp->flags & mask) {
1151 cpu_watchpoint_remove_by_ref(cpu, wp);
1156 /* Return true if this watchpoint address matches the specified
1157 * access (ie the address range covered by the watchpoint overlaps
1158 * partially or completely with the address range covered by the
1159 * access).
1161 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
1162 vaddr addr,
1163 vaddr len)
1165 /* We know the lengths are non-zero, but a little caution is
1166 * required to avoid errors in the case where the range ends
1167 * exactly at the top of the address space and so addr + len
1168 * wraps round to zero.
1170 vaddr wpend = wp->vaddr + wp->len - 1;
1171 vaddr addrend = addr + len - 1;
1173 return !(addr > wpend || wp->vaddr > addrend);
1176 #endif
1178 /* Add a breakpoint. */
1179 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1180 CPUBreakpoint **breakpoint)
1182 CPUBreakpoint *bp;
1184 bp = g_malloc(sizeof(*bp));
1186 bp->pc = pc;
1187 bp->flags = flags;
1189 /* keep all GDB-injected breakpoints in front */
1190 if (flags & BP_GDB) {
1191 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
1192 } else {
1193 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
1196 breakpoint_invalidate(cpu, pc);
1198 if (breakpoint) {
1199 *breakpoint = bp;
1201 return 0;
1204 /* Remove a specific breakpoint. */
1205 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
1207 CPUBreakpoint *bp;
1209 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1210 if (bp->pc == pc && bp->flags == flags) {
1211 cpu_breakpoint_remove_by_ref(cpu, bp);
1212 return 0;
1215 return -ENOENT;
1218 /* Remove a specific breakpoint by reference. */
1219 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
1221 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
1223 breakpoint_invalidate(cpu, breakpoint->pc);
1225 g_free(breakpoint);
1228 /* Remove all matching breakpoints. */
1229 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
1231 CPUBreakpoint *bp, *next;
1233 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
1234 if (bp->flags & mask) {
1235 cpu_breakpoint_remove_by_ref(cpu, bp);
1240 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1241 CPU loop after each instruction */
1242 void cpu_single_step(CPUState *cpu, int enabled)
1244 if (cpu->singlestep_enabled != enabled) {
1245 cpu->singlestep_enabled = enabled;
1246 if (kvm_enabled()) {
1247 kvm_update_guest_debug(cpu, 0);
1248 } else {
1249 /* must flush all the translated code to avoid inconsistencies */
1250 /* XXX: only flush what is necessary */
1251 tb_flush(cpu);
1256 void cpu_abort(CPUState *cpu, const char *fmt, ...)
1258 va_list ap;
1259 va_list ap2;
1261 va_start(ap, fmt);
1262 va_copy(ap2, ap);
1263 fprintf(stderr, "qemu: fatal: ");
1264 vfprintf(stderr, fmt, ap);
1265 fprintf(stderr, "\n");
1266 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1267 if (qemu_log_separate()) {
1268 qemu_log_lock();
1269 qemu_log("qemu: fatal: ");
1270 qemu_log_vprintf(fmt, ap2);
1271 qemu_log("\n");
1272 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1273 qemu_log_flush();
1274 qemu_log_unlock();
1275 qemu_log_close();
1277 va_end(ap2);
1278 va_end(ap);
1279 replay_finish();
1280 #if defined(CONFIG_USER_ONLY)
1282 struct sigaction act;
1283 sigfillset(&act.sa_mask);
1284 act.sa_handler = SIG_DFL;
1285 act.sa_flags = 0;
1286 sigaction(SIGABRT, &act, NULL);
1288 #endif
1289 abort();
1292 #if !defined(CONFIG_USER_ONLY)
1293 /* Called from RCU critical section */
1294 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1296 RAMBlock *block;
1298 block = atomic_rcu_read(&ram_list.mru_block);
1299 if (block && addr - block->offset < block->max_length) {
1300 return block;
1302 RAMBLOCK_FOREACH(block) {
1303 if (addr - block->offset < block->max_length) {
1304 goto found;
1308 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1309 abort();
1311 found:
1312 /* It is safe to write mru_block outside the iothread lock. This
1313 * is what happens:
1315 * mru_block = xxx
1316 * rcu_read_unlock()
1317 * xxx removed from list
1318 * rcu_read_lock()
1319 * read mru_block
1320 * mru_block = NULL;
1321 * call_rcu(reclaim_ramblock, xxx);
1322 * rcu_read_unlock()
1324 * atomic_rcu_set is not needed here. The block was already published
1325 * when it was placed into the list. Here we're just making an extra
1326 * copy of the pointer.
1328 ram_list.mru_block = block;
1329 return block;
1332 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1334 CPUState *cpu;
1335 ram_addr_t start1;
1336 RAMBlock *block;
1337 ram_addr_t end;
1339 assert(tcg_enabled());
1340 end = TARGET_PAGE_ALIGN(start + length);
1341 start &= TARGET_PAGE_MASK;
1343 rcu_read_lock();
1344 block = qemu_get_ram_block(start);
1345 assert(block == qemu_get_ram_block(end - 1));
1346 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1347 CPU_FOREACH(cpu) {
1348 tlb_reset_dirty(cpu, start1, length);
1350 rcu_read_unlock();
1353 /* Note: start and end must be within the same ram block. */
1354 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1355 ram_addr_t length,
1356 unsigned client)
1358 DirtyMemoryBlocks *blocks;
1359 unsigned long end, page;
1360 bool dirty = false;
1362 if (length == 0) {
1363 return false;
1366 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1367 page = start >> TARGET_PAGE_BITS;
1369 rcu_read_lock();
1371 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1373 while (page < end) {
1374 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1375 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1376 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1378 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1379 offset, num);
1380 page += num;
1383 rcu_read_unlock();
1385 if (dirty && tcg_enabled()) {
1386 tlb_reset_dirty_range_all(start, length);
1389 return dirty;
1392 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1393 (ram_addr_t start, ram_addr_t length, unsigned client)
1395 DirtyMemoryBlocks *blocks;
1396 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1397 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1398 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1399 DirtyBitmapSnapshot *snap;
1400 unsigned long page, end, dest;
1402 snap = g_malloc0(sizeof(*snap) +
1403 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1404 snap->start = first;
1405 snap->end = last;
1407 page = first >> TARGET_PAGE_BITS;
1408 end = last >> TARGET_PAGE_BITS;
1409 dest = 0;
1411 rcu_read_lock();
1413 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1415 while (page < end) {
1416 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1417 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1418 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1420 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1421 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1422 offset >>= BITS_PER_LEVEL;
1424 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1425 blocks->blocks[idx] + offset,
1426 num);
1427 page += num;
1428 dest += num >> BITS_PER_LEVEL;
1431 rcu_read_unlock();
1433 if (tcg_enabled()) {
1434 tlb_reset_dirty_range_all(start, length);
1437 return snap;
1440 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1441 ram_addr_t start,
1442 ram_addr_t length)
1444 unsigned long page, end;
1446 assert(start >= snap->start);
1447 assert(start + length <= snap->end);
1449 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1450 page = (start - snap->start) >> TARGET_PAGE_BITS;
1452 while (page < end) {
1453 if (test_bit(page, snap->dirty)) {
1454 return true;
1456 page++;
1458 return false;
1461 /* Called from RCU critical section */
1462 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1463 MemoryRegionSection *section,
1464 target_ulong vaddr,
1465 hwaddr paddr, hwaddr xlat,
1466 int prot,
1467 target_ulong *address)
1469 hwaddr iotlb;
1470 CPUWatchpoint *wp;
1472 if (memory_region_is_ram(section->mr)) {
1473 /* Normal RAM. */
1474 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1475 if (!section->readonly) {
1476 iotlb |= PHYS_SECTION_NOTDIRTY;
1477 } else {
1478 iotlb |= PHYS_SECTION_ROM;
1480 } else {
1481 AddressSpaceDispatch *d;
1483 d = flatview_to_dispatch(section->fv);
1484 iotlb = section - d->map.sections;
1485 iotlb += xlat;
1488 /* Make accesses to pages with watchpoints go via the
1489 watchpoint trap routines. */
1490 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1491 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1492 /* Avoid trapping reads of pages with a write breakpoint. */
1493 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1494 iotlb = PHYS_SECTION_WATCH + paddr;
1495 *address |= TLB_MMIO;
1496 break;
1501 return iotlb;
1503 #endif /* defined(CONFIG_USER_ONLY) */
1505 #if !defined(CONFIG_USER_ONLY)
1507 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1508 uint16_t section);
1509 static subpage_t *subpage_init(FlatView *fv, hwaddr base);
1511 static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) =
1512 qemu_anon_ram_alloc;
1515 * Set a custom physical guest memory alloator.
1516 * Accelerators with unusual needs may need this. Hopefully, we can
1517 * get rid of it eventually.
1519 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align, bool shared))
1521 phys_mem_alloc = alloc;
1524 static uint16_t phys_section_add(PhysPageMap *map,
1525 MemoryRegionSection *section)
1527 /* The physical section number is ORed with a page-aligned
1528 * pointer to produce the iotlb entries. Thus it should
1529 * never overflow into the page-aligned value.
1531 assert(map->sections_nb < TARGET_PAGE_SIZE);
1533 if (map->sections_nb == map->sections_nb_alloc) {
1534 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1535 map->sections = g_renew(MemoryRegionSection, map->sections,
1536 map->sections_nb_alloc);
1538 map->sections[map->sections_nb] = *section;
1539 memory_region_ref(section->mr);
1540 return map->sections_nb++;
1543 static void phys_section_destroy(MemoryRegion *mr)
1545 bool have_sub_page = mr->subpage;
1547 memory_region_unref(mr);
1549 if (have_sub_page) {
1550 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1551 object_unref(OBJECT(&subpage->iomem));
1552 g_free(subpage);
1556 static void phys_sections_free(PhysPageMap *map)
1558 while (map->sections_nb > 0) {
1559 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1560 phys_section_destroy(section->mr);
1562 g_free(map->sections);
1563 g_free(map->nodes);
1566 static void register_subpage(FlatView *fv, MemoryRegionSection *section)
1568 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1569 subpage_t *subpage;
1570 hwaddr base = section->offset_within_address_space
1571 & TARGET_PAGE_MASK;
1572 MemoryRegionSection *existing = phys_page_find(d, base);
1573 MemoryRegionSection subsection = {
1574 .offset_within_address_space = base,
1575 .size = int128_make64(TARGET_PAGE_SIZE),
1577 hwaddr start, end;
1579 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1581 if (!(existing->mr->subpage)) {
1582 subpage = subpage_init(fv, base);
1583 subsection.fv = fv;
1584 subsection.mr = &subpage->iomem;
1585 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1586 phys_section_add(&d->map, &subsection));
1587 } else {
1588 subpage = container_of(existing->mr, subpage_t, iomem);
1590 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1591 end = start + int128_get64(section->size) - 1;
1592 subpage_register(subpage, start, end,
1593 phys_section_add(&d->map, section));
1597 static void register_multipage(FlatView *fv,
1598 MemoryRegionSection *section)
1600 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1601 hwaddr start_addr = section->offset_within_address_space;
1602 uint16_t section_index = phys_section_add(&d->map, section);
1603 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1604 TARGET_PAGE_BITS));
1606 assert(num_pages);
1607 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1611 * The range in *section* may look like this:
1613 * |s|PPPPPPP|s|
1615 * where s stands for subpage and P for page.
1617 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section)
1619 MemoryRegionSection remain = *section;
1620 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1622 /* register first subpage */
1623 if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1624 uint64_t left = TARGET_PAGE_ALIGN(remain.offset_within_address_space)
1625 - remain.offset_within_address_space;
1627 MemoryRegionSection now = remain;
1628 now.size = int128_min(int128_make64(left), now.size);
1629 register_subpage(fv, &now);
1630 if (int128_eq(remain.size, now.size)) {
1631 return;
1633 remain.size = int128_sub(remain.size, now.size);
1634 remain.offset_within_address_space += int128_get64(now.size);
1635 remain.offset_within_region += int128_get64(now.size);
1638 /* register whole pages */
1639 if (int128_ge(remain.size, page_size)) {
1640 MemoryRegionSection now = remain;
1641 now.size = int128_and(now.size, int128_neg(page_size));
1642 register_multipage(fv, &now);
1643 if (int128_eq(remain.size, now.size)) {
1644 return;
1646 remain.size = int128_sub(remain.size, now.size);
1647 remain.offset_within_address_space += int128_get64(now.size);
1648 remain.offset_within_region += int128_get64(now.size);
1651 /* register last subpage */
1652 register_subpage(fv, &remain);
1655 void qemu_flush_coalesced_mmio_buffer(void)
1657 if (kvm_enabled())
1658 kvm_flush_coalesced_mmio_buffer();
1661 void qemu_mutex_lock_ramlist(void)
1663 qemu_mutex_lock(&ram_list.mutex);
1666 void qemu_mutex_unlock_ramlist(void)
1668 qemu_mutex_unlock(&ram_list.mutex);
1671 void ram_block_dump(Monitor *mon)
1673 RAMBlock *block;
1674 char *psize;
1676 rcu_read_lock();
1677 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1678 "Block Name", "PSize", "Offset", "Used", "Total");
1679 RAMBLOCK_FOREACH(block) {
1680 psize = size_to_str(block->page_size);
1681 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1682 " 0x%016" PRIx64 "\n", block->idstr, psize,
1683 (uint64_t)block->offset,
1684 (uint64_t)block->used_length,
1685 (uint64_t)block->max_length);
1686 g_free(psize);
1688 rcu_read_unlock();
1691 #ifdef __linux__
1693 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1694 * may or may not name the same files / on the same filesystem now as
1695 * when we actually open and map them. Iterate over the file
1696 * descriptors instead, and use qemu_fd_getpagesize().
1698 static int find_min_backend_pagesize(Object *obj, void *opaque)
1700 long *hpsize_min = opaque;
1702 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1703 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1704 long hpsize = host_memory_backend_pagesize(backend);
1706 if (host_memory_backend_is_mapped(backend) && (hpsize < *hpsize_min)) {
1707 *hpsize_min = hpsize;
1711 return 0;
1714 static int find_max_backend_pagesize(Object *obj, void *opaque)
1716 long *hpsize_max = opaque;
1718 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1719 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1720 long hpsize = host_memory_backend_pagesize(backend);
1722 if (host_memory_backend_is_mapped(backend) && (hpsize > *hpsize_max)) {
1723 *hpsize_max = hpsize;
1727 return 0;
1731 * TODO: We assume right now that all mapped host memory backends are
1732 * used as RAM, however some might be used for different purposes.
1734 long qemu_minrampagesize(void)
1736 long hpsize = LONG_MAX;
1737 long mainrampagesize;
1738 Object *memdev_root;
1740 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1742 /* it's possible we have memory-backend objects with
1743 * hugepage-backed RAM. these may get mapped into system
1744 * address space via -numa parameters or memory hotplug
1745 * hooks. we want to take these into account, but we
1746 * also want to make sure these supported hugepage
1747 * sizes are applicable across the entire range of memory
1748 * we may boot from, so we take the min across all
1749 * backends, and assume normal pages in cases where a
1750 * backend isn't backed by hugepages.
1752 memdev_root = object_resolve_path("/objects", NULL);
1753 if (memdev_root) {
1754 object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize);
1756 if (hpsize == LONG_MAX) {
1757 /* No additional memory regions found ==> Report main RAM page size */
1758 return mainrampagesize;
1761 /* If NUMA is disabled or the NUMA nodes are not backed with a
1762 * memory-backend, then there is at least one node using "normal" RAM,
1763 * so if its page size is smaller we have got to report that size instead.
1765 if (hpsize > mainrampagesize &&
1766 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1767 static bool warned;
1768 if (!warned) {
1769 error_report("Huge page support disabled (n/a for main memory).");
1770 warned = true;
1772 return mainrampagesize;
1775 return hpsize;
1778 long qemu_maxrampagesize(void)
1780 long pagesize = qemu_mempath_getpagesize(mem_path);
1781 Object *memdev_root = object_resolve_path("/objects", NULL);
1783 if (memdev_root) {
1784 object_child_foreach(memdev_root, find_max_backend_pagesize,
1785 &pagesize);
1787 return pagesize;
1789 #else
1790 long qemu_minrampagesize(void)
1792 return getpagesize();
1794 long qemu_maxrampagesize(void)
1796 return getpagesize();
1798 #endif
1800 #ifdef CONFIG_POSIX
1801 static int64_t get_file_size(int fd)
1803 int64_t size = lseek(fd, 0, SEEK_END);
1804 if (size < 0) {
1805 return -errno;
1807 return size;
1810 static int file_ram_open(const char *path,
1811 const char *region_name,
1812 bool *created,
1813 Error **errp)
1815 char *filename;
1816 char *sanitized_name;
1817 char *c;
1818 int fd = -1;
1820 *created = false;
1821 for (;;) {
1822 fd = open(path, O_RDWR);
1823 if (fd >= 0) {
1824 /* @path names an existing file, use it */
1825 break;
1827 if (errno == ENOENT) {
1828 /* @path names a file that doesn't exist, create it */
1829 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1830 if (fd >= 0) {
1831 *created = true;
1832 break;
1834 } else if (errno == EISDIR) {
1835 /* @path names a directory, create a file there */
1836 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1837 sanitized_name = g_strdup(region_name);
1838 for (c = sanitized_name; *c != '\0'; c++) {
1839 if (*c == '/') {
1840 *c = '_';
1844 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1845 sanitized_name);
1846 g_free(sanitized_name);
1848 fd = mkstemp(filename);
1849 if (fd >= 0) {
1850 unlink(filename);
1851 g_free(filename);
1852 break;
1854 g_free(filename);
1856 if (errno != EEXIST && errno != EINTR) {
1857 error_setg_errno(errp, errno,
1858 "can't open backing store %s for guest RAM",
1859 path);
1860 return -1;
1863 * Try again on EINTR and EEXIST. The latter happens when
1864 * something else creates the file between our two open().
1868 return fd;
1871 static void *file_ram_alloc(RAMBlock *block,
1872 ram_addr_t memory,
1873 int fd,
1874 bool truncate,
1875 Error **errp)
1877 void *area;
1879 block->page_size = qemu_fd_getpagesize(fd);
1880 if (block->mr->align % block->page_size) {
1881 error_setg(errp, "alignment 0x%" PRIx64
1882 " must be multiples of page size 0x%zx",
1883 block->mr->align, block->page_size);
1884 return NULL;
1885 } else if (block->mr->align && !is_power_of_2(block->mr->align)) {
1886 error_setg(errp, "alignment 0x%" PRIx64
1887 " must be a power of two", block->mr->align);
1888 return NULL;
1890 block->mr->align = MAX(block->page_size, block->mr->align);
1891 #if defined(__s390x__)
1892 if (kvm_enabled()) {
1893 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1895 #endif
1897 if (memory < block->page_size) {
1898 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1899 "or larger than page size 0x%zx",
1900 memory, block->page_size);
1901 return NULL;
1904 memory = ROUND_UP(memory, block->page_size);
1907 * ftruncate is not supported by hugetlbfs in older
1908 * hosts, so don't bother bailing out on errors.
1909 * If anything goes wrong with it under other filesystems,
1910 * mmap will fail.
1912 * Do not truncate the non-empty backend file to avoid corrupting
1913 * the existing data in the file. Disabling shrinking is not
1914 * enough. For example, the current vNVDIMM implementation stores
1915 * the guest NVDIMM labels at the end of the backend file. If the
1916 * backend file is later extended, QEMU will not be able to find
1917 * those labels. Therefore, extending the non-empty backend file
1918 * is disabled as well.
1920 if (truncate && ftruncate(fd, memory)) {
1921 perror("ftruncate");
1924 area = qemu_ram_mmap(fd, memory, block->mr->align,
1925 block->flags & RAM_SHARED, block->flags & RAM_PMEM);
1926 if (area == MAP_FAILED) {
1927 error_setg_errno(errp, errno,
1928 "unable to map backing store for guest RAM");
1929 return NULL;
1932 if (mem_prealloc) {
1933 os_mem_prealloc(fd, area, memory, smp_cpus, errp);
1934 if (errp && *errp) {
1935 qemu_ram_munmap(fd, area, memory);
1936 return NULL;
1940 block->fd = fd;
1941 return area;
1943 #endif
1945 /* Allocate space within the ram_addr_t space that governs the
1946 * dirty bitmaps.
1947 * Called with the ramlist lock held.
1949 static ram_addr_t find_ram_offset(ram_addr_t size)
1951 RAMBlock *block, *next_block;
1952 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1954 assert(size != 0); /* it would hand out same offset multiple times */
1956 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1957 return 0;
1960 RAMBLOCK_FOREACH(block) {
1961 ram_addr_t candidate, next = RAM_ADDR_MAX;
1963 /* Align blocks to start on a 'long' in the bitmap
1964 * which makes the bitmap sync'ing take the fast path.
1966 candidate = block->offset + block->max_length;
1967 candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS);
1969 /* Search for the closest following block
1970 * and find the gap.
1972 RAMBLOCK_FOREACH(next_block) {
1973 if (next_block->offset >= candidate) {
1974 next = MIN(next, next_block->offset);
1978 /* If it fits remember our place and remember the size
1979 * of gap, but keep going so that we might find a smaller
1980 * gap to fill so avoiding fragmentation.
1982 if (next - candidate >= size && next - candidate < mingap) {
1983 offset = candidate;
1984 mingap = next - candidate;
1987 trace_find_ram_offset_loop(size, candidate, offset, next, mingap);
1990 if (offset == RAM_ADDR_MAX) {
1991 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1992 (uint64_t)size);
1993 abort();
1996 trace_find_ram_offset(size, offset);
1998 return offset;
2001 static unsigned long last_ram_page(void)
2003 RAMBlock *block;
2004 ram_addr_t last = 0;
2006 rcu_read_lock();
2007 RAMBLOCK_FOREACH(block) {
2008 last = MAX(last, block->offset + block->max_length);
2010 rcu_read_unlock();
2011 return last >> TARGET_PAGE_BITS;
2014 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
2016 int ret;
2018 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
2019 if (!machine_dump_guest_core(current_machine)) {
2020 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
2021 if (ret) {
2022 perror("qemu_madvise");
2023 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
2024 "but dump_guest_core=off specified\n");
2029 const char *qemu_ram_get_idstr(RAMBlock *rb)
2031 return rb->idstr;
2034 void *qemu_ram_get_host_addr(RAMBlock *rb)
2036 return rb->host;
2039 ram_addr_t qemu_ram_get_offset(RAMBlock *rb)
2041 return rb->offset;
2044 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb)
2046 return rb->used_length;
2049 bool qemu_ram_is_shared(RAMBlock *rb)
2051 return rb->flags & RAM_SHARED;
2054 /* Note: Only set at the start of postcopy */
2055 bool qemu_ram_is_uf_zeroable(RAMBlock *rb)
2057 return rb->flags & RAM_UF_ZEROPAGE;
2060 void qemu_ram_set_uf_zeroable(RAMBlock *rb)
2062 rb->flags |= RAM_UF_ZEROPAGE;
2065 bool qemu_ram_is_migratable(RAMBlock *rb)
2067 return rb->flags & RAM_MIGRATABLE;
2070 void qemu_ram_set_migratable(RAMBlock *rb)
2072 rb->flags |= RAM_MIGRATABLE;
2075 void qemu_ram_unset_migratable(RAMBlock *rb)
2077 rb->flags &= ~RAM_MIGRATABLE;
2080 /* Called with iothread lock held. */
2081 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
2083 RAMBlock *block;
2085 assert(new_block);
2086 assert(!new_block->idstr[0]);
2088 if (dev) {
2089 char *id = qdev_get_dev_path(dev);
2090 if (id) {
2091 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
2092 g_free(id);
2095 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
2097 rcu_read_lock();
2098 RAMBLOCK_FOREACH(block) {
2099 if (block != new_block &&
2100 !strcmp(block->idstr, new_block->idstr)) {
2101 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
2102 new_block->idstr);
2103 abort();
2106 rcu_read_unlock();
2109 /* Called with iothread lock held. */
2110 void qemu_ram_unset_idstr(RAMBlock *block)
2112 /* FIXME: arch_init.c assumes that this is not called throughout
2113 * migration. Ignore the problem since hot-unplug during migration
2114 * does not work anyway.
2116 if (block) {
2117 memset(block->idstr, 0, sizeof(block->idstr));
2121 size_t qemu_ram_pagesize(RAMBlock *rb)
2123 return rb->page_size;
2126 /* Returns the largest size of page in use */
2127 size_t qemu_ram_pagesize_largest(void)
2129 RAMBlock *block;
2130 size_t largest = 0;
2132 RAMBLOCK_FOREACH(block) {
2133 largest = MAX(largest, qemu_ram_pagesize(block));
2136 return largest;
2139 static int memory_try_enable_merging(void *addr, size_t len)
2141 if (!machine_mem_merge(current_machine)) {
2142 /* disabled by the user */
2143 return 0;
2146 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
2149 /* Only legal before guest might have detected the memory size: e.g. on
2150 * incoming migration, or right after reset.
2152 * As memory core doesn't know how is memory accessed, it is up to
2153 * resize callback to update device state and/or add assertions to detect
2154 * misuse, if necessary.
2156 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
2158 assert(block);
2160 newsize = HOST_PAGE_ALIGN(newsize);
2162 if (block->used_length == newsize) {
2163 return 0;
2166 if (!(block->flags & RAM_RESIZEABLE)) {
2167 error_setg_errno(errp, EINVAL,
2168 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2169 " in != 0x" RAM_ADDR_FMT, block->idstr,
2170 newsize, block->used_length);
2171 return -EINVAL;
2174 if (block->max_length < newsize) {
2175 error_setg_errno(errp, EINVAL,
2176 "Length too large: %s: 0x" RAM_ADDR_FMT
2177 " > 0x" RAM_ADDR_FMT, block->idstr,
2178 newsize, block->max_length);
2179 return -EINVAL;
2182 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
2183 block->used_length = newsize;
2184 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
2185 DIRTY_CLIENTS_ALL);
2186 memory_region_set_size(block->mr, newsize);
2187 if (block->resized) {
2188 block->resized(block->idstr, newsize, block->host);
2190 return 0;
2193 /* Called with ram_list.mutex held */
2194 static void dirty_memory_extend(ram_addr_t old_ram_size,
2195 ram_addr_t new_ram_size)
2197 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
2198 DIRTY_MEMORY_BLOCK_SIZE);
2199 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
2200 DIRTY_MEMORY_BLOCK_SIZE);
2201 int i;
2203 /* Only need to extend if block count increased */
2204 if (new_num_blocks <= old_num_blocks) {
2205 return;
2208 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
2209 DirtyMemoryBlocks *old_blocks;
2210 DirtyMemoryBlocks *new_blocks;
2211 int j;
2213 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
2214 new_blocks = g_malloc(sizeof(*new_blocks) +
2215 sizeof(new_blocks->blocks[0]) * new_num_blocks);
2217 if (old_num_blocks) {
2218 memcpy(new_blocks->blocks, old_blocks->blocks,
2219 old_num_blocks * sizeof(old_blocks->blocks[0]));
2222 for (j = old_num_blocks; j < new_num_blocks; j++) {
2223 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
2226 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
2228 if (old_blocks) {
2229 g_free_rcu(old_blocks, rcu);
2234 static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared)
2236 RAMBlock *block;
2237 RAMBlock *last_block = NULL;
2238 ram_addr_t old_ram_size, new_ram_size;
2239 Error *err = NULL;
2241 old_ram_size = last_ram_page();
2243 qemu_mutex_lock_ramlist();
2244 new_block->offset = find_ram_offset(new_block->max_length);
2246 if (!new_block->host) {
2247 if (xen_enabled()) {
2248 xen_ram_alloc(new_block->offset, new_block->max_length,
2249 new_block->mr, &err);
2250 if (err) {
2251 error_propagate(errp, err);
2252 qemu_mutex_unlock_ramlist();
2253 return;
2255 } else {
2256 new_block->host = phys_mem_alloc(new_block->max_length,
2257 &new_block->mr->align, shared);
2258 if (!new_block->host) {
2259 error_setg_errno(errp, errno,
2260 "cannot set up guest memory '%s'",
2261 memory_region_name(new_block->mr));
2262 qemu_mutex_unlock_ramlist();
2263 return;
2265 memory_try_enable_merging(new_block->host, new_block->max_length);
2269 new_ram_size = MAX(old_ram_size,
2270 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
2271 if (new_ram_size > old_ram_size) {
2272 dirty_memory_extend(old_ram_size, new_ram_size);
2274 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2275 * QLIST (which has an RCU-friendly variant) does not have insertion at
2276 * tail, so save the last element in last_block.
2278 RAMBLOCK_FOREACH(block) {
2279 last_block = block;
2280 if (block->max_length < new_block->max_length) {
2281 break;
2284 if (block) {
2285 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
2286 } else if (last_block) {
2287 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
2288 } else { /* list is empty */
2289 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
2291 ram_list.mru_block = NULL;
2293 /* Write list before version */
2294 smp_wmb();
2295 ram_list.version++;
2296 qemu_mutex_unlock_ramlist();
2298 cpu_physical_memory_set_dirty_range(new_block->offset,
2299 new_block->used_length,
2300 DIRTY_CLIENTS_ALL);
2302 if (new_block->host) {
2303 qemu_ram_setup_dump(new_block->host, new_block->max_length);
2304 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
2305 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2306 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
2307 ram_block_notify_add(new_block->host, new_block->max_length);
2311 #ifdef CONFIG_POSIX
2312 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
2313 uint32_t ram_flags, int fd,
2314 Error **errp)
2316 RAMBlock *new_block;
2317 Error *local_err = NULL;
2318 int64_t file_size;
2320 /* Just support these ram flags by now. */
2321 assert((ram_flags & ~(RAM_SHARED | RAM_PMEM)) == 0);
2323 if (xen_enabled()) {
2324 error_setg(errp, "-mem-path not supported with Xen");
2325 return NULL;
2328 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2329 error_setg(errp,
2330 "host lacks kvm mmu notifiers, -mem-path unsupported");
2331 return NULL;
2334 if (phys_mem_alloc != qemu_anon_ram_alloc) {
2336 * file_ram_alloc() needs to allocate just like
2337 * phys_mem_alloc, but we haven't bothered to provide
2338 * a hook there.
2340 error_setg(errp,
2341 "-mem-path not supported with this accelerator");
2342 return NULL;
2345 size = HOST_PAGE_ALIGN(size);
2346 file_size = get_file_size(fd);
2347 if (file_size > 0 && file_size < size) {
2348 error_setg(errp, "backing store %s size 0x%" PRIx64
2349 " does not match 'size' option 0x" RAM_ADDR_FMT,
2350 mem_path, file_size, size);
2351 return NULL;
2354 new_block = g_malloc0(sizeof(*new_block));
2355 new_block->mr = mr;
2356 new_block->used_length = size;
2357 new_block->max_length = size;
2358 new_block->flags = ram_flags;
2359 new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp);
2360 if (!new_block->host) {
2361 g_free(new_block);
2362 return NULL;
2365 ram_block_add(new_block, &local_err, ram_flags & RAM_SHARED);
2366 if (local_err) {
2367 g_free(new_block);
2368 error_propagate(errp, local_err);
2369 return NULL;
2371 return new_block;
2376 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
2377 uint32_t ram_flags, const char *mem_path,
2378 Error **errp)
2380 int fd;
2381 bool created;
2382 RAMBlock *block;
2384 fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp);
2385 if (fd < 0) {
2386 return NULL;
2389 block = qemu_ram_alloc_from_fd(size, mr, ram_flags, fd, errp);
2390 if (!block) {
2391 if (created) {
2392 unlink(mem_path);
2394 close(fd);
2395 return NULL;
2398 return block;
2400 #endif
2402 static
2403 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2404 void (*resized)(const char*,
2405 uint64_t length,
2406 void *host),
2407 void *host, bool resizeable, bool share,
2408 MemoryRegion *mr, Error **errp)
2410 RAMBlock *new_block;
2411 Error *local_err = NULL;
2413 size = HOST_PAGE_ALIGN(size);
2414 max_size = HOST_PAGE_ALIGN(max_size);
2415 new_block = g_malloc0(sizeof(*new_block));
2416 new_block->mr = mr;
2417 new_block->resized = resized;
2418 new_block->used_length = size;
2419 new_block->max_length = max_size;
2420 assert(max_size >= size);
2421 new_block->fd = -1;
2422 new_block->page_size = getpagesize();
2423 new_block->host = host;
2424 if (host) {
2425 new_block->flags |= RAM_PREALLOC;
2427 if (resizeable) {
2428 new_block->flags |= RAM_RESIZEABLE;
2430 ram_block_add(new_block, &local_err, share);
2431 if (local_err) {
2432 g_free(new_block);
2433 error_propagate(errp, local_err);
2434 return NULL;
2436 return new_block;
2439 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2440 MemoryRegion *mr, Error **errp)
2442 return qemu_ram_alloc_internal(size, size, NULL, host, false,
2443 false, mr, errp);
2446 RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share,
2447 MemoryRegion *mr, Error **errp)
2449 return qemu_ram_alloc_internal(size, size, NULL, NULL, false,
2450 share, mr, errp);
2453 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2454 void (*resized)(const char*,
2455 uint64_t length,
2456 void *host),
2457 MemoryRegion *mr, Error **errp)
2459 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true,
2460 false, mr, errp);
2463 static void reclaim_ramblock(RAMBlock *block)
2465 if (block->flags & RAM_PREALLOC) {
2467 } else if (xen_enabled()) {
2468 xen_invalidate_map_cache_entry(block->host);
2469 #ifndef _WIN32
2470 } else if (block->fd >= 0) {
2471 qemu_ram_munmap(block->fd, block->host, block->max_length);
2472 close(block->fd);
2473 #endif
2474 } else {
2475 qemu_anon_ram_free(block->host, block->max_length);
2477 g_free(block);
2480 void qemu_ram_free(RAMBlock *block)
2482 if (!block) {
2483 return;
2486 if (block->host) {
2487 ram_block_notify_remove(block->host, block->max_length);
2490 qemu_mutex_lock_ramlist();
2491 QLIST_REMOVE_RCU(block, next);
2492 ram_list.mru_block = NULL;
2493 /* Write list before version */
2494 smp_wmb();
2495 ram_list.version++;
2496 call_rcu(block, reclaim_ramblock, rcu);
2497 qemu_mutex_unlock_ramlist();
2500 #ifndef _WIN32
2501 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2503 RAMBlock *block;
2504 ram_addr_t offset;
2505 int flags;
2506 void *area, *vaddr;
2508 RAMBLOCK_FOREACH(block) {
2509 offset = addr - block->offset;
2510 if (offset < block->max_length) {
2511 vaddr = ramblock_ptr(block, offset);
2512 if (block->flags & RAM_PREALLOC) {
2514 } else if (xen_enabled()) {
2515 abort();
2516 } else {
2517 flags = MAP_FIXED;
2518 if (block->fd >= 0) {
2519 flags |= (block->flags & RAM_SHARED ?
2520 MAP_SHARED : MAP_PRIVATE);
2521 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2522 flags, block->fd, offset);
2523 } else {
2525 * Remap needs to match alloc. Accelerators that
2526 * set phys_mem_alloc never remap. If they did,
2527 * we'd need a remap hook here.
2529 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2531 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2532 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2533 flags, -1, 0);
2535 if (area != vaddr) {
2536 error_report("Could not remap addr: "
2537 RAM_ADDR_FMT "@" RAM_ADDR_FMT "",
2538 length, addr);
2539 exit(1);
2541 memory_try_enable_merging(vaddr, length);
2542 qemu_ram_setup_dump(vaddr, length);
2547 #endif /* !_WIN32 */
2549 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2550 * This should not be used for general purpose DMA. Use address_space_map
2551 * or address_space_rw instead. For local memory (e.g. video ram) that the
2552 * device owns, use memory_region_get_ram_ptr.
2554 * Called within RCU critical section.
2556 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2558 RAMBlock *block = ram_block;
2560 if (block == NULL) {
2561 block = qemu_get_ram_block(addr);
2562 addr -= block->offset;
2565 if (xen_enabled() && block->host == NULL) {
2566 /* We need to check if the requested address is in the RAM
2567 * because we don't want to map the entire memory in QEMU.
2568 * In that case just map until the end of the page.
2570 if (block->offset == 0) {
2571 return xen_map_cache(addr, 0, 0, false);
2574 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2576 return ramblock_ptr(block, addr);
2579 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2580 * but takes a size argument.
2582 * Called within RCU critical section.
2584 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2585 hwaddr *size, bool lock)
2587 RAMBlock *block = ram_block;
2588 if (*size == 0) {
2589 return NULL;
2592 if (block == NULL) {
2593 block = qemu_get_ram_block(addr);
2594 addr -= block->offset;
2596 *size = MIN(*size, block->max_length - addr);
2598 if (xen_enabled() && block->host == NULL) {
2599 /* We need to check if the requested address is in the RAM
2600 * because we don't want to map the entire memory in QEMU.
2601 * In that case just map the requested area.
2603 if (block->offset == 0) {
2604 return xen_map_cache(addr, *size, lock, lock);
2607 block->host = xen_map_cache(block->offset, block->max_length, 1, lock);
2610 return ramblock_ptr(block, addr);
2613 /* Return the offset of a hostpointer within a ramblock */
2614 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host)
2616 ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host;
2617 assert((uintptr_t)host >= (uintptr_t)rb->host);
2618 assert(res < rb->max_length);
2620 return res;
2624 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2625 * in that RAMBlock.
2627 * ptr: Host pointer to look up
2628 * round_offset: If true round the result offset down to a page boundary
2629 * *ram_addr: set to result ram_addr
2630 * *offset: set to result offset within the RAMBlock
2632 * Returns: RAMBlock (or NULL if not found)
2634 * By the time this function returns, the returned pointer is not protected
2635 * by RCU anymore. If the caller is not within an RCU critical section and
2636 * does not hold the iothread lock, it must have other means of protecting the
2637 * pointer, such as a reference to the region that includes the incoming
2638 * ram_addr_t.
2640 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2641 ram_addr_t *offset)
2643 RAMBlock *block;
2644 uint8_t *host = ptr;
2646 if (xen_enabled()) {
2647 ram_addr_t ram_addr;
2648 rcu_read_lock();
2649 ram_addr = xen_ram_addr_from_mapcache(ptr);
2650 block = qemu_get_ram_block(ram_addr);
2651 if (block) {
2652 *offset = ram_addr - block->offset;
2654 rcu_read_unlock();
2655 return block;
2658 rcu_read_lock();
2659 block = atomic_rcu_read(&ram_list.mru_block);
2660 if (block && block->host && host - block->host < block->max_length) {
2661 goto found;
2664 RAMBLOCK_FOREACH(block) {
2665 /* This case append when the block is not mapped. */
2666 if (block->host == NULL) {
2667 continue;
2669 if (host - block->host < block->max_length) {
2670 goto found;
2674 rcu_read_unlock();
2675 return NULL;
2677 found:
2678 *offset = (host - block->host);
2679 if (round_offset) {
2680 *offset &= TARGET_PAGE_MASK;
2682 rcu_read_unlock();
2683 return block;
2687 * Finds the named RAMBlock
2689 * name: The name of RAMBlock to find
2691 * Returns: RAMBlock (or NULL if not found)
2693 RAMBlock *qemu_ram_block_by_name(const char *name)
2695 RAMBlock *block;
2697 RAMBLOCK_FOREACH(block) {
2698 if (!strcmp(name, block->idstr)) {
2699 return block;
2703 return NULL;
2706 /* Some of the softmmu routines need to translate from a host pointer
2707 (typically a TLB entry) back to a ram offset. */
2708 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2710 RAMBlock *block;
2711 ram_addr_t offset;
2713 block = qemu_ram_block_from_host(ptr, false, &offset);
2714 if (!block) {
2715 return RAM_ADDR_INVALID;
2718 return block->offset + offset;
2721 /* Called within RCU critical section. */
2722 void memory_notdirty_write_prepare(NotDirtyInfo *ndi,
2723 CPUState *cpu,
2724 vaddr mem_vaddr,
2725 ram_addr_t ram_addr,
2726 unsigned size)
2728 ndi->cpu = cpu;
2729 ndi->ram_addr = ram_addr;
2730 ndi->mem_vaddr = mem_vaddr;
2731 ndi->size = size;
2732 ndi->pages = NULL;
2734 assert(tcg_enabled());
2735 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2736 ndi->pages = page_collection_lock(ram_addr, ram_addr + size);
2737 tb_invalidate_phys_page_fast(ndi->pages, ram_addr, size);
2741 /* Called within RCU critical section. */
2742 void memory_notdirty_write_complete(NotDirtyInfo *ndi)
2744 if (ndi->pages) {
2745 assert(tcg_enabled());
2746 page_collection_unlock(ndi->pages);
2747 ndi->pages = NULL;
2750 /* Set both VGA and migration bits for simplicity and to remove
2751 * the notdirty callback faster.
2753 cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size,
2754 DIRTY_CLIENTS_NOCODE);
2755 /* we remove the notdirty callback only if the code has been
2756 flushed */
2757 if (!cpu_physical_memory_is_clean(ndi->ram_addr)) {
2758 tlb_set_dirty(ndi->cpu, ndi->mem_vaddr);
2762 /* Called within RCU critical section. */
2763 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2764 uint64_t val, unsigned size)
2766 NotDirtyInfo ndi;
2768 memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr,
2769 ram_addr, size);
2771 stn_p(qemu_map_ram_ptr(NULL, ram_addr), size, val);
2772 memory_notdirty_write_complete(&ndi);
2775 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2776 unsigned size, bool is_write,
2777 MemTxAttrs attrs)
2779 return is_write;
2782 static const MemoryRegionOps notdirty_mem_ops = {
2783 .write = notdirty_mem_write,
2784 .valid.accepts = notdirty_mem_accepts,
2785 .endianness = DEVICE_NATIVE_ENDIAN,
2786 .valid = {
2787 .min_access_size = 1,
2788 .max_access_size = 8,
2789 .unaligned = false,
2791 .impl = {
2792 .min_access_size = 1,
2793 .max_access_size = 8,
2794 .unaligned = false,
2798 /* Generate a debug exception if a watchpoint has been hit. */
2799 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2801 CPUState *cpu = current_cpu;
2802 CPUClass *cc = CPU_GET_CLASS(cpu);
2803 target_ulong vaddr;
2804 CPUWatchpoint *wp;
2806 assert(tcg_enabled());
2807 if (cpu->watchpoint_hit) {
2808 /* We re-entered the check after replacing the TB. Now raise
2809 * the debug interrupt so that is will trigger after the
2810 * current instruction. */
2811 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2812 return;
2814 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2815 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2816 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2817 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2818 && (wp->flags & flags)) {
2819 if (flags == BP_MEM_READ) {
2820 wp->flags |= BP_WATCHPOINT_HIT_READ;
2821 } else {
2822 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2824 wp->hitaddr = vaddr;
2825 wp->hitattrs = attrs;
2826 if (!cpu->watchpoint_hit) {
2827 if (wp->flags & BP_CPU &&
2828 !cc->debug_check_watchpoint(cpu, wp)) {
2829 wp->flags &= ~BP_WATCHPOINT_HIT;
2830 continue;
2832 cpu->watchpoint_hit = wp;
2834 mmap_lock();
2835 tb_check_watchpoint(cpu);
2836 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2837 cpu->exception_index = EXCP_DEBUG;
2838 mmap_unlock();
2839 cpu_loop_exit(cpu);
2840 } else {
2841 /* Force execution of one insn next time. */
2842 cpu->cflags_next_tb = 1 | curr_cflags();
2843 mmap_unlock();
2844 cpu_loop_exit_noexc(cpu);
2847 } else {
2848 wp->flags &= ~BP_WATCHPOINT_HIT;
2853 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2854 so these check for a hit then pass through to the normal out-of-line
2855 phys routines. */
2856 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2857 unsigned size, MemTxAttrs attrs)
2859 MemTxResult res;
2860 uint64_t data;
2861 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2862 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2864 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2865 switch (size) {
2866 case 1:
2867 data = address_space_ldub(as, addr, attrs, &res);
2868 break;
2869 case 2:
2870 data = address_space_lduw(as, addr, attrs, &res);
2871 break;
2872 case 4:
2873 data = address_space_ldl(as, addr, attrs, &res);
2874 break;
2875 case 8:
2876 data = address_space_ldq(as, addr, attrs, &res);
2877 break;
2878 default: abort();
2880 *pdata = data;
2881 return res;
2884 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2885 uint64_t val, unsigned size,
2886 MemTxAttrs attrs)
2888 MemTxResult res;
2889 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2890 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2892 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2893 switch (size) {
2894 case 1:
2895 address_space_stb(as, addr, val, attrs, &res);
2896 break;
2897 case 2:
2898 address_space_stw(as, addr, val, attrs, &res);
2899 break;
2900 case 4:
2901 address_space_stl(as, addr, val, attrs, &res);
2902 break;
2903 case 8:
2904 address_space_stq(as, addr, val, attrs, &res);
2905 break;
2906 default: abort();
2908 return res;
2911 static const MemoryRegionOps watch_mem_ops = {
2912 .read_with_attrs = watch_mem_read,
2913 .write_with_attrs = watch_mem_write,
2914 .endianness = DEVICE_NATIVE_ENDIAN,
2915 .valid = {
2916 .min_access_size = 1,
2917 .max_access_size = 8,
2918 .unaligned = false,
2920 .impl = {
2921 .min_access_size = 1,
2922 .max_access_size = 8,
2923 .unaligned = false,
2927 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
2928 MemTxAttrs attrs, uint8_t *buf, hwaddr len);
2929 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
2930 const uint8_t *buf, hwaddr len);
2931 static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,
2932 bool is_write, MemTxAttrs attrs);
2934 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2935 unsigned len, MemTxAttrs attrs)
2937 subpage_t *subpage = opaque;
2938 uint8_t buf[8];
2939 MemTxResult res;
2941 #if defined(DEBUG_SUBPAGE)
2942 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2943 subpage, len, addr);
2944 #endif
2945 res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
2946 if (res) {
2947 return res;
2949 *data = ldn_p(buf, len);
2950 return MEMTX_OK;
2953 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2954 uint64_t value, unsigned len, MemTxAttrs attrs)
2956 subpage_t *subpage = opaque;
2957 uint8_t buf[8];
2959 #if defined(DEBUG_SUBPAGE)
2960 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2961 " value %"PRIx64"\n",
2962 __func__, subpage, len, addr, value);
2963 #endif
2964 stn_p(buf, len, value);
2965 return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);
2968 static bool subpage_accepts(void *opaque, hwaddr addr,
2969 unsigned len, bool is_write,
2970 MemTxAttrs attrs)
2972 subpage_t *subpage = opaque;
2973 #if defined(DEBUG_SUBPAGE)
2974 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2975 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2976 #endif
2978 return flatview_access_valid(subpage->fv, addr + subpage->base,
2979 len, is_write, attrs);
2982 static const MemoryRegionOps subpage_ops = {
2983 .read_with_attrs = subpage_read,
2984 .write_with_attrs = subpage_write,
2985 .impl.min_access_size = 1,
2986 .impl.max_access_size = 8,
2987 .valid.min_access_size = 1,
2988 .valid.max_access_size = 8,
2989 .valid.accepts = subpage_accepts,
2990 .endianness = DEVICE_NATIVE_ENDIAN,
2993 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2994 uint16_t section)
2996 int idx, eidx;
2998 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2999 return -1;
3000 idx = SUBPAGE_IDX(start);
3001 eidx = SUBPAGE_IDX(end);
3002 #if defined(DEBUG_SUBPAGE)
3003 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
3004 __func__, mmio, start, end, idx, eidx, section);
3005 #endif
3006 for (; idx <= eidx; idx++) {
3007 mmio->sub_section[idx] = section;
3010 return 0;
3013 static subpage_t *subpage_init(FlatView *fv, hwaddr base)
3015 subpage_t *mmio;
3017 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
3018 mmio->fv = fv;
3019 mmio->base = base;
3020 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
3021 NULL, TARGET_PAGE_SIZE);
3022 mmio->iomem.subpage = true;
3023 #if defined(DEBUG_SUBPAGE)
3024 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
3025 mmio, base, TARGET_PAGE_SIZE);
3026 #endif
3027 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
3029 return mmio;
3032 static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr)
3034 assert(fv);
3035 MemoryRegionSection section = {
3036 .fv = fv,
3037 .mr = mr,
3038 .offset_within_address_space = 0,
3039 .offset_within_region = 0,
3040 .size = int128_2_64(),
3043 return phys_section_add(map, &section);
3046 static void readonly_mem_write(void *opaque, hwaddr addr,
3047 uint64_t val, unsigned size)
3049 /* Ignore any write to ROM. */
3052 static bool readonly_mem_accepts(void *opaque, hwaddr addr,
3053 unsigned size, bool is_write,
3054 MemTxAttrs attrs)
3056 return is_write;
3059 /* This will only be used for writes, because reads are special cased
3060 * to directly access the underlying host ram.
3062 static const MemoryRegionOps readonly_mem_ops = {
3063 .write = readonly_mem_write,
3064 .valid.accepts = readonly_mem_accepts,
3065 .endianness = DEVICE_NATIVE_ENDIAN,
3066 .valid = {
3067 .min_access_size = 1,
3068 .max_access_size = 8,
3069 .unaligned = false,
3071 .impl = {
3072 .min_access_size = 1,
3073 .max_access_size = 8,
3074 .unaligned = false,
3078 MemoryRegionSection *iotlb_to_section(CPUState *cpu,
3079 hwaddr index, MemTxAttrs attrs)
3081 int asidx = cpu_asidx_from_attrs(cpu, attrs);
3082 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
3083 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
3084 MemoryRegionSection *sections = d->map.sections;
3086 return &sections[index & ~TARGET_PAGE_MASK];
3089 static void io_mem_init(void)
3091 memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops,
3092 NULL, NULL, UINT64_MAX);
3093 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
3094 NULL, UINT64_MAX);
3096 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3097 * which can be called without the iothread mutex.
3099 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
3100 NULL, UINT64_MAX);
3101 memory_region_clear_global_locking(&io_mem_notdirty);
3103 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
3104 NULL, UINT64_MAX);
3107 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv)
3109 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
3110 uint16_t n;
3112 n = dummy_section(&d->map, fv, &io_mem_unassigned);
3113 assert(n == PHYS_SECTION_UNASSIGNED);
3114 n = dummy_section(&d->map, fv, &io_mem_notdirty);
3115 assert(n == PHYS_SECTION_NOTDIRTY);
3116 n = dummy_section(&d->map, fv, &io_mem_rom);
3117 assert(n == PHYS_SECTION_ROM);
3118 n = dummy_section(&d->map, fv, &io_mem_watch);
3119 assert(n == PHYS_SECTION_WATCH);
3121 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
3123 return d;
3126 void address_space_dispatch_free(AddressSpaceDispatch *d)
3128 phys_sections_free(&d->map);
3129 g_free(d);
3132 static void tcg_commit(MemoryListener *listener)
3134 CPUAddressSpace *cpuas;
3135 AddressSpaceDispatch *d;
3137 assert(tcg_enabled());
3138 /* since each CPU stores ram addresses in its TLB cache, we must
3139 reset the modified entries */
3140 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
3141 cpu_reloading_memory_map();
3142 /* The CPU and TLB are protected by the iothread lock.
3143 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3144 * may have split the RCU critical section.
3146 d = address_space_to_dispatch(cpuas->as);
3147 atomic_rcu_set(&cpuas->memory_dispatch, d);
3148 tlb_flush(cpuas->cpu);
3151 static void memory_map_init(void)
3153 system_memory = g_malloc(sizeof(*system_memory));
3155 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
3156 address_space_init(&address_space_memory, system_memory, "memory");
3158 system_io = g_malloc(sizeof(*system_io));
3159 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
3160 65536);
3161 address_space_init(&address_space_io, system_io, "I/O");
3164 MemoryRegion *get_system_memory(void)
3166 return system_memory;
3169 MemoryRegion *get_system_io(void)
3171 return system_io;
3174 #endif /* !defined(CONFIG_USER_ONLY) */
3176 /* physical memory access (slow version, mainly for debug) */
3177 #if defined(CONFIG_USER_ONLY)
3178 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3179 uint8_t *buf, target_ulong len, int is_write)
3181 int flags;
3182 target_ulong l, page;
3183 void * p;
3185 while (len > 0) {
3186 page = addr & TARGET_PAGE_MASK;
3187 l = (page + TARGET_PAGE_SIZE) - addr;
3188 if (l > len)
3189 l = len;
3190 flags = page_get_flags(page);
3191 if (!(flags & PAGE_VALID))
3192 return -1;
3193 if (is_write) {
3194 if (!(flags & PAGE_WRITE))
3195 return -1;
3196 /* XXX: this code should not depend on lock_user */
3197 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
3198 return -1;
3199 memcpy(p, buf, l);
3200 unlock_user(p, addr, l);
3201 } else {
3202 if (!(flags & PAGE_READ))
3203 return -1;
3204 /* XXX: this code should not depend on lock_user */
3205 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
3206 return -1;
3207 memcpy(buf, p, l);
3208 unlock_user(p, addr, 0);
3210 len -= l;
3211 buf += l;
3212 addr += l;
3214 return 0;
3217 #else
3219 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
3220 hwaddr length)
3222 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
3223 addr += memory_region_get_ram_addr(mr);
3225 /* No early return if dirty_log_mask is or becomes 0, because
3226 * cpu_physical_memory_set_dirty_range will still call
3227 * xen_modified_memory.
3229 if (dirty_log_mask) {
3230 dirty_log_mask =
3231 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
3233 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
3234 assert(tcg_enabled());
3235 tb_invalidate_phys_range(addr, addr + length);
3236 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
3238 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
3241 void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr size)
3244 * In principle this function would work on other memory region types too,
3245 * but the ROM device use case is the only one where this operation is
3246 * necessary. Other memory regions should use the
3247 * address_space_read/write() APIs.
3249 assert(memory_region_is_romd(mr));
3251 invalidate_and_set_dirty(mr, addr, size);
3254 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
3256 unsigned access_size_max = mr->ops->valid.max_access_size;
3258 /* Regions are assumed to support 1-4 byte accesses unless
3259 otherwise specified. */
3260 if (access_size_max == 0) {
3261 access_size_max = 4;
3264 /* Bound the maximum access by the alignment of the address. */
3265 if (!mr->ops->impl.unaligned) {
3266 unsigned align_size_max = addr & -addr;
3267 if (align_size_max != 0 && align_size_max < access_size_max) {
3268 access_size_max = align_size_max;
3272 /* Don't attempt accesses larger than the maximum. */
3273 if (l > access_size_max) {
3274 l = access_size_max;
3276 l = pow2floor(l);
3278 return l;
3281 static bool prepare_mmio_access(MemoryRegion *mr)
3283 bool unlocked = !qemu_mutex_iothread_locked();
3284 bool release_lock = false;
3286 if (unlocked && mr->global_locking) {
3287 qemu_mutex_lock_iothread();
3288 unlocked = false;
3289 release_lock = true;
3291 if (mr->flush_coalesced_mmio) {
3292 if (unlocked) {
3293 qemu_mutex_lock_iothread();
3295 qemu_flush_coalesced_mmio_buffer();
3296 if (unlocked) {
3297 qemu_mutex_unlock_iothread();
3301 return release_lock;
3304 /* Called within RCU critical section. */
3305 static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
3306 MemTxAttrs attrs,
3307 const uint8_t *buf,
3308 hwaddr len, hwaddr addr1,
3309 hwaddr l, MemoryRegion *mr)
3311 uint8_t *ptr;
3312 uint64_t val;
3313 MemTxResult result = MEMTX_OK;
3314 bool release_lock = false;
3316 for (;;) {
3317 if (!memory_access_is_direct(mr, true)) {
3318 release_lock |= prepare_mmio_access(mr);
3319 l = memory_access_size(mr, l, addr1);
3320 /* XXX: could force current_cpu to NULL to avoid
3321 potential bugs */
3322 val = ldn_p(buf, l);
3323 result |= memory_region_dispatch_write(mr, addr1, val, l, attrs);
3324 } else {
3325 /* RAM case */
3326 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3327 memcpy(ptr, buf, l);
3328 invalidate_and_set_dirty(mr, addr1, l);
3331 if (release_lock) {
3332 qemu_mutex_unlock_iothread();
3333 release_lock = false;
3336 len -= l;
3337 buf += l;
3338 addr += l;
3340 if (!len) {
3341 break;
3344 l = len;
3345 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3348 return result;
3351 /* Called from RCU critical section. */
3352 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
3353 const uint8_t *buf, hwaddr len)
3355 hwaddr l;
3356 hwaddr addr1;
3357 MemoryRegion *mr;
3358 MemTxResult result = MEMTX_OK;
3360 l = len;
3361 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3362 result = flatview_write_continue(fv, addr, attrs, buf, len,
3363 addr1, l, mr);
3365 return result;
3368 /* Called within RCU critical section. */
3369 MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
3370 MemTxAttrs attrs, uint8_t *buf,
3371 hwaddr len, hwaddr addr1, hwaddr l,
3372 MemoryRegion *mr)
3374 uint8_t *ptr;
3375 uint64_t val;
3376 MemTxResult result = MEMTX_OK;
3377 bool release_lock = false;
3379 for (;;) {
3380 if (!memory_access_is_direct(mr, false)) {
3381 /* I/O case */
3382 release_lock |= prepare_mmio_access(mr);
3383 l = memory_access_size(mr, l, addr1);
3384 result |= memory_region_dispatch_read(mr, addr1, &val, l, attrs);
3385 stn_p(buf, l, val);
3386 } else {
3387 /* RAM case */
3388 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3389 memcpy(buf, ptr, l);
3392 if (release_lock) {
3393 qemu_mutex_unlock_iothread();
3394 release_lock = false;
3397 len -= l;
3398 buf += l;
3399 addr += l;
3401 if (!len) {
3402 break;
3405 l = len;
3406 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3409 return result;
3412 /* Called from RCU critical section. */
3413 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
3414 MemTxAttrs attrs, uint8_t *buf, hwaddr len)
3416 hwaddr l;
3417 hwaddr addr1;
3418 MemoryRegion *mr;
3420 l = len;
3421 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3422 return flatview_read_continue(fv, addr, attrs, buf, len,
3423 addr1, l, mr);
3426 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3427 MemTxAttrs attrs, uint8_t *buf, hwaddr len)
3429 MemTxResult result = MEMTX_OK;
3430 FlatView *fv;
3432 if (len > 0) {
3433 rcu_read_lock();
3434 fv = address_space_to_flatview(as);
3435 result = flatview_read(fv, addr, attrs, buf, len);
3436 rcu_read_unlock();
3439 return result;
3442 MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
3443 MemTxAttrs attrs,
3444 const uint8_t *buf, hwaddr len)
3446 MemTxResult result = MEMTX_OK;
3447 FlatView *fv;
3449 if (len > 0) {
3450 rcu_read_lock();
3451 fv = address_space_to_flatview(as);
3452 result = flatview_write(fv, addr, attrs, buf, len);
3453 rcu_read_unlock();
3456 return result;
3459 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3460 uint8_t *buf, hwaddr len, bool is_write)
3462 if (is_write) {
3463 return address_space_write(as, addr, attrs, buf, len);
3464 } else {
3465 return address_space_read_full(as, addr, attrs, buf, len);
3469 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
3470 hwaddr len, int is_write)
3472 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3473 buf, len, is_write);
3476 enum write_rom_type {
3477 WRITE_DATA,
3478 FLUSH_CACHE,
3481 static inline MemTxResult address_space_write_rom_internal(AddressSpace *as,
3482 hwaddr addr,
3483 MemTxAttrs attrs,
3484 const uint8_t *buf,
3485 hwaddr len,
3486 enum write_rom_type type)
3488 hwaddr l;
3489 uint8_t *ptr;
3490 hwaddr addr1;
3491 MemoryRegion *mr;
3493 rcu_read_lock();
3494 while (len > 0) {
3495 l = len;
3496 mr = address_space_translate(as, addr, &addr1, &l, true, attrs);
3498 if (!(memory_region_is_ram(mr) ||
3499 memory_region_is_romd(mr))) {
3500 l = memory_access_size(mr, l, addr1);
3501 } else {
3502 /* ROM/RAM case */
3503 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3504 switch (type) {
3505 case WRITE_DATA:
3506 memcpy(ptr, buf, l);
3507 invalidate_and_set_dirty(mr, addr1, l);
3508 break;
3509 case FLUSH_CACHE:
3510 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
3511 break;
3514 len -= l;
3515 buf += l;
3516 addr += l;
3518 rcu_read_unlock();
3519 return MEMTX_OK;
3522 /* used for ROM loading : can write in RAM and ROM */
3523 MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr,
3524 MemTxAttrs attrs,
3525 const uint8_t *buf, hwaddr len)
3527 return address_space_write_rom_internal(as, addr, attrs,
3528 buf, len, WRITE_DATA);
3531 void cpu_flush_icache_range(hwaddr start, hwaddr len)
3534 * This function should do the same thing as an icache flush that was
3535 * triggered from within the guest. For TCG we are always cache coherent,
3536 * so there is no need to flush anything. For KVM / Xen we need to flush
3537 * the host's instruction cache at least.
3539 if (tcg_enabled()) {
3540 return;
3543 address_space_write_rom_internal(&address_space_memory,
3544 start, MEMTXATTRS_UNSPECIFIED,
3545 NULL, len, FLUSH_CACHE);
3548 typedef struct {
3549 MemoryRegion *mr;
3550 void *buffer;
3551 hwaddr addr;
3552 hwaddr len;
3553 bool in_use;
3554 } BounceBuffer;
3556 static BounceBuffer bounce;
3558 typedef struct MapClient {
3559 QEMUBH *bh;
3560 QLIST_ENTRY(MapClient) link;
3561 } MapClient;
3563 QemuMutex map_client_list_lock;
3564 static QLIST_HEAD(, MapClient) map_client_list
3565 = QLIST_HEAD_INITIALIZER(map_client_list);
3567 static void cpu_unregister_map_client_do(MapClient *client)
3569 QLIST_REMOVE(client, link);
3570 g_free(client);
3573 static void cpu_notify_map_clients_locked(void)
3575 MapClient *client;
3577 while (!QLIST_EMPTY(&map_client_list)) {
3578 client = QLIST_FIRST(&map_client_list);
3579 qemu_bh_schedule(client->bh);
3580 cpu_unregister_map_client_do(client);
3584 void cpu_register_map_client(QEMUBH *bh)
3586 MapClient *client = g_malloc(sizeof(*client));
3588 qemu_mutex_lock(&map_client_list_lock);
3589 client->bh = bh;
3590 QLIST_INSERT_HEAD(&map_client_list, client, link);
3591 if (!atomic_read(&bounce.in_use)) {
3592 cpu_notify_map_clients_locked();
3594 qemu_mutex_unlock(&map_client_list_lock);
3597 void cpu_exec_init_all(void)
3599 qemu_mutex_init(&ram_list.mutex);
3600 /* The data structures we set up here depend on knowing the page size,
3601 * so no more changes can be made after this point.
3602 * In an ideal world, nothing we did before we had finished the
3603 * machine setup would care about the target page size, and we could
3604 * do this much later, rather than requiring board models to state
3605 * up front what their requirements are.
3607 finalize_target_page_bits();
3608 io_mem_init();
3609 memory_map_init();
3610 qemu_mutex_init(&map_client_list_lock);
3613 void cpu_unregister_map_client(QEMUBH *bh)
3615 MapClient *client;
3617 qemu_mutex_lock(&map_client_list_lock);
3618 QLIST_FOREACH(client, &map_client_list, link) {
3619 if (client->bh == bh) {
3620 cpu_unregister_map_client_do(client);
3621 break;
3624 qemu_mutex_unlock(&map_client_list_lock);
3627 static void cpu_notify_map_clients(void)
3629 qemu_mutex_lock(&map_client_list_lock);
3630 cpu_notify_map_clients_locked();
3631 qemu_mutex_unlock(&map_client_list_lock);
3634 static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,
3635 bool is_write, MemTxAttrs attrs)
3637 MemoryRegion *mr;
3638 hwaddr l, xlat;
3640 while (len > 0) {
3641 l = len;
3642 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3643 if (!memory_access_is_direct(mr, is_write)) {
3644 l = memory_access_size(mr, l, addr);
3645 if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
3646 return false;
3650 len -= l;
3651 addr += l;
3653 return true;
3656 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
3657 hwaddr len, bool is_write,
3658 MemTxAttrs attrs)
3660 FlatView *fv;
3661 bool result;
3663 rcu_read_lock();
3664 fv = address_space_to_flatview(as);
3665 result = flatview_access_valid(fv, addr, len, is_write, attrs);
3666 rcu_read_unlock();
3667 return result;
3670 static hwaddr
3671 flatview_extend_translation(FlatView *fv, hwaddr addr,
3672 hwaddr target_len,
3673 MemoryRegion *mr, hwaddr base, hwaddr len,
3674 bool is_write, MemTxAttrs attrs)
3676 hwaddr done = 0;
3677 hwaddr xlat;
3678 MemoryRegion *this_mr;
3680 for (;;) {
3681 target_len -= len;
3682 addr += len;
3683 done += len;
3684 if (target_len == 0) {
3685 return done;
3688 len = target_len;
3689 this_mr = flatview_translate(fv, addr, &xlat,
3690 &len, is_write, attrs);
3691 if (this_mr != mr || xlat != base + done) {
3692 return done;
3697 /* Map a physical memory region into a host virtual address.
3698 * May map a subset of the requested range, given by and returned in *plen.
3699 * May return NULL if resources needed to perform the mapping are exhausted.
3700 * Use only for reads OR writes - not for read-modify-write operations.
3701 * Use cpu_register_map_client() to know when retrying the map operation is
3702 * likely to succeed.
3704 void *address_space_map(AddressSpace *as,
3705 hwaddr addr,
3706 hwaddr *plen,
3707 bool is_write,
3708 MemTxAttrs attrs)
3710 hwaddr len = *plen;
3711 hwaddr l, xlat;
3712 MemoryRegion *mr;
3713 void *ptr;
3714 FlatView *fv;
3716 if (len == 0) {
3717 return NULL;
3720 l = len;
3721 rcu_read_lock();
3722 fv = address_space_to_flatview(as);
3723 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3725 if (!memory_access_is_direct(mr, is_write)) {
3726 if (atomic_xchg(&bounce.in_use, true)) {
3727 rcu_read_unlock();
3728 return NULL;
3730 /* Avoid unbounded allocations */
3731 l = MIN(l, TARGET_PAGE_SIZE);
3732 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3733 bounce.addr = addr;
3734 bounce.len = l;
3736 memory_region_ref(mr);
3737 bounce.mr = mr;
3738 if (!is_write) {
3739 flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED,
3740 bounce.buffer, l);
3743 rcu_read_unlock();
3744 *plen = l;
3745 return bounce.buffer;
3749 memory_region_ref(mr);
3750 *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
3751 l, is_write, attrs);
3752 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
3753 rcu_read_unlock();
3755 return ptr;
3758 /* Unmaps a memory region previously mapped by address_space_map().
3759 * Will also mark the memory as dirty if is_write == 1. access_len gives
3760 * the amount of memory that was actually read or written by the caller.
3762 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3763 int is_write, hwaddr access_len)
3765 if (buffer != bounce.buffer) {
3766 MemoryRegion *mr;
3767 ram_addr_t addr1;
3769 mr = memory_region_from_host(buffer, &addr1);
3770 assert(mr != NULL);
3771 if (is_write) {
3772 invalidate_and_set_dirty(mr, addr1, access_len);
3774 if (xen_enabled()) {
3775 xen_invalidate_map_cache_entry(buffer);
3777 memory_region_unref(mr);
3778 return;
3780 if (is_write) {
3781 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3782 bounce.buffer, access_len);
3784 qemu_vfree(bounce.buffer);
3785 bounce.buffer = NULL;
3786 memory_region_unref(bounce.mr);
3787 atomic_mb_set(&bounce.in_use, false);
3788 cpu_notify_map_clients();
3791 void *cpu_physical_memory_map(hwaddr addr,
3792 hwaddr *plen,
3793 int is_write)
3795 return address_space_map(&address_space_memory, addr, plen, is_write,
3796 MEMTXATTRS_UNSPECIFIED);
3799 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3800 int is_write, hwaddr access_len)
3802 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3805 #define ARG1_DECL AddressSpace *as
3806 #define ARG1 as
3807 #define SUFFIX
3808 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3809 #define RCU_READ_LOCK(...) rcu_read_lock()
3810 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3811 #include "memory_ldst.inc.c"
3813 int64_t address_space_cache_init(MemoryRegionCache *cache,
3814 AddressSpace *as,
3815 hwaddr addr,
3816 hwaddr len,
3817 bool is_write)
3819 AddressSpaceDispatch *d;
3820 hwaddr l;
3821 MemoryRegion *mr;
3823 assert(len > 0);
3825 l = len;
3826 cache->fv = address_space_get_flatview(as);
3827 d = flatview_to_dispatch(cache->fv);
3828 cache->mrs = *address_space_translate_internal(d, addr, &cache->xlat, &l, true);
3830 mr = cache->mrs.mr;
3831 memory_region_ref(mr);
3832 if (memory_access_is_direct(mr, is_write)) {
3833 /* We don't care about the memory attributes here as we're only
3834 * doing this if we found actual RAM, which behaves the same
3835 * regardless of attributes; so UNSPECIFIED is fine.
3837 l = flatview_extend_translation(cache->fv, addr, len, mr,
3838 cache->xlat, l, is_write,
3839 MEMTXATTRS_UNSPECIFIED);
3840 cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
3841 } else {
3842 cache->ptr = NULL;
3845 cache->len = l;
3846 cache->is_write = is_write;
3847 return l;
3850 void address_space_cache_invalidate(MemoryRegionCache *cache,
3851 hwaddr addr,
3852 hwaddr access_len)
3854 assert(cache->is_write);
3855 if (likely(cache->ptr)) {
3856 invalidate_and_set_dirty(cache->mrs.mr, addr + cache->xlat, access_len);
3860 void address_space_cache_destroy(MemoryRegionCache *cache)
3862 if (!cache->mrs.mr) {
3863 return;
3866 if (xen_enabled()) {
3867 xen_invalidate_map_cache_entry(cache->ptr);
3869 memory_region_unref(cache->mrs.mr);
3870 flatview_unref(cache->fv);
3871 cache->mrs.mr = NULL;
3872 cache->fv = NULL;
3875 /* Called from RCU critical section. This function has the same
3876 * semantics as address_space_translate, but it only works on a
3877 * predefined range of a MemoryRegion that was mapped with
3878 * address_space_cache_init.
3880 static inline MemoryRegion *address_space_translate_cached(
3881 MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
3882 hwaddr *plen, bool is_write, MemTxAttrs attrs)
3884 MemoryRegionSection section;
3885 MemoryRegion *mr;
3886 IOMMUMemoryRegion *iommu_mr;
3887 AddressSpace *target_as;
3889 assert(!cache->ptr);
3890 *xlat = addr + cache->xlat;
3892 mr = cache->mrs.mr;
3893 iommu_mr = memory_region_get_iommu(mr);
3894 if (!iommu_mr) {
3895 /* MMIO region. */
3896 return mr;
3899 section = address_space_translate_iommu(iommu_mr, xlat, plen,
3900 NULL, is_write, true,
3901 &target_as, attrs);
3902 return section.mr;
3905 /* Called from RCU critical section. address_space_read_cached uses this
3906 * out of line function when the target is an MMIO or IOMMU region.
3908 void
3909 address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
3910 void *buf, hwaddr len)
3912 hwaddr addr1, l;
3913 MemoryRegion *mr;
3915 l = len;
3916 mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
3917 MEMTXATTRS_UNSPECIFIED);
3918 flatview_read_continue(cache->fv,
3919 addr, MEMTXATTRS_UNSPECIFIED, buf, len,
3920 addr1, l, mr);
3923 /* Called from RCU critical section. address_space_write_cached uses this
3924 * out of line function when the target is an MMIO or IOMMU region.
3926 void
3927 address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
3928 const void *buf, hwaddr len)
3930 hwaddr addr1, l;
3931 MemoryRegion *mr;
3933 l = len;
3934 mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
3935 MEMTXATTRS_UNSPECIFIED);
3936 flatview_write_continue(cache->fv,
3937 addr, MEMTXATTRS_UNSPECIFIED, buf, len,
3938 addr1, l, mr);
3941 #define ARG1_DECL MemoryRegionCache *cache
3942 #define ARG1 cache
3943 #define SUFFIX _cached_slow
3944 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3945 #define RCU_READ_LOCK() ((void)0)
3946 #define RCU_READ_UNLOCK() ((void)0)
3947 #include "memory_ldst.inc.c"
3949 /* virtual memory access for debug (includes writing to ROM) */
3950 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3951 uint8_t *buf, target_ulong len, int is_write)
3953 hwaddr phys_addr;
3954 target_ulong l, page;
3956 cpu_synchronize_state(cpu);
3957 while (len > 0) {
3958 int asidx;
3959 MemTxAttrs attrs;
3961 page = addr & TARGET_PAGE_MASK;
3962 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3963 asidx = cpu_asidx_from_attrs(cpu, attrs);
3964 /* if no physical page mapped, return an error */
3965 if (phys_addr == -1)
3966 return -1;
3967 l = (page + TARGET_PAGE_SIZE) - addr;
3968 if (l > len)
3969 l = len;
3970 phys_addr += (addr & ~TARGET_PAGE_MASK);
3971 if (is_write) {
3972 address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr,
3973 attrs, buf, l);
3974 } else {
3975 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3976 attrs, buf, l, 0);
3978 len -= l;
3979 buf += l;
3980 addr += l;
3982 return 0;
3986 * Allows code that needs to deal with migration bitmaps etc to still be built
3987 * target independent.
3989 size_t qemu_target_page_size(void)
3991 return TARGET_PAGE_SIZE;
3994 int qemu_target_page_bits(void)
3996 return TARGET_PAGE_BITS;
3999 int qemu_target_page_bits_min(void)
4001 return TARGET_PAGE_BITS_MIN;
4003 #endif
4005 bool target_words_bigendian(void)
4007 #if defined(TARGET_WORDS_BIGENDIAN)
4008 return true;
4009 #else
4010 return false;
4011 #endif
4014 #ifndef CONFIG_USER_ONLY
4015 bool cpu_physical_memory_is_io(hwaddr phys_addr)
4017 MemoryRegion*mr;
4018 hwaddr l = 1;
4019 bool res;
4021 rcu_read_lock();
4022 mr = address_space_translate(&address_space_memory,
4023 phys_addr, &phys_addr, &l, false,
4024 MEMTXATTRS_UNSPECIFIED);
4026 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
4027 rcu_read_unlock();
4028 return res;
4031 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
4033 RAMBlock *block;
4034 int ret = 0;
4036 rcu_read_lock();
4037 RAMBLOCK_FOREACH(block) {
4038 ret = func(block, opaque);
4039 if (ret) {
4040 break;
4043 rcu_read_unlock();
4044 return ret;
4048 * Unmap pages of memory from start to start+length such that
4049 * they a) read as 0, b) Trigger whatever fault mechanism
4050 * the OS provides for postcopy.
4051 * The pages must be unmapped by the end of the function.
4052 * Returns: 0 on success, none-0 on failure
4055 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
4057 int ret = -1;
4059 uint8_t *host_startaddr = rb->host + start;
4061 if ((uintptr_t)host_startaddr & (rb->page_size - 1)) {
4062 error_report("ram_block_discard_range: Unaligned start address: %p",
4063 host_startaddr);
4064 goto err;
4067 if ((start + length) <= rb->used_length) {
4068 bool need_madvise, need_fallocate;
4069 uint8_t *host_endaddr = host_startaddr + length;
4070 if ((uintptr_t)host_endaddr & (rb->page_size - 1)) {
4071 error_report("ram_block_discard_range: Unaligned end address: %p",
4072 host_endaddr);
4073 goto err;
4076 errno = ENOTSUP; /* If we are missing MADVISE etc */
4078 /* The logic here is messy;
4079 * madvise DONTNEED fails for hugepages
4080 * fallocate works on hugepages and shmem
4082 need_madvise = (rb->page_size == qemu_host_page_size);
4083 need_fallocate = rb->fd != -1;
4084 if (need_fallocate) {
4085 /* For a file, this causes the area of the file to be zero'd
4086 * if read, and for hugetlbfs also causes it to be unmapped
4087 * so a userfault will trigger.
4089 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
4090 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
4091 start, length);
4092 if (ret) {
4093 ret = -errno;
4094 error_report("ram_block_discard_range: Failed to fallocate "
4095 "%s:%" PRIx64 " +%zx (%d)",
4096 rb->idstr, start, length, ret);
4097 goto err;
4099 #else
4100 ret = -ENOSYS;
4101 error_report("ram_block_discard_range: fallocate not available/file"
4102 "%s:%" PRIx64 " +%zx (%d)",
4103 rb->idstr, start, length, ret);
4104 goto err;
4105 #endif
4107 if (need_madvise) {
4108 /* For normal RAM this causes it to be unmapped,
4109 * for shared memory it causes the local mapping to disappear
4110 * and to fall back on the file contents (which we just
4111 * fallocate'd away).
4113 #if defined(CONFIG_MADVISE)
4114 ret = madvise(host_startaddr, length, MADV_DONTNEED);
4115 if (ret) {
4116 ret = -errno;
4117 error_report("ram_block_discard_range: Failed to discard range "
4118 "%s:%" PRIx64 " +%zx (%d)",
4119 rb->idstr, start, length, ret);
4120 goto err;
4122 #else
4123 ret = -ENOSYS;
4124 error_report("ram_block_discard_range: MADVISE not available"
4125 "%s:%" PRIx64 " +%zx (%d)",
4126 rb->idstr, start, length, ret);
4127 goto err;
4128 #endif
4130 trace_ram_block_discard_range(rb->idstr, host_startaddr, length,
4131 need_madvise, need_fallocate, ret);
4132 } else {
4133 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
4134 "/%zx/" RAM_ADDR_FMT")",
4135 rb->idstr, start, length, rb->used_length);
4138 err:
4139 return ret;
4142 bool ramblock_is_pmem(RAMBlock *rb)
4144 return rb->flags & RAM_PMEM;
4147 #endif
4149 void page_size_init(void)
4151 /* NOTE: we can always suppose that qemu_host_page_size >=
4152 TARGET_PAGE_SIZE */
4153 if (qemu_host_page_size == 0) {
4154 qemu_host_page_size = qemu_real_host_page_size;
4156 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
4157 qemu_host_page_size = TARGET_PAGE_SIZE;
4159 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
4162 #if !defined(CONFIG_USER_ONLY)
4164 static void mtree_print_phys_entries(int start, int end, int skip, int ptr)
4166 if (start == end - 1) {
4167 qemu_printf("\t%3d ", start);
4168 } else {
4169 qemu_printf("\t%3d..%-3d ", start, end - 1);
4171 qemu_printf(" skip=%d ", skip);
4172 if (ptr == PHYS_MAP_NODE_NIL) {
4173 qemu_printf(" ptr=NIL");
4174 } else if (!skip) {
4175 qemu_printf(" ptr=#%d", ptr);
4176 } else {
4177 qemu_printf(" ptr=[%d]", ptr);
4179 qemu_printf("\n");
4182 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4183 int128_sub((size), int128_one())) : 0)
4185 void mtree_print_dispatch(AddressSpaceDispatch *d, MemoryRegion *root)
4187 int i;
4189 qemu_printf(" Dispatch\n");
4190 qemu_printf(" Physical sections\n");
4192 for (i = 0; i < d->map.sections_nb; ++i) {
4193 MemoryRegionSection *s = d->map.sections + i;
4194 const char *names[] = { " [unassigned]", " [not dirty]",
4195 " [ROM]", " [watch]" };
4197 qemu_printf(" #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx
4198 " %s%s%s%s%s",
4200 s->offset_within_address_space,
4201 s->offset_within_address_space + MR_SIZE(s->mr->size),
4202 s->mr->name ? s->mr->name : "(noname)",
4203 i < ARRAY_SIZE(names) ? names[i] : "",
4204 s->mr == root ? " [ROOT]" : "",
4205 s == d->mru_section ? " [MRU]" : "",
4206 s->mr->is_iommu ? " [iommu]" : "");
4208 if (s->mr->alias) {
4209 qemu_printf(" alias=%s", s->mr->alias->name ?
4210 s->mr->alias->name : "noname");
4212 qemu_printf("\n");
4215 qemu_printf(" Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4216 P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip);
4217 for (i = 0; i < d->map.nodes_nb; ++i) {
4218 int j, jprev;
4219 PhysPageEntry prev;
4220 Node *n = d->map.nodes + i;
4222 qemu_printf(" [%d]\n", i);
4224 for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) {
4225 PhysPageEntry *pe = *n + j;
4227 if (pe->ptr == prev.ptr && pe->skip == prev.skip) {
4228 continue;
4231 mtree_print_phys_entries(jprev, j, prev.skip, prev.ptr);
4233 jprev = j;
4234 prev = *pe;
4237 if (jprev != ARRAY_SIZE(*n)) {
4238 mtree_print_phys_entries(jprev, j, prev.skip, prev.ptr);
4243 #endif