hw/riscv/sifive_e.c

   1 /*
   2  * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * Provides a board compatible with the SiFive Freedom E SDK:
   7  *
   8  * 0) UART
   9  * 1) CLINT (Core Level Interruptor)
  10  * 2) PLIC (Platform Level Interrupt Controller)
  11  * 3) PRCI (Power, Reset, Clock, Interrupt)
  12  * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
  13  * 5) Flash memory emulated as RAM
  14  *
  15  * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
  16  * The OTP ROM and Flash boot code will be emulated in a future version.
  17  *
  18  * This program is free software; you can redistribute it and/or modify it
  19  * under the terms and conditions of the GNU General Public License,
  20  * version 2 or later, as published by the Free Software Foundation.
  21  *
  22  * This program is distributed in the hope it will be useful, but WITHOUT
  23  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  24  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  25  * more details.
  26  *
  27  * You should have received a copy of the GNU General Public License along with
  28  * this program.  If not, see <http://www.gnu.org/licenses/>.
  29  */
  30
  31 #include "qemu/osdep.h"
  32 #include "qemu/log.h"
  33 #include "qemu/error-report.h"
  34 #include "qapi/error.h"
  35 #include "hw/boards.h"
  36 #include "hw/loader.h"
  37 #include "hw/sysbus.h"
  38 #include "hw/char/serial.h"
  39 #include "hw/misc/unimp.h"
  40 #include "target/riscv/cpu.h"
  41 #include "hw/riscv/riscv_hart.h"
  42 #include "hw/riscv/sifive_e.h"
  43 #include "hw/riscv/boot.h"
  44 #include "hw/char/sifive_uart.h"
  45 #include "hw/intc/sifive_clint.h"
  46 #include "hw/intc/sifive_plic.h"
  47 #include "hw/misc/sifive_e_prci.h"
  48 #include "chardev/char.h"
  49 #include "sysemu/arch_init.h"
  50 #include "sysemu/sysemu.h"
  51 #include "exec/address-spaces.h"
  52
  53 static MemMapEntry sifive_e_memmap[] = {
  54     [SIFIVE_E_DEV_DEBUG] =    {        0x0,     0x1000 },
  55     [SIFIVE_E_DEV_MROM] =     {     0x1000,     0x2000 },
  56     [SIFIVE_E_DEV_OTP] =      {    0x20000,     0x2000 },
  57     [SIFIVE_E_DEV_CLINT] =    {  0x2000000,    0x10000 },
  58     [SIFIVE_E_DEV_PLIC] =     {  0xc000000,  0x4000000 },
  59     [SIFIVE_E_DEV_AON] =      { 0x10000000,     0x8000 },
  60     [SIFIVE_E_DEV_PRCI] =     { 0x10008000,     0x8000 },
  61     [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000,     0x1000 },
  62     [SIFIVE_E_DEV_GPIO0] =    { 0x10012000,     0x1000 },
  63     [SIFIVE_E_DEV_UART0] =    { 0x10013000,     0x1000 },
  64     [SIFIVE_E_DEV_QSPI0] =    { 0x10014000,     0x1000 },
  65     [SIFIVE_E_DEV_PWM0] =     { 0x10015000,     0x1000 },
  66     [SIFIVE_E_DEV_UART1] =    { 0x10023000,     0x1000 },
  67     [SIFIVE_E_DEV_QSPI1] =    { 0x10024000,     0x1000 },
  68     [SIFIVE_E_DEV_PWM1] =     { 0x10025000,     0x1000 },
  69     [SIFIVE_E_DEV_QSPI2] =    { 0x10034000,     0x1000 },
  70     [SIFIVE_E_DEV_PWM2] =     { 0x10035000,     0x1000 },
  71     [SIFIVE_E_DEV_XIP] =      { 0x20000000, 0x20000000 },
  72     [SIFIVE_E_DEV_DTIM] =     { 0x80000000,     0x4000 }
  73 };
  74
  75 static void sifive_e_machine_init(MachineState *machine)
  76 {
  77     const MemMapEntry *memmap = sifive_e_memmap;
  78
  79     SiFiveEState *s = RISCV_E_MACHINE(machine);
  80     MemoryRegion *sys_mem = get_system_memory();
  81     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
  82     int i;
  83
  84     /* Initialize SoC */
  85     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
  86     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
  87
  88     /* Data Tightly Integrated Memory */
  89     memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
  90         memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
  91     memory_region_add_subregion(sys_mem,
  92         memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
  93
  94     /* Mask ROM reset vector */
  95     uint32_t reset_vec[4];
  96
  97     if (s->revb) {
  98         reset_vec[1] = 0x200102b7;  /* 0x1004: lui     t0,0x20010 */
  99     } else {
 100         reset_vec[1] = 0x204002b7;  /* 0x1004: lui     t0,0x20400 */
 101     }
 102     reset_vec[2] = 0x00028067;      /* 0x1008: jr      t0 */
 103
 104     reset_vec[0] = reset_vec[3] = 0;
 105
 106     /* copy in the reset vector in little_endian byte order */
 107     for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 108         reset_vec[i] = cpu_to_le32(reset_vec[i]);
 109     }
 110     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 111                           memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
 112
 113     if (machine->kernel_filename) {
 114         riscv_load_kernel(machine->kernel_filename,
 115                           memmap[SIFIVE_E_DEV_DTIM].base, NULL);
 116     }
 117 }
 118
 119 static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
 120 {
 121     SiFiveEState *s = RISCV_E_MACHINE(obj);
 122
 123     return s->revb;
 124 }
 125
 126 static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
 127 {
 128     SiFiveEState *s = RISCV_E_MACHINE(obj);
 129
 130     s->revb = value;
 131 }
 132
 133 static void sifive_e_machine_instance_init(Object *obj)
 134 {
 135     SiFiveEState *s = RISCV_E_MACHINE(obj);
 136
 137     s->revb = false;
 138 }
 139
 140 static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
 141 {
 142     MachineClass *mc = MACHINE_CLASS(oc);
 143
 144     mc->desc = "RISC-V Board compatible with SiFive E SDK";
 145     mc->init = sifive_e_machine_init;
 146     mc->max_cpus = 1;
 147     mc->default_cpu_type = SIFIVE_E_CPU;
 148
 149     object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
 150                                    sifive_e_machine_set_revb);
 151     object_class_property_set_description(oc, "revb",
 152                                           "Set on to tell QEMU that it should model "
 153                                           "the revB HiFive1 board");
 154 }
 155
 156 static const TypeInfo sifive_e_machine_typeinfo = {
 157     .name       = MACHINE_TYPE_NAME("sifive_e"),
 158     .parent     = TYPE_MACHINE,
 159     .class_init = sifive_e_machine_class_init,
 160     .instance_init = sifive_e_machine_instance_init,
 161     .instance_size = sizeof(SiFiveEState),
 162 };
 163
 164 static void sifive_e_machine_init_register_types(void)
 165 {
 166     type_register_static(&sifive_e_machine_typeinfo);
 167 }
 168
 169 type_init(sifive_e_machine_init_register_types)
 170
 171 static void sifive_e_soc_init(Object *obj)
 172 {
 173     MachineState *ms = MACHINE(qdev_get_machine());
 174     SiFiveESoCState *s = RISCV_E_SOC(obj);
 175
 176     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
 177     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
 178                             &error_abort);
 179     object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
 180     object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
 181                             TYPE_SIFIVE_GPIO);
 182 }
 183
 184 static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
 185 {
 186     MachineState *ms = MACHINE(qdev_get_machine());
 187     const MemMapEntry *memmap = sifive_e_memmap;
 188     SiFiveESoCState *s = RISCV_E_SOC(dev);
 189     MemoryRegion *sys_mem = get_system_memory();
 190
 191     object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
 192                             &error_abort);
 193     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
 194
 195     /* Mask ROM */
 196     memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
 197                            memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
 198     memory_region_add_subregion(sys_mem,
 199         memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
 200
 201     /* MMIO */
 202     s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
 203         (char *)SIFIVE_E_PLIC_HART_CONFIG, 0,
 204         SIFIVE_E_PLIC_NUM_SOURCES,
 205         SIFIVE_E_PLIC_NUM_PRIORITIES,
 206         SIFIVE_E_PLIC_PRIORITY_BASE,
 207         SIFIVE_E_PLIC_PENDING_BASE,
 208         SIFIVE_E_PLIC_ENABLE_BASE,
 209         SIFIVE_E_PLIC_ENABLE_STRIDE,
 210         SIFIVE_E_PLIC_CONTEXT_BASE,
 211         SIFIVE_E_PLIC_CONTEXT_STRIDE,
 212         memmap[SIFIVE_E_DEV_PLIC].size);
 213     sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base,
 214         memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus,
 215         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
 216         SIFIVE_CLINT_TIMEBASE_FREQ, false);
 217     create_unimplemented_device("riscv.sifive.e.aon",
 218         memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
 219     sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
 220
 221     /* GPIO */
 222
 223     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
 224         return;
 225     }
 226
 227     /* Map GPIO registers */
 228     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
 229
 230     /* Pass all GPIOs to the SOC layer so they are available to the board */
 231     qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
 232
 233     /* Connect GPIO interrupts to the PLIC */
 234     for (int i = 0; i < 32; i++) {
 235         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
 236                            qdev_get_gpio_in(DEVICE(s->plic),
 237                                             SIFIVE_E_GPIO0_IRQ0 + i));
 238     }
 239
 240     sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
 241         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
 242     create_unimplemented_device("riscv.sifive.e.qspi0",
 243         memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
 244     create_unimplemented_device("riscv.sifive.e.pwm0",
 245         memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
 246     sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
 247         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
 248     create_unimplemented_device("riscv.sifive.e.qspi1",
 249         memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
 250     create_unimplemented_device("riscv.sifive.e.pwm1",
 251         memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
 252     create_unimplemented_device("riscv.sifive.e.qspi2",
 253         memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
 254     create_unimplemented_device("riscv.sifive.e.pwm2",
 255         memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
 256
 257     /* Flash memory */
 258     memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
 259                            memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
 260     memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
 261         &s->xip_mem);
 262 }
 263
 264 static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
 265 {
 266     DeviceClass *dc = DEVICE_CLASS(oc);
 267
 268     dc->realize = sifive_e_soc_realize;
 269     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 270     dc->user_creatable = false;
 271 }
 272
 273 static const TypeInfo sifive_e_soc_type_info = {
 274     .name = TYPE_RISCV_E_SOC,
 275     .parent = TYPE_DEVICE,
 276     .instance_size = sizeof(SiFiveESoCState),
 277     .instance_init = sifive_e_soc_init,
 278     .class_init = sifive_e_soc_class_init,
 279 };
 280
 281 static void sifive_e_soc_register_types(void)
 282 {
 283     type_register_static(&sifive_e_soc_type_info);
 284 }
 285
 286 type_init(sifive_e_soc_register_types)