target/mips: Remove XBurst Media eXtension Unit dead code
[qemu/ar7.git] / hw / arm / xlnx-versal-virt.c
blob8482cd61960e72f25001a146c147c295b4378d8f
1 /*
2 * Xilinx Versal Virtual board.
4 * Copyright (c) 2018 Xilinx Inc.
5 * Written by Edgar E. Iglesias
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 #include "qemu/osdep.h"
13 #include "qemu/log.h"
14 #include "qemu/error-report.h"
15 #include "qapi/error.h"
16 #include "sysemu/device_tree.h"
17 #include "exec/address-spaces.h"
18 #include "hw/boards.h"
19 #include "hw/sysbus.h"
20 #include "hw/arm/sysbus-fdt.h"
21 #include "hw/arm/fdt.h"
22 #include "cpu.h"
23 #include "hw/qdev-properties.h"
24 #include "hw/arm/xlnx-versal.h"
25 #include "qom/object.h"
27 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
28 OBJECT_DECLARE_SIMPLE_TYPE(VersalVirt, XLNX_VERSAL_VIRT_MACHINE)
30 struct VersalVirt {
31 MachineState parent_obj;
33 Versal soc;
35 void *fdt;
36 int fdt_size;
37 struct {
38 uint32_t gic;
39 uint32_t ethernet_phy[2];
40 uint32_t clk_125Mhz;
41 uint32_t clk_25Mhz;
42 uint32_t usb;
43 uint32_t dwc;
44 } phandle;
45 struct arm_boot_info binfo;
47 struct {
48 bool secure;
49 } cfg;
52 static void fdt_create(VersalVirt *s)
54 MachineClass *mc = MACHINE_GET_CLASS(s);
55 int i;
57 s->fdt = create_device_tree(&s->fdt_size);
58 if (!s->fdt) {
59 error_report("create_device_tree() failed");
60 exit(1);
63 /* Allocate all phandles. */
64 s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt);
65 for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) {
66 s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt);
68 s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
69 s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
71 s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt);
72 s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt);
73 /* Create /chosen node for load_dtb. */
74 qemu_fdt_add_subnode(s->fdt, "/chosen");
76 /* Header */
77 qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic);
78 qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2);
79 qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2);
80 qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc);
81 qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt");
84 static void fdt_add_clk_node(VersalVirt *s, const char *name,
85 unsigned int freq_hz, uint32_t phandle)
87 qemu_fdt_add_subnode(s->fdt, name);
88 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
89 qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz);
90 qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0);
91 qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock");
92 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
95 static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
97 int i;
99 qemu_fdt_add_subnode(s->fdt, "/cpus");
100 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0);
101 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1);
103 for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) {
104 char *name = g_strdup_printf("/cpus/cpu@%d", i);
105 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
107 qemu_fdt_add_subnode(s->fdt, name);
108 qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
109 if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
110 qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci");
112 qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu");
113 qemu_fdt_setprop_string(s->fdt, name, "compatible",
114 armcpu->dtb_compatible);
115 g_free(name);
119 static void fdt_add_gic_nodes(VersalVirt *s)
121 char *nodename;
123 nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN);
124 qemu_fdt_add_subnode(s->fdt, nodename);
125 qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic);
126 qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts",
127 GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ,
128 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
129 qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0);
130 qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
131 2, MM_GIC_APU_DIST_MAIN,
132 2, MM_GIC_APU_DIST_MAIN_SIZE,
133 2, MM_GIC_APU_REDIST_0,
134 2, MM_GIC_APU_REDIST_0_SIZE);
135 qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3);
136 qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3");
137 g_free(nodename);
140 static void fdt_add_timer_nodes(VersalVirt *s)
142 const char compat[] = "arm,armv8-timer";
143 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
145 qemu_fdt_add_subnode(s->fdt, "/timer");
146 qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts",
147 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags,
148 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags,
149 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags,
150 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags);
151 qemu_fdt_setprop(s->fdt, "/timer", "compatible",
152 compat, sizeof(compat));
155 static void fdt_add_usb_xhci_nodes(VersalVirt *s)
157 const char clocknames[] = "bus_clk\0ref_clk";
158 const char irq_name[] = "dwc_usb3";
159 const char compatVersalDWC3[] = "xlnx,versal-dwc3";
160 const char compatDWC3[] = "snps,dwc3";
161 char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS);
163 qemu_fdt_add_subnode(s->fdt, name);
164 qemu_fdt_setprop(s->fdt, name, "compatible",
165 compatVersalDWC3, sizeof(compatVersalDWC3));
166 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
167 2, MM_USB2_CTRL_REGS,
168 2, MM_USB2_CTRL_REGS_SIZE);
169 qemu_fdt_setprop(s->fdt, name, "clock-names",
170 clocknames, sizeof(clocknames));
171 qemu_fdt_setprop_cells(s->fdt, name, "clocks",
172 s->phandle.clk_25Mhz, s->phandle.clk_125Mhz);
173 qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0);
174 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2);
175 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2);
176 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb);
177 g_free(name);
179 name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32,
180 MM_USB2_CTRL_REGS, MM_USB_0);
181 qemu_fdt_add_subnode(s->fdt, name);
182 qemu_fdt_setprop(s->fdt, name, "compatible",
183 compatDWC3, sizeof(compatDWC3));
184 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
185 2, MM_USB_0, 2, MM_USB_0_SIZE);
186 qemu_fdt_setprop(s->fdt, name, "interrupt-names",
187 irq_name, sizeof(irq_name));
188 qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
189 GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0,
190 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
191 qemu_fdt_setprop_cell(s->fdt, name,
192 "snps,quirk-frame-length-adjustment", 0x20);
193 qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1);
194 qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host");
195 qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy");
196 qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0);
197 qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0);
198 qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0);
199 qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0);
200 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc);
201 qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed");
202 g_free(name);
205 static void fdt_add_uart_nodes(VersalVirt *s)
207 uint64_t addrs[] = { MM_UART1, MM_UART0 };
208 unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 };
209 const char compat[] = "arm,pl011\0arm,sbsa-uart";
210 const char clocknames[] = "uartclk\0apb_pclk";
211 int i;
213 for (i = 0; i < ARRAY_SIZE(addrs); i++) {
214 char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]);
215 qemu_fdt_add_subnode(s->fdt, name);
216 qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200);
217 qemu_fdt_setprop_cells(s->fdt, name, "clocks",
218 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz);
219 qemu_fdt_setprop(s->fdt, name, "clock-names",
220 clocknames, sizeof(clocknames));
222 qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
223 GIC_FDT_IRQ_TYPE_SPI, irqs[i],
224 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
225 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
226 2, addrs[i], 2, 0x1000);
227 qemu_fdt_setprop(s->fdt, name, "compatible",
228 compat, sizeof(compat));
229 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
231 if (addrs[i] == MM_UART0) {
232 /* Select UART0. */
233 qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name);
235 g_free(name);
239 static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname,
240 uint32_t phandle)
242 char *name = g_strdup_printf("%s/fixed-link", gemname);
244 qemu_fdt_add_subnode(s->fdt, name);
245 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
246 qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0);
247 qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000);
248 g_free(name);
251 static void fdt_add_gem_nodes(VersalVirt *s)
253 uint64_t addrs[] = { MM_GEM1, MM_GEM0 };
254 unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 };
255 const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk";
256 const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem";
257 int i;
259 for (i = 0; i < ARRAY_SIZE(addrs); i++) {
260 char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]);
261 qemu_fdt_add_subnode(s->fdt, name);
263 fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]);
264 qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id");
265 qemu_fdt_setprop_cell(s->fdt, name, "phy-handle",
266 s->phandle.ethernet_phy[i]);
267 qemu_fdt_setprop_cells(s->fdt, name, "clocks",
268 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz,
269 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz);
270 qemu_fdt_setprop(s->fdt, name, "clock-names",
271 clocknames, sizeof(clocknames));
272 qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
273 GIC_FDT_IRQ_TYPE_SPI, irqs[i],
274 GIC_FDT_IRQ_FLAGS_LEVEL_HI,
275 GIC_FDT_IRQ_TYPE_SPI, irqs[i],
276 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
277 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
278 2, addrs[i], 2, 0x1000);
279 qemu_fdt_setprop(s->fdt, name, "compatible",
280 compat_gem, sizeof(compat_gem));
281 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1);
282 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0);
283 g_free(name);
287 static void fdt_add_zdma_nodes(VersalVirt *s)
289 const char clocknames[] = "clk_main\0clk_apb";
290 const char compat[] = "xlnx,zynqmp-dma-1.0";
291 int i;
293 for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) {
294 uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i;
295 char *name = g_strdup_printf("/dma@%" PRIx64, addr);
297 qemu_fdt_add_subnode(s->fdt, name);
299 qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64);
300 qemu_fdt_setprop_cells(s->fdt, name, "clocks",
301 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
302 qemu_fdt_setprop(s->fdt, name, "clock-names",
303 clocknames, sizeof(clocknames));
304 qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
305 GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i,
306 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
307 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
308 2, addr, 2, 0x1000);
309 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
310 g_free(name);
314 static void fdt_add_sd_nodes(VersalVirt *s)
316 const char clocknames[] = "clk_xin\0clk_ahb";
317 const char compat[] = "arasan,sdhci-8.9a";
318 int i;
320 for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) {
321 uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i;
322 char *name = g_strdup_printf("/sdhci@%" PRIx64, addr);
324 qemu_fdt_add_subnode(s->fdt, name);
326 qemu_fdt_setprop_cells(s->fdt, name, "clocks",
327 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
328 qemu_fdt_setprop(s->fdt, name, "clock-names",
329 clocknames, sizeof(clocknames));
330 qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
331 GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2,
332 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
333 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
334 2, addr, 2, MM_PMC_SD0_SIZE);
335 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
336 g_free(name);
340 static void fdt_add_rtc_node(VersalVirt *s)
342 const char compat[] = "xlnx,zynqmp-rtc";
343 const char interrupt_names[] = "alarm\0sec";
344 char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC);
346 qemu_fdt_add_subnode(s->fdt, name);
348 qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
349 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ,
350 GIC_FDT_IRQ_FLAGS_LEVEL_HI,
351 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ,
352 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
353 qemu_fdt_setprop(s->fdt, name, "interrupt-names",
354 interrupt_names, sizeof(interrupt_names));
355 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
356 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE);
357 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
358 g_free(name);
361 static void fdt_nop_memory_nodes(void *fdt, Error **errp)
363 Error *err = NULL;
364 char **node_path;
365 int n = 0;
367 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
368 if (err) {
369 error_propagate(errp, err);
370 return;
372 while (node_path[n]) {
373 if (g_str_has_prefix(node_path[n], "/memory")) {
374 qemu_fdt_nop_node(fdt, node_path[n]);
376 n++;
378 g_strfreev(node_path);
381 static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size)
383 /* Describes the various split DDR access regions. */
384 static const struct {
385 uint64_t base;
386 uint64_t size;
387 } addr_ranges[] = {
388 { MM_TOP_DDR, MM_TOP_DDR_SIZE },
389 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
390 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
391 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
393 uint64_t mem_reg_prop[8] = {0};
394 uint64_t size = ram_size;
395 Error *err = NULL;
396 char *name;
397 int i;
399 fdt_nop_memory_nodes(fdt, &err);
400 if (err) {
401 error_report_err(err);
402 return;
405 name = g_strdup_printf("/memory@%x", MM_TOP_DDR);
406 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
407 uint64_t mapsize;
409 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
411 mem_reg_prop[i * 2] = addr_ranges[i].base;
412 mem_reg_prop[i * 2 + 1] = mapsize;
413 size -= mapsize;
415 qemu_fdt_add_subnode(fdt, name);
416 qemu_fdt_setprop_string(fdt, name, "device_type", "memory");
418 switch (i) {
419 case 1:
420 qemu_fdt_setprop_sized_cells(fdt, name, "reg",
421 2, mem_reg_prop[0],
422 2, mem_reg_prop[1]);
423 break;
424 case 2:
425 qemu_fdt_setprop_sized_cells(fdt, name, "reg",
426 2, mem_reg_prop[0],
427 2, mem_reg_prop[1],
428 2, mem_reg_prop[2],
429 2, mem_reg_prop[3]);
430 break;
431 case 3:
432 qemu_fdt_setprop_sized_cells(fdt, name, "reg",
433 2, mem_reg_prop[0],
434 2, mem_reg_prop[1],
435 2, mem_reg_prop[2],
436 2, mem_reg_prop[3],
437 2, mem_reg_prop[4],
438 2, mem_reg_prop[5]);
439 break;
440 case 4:
441 qemu_fdt_setprop_sized_cells(fdt, name, "reg",
442 2, mem_reg_prop[0],
443 2, mem_reg_prop[1],
444 2, mem_reg_prop[2],
445 2, mem_reg_prop[3],
446 2, mem_reg_prop[4],
447 2, mem_reg_prop[5],
448 2, mem_reg_prop[6],
449 2, mem_reg_prop[7]);
450 break;
451 default:
452 g_assert_not_reached();
454 g_free(name);
457 static void versal_virt_modify_dtb(const struct arm_boot_info *binfo,
458 void *fdt)
460 VersalVirt *s = container_of(binfo, VersalVirt, binfo);
462 fdt_add_memory_nodes(s, fdt, binfo->ram_size);
465 static void *versal_virt_get_dtb(const struct arm_boot_info *binfo,
466 int *fdt_size)
468 const VersalVirt *board = container_of(binfo, VersalVirt, binfo);
470 *fdt_size = board->fdt_size;
471 return board->fdt;
474 #define NUM_VIRTIO_TRANSPORT 8
475 static void create_virtio_regions(VersalVirt *s)
477 int virtio_mmio_size = 0x200;
478 int i;
480 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
481 char *name = g_strdup_printf("virtio%d", i);
482 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
483 int irq = VERSAL_RSVD_IRQ_FIRST + i;
484 MemoryRegion *mr;
485 DeviceState *dev;
486 qemu_irq pic_irq;
488 pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
489 dev = qdev_new("virtio-mmio");
490 object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev));
491 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
492 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
493 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
494 memory_region_add_subregion(&s->soc.mr_ps, base, mr);
495 g_free(name);
498 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
499 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
500 int irq = VERSAL_RSVD_IRQ_FIRST + i;
501 char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
503 qemu_fdt_add_subnode(s->fdt, name);
504 qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0);
505 qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
506 GIC_FDT_IRQ_TYPE_SPI, irq,
507 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
508 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
509 2, base, 2, virtio_mmio_size);
510 qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio");
511 g_free(name);
515 static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
517 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
518 DeviceState *card;
520 card = qdev_new(TYPE_SD_CARD);
521 object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card));
522 qdev_prop_set_drive_err(card, "drive", blk, &error_fatal);
523 qdev_realize_and_unref(card, qdev_get_child_bus(DEVICE(sd), "sd-bus"),
524 &error_fatal);
527 static void versal_virt_init(MachineState *machine)
529 VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine);
530 int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
531 int i;
534 * If the user provides an Operating System to be loaded, we expect them
535 * to use the -kernel command line option.
537 * Users can load firmware or boot-loaders with the -device loader options.
539 * When loading an OS, we generate a dtb and let arm_load_kernel() select
540 * where it gets loaded. This dtb will be passed to the kernel in x0.
542 * If there's no -kernel option, we generate a DTB and place it at 0x1000
543 * for the bootloaders or firmware to pick up.
545 * If users want to provide their own DTB, they can use the -dtb option.
546 * These dtb's will have their memory nodes modified to match QEMU's
547 * selected ram_size option before they get passed to the kernel or fw.
549 * When loading an OS, we turn on QEMU's PSCI implementation with SMC
550 * as the PSCI conduit. When there's no -kernel, we assume the user
551 * provides EL3 firmware to handle PSCI.
553 if (machine->kernel_filename) {
554 psci_conduit = QEMU_PSCI_CONDUIT_SMC;
557 object_initialize_child(OBJECT(machine), "xlnx-versal", &s->soc,
558 TYPE_XLNX_VERSAL);
559 object_property_set_link(OBJECT(&s->soc), "ddr", OBJECT(machine->ram),
560 &error_abort);
561 object_property_set_int(OBJECT(&s->soc), "psci-conduit", psci_conduit,
562 &error_abort);
563 sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
565 fdt_create(s);
566 create_virtio_regions(s);
567 fdt_add_gem_nodes(s);
568 fdt_add_uart_nodes(s);
569 fdt_add_gic_nodes(s);
570 fdt_add_timer_nodes(s);
571 fdt_add_zdma_nodes(s);
572 fdt_add_usb_xhci_nodes(s);
573 fdt_add_sd_nodes(s);
574 fdt_add_rtc_node(s);
575 fdt_add_cpu_nodes(s, psci_conduit);
576 fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
577 fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
579 /* Make the APU cpu address space visible to virtio and other
580 * modules unaware of muliple address-spaces. */
581 memory_region_add_subregion_overlap(get_system_memory(),
582 0, &s->soc.fpd.apu.mr, 0);
584 /* Plugin SD cards. */
585 for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
586 sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
589 s->binfo.ram_size = machine->ram_size;
590 s->binfo.loader_start = 0x0;
591 s->binfo.get_dtb = versal_virt_get_dtb;
592 s->binfo.modify_dtb = versal_virt_modify_dtb;
593 if (machine->kernel_filename) {
594 arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo);
595 } else {
596 AddressSpace *as = arm_boot_address_space(&s->soc.fpd.apu.cpu[0],
597 &s->binfo);
598 /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
599 * Offset things by 4K. */
600 s->binfo.loader_start = 0x1000;
601 s->binfo.dtb_limit = 0x1000000;
602 if (arm_load_dtb(s->binfo.loader_start,
603 &s->binfo, s->binfo.dtb_limit, as, machine) < 0) {
604 exit(EXIT_FAILURE);
609 static void versal_virt_machine_instance_init(Object *obj)
613 static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
615 MachineClass *mc = MACHINE_CLASS(oc);
617 mc->desc = "Xilinx Versal Virtual development board";
618 mc->init = versal_virt_init;
619 mc->min_cpus = XLNX_VERSAL_NR_ACPUS;
620 mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
621 mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
622 mc->no_cdrom = true;
623 mc->default_ram_id = "ddr";
626 static const TypeInfo versal_virt_machine_init_typeinfo = {
627 .name = TYPE_XLNX_VERSAL_VIRT_MACHINE,
628 .parent = TYPE_MACHINE,
629 .class_init = versal_virt_machine_class_init,
630 .instance_init = versal_virt_machine_instance_init,
631 .instance_size = sizeof(VersalVirt),
634 static void versal_virt_machine_init_register_types(void)
636 type_register_static(&versal_virt_machine_init_typeinfo);
639 type_init(versal_virt_machine_init_register_types)