2 * Luminary Micro Stellaris peripherals
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/sysbus.h"
13 #include "hw/ssi/ssi.h"
14 #include "hw/arm/boot.h"
15 #include "qemu/timer.h"
16 #include "hw/i2c/i2c.h"
18 #include "hw/boards.h"
20 #include "exec/address-spaces.h"
21 #include "sysemu/sysemu.h"
22 #include "hw/arm/armv7m.h"
23 #include "hw/char/pl011.h"
24 #include "hw/input/gamepad.h"
26 #include "hw/watchdog/cmsdk-apb-watchdog.h"
27 #include "migration/vmstate.h"
28 #include "hw/misc/unimp.h"
29 #include "hw/qdev-clock.h"
31 #include "qom/object.h"
41 #define BP_OLED_I2C 0x01
42 #define BP_OLED_SSI 0x02
43 #define BP_GAMEPAD 0x04
45 #define NUM_IRQ_LINES 64
47 typedef const struct {
57 } stellaris_board_info;
59 /* General purpose timer module. */
61 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
62 OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM)
65 SysBusDevice parent_obj;
76 uint32_t match_prescale[2];
79 struct gptm_state *opaque[2];
81 /* The timers have an alternate output used to trigger the ADC. */
86 static void gptm_update_irq(gptm_state *s)
89 level = (s->state & s->mask) != 0;
90 qemu_set_irq(s->irq, level);
93 static void gptm_stop(gptm_state *s, int n)
95 timer_del(s->timer[n]);
98 static void gptm_reload(gptm_state *s, int n, int reset)
102 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
106 if (s->config == 0) {
107 /* 32-bit CountDown. */
109 count = s->load[0] | (s->load[1] << 16);
110 tick += (int64_t)count * system_clock_scale;
111 } else if (s->config == 1) {
112 /* 32-bit RTC. 1Hz tick. */
113 tick += NANOSECONDS_PER_SECOND;
114 } else if (s->mode[n] == 0xa) {
115 /* PWM mode. Not implemented. */
117 qemu_log_mask(LOG_UNIMP,
118 "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
123 timer_mod(s->timer[n], tick);
126 static void gptm_tick(void *opaque)
128 gptm_state **p = (gptm_state **)opaque;
134 if (s->config == 0) {
136 if ((s->control & 0x20)) {
137 /* Output trigger. */
138 qemu_irq_pulse(s->trigger);
140 if (s->mode[0] & 1) {
145 gptm_reload(s, 0, 0);
147 } else if (s->config == 1) {
151 match = s->match[0] | (s->match[1] << 16);
157 gptm_reload(s, 0, 0);
158 } else if (s->mode[n] == 0xa) {
159 /* PWM mode. Not implemented. */
161 qemu_log_mask(LOG_UNIMP,
162 "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
168 static uint64_t gptm_read(void *opaque, hwaddr offset,
171 gptm_state *s = (gptm_state *)opaque;
176 case 0x04: /* TAMR */
178 case 0x08: /* TBMR */
187 return s->state & s->mask;
190 case 0x28: /* TAILR */
191 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
192 case 0x2c: /* TBILR */
194 case 0x30: /* TAMARCHR */
195 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
196 case 0x34: /* TBMATCHR */
198 case 0x38: /* TAPR */
199 return s->prescale[0];
200 case 0x3c: /* TBPR */
201 return s->prescale[1];
202 case 0x40: /* TAPMR */
203 return s->match_prescale[0];
204 case 0x44: /* TBPMR */
205 return s->match_prescale[1];
207 if (s->config == 1) {
210 qemu_log_mask(LOG_UNIMP,
211 "GPTM: read of TAR but timer read not supported\n");
214 qemu_log_mask(LOG_UNIMP,
215 "GPTM: read of TBR but timer read not supported\n");
218 qemu_log_mask(LOG_GUEST_ERROR,
219 "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n",
225 static void gptm_write(void *opaque, hwaddr offset,
226 uint64_t value, unsigned size)
228 gptm_state *s = (gptm_state *)opaque;
231 /* The timers should be disabled before changing the configuration.
232 We take advantage of this and defer everything until the timer
238 case 0x04: /* TAMR */
241 case 0x08: /* TBMR */
247 /* TODO: Implement pause. */
248 if ((oldval ^ value) & 1) {
250 gptm_reload(s, 0, 1);
255 if (((oldval ^ value) & 0x100) && s->config >= 4) {
257 gptm_reload(s, 1, 1);
264 s->mask = value & 0x77;
270 case 0x28: /* TAILR */
271 s->load[0] = value & 0xffff;
273 s->load[1] = value >> 16;
276 case 0x2c: /* TBILR */
277 s->load[1] = value & 0xffff;
279 case 0x30: /* TAMARCHR */
280 s->match[0] = value & 0xffff;
282 s->match[1] = value >> 16;
285 case 0x34: /* TBMATCHR */
286 s->match[1] = value >> 16;
288 case 0x38: /* TAPR */
289 s->prescale[0] = value;
291 case 0x3c: /* TBPR */
292 s->prescale[1] = value;
294 case 0x40: /* TAPMR */
295 s->match_prescale[0] = value;
297 case 0x44: /* TBPMR */
298 s->match_prescale[0] = value;
301 qemu_log_mask(LOG_GUEST_ERROR,
302 "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n",
308 static const MemoryRegionOps gptm_ops = {
311 .endianness = DEVICE_NATIVE_ENDIAN,
314 static const VMStateDescription vmstate_stellaris_gptm = {
315 .name = "stellaris_gptm",
317 .minimum_version_id = 1,
318 .fields = (VMStateField[]) {
319 VMSTATE_UINT32(config, gptm_state),
320 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
321 VMSTATE_UINT32(control, gptm_state),
322 VMSTATE_UINT32(state, gptm_state),
323 VMSTATE_UINT32(mask, gptm_state),
325 VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
326 VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
327 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
328 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
329 VMSTATE_UINT32(rtc, gptm_state),
330 VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
331 VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
332 VMSTATE_END_OF_LIST()
336 static void stellaris_gptm_init(Object *obj)
338 DeviceState *dev = DEVICE(obj);
339 gptm_state *s = STELLARIS_GPTM(obj);
340 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
342 sysbus_init_irq(sbd, &s->irq);
343 qdev_init_gpio_out(dev, &s->trigger, 1);
345 memory_region_init_io(&s->iomem, obj, &gptm_ops, s,
347 sysbus_init_mmio(sbd, &s->iomem);
349 s->opaque[0] = s->opaque[1] = s;
352 static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
354 gptm_state *s = STELLARIS_GPTM(dev);
355 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
356 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
359 /* System controller. */
361 #define TYPE_STELLARIS_SYS "stellaris-sys"
362 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
365 SysBusDevice parent_obj;
382 /* Properties (all read-only registers) */
394 static void ssys_update(ssys_state *s)
396 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
399 static uint32_t pllcfg_sandstorm[16] = {
401 0x1ae0, /* 1.8432 Mhz */
403 0xd573, /* 2.4576 Mhz */
404 0x37a6, /* 3.57954 Mhz */
405 0x1ae2, /* 3.6864 Mhz */
407 0x98bc, /* 4.906 Mhz */
408 0x935b, /* 4.9152 Mhz */
410 0x4dee, /* 5.12 Mhz */
412 0x75db, /* 6.144 Mhz */
413 0x1ae6, /* 7.3728 Mhz */
415 0x585b /* 8.192 Mhz */
418 static uint32_t pllcfg_fury[16] = {
420 0x1b20, /* 1.8432 Mhz */
422 0xf42b, /* 2.4576 Mhz */
423 0x37e3, /* 3.57954 Mhz */
424 0x1b21, /* 3.6864 Mhz */
426 0x98ee, /* 4.906 Mhz */
427 0xd5b4, /* 4.9152 Mhz */
429 0x4e27, /* 5.12 Mhz */
431 0xec1c, /* 6.144 Mhz */
432 0x1b23, /* 7.3728 Mhz */
434 0xb11c /* 8.192 Mhz */
437 #define DID0_VER_MASK 0x70000000
438 #define DID0_VER_0 0x00000000
439 #define DID0_VER_1 0x10000000
441 #define DID0_CLASS_MASK 0x00FF0000
442 #define DID0_CLASS_SANDSTORM 0x00000000
443 #define DID0_CLASS_FURY 0x00010000
445 static int ssys_board_class(const ssys_state *s)
447 uint32_t did0 = s->did0;
448 switch (did0 & DID0_VER_MASK) {
450 return DID0_CLASS_SANDSTORM;
452 switch (did0 & DID0_CLASS_MASK) {
453 case DID0_CLASS_SANDSTORM:
454 case DID0_CLASS_FURY:
455 return did0 & DID0_CLASS_MASK;
457 /* for unknown classes, fall through */
459 /* This can only happen if the hardwired constant did0 value
460 * in this board's stellaris_board_info struct is wrong.
462 g_assert_not_reached();
466 static uint64_t ssys_read(void *opaque, hwaddr offset,
469 ssys_state *s = (ssys_state *)opaque;
472 case 0x000: /* DID0 */
474 case 0x004: /* DID1 */
476 case 0x008: /* DC0 */
478 case 0x010: /* DC1 */
480 case 0x014: /* DC2 */
482 case 0x018: /* DC3 */
484 case 0x01c: /* DC4 */
486 case 0x030: /* PBORCTL */
488 case 0x034: /* LDOPCTL */
490 case 0x040: /* SRCR0 */
492 case 0x044: /* SRCR1 */
494 case 0x048: /* SRCR2 */
496 case 0x050: /* RIS */
497 return s->int_status;
498 case 0x054: /* IMC */
500 case 0x058: /* MISC */
501 return s->int_status & s->int_mask;
502 case 0x05c: /* RESC */
504 case 0x060: /* RCC */
506 case 0x064: /* PLLCFG */
509 xtal = (s->rcc >> 6) & 0xf;
510 switch (ssys_board_class(s)) {
511 case DID0_CLASS_FURY:
512 return pllcfg_fury[xtal];
513 case DID0_CLASS_SANDSTORM:
514 return pllcfg_sandstorm[xtal];
516 g_assert_not_reached();
519 case 0x070: /* RCC2 */
521 case 0x100: /* RCGC0 */
523 case 0x104: /* RCGC1 */
525 case 0x108: /* RCGC2 */
527 case 0x110: /* SCGC0 */
529 case 0x114: /* SCGC1 */
531 case 0x118: /* SCGC2 */
533 case 0x120: /* DCGC0 */
535 case 0x124: /* DCGC1 */
537 case 0x128: /* DCGC2 */
539 case 0x150: /* CLKVCLR */
541 case 0x160: /* LDOARST */
543 case 0x1e0: /* USER0 */
545 case 0x1e4: /* USER1 */
548 qemu_log_mask(LOG_GUEST_ERROR,
549 "SSYS: read at bad offset 0x%x\n", (int)offset);
554 static bool ssys_use_rcc2(ssys_state *s)
556 return (s->rcc2 >> 31) & 0x1;
560 * Calculate the system clock period. We only want to propagate
561 * this change to the rest of the system if we're not being called
562 * from migration post-load.
564 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
567 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
568 * clock is 200MHz, which is a period of 5 ns. Dividing the clock
569 * frequency by X is the same as multiplying the period by X.
571 if (ssys_use_rcc2(s)) {
572 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
574 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
576 clock_set_ns(s->sysclk, system_clock_scale);
577 if (propagate_clock) {
578 clock_propagate(s->sysclk);
582 static void ssys_write(void *opaque, hwaddr offset,
583 uint64_t value, unsigned size)
585 ssys_state *s = (ssys_state *)opaque;
588 case 0x030: /* PBORCTL */
589 s->pborctl = value & 0xffff;
591 case 0x034: /* LDOPCTL */
592 s->ldopctl = value & 0x1f;
594 case 0x040: /* SRCR0 */
595 case 0x044: /* SRCR1 */
596 case 0x048: /* SRCR2 */
597 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n");
599 case 0x054: /* IMC */
600 s->int_mask = value & 0x7f;
602 case 0x058: /* MISC */
603 s->int_status &= ~value;
605 case 0x05c: /* RESC */
606 s->resc = value & 0x3f;
608 case 0x060: /* RCC */
609 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
611 s->int_status |= (1 << 6);
614 ssys_calculate_system_clock(s, true);
616 case 0x070: /* RCC2 */
617 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
621 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
623 s->int_status |= (1 << 6);
626 ssys_calculate_system_clock(s, true);
628 case 0x100: /* RCGC0 */
631 case 0x104: /* RCGC1 */
634 case 0x108: /* RCGC2 */
637 case 0x110: /* SCGC0 */
640 case 0x114: /* SCGC1 */
643 case 0x118: /* SCGC2 */
646 case 0x120: /* DCGC0 */
649 case 0x124: /* DCGC1 */
652 case 0x128: /* DCGC2 */
655 case 0x150: /* CLKVCLR */
658 case 0x160: /* LDOARST */
662 qemu_log_mask(LOG_GUEST_ERROR,
663 "SSYS: write at bad offset 0x%x\n", (int)offset);
668 static const MemoryRegionOps ssys_ops = {
671 .endianness = DEVICE_NATIVE_ENDIAN,
674 static void stellaris_sys_reset_enter(Object *obj, ResetType type)
676 ssys_state *s = STELLARIS_SYS(obj);
681 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
684 s->rcc2 = 0x07802810;
691 static void stellaris_sys_reset_hold(Object *obj)
693 ssys_state *s = STELLARIS_SYS(obj);
695 /* OK to propagate clocks from the hold phase */
696 ssys_calculate_system_clock(s, true);
699 static void stellaris_sys_reset_exit(Object *obj)
703 static int stellaris_sys_post_load(void *opaque, int version_id)
705 ssys_state *s = opaque;
707 ssys_calculate_system_clock(s, false);
712 static const VMStateDescription vmstate_stellaris_sys = {
713 .name = "stellaris_sys",
715 .minimum_version_id = 1,
716 .post_load = stellaris_sys_post_load,
717 .fields = (VMStateField[]) {
718 VMSTATE_UINT32(pborctl, ssys_state),
719 VMSTATE_UINT32(ldopctl, ssys_state),
720 VMSTATE_UINT32(int_mask, ssys_state),
721 VMSTATE_UINT32(int_status, ssys_state),
722 VMSTATE_UINT32(resc, ssys_state),
723 VMSTATE_UINT32(rcc, ssys_state),
724 VMSTATE_UINT32_V(rcc2, ssys_state, 2),
725 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
726 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
727 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
728 VMSTATE_UINT32(clkvclr, ssys_state),
729 VMSTATE_UINT32(ldoarst, ssys_state),
730 /* No field for sysclk -- handled in post-load instead */
731 VMSTATE_END_OF_LIST()
735 static Property stellaris_sys_properties[] = {
736 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
737 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
738 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
739 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
740 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
741 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
742 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
743 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
744 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
745 DEFINE_PROP_END_OF_LIST()
748 static void stellaris_sys_instance_init(Object *obj)
750 ssys_state *s = STELLARIS_SYS(obj);
751 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
753 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
754 sysbus_init_mmio(sbd, &s->iomem);
755 sysbus_init_irq(sbd, &s->irq);
756 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
759 static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq,
760 stellaris_board_info *board,
763 DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS);
764 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
766 /* Most devices come preprogrammed with a MAC address in the user data. */
767 qdev_prop_set_uint32(dev, "user0",
768 macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16));
769 qdev_prop_set_uint32(dev, "user1",
770 macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16));
771 qdev_prop_set_uint32(dev, "did0", board->did0);
772 qdev_prop_set_uint32(dev, "did1", board->did1);
773 qdev_prop_set_uint32(dev, "dc0", board->dc0);
774 qdev_prop_set_uint32(dev, "dc1", board->dc1);
775 qdev_prop_set_uint32(dev, "dc2", board->dc2);
776 qdev_prop_set_uint32(dev, "dc3", board->dc3);
777 qdev_prop_set_uint32(dev, "dc4", board->dc4);
779 sysbus_realize_and_unref(sbd, &error_fatal);
780 sysbus_mmio_map(sbd, 0, base);
781 sysbus_connect_irq(sbd, 0, irq);
786 /* I2C controller. */
788 #define TYPE_STELLARIS_I2C "stellaris-i2c"
789 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
791 struct stellaris_i2c_state {
792 SysBusDevice parent_obj;
806 #define STELLARIS_I2C_MCS_BUSY 0x01
807 #define STELLARIS_I2C_MCS_ERROR 0x02
808 #define STELLARIS_I2C_MCS_ADRACK 0x04
809 #define STELLARIS_I2C_MCS_DATACK 0x08
810 #define STELLARIS_I2C_MCS_ARBLST 0x10
811 #define STELLARIS_I2C_MCS_IDLE 0x20
812 #define STELLARIS_I2C_MCS_BUSBSY 0x40
814 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
817 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
823 /* We don't emulate timing, so the controller is never busy. */
824 return s->mcs | STELLARIS_I2C_MCS_IDLE;
827 case 0x0c: /* MTPR */
829 case 0x10: /* MIMR */
831 case 0x14: /* MRIS */
833 case 0x18: /* MMIS */
834 return s->mris & s->mimr;
838 qemu_log_mask(LOG_GUEST_ERROR,
839 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
844 static void stellaris_i2c_update(stellaris_i2c_state *s)
848 level = (s->mris & s->mimr) != 0;
849 qemu_set_irq(s->irq, level);
852 static void stellaris_i2c_write(void *opaque, hwaddr offset,
853 uint64_t value, unsigned size)
855 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
859 s->msa = value & 0xff;
862 if ((s->mcr & 0x10) == 0) {
863 /* Disabled. Do nothing. */
866 /* Grab the bus if this is starting a transfer. */
867 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
868 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
869 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
871 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
872 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
875 /* If we don't have the bus then indicate an error. */
876 if (!i2c_bus_busy(s->bus)
877 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
878 s->mcs |= STELLARIS_I2C_MCS_ERROR;
881 s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
883 /* Transfer a byte. */
884 /* TODO: Handle errors. */
887 s->mdr = i2c_recv(s->bus);
890 i2c_send(s->bus, s->mdr);
892 /* Raise an interrupt. */
896 /* Finish transfer. */
897 i2c_end_transfer(s->bus);
898 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
902 s->mdr = value & 0xff;
904 case 0x0c: /* MTPR */
905 s->mtpr = value & 0xff;
907 case 0x10: /* MIMR */
910 case 0x1c: /* MICR */
915 qemu_log_mask(LOG_UNIMP,
916 "stellaris_i2c: Loopback not implemented\n");
919 qemu_log_mask(LOG_UNIMP,
920 "stellaris_i2c: Slave mode not implemented\n");
922 s->mcr = value & 0x31;
925 qemu_log_mask(LOG_GUEST_ERROR,
926 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
928 stellaris_i2c_update(s);
931 static void stellaris_i2c_reset(stellaris_i2c_state *s)
933 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
934 i2c_end_transfer(s->bus);
943 stellaris_i2c_update(s);
946 static const MemoryRegionOps stellaris_i2c_ops = {
947 .read = stellaris_i2c_read,
948 .write = stellaris_i2c_write,
949 .endianness = DEVICE_NATIVE_ENDIAN,
952 static const VMStateDescription vmstate_stellaris_i2c = {
953 .name = "stellaris_i2c",
955 .minimum_version_id = 1,
956 .fields = (VMStateField[]) {
957 VMSTATE_UINT32(msa, stellaris_i2c_state),
958 VMSTATE_UINT32(mcs, stellaris_i2c_state),
959 VMSTATE_UINT32(mdr, stellaris_i2c_state),
960 VMSTATE_UINT32(mtpr, stellaris_i2c_state),
961 VMSTATE_UINT32(mimr, stellaris_i2c_state),
962 VMSTATE_UINT32(mris, stellaris_i2c_state),
963 VMSTATE_UINT32(mcr, stellaris_i2c_state),
964 VMSTATE_END_OF_LIST()
968 static void stellaris_i2c_init(Object *obj)
970 DeviceState *dev = DEVICE(obj);
971 stellaris_i2c_state *s = STELLARIS_I2C(obj);
972 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
975 sysbus_init_irq(sbd, &s->irq);
976 bus = i2c_init_bus(dev, "i2c");
979 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
981 sysbus_init_mmio(sbd, &s->iomem);
982 /* ??? For now we only implement the master interface. */
983 stellaris_i2c_reset(s);
986 /* Analogue to Digital Converter. This is only partially implemented,
987 enough for applications that use a combined ADC and timer tick. */
989 #define STELLARIS_ADC_EM_CONTROLLER 0
990 #define STELLARIS_ADC_EM_COMP 1
991 #define STELLARIS_ADC_EM_EXTERNAL 4
992 #define STELLARIS_ADC_EM_TIMER 5
993 #define STELLARIS_ADC_EM_PWM0 6
994 #define STELLARIS_ADC_EM_PWM1 7
995 #define STELLARIS_ADC_EM_PWM2 8
997 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
998 #define STELLARIS_ADC_FIFO_FULL 0x1000
1000 #define TYPE_STELLARIS_ADC "stellaris-adc"
1001 typedef struct StellarisADCState stellaris_adc_state;
1002 DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
1005 struct StellarisADCState {
1006 SysBusDevice parent_obj;
1027 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
1031 tail = s->fifo[n].state & 0xf;
1032 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
1035 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
1036 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
1037 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
1038 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
1040 return s->fifo[n].data[tail];
1043 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
1048 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
1049 FIFO fir each sequencer. */
1050 head = (s->fifo[n].state >> 4) & 0xf;
1051 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
1055 s->fifo[n].data[head] = value;
1056 head = (head + 1) & 0xf;
1057 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
1058 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
1059 if ((s->fifo[n].state & 0xf) == head)
1060 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
1063 static void stellaris_adc_update(stellaris_adc_state *s)
1068 for (n = 0; n < 4; n++) {
1069 level = (s->ris & s->im & (1 << n)) != 0;
1070 qemu_set_irq(s->irq[n], level);
1074 static void stellaris_adc_trigger(void *opaque, int irq, int level)
1076 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1079 for (n = 0; n < 4; n++) {
1080 if ((s->actss & (1 << n)) == 0) {
1084 if (((s->emux >> (n * 4)) & 0xff) != 5) {
1088 /* Some applications use the ADC as a random number source, so introduce
1089 some variation into the signal. */
1090 s->noise = s->noise * 314159 + 1;
1091 /* ??? actual inputs not implemented. Return an arbitrary value. */
1092 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
1094 stellaris_adc_update(s);
1098 static void stellaris_adc_reset(stellaris_adc_state *s)
1102 for (n = 0; n < 4; n++) {
1105 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1109 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
1112 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1114 /* TODO: Implement this. */
1115 if (offset >= 0x40 && offset < 0xc0) {
1117 n = (offset - 0x40) >> 5;
1118 switch (offset & 0x1f) {
1119 case 0x00: /* SSMUX */
1121 case 0x04: /* SSCTL */
1123 case 0x08: /* SSFIFO */
1124 return stellaris_adc_fifo_read(s, n);
1125 case 0x0c: /* SSFSTAT */
1126 return s->fifo[n].state;
1132 case 0x00: /* ACTSS */
1134 case 0x04: /* RIS */
1138 case 0x0c: /* ISC */
1139 return s->ris & s->im;
1140 case 0x10: /* OSTAT */
1142 case 0x14: /* EMUX */
1144 case 0x18: /* USTAT */
1146 case 0x20: /* SSPRI */
1148 case 0x30: /* SAC */
1151 qemu_log_mask(LOG_GUEST_ERROR,
1152 "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
1157 static void stellaris_adc_write(void *opaque, hwaddr offset,
1158 uint64_t value, unsigned size)
1160 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1162 /* TODO: Implement this. */
1163 if (offset >= 0x40 && offset < 0xc0) {
1165 n = (offset - 0x40) >> 5;
1166 switch (offset & 0x1f) {
1167 case 0x00: /* SSMUX */
1168 s->ssmux[n] = value & 0x33333333;
1170 case 0x04: /* SSCTL */
1172 qemu_log_mask(LOG_UNIMP,
1173 "ADC: Unimplemented sequence %" PRIx64 "\n",
1176 s->ssctl[n] = value;
1183 case 0x00: /* ACTSS */
1184 s->actss = value & 0xf;
1189 case 0x0c: /* ISC */
1192 case 0x10: /* OSTAT */
1195 case 0x14: /* EMUX */
1198 case 0x18: /* USTAT */
1201 case 0x20: /* SSPRI */
1204 case 0x28: /* PSSI */
1205 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
1207 case 0x30: /* SAC */
1211 qemu_log_mask(LOG_GUEST_ERROR,
1212 "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
1214 stellaris_adc_update(s);
1217 static const MemoryRegionOps stellaris_adc_ops = {
1218 .read = stellaris_adc_read,
1219 .write = stellaris_adc_write,
1220 .endianness = DEVICE_NATIVE_ENDIAN,
1223 static const VMStateDescription vmstate_stellaris_adc = {
1224 .name = "stellaris_adc",
1226 .minimum_version_id = 1,
1227 .fields = (VMStateField[]) {
1228 VMSTATE_UINT32(actss, stellaris_adc_state),
1229 VMSTATE_UINT32(ris, stellaris_adc_state),
1230 VMSTATE_UINT32(im, stellaris_adc_state),
1231 VMSTATE_UINT32(emux, stellaris_adc_state),
1232 VMSTATE_UINT32(ostat, stellaris_adc_state),
1233 VMSTATE_UINT32(ustat, stellaris_adc_state),
1234 VMSTATE_UINT32(sspri, stellaris_adc_state),
1235 VMSTATE_UINT32(sac, stellaris_adc_state),
1236 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1237 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1238 VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1239 VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1240 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1241 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1242 VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1243 VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1244 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1245 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1246 VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1247 VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1248 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1249 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1250 VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1251 VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1252 VMSTATE_UINT32(noise, stellaris_adc_state),
1253 VMSTATE_END_OF_LIST()
1257 static void stellaris_adc_init(Object *obj)
1259 DeviceState *dev = DEVICE(obj);
1260 stellaris_adc_state *s = STELLARIS_ADC(obj);
1261 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1264 for (n = 0; n < 4; n++) {
1265 sysbus_init_irq(sbd, &s->irq[n]);
1268 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
1270 sysbus_init_mmio(sbd, &s->iomem);
1271 stellaris_adc_reset(s);
1272 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
1276 static stellaris_board_info stellaris_boards[] = {
1280 0x001f001f, /* dc0 */
1290 0x00ff007f, /* dc0 */
1295 BP_OLED_SSI | BP_GAMEPAD
1299 static void stellaris_init(MachineState *ms, stellaris_board_info *board)
1301 static const int uart_irq[] = {5, 6, 33, 34};
1302 static const int timer_irq[] = {19, 21, 23, 35};
1303 static const uint32_t gpio_addr[7] =
1304 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1305 0x40024000, 0x40025000, 0x40026000};
1306 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1308 /* Memory map of SoC devices, from
1309 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
1310 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
1313 * 40002000 i2c (unimplemented)
1323 * 40021000 i2c (unimplemented)
1327 * 40028000 PWM (unimplemented)
1328 * 4002c000 QEI (unimplemented)
1329 * 4002d000 QEI (unimplemented)
1335 * 4003c000 analogue comparator (unimplemented)
1337 * 400fc000 hibernation module (unimplemented)
1338 * 400fd000 flash memory control (unimplemented)
1339 * 400fe000 system control
1342 DeviceState *gpio_dev[7], *nvic;
1343 qemu_irq gpio_in[7][8];
1344 qemu_irq gpio_out[7][8];
1350 DeviceState *ssys_dev;
1354 MemoryRegion *sram = g_new(MemoryRegion, 1);
1355 MemoryRegion *flash = g_new(MemoryRegion, 1);
1356 MemoryRegion *system_memory = get_system_memory();
1358 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1359 sram_size = ((board->dc0 >> 18) + 1) * 1024;
1361 /* Flash programming is done via the SCU, so pretend it is ROM. */
1362 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
1364 memory_region_add_subregion(system_memory, 0, flash);
1366 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1368 memory_region_add_subregion(system_memory, 0x20000000, sram);
1370 nvic = qdev_new(TYPE_ARMV7M);
1371 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
1372 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
1373 qdev_prop_set_bit(nvic, "enable-bitband", true);
1374 object_property_set_link(OBJECT(nvic), "memory",
1375 OBJECT(get_system_memory()), &error_abort);
1376 /* This will exit with an error if the user passed us a bad cpu_type */
1377 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
1379 if (board->dc1 & (1 << 16)) {
1380 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1381 qdev_get_gpio_in(nvic, 14),
1382 qdev_get_gpio_in(nvic, 15),
1383 qdev_get_gpio_in(nvic, 16),
1384 qdev_get_gpio_in(nvic, 17),
1386 adc = qdev_get_gpio_in(dev, 0);
1390 for (i = 0; i < 4; i++) {
1391 if (board->dc2 & (0x10000 << i)) {
1392 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
1393 0x40030000 + i * 0x1000,
1394 qdev_get_gpio_in(nvic, timer_irq[i]));
1395 /* TODO: This is incorrect, but we get away with it because
1396 the ADC output is only ever pulsed. */
1397 qdev_connect_gpio_out(dev, 0, adc);
1401 ssys_dev = stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
1402 board, nd_table[0].macaddr.a);
1405 if (board->dc1 & (1 << 3)) { /* watchdog present */
1406 dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
1408 qdev_connect_clock_in(dev, "WDOGCLK",
1409 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1411 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1412 sysbus_mmio_map(SYS_BUS_DEVICE(dev),
1415 sysbus_connect_irq(SYS_BUS_DEVICE(dev),
1417 qdev_get_gpio_in(nvic, 18));
1421 for (i = 0; i < 7; i++) {
1422 if (board->dc4 & (1 << i)) {
1423 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1424 qdev_get_gpio_in(nvic,
1426 for (j = 0; j < 8; j++) {
1427 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1428 gpio_out[i][j] = NULL;
1433 if (board->dc2 & (1 << 12)) {
1434 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
1435 qdev_get_gpio_in(nvic, 8));
1436 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1437 if (board->peripherals & BP_OLED_I2C) {
1438 i2c_slave_create_simple(i2c, "ssd0303", 0x3d);
1442 for (i = 0; i < 4; i++) {
1443 if (board->dc2 & (1 << i)) {
1444 pl011_luminary_create(0x4000c000 + i * 0x1000,
1445 qdev_get_gpio_in(nvic, uart_irq[i]),
1449 if (board->dc2 & (1 << 4)) {
1450 dev = sysbus_create_simple("pl022", 0x40008000,
1451 qdev_get_gpio_in(nvic, 7));
1452 if (board->peripherals & BP_OLED_SSI) {
1455 DeviceState *ssddev;
1457 /* Some boards have both an OLED controller and SD card connected to
1458 * the same SSI port, with the SD card chip select connected to a
1459 * GPIO pin. Technically the OLED chip select is connected to the
1460 * SSI Fss pin. We do not bother emulating that as both devices
1461 * should never be selected simultaneously, and our OLED controller
1462 * ignores stray 0xff commands that occur when deselecting the SD
1465 bus = qdev_get_child_bus(dev, "ssi");
1467 sddev = ssi_create_peripheral(bus, "ssi-sd");
1468 ssddev = ssi_create_peripheral(bus, "ssd0323");
1469 gpio_out[GPIO_D][0] = qemu_irq_split(
1470 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
1471 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1472 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1474 /* Make sure the select pin is high. */
1475 qemu_irq_raise(gpio_out[GPIO_D][0]);
1478 if (board->dc4 & (1 << 28)) {
1481 qemu_check_nic_model(&nd_table[0], "stellaris");
1483 enet = qdev_new("stellaris_enet");
1484 qdev_set_nic_properties(enet, &nd_table[0]);
1485 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal);
1486 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1487 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1489 if (board->peripherals & BP_GAMEPAD) {
1490 qemu_irq gpad_irq[5];
1491 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1493 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1494 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1495 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1496 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1497 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1499 stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1501 for (i = 0; i < 7; i++) {
1502 if (board->dc4 & (1 << i)) {
1503 for (j = 0; j < 8; j++) {
1504 if (gpio_out[i][j]) {
1505 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1511 /* Add dummy regions for the devices we don't implement yet,
1512 * so guest accesses don't cause unlogged crashes.
1514 create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1515 create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1516 create_unimplemented_device("PWM", 0x40028000, 0x1000);
1517 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1518 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1519 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1520 create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1521 create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1523 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size);
1526 /* FIXME: Figure out how to generate these from stellaris_boards. */
1527 static void lm3s811evb_init(MachineState *machine)
1529 stellaris_init(machine, &stellaris_boards[0]);
1532 static void lm3s6965evb_init(MachineState *machine)
1534 stellaris_init(machine, &stellaris_boards[1]);
1537 static void lm3s811evb_class_init(ObjectClass *oc, void *data)
1539 MachineClass *mc = MACHINE_CLASS(oc);
1541 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)";
1542 mc->init = lm3s811evb_init;
1543 mc->ignore_memory_transaction_failures = true;
1544 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1547 static const TypeInfo lm3s811evb_type = {
1548 .name = MACHINE_TYPE_NAME("lm3s811evb"),
1549 .parent = TYPE_MACHINE,
1550 .class_init = lm3s811evb_class_init,
1553 static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
1555 MachineClass *mc = MACHINE_CLASS(oc);
1557 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)";
1558 mc->init = lm3s6965evb_init;
1559 mc->ignore_memory_transaction_failures = true;
1560 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1563 static const TypeInfo lm3s6965evb_type = {
1564 .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1565 .parent = TYPE_MACHINE,
1566 .class_init = lm3s6965evb_class_init,
1569 static void stellaris_machine_init(void)
1571 type_register_static(&lm3s811evb_type);
1572 type_register_static(&lm3s6965evb_type);
1575 type_init(stellaris_machine_init)
1577 static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1579 DeviceClass *dc = DEVICE_CLASS(klass);
1581 dc->vmsd = &vmstate_stellaris_i2c;
1584 static const TypeInfo stellaris_i2c_info = {
1585 .name = TYPE_STELLARIS_I2C,
1586 .parent = TYPE_SYS_BUS_DEVICE,
1587 .instance_size = sizeof(stellaris_i2c_state),
1588 .instance_init = stellaris_i2c_init,
1589 .class_init = stellaris_i2c_class_init,
1592 static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
1594 DeviceClass *dc = DEVICE_CLASS(klass);
1596 dc->vmsd = &vmstate_stellaris_gptm;
1597 dc->realize = stellaris_gptm_realize;
1600 static const TypeInfo stellaris_gptm_info = {
1601 .name = TYPE_STELLARIS_GPTM,
1602 .parent = TYPE_SYS_BUS_DEVICE,
1603 .instance_size = sizeof(gptm_state),
1604 .instance_init = stellaris_gptm_init,
1605 .class_init = stellaris_gptm_class_init,
1608 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1610 DeviceClass *dc = DEVICE_CLASS(klass);
1612 dc->vmsd = &vmstate_stellaris_adc;
1615 static const TypeInfo stellaris_adc_info = {
1616 .name = TYPE_STELLARIS_ADC,
1617 .parent = TYPE_SYS_BUS_DEVICE,
1618 .instance_size = sizeof(stellaris_adc_state),
1619 .instance_init = stellaris_adc_init,
1620 .class_init = stellaris_adc_class_init,
1623 static void stellaris_sys_class_init(ObjectClass *klass, void *data)
1625 DeviceClass *dc = DEVICE_CLASS(klass);
1626 ResettableClass *rc = RESETTABLE_CLASS(klass);
1628 dc->vmsd = &vmstate_stellaris_sys;
1629 rc->phases.enter = stellaris_sys_reset_enter;
1630 rc->phases.hold = stellaris_sys_reset_hold;
1631 rc->phases.exit = stellaris_sys_reset_exit;
1632 device_class_set_props(dc, stellaris_sys_properties);
1635 static const TypeInfo stellaris_sys_info = {
1636 .name = TYPE_STELLARIS_SYS,
1637 .parent = TYPE_SYS_BUS_DEVICE,
1638 .instance_size = sizeof(ssys_state),
1639 .instance_init = stellaris_sys_instance_init,
1640 .class_init = stellaris_sys_class_init,
1643 static void stellaris_register_types(void)
1645 type_register_static(&stellaris_i2c_info);
1646 type_register_static(&stellaris_gptm_info);
1647 type_register_static(&stellaris_adc_info);
1648 type_register_static(&stellaris_sys_info);
1651 type_init(stellaris_register_types)